TWI841037B - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A semiconductor device includes a substrate, a gate dielectric layer, and plural gate electrode structures. The substrate has a crown structure having plural protruding portions and plural trenches. Each of the trenches is between two adjacent protruding portions. Each of the protruding portions has an upper portion, a middle portion, and a lower portion, and a width of the middle portion is less than a width of the upper portion and a width of the lower portion. The gate dielectric layer is located on the substrate and disposed along a surface of the crown structure. A thickness of the gate dielectric layer on the middle portion is greater than a thickness of the gate dielectric layer on the upper portion and a thickness of the gate dielectric layer on the lower portion. The gate electrode structures are respectively located in the trenches. The gate dielectric layer is located between one of the gate electrode structures and one of the protruding portions.

Description

Semiconductor device and method for manufacturing the same

The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device.

Generally speaking, in the manufacture of integrated circuits, since the current driving capability is the function of source resistance and gate oxide, better performance in the device can be achieved through thicker gate oxides and complex spacer layers.

However, when the size of a device such as a metal oxide semiconductor field effect transistor (MOSFET) is reduced (e.g., from 20 nm to 10 nm), the current driving capability of the semiconductor device is affected and performance issues arise. For example, when the gate oxide of a semiconductor device is made too thin, gate-induced drain leakage (GIDL) may occur. In logic circuits, GIDL increases standby power requirements, while in dynamic random access memory (DRAM) arrays, GIDL shortens data retention time. In addition, when the channel area of a semiconductor device is small, a larger subthreshold swing (SS) may be generated, which means that the switching characteristics between the on state and the off state of the device are poor. The above problems will be detrimental to product design and competitiveness.

One technical aspect of the present disclosure is a semiconductor device.

According to some embodiments of the present disclosure, a semiconductor device includes a substrate, a gate dielectric layer and a plurality of gate structures. The substrate has a crown structure, and the crown structure has a plurality of protrusions and a plurality of trenches. Each of the trenches is located between two adjacent protrusions. Each of the protrusions has an upper portion, a middle portion and a lower portion, and the width of the middle portion is smaller than the width of the upper portion and the width of the lower portion. The gate dielectric layer is located on the substrate and is arranged along the surface of the crown structure. The thickness of the gate dielectric layer in the middle portion is greater than its thickness in the upper portion and the thickness in the lower portion. The gate structures are respectively located in the trenches. The gate dielectric layer is located between one of the gate structures and one of the protrusions.

In some embodiments, the middle portion of each of the above-mentioned protrusions has an arc-shaped concave side wall.

In some embodiments, the top surface of the gate structure is lower than the upper portion of the protrusion and higher than the lower portion of the protrusion.

In some embodiments, the ratio of the width of the middle portion to the width of the lower portion of each of the above-mentioned protrusions is in the range of 50% to 70%.

In some embodiments, each of the trenches has a saddle fin at its bottom, the saddle fin has an arc-shaped surface, and the saddle fin is covered by one of the gate structures and a gate dielectric layer.

One technical aspect of the present disclosure is a method for manufacturing a semiconductor device.

According to some embodiments of the present disclosure, a method for manufacturing a semiconductor device includes: forming a crown structure on a substrate, wherein the crown structure has a plurality of protrusions and a plurality of trenches, each of the trenches is located between two adjacent protrusions, and each of the protrusions has an upper portion, a middle portion, and a lower portion; reducing the width of the middle portion of each protrusion of the crown structure so that the middle portion The width of the crown structure is smaller than the width of the upper portion and the width of the lower portion; a gate dielectric layer is formed on the substrate, wherein the gate dielectric layer is arranged along the surface of the crown structure, and the thickness of the gate dielectric layer in the middle portion is greater than the thickness of the gate dielectric layer in the upper portion and the thickness of the gate dielectric layer in the lower portion; and a plurality of gate structures are formed in the trenches respectively, so that the gate dielectric layer is located between one of the gate structures and one of the protrusions.

In some embodiments, the gate dielectric layer is formed on the substrate using an on-site vapor deposition method or a combination thereof with an atomic layer deposition method, and the crown structure is formed on the substrate using a dry etching method.

In some embodiments, the width of the middle portion of each of the protrusions of the crown structure is reduced by wet etching or a cleaning step.

In some embodiments, the width of the middle portion of each of the convex portions of the reduced crown structure is such that the ratio of the width of the middle portion to the width of the lower portion is in the range of 50% to 70%.

In some embodiments, the bottom of each of the grooves has a saddle-shaped fin, and the width of the middle portion of each of the convex portions of the crown structure is reduced so that the saddle-shaped fin has an arc-shaped surface.

In the above-mentioned embodiments of the present disclosure, since the width of the middle portion of the convex portion of the crown structure of the semiconductor device is smaller than the width of the upper portion of the convex portion and the width of the lower portion of the convex portion, after the gate dielectric layer is subsequently formed, the thickness of the gate dielectric layer in the middle portion of the convex portion will be greater than its thickness in the upper portion of the convex portion and the thickness in the lower portion of the convex portion. In this way, when the size specification of the semiconductor device is miniaturized, the gate dielectric layer in the middle portion of the convex portion can still have a larger thickness, thereby improving the gate-induced drain leakage (GIDL), which can enhance the current driving capability and performance of the semiconductor device, and is beneficial to product design and competitiveness.

The embodiments disclosed below provide many different embodiments, or examples, for implementing the different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these examples are only examples and are not intended to be limiting. In addition, the present invention may repeat component symbols and/or letters in each example. This repetition is for the purpose of simplicity and clarity, and does not itself specify the relationship between the various embodiments and/or configurations discussed.

Spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein for descriptive purposes to describe the relationship of one element or feature to another element or feature as illustrated in the accompanying figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the accompanying figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

FIG. 1 shows a cross-sectional view of a semiconductor device 100 according to an embodiment of the present disclosure. The semiconductor device 100 includes a substrate 110, a gate dielectric layer 120, and a plurality of gate structures 130. The substrate 110 has a crown structure 112, and the crown structure 112 has a plurality of protrusions 113 and a plurality of trenches 114. Each of the trenches 114 is located between two adjacent protrusions 113. Each of the protrusions 113 has an upper portion 115, a middle portion 116, and a lower portion 117. The upper portion 115 of the protrusion 113 has a width W1, the middle portion 116 has a width W2, and the lower portion 117 has a width W3, and the width W2 of the middle portion 116 is smaller than the width W1 of the upper portion 115 and the width W3 of the lower portion 117. The gate dielectric layer 120 is located on the substrate 110 and is disposed along the surface of the crown structure 112. The gate dielectric layer 120 has a width variation on the sidewall of the protrusion 113, and the gate dielectric layer 120 has thicknesses t1, t2, and t3 at the upper portion 115, the middle portion 116, and the lower portion 117, respectively. In addition, the thickness t2 of the gate dielectric layer 120 in the middle portion 116 is greater than the thickness t1 of the upper portion 115 and the thickness t3 of the lower portion 117. The gate structure 130 is respectively located in the trench 114, so that a portion of the gate dielectric layer 120 is located between the gate structure 130 and the protrusion 113 of the crown structure 112.

In this embodiment, the material of the substrate 110 may be silicon, the material of the gate dielectric layer 120 may be oxide, and the material of the gate structure 130 may be metal, such as tungsten, but this is not intended to limit the present disclosure. In addition, the semiconductor device 100 may be applied to dynamic random access memory (DRAM).

Since the width W2 of the middle portion 116 of the protrusion 113 of the crown structure 112 of the semiconductor device 100 is smaller than the width W1 of the upper portion 115 of the protrusion 113 and the width W3 of the lower portion 117 of the protrusion 113, after the gate dielectric layer 120 is subsequently formed, the thickness t2 of the gate dielectric layer 120 in the middle portion 116 of the protrusion 113 will be greater than the thickness t1 of the upper portion 115 of the protrusion 113 and the thickness t3 of the lower portion 117 of the protrusion 113. In this way, when the size of the semiconductor device 100 is miniaturized (for example, from 20nm to 10nm), the gate dielectric layer 120 in the middle portion 116 of the protrusion 113 can still have a relatively large thickness t2, thereby improving the gate-induced drain leakage (GIDL), thereby enhancing the current driving capability and performance of the semiconductor device 100, and being beneficial to product design and competitiveness.

In addition, each of the trenches 114 has a saddle fin 111 at the bottom thereof, the saddle fin 111 having an arc-shaped surface 119 (see FIG. 5 for details), and the saddle fin 111 is covered by a gate structure 130 and a gate dielectric layer 120, and the gate dielectric layer 120 is located between the gate structure 130 and the saddle fin 111. The position of the saddle fin 111 is hidden in the position of the gate structure 130 in FIG. Since the position of the saddle fin 111 is different from the cross-sectional position of FIG. 2, FIG. 3, FIG. 4 and FIG. 6, it is only indicated by a dotted line, and it is explained first. Through the above design, the channel area of the semiconductor device 100 is increased, thereby effectively reducing the subthreshold swing (SS), which means that the switching characteristics between the on state and the off state of the device are better, which is beneficial to product design and competitiveness.

In this embodiment, the width of the convex portion 113 gradually decreases from the upper portion 115 to the lower portion 117 and then gradually increases, and the narrowest position is the position of the middle portion 116. The middle portion 116 of the convex portion 113 has an arc-shaped concave side wall 118. The ratio of the width W2 of the middle portion 116 of the convex portion 113 to the width W3 of the lower portion 117 is in the range of 50% to 70%.

In addition, the top surface of the gate structure 130 is lower than the upper portion 115 of the protrusion 113 and higher than the lower portion 117 of the protrusion 113. The position of the top surface of the gate structure 130 corresponds to the horizontal position of the narrower middle portion 116 (having a width W2), that is, corresponds to the horizontal position of the wider gate dielectric layer 120 (having a thickness t3). Such a configuration can effectively improve the gate-induced drain leakage and enhance the current driving capability and performance of the semiconductor device 100.

It should be understood that the connection relationship, materials and functions of the components described above will not be repeated, and are described first. In the following description, a method for manufacturing the semiconductor device 100 will be described.

Figure 2 shows a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. The method for manufacturing a semiconductor device includes the following steps. In step S1, a crown structure is formed on a substrate, wherein the crown structure has a plurality of protrusions and a plurality of trenches, each of the trenches is located between two adjacent protrusions, and each of the protrusions has an upper portion, a middle portion, and a lower portion. Then in step S2, the width of the middle portion of each of the protrusions of the crown structure is reduced so that the width of the middle portion is smaller than the width of the upper portion and the width of the lower portion. Thereafter, in step S3, a gate dielectric layer is formed on the substrate, wherein the gate dielectric layer is disposed along the surface of the crown structure, and the thickness of the gate dielectric layer in the middle portion is greater than its thickness in the upper portion and the thickness in the lower portion. Then, in step S4, a plurality of gate structures are formed in the trenches respectively, so that the gate dielectric layer is located between one of the gate structures and one of the protrusions.

In some embodiments, the method for manufacturing a semiconductor substrate is not limited to the above-mentioned steps S1 to S4. For example, in some embodiments, steps S1 to S4 may further include other steps between two successive steps, or may further include other steps before step S1 and further include other steps after step S4.

In the following description, each step of the method for manufacturing the semiconductor device will be described in detail.

Figures 3 to 6 are cross-sectional views of intermediate steps of a method for manufacturing a semiconductor substrate according to an embodiment of the present disclosure. Referring to Figure 3, first, a crown structure 112 is formed on a substrate 110, so that the crown structure 112 has a plurality of protrusions 113 and a plurality of grooves 114, and each of the grooves 114 is located between two adjacent protrusions 113. The above steps may be performed by dry etching. Through this step, the groove 114 may have a width W4, and the widths of the upper portion 115 and the middle portion 116 of the protrusion 113 are substantially the same, for example, both are width W, or the width of the upper portion 115 is slightly smaller than the width W of the middle portion 116. In addition, after the dry etching step, the bottom of the trench 114 may have a saddle-shaped fin 111 with a flat surface.

Referring to FIG. 4, the width W of the middle portion 116 of each of the protrusions 113 of the crown structure 112 is then reduced (see FIG. 3) so that the reduced width W2 of the middle portion 116 is smaller than the width W1 of the upper portion 115 and the width W3 of the lower portion 117. The above step may be performed by isotropic etching, such as wet etching or a clean step. The clean step includes acid etching, but is not limited thereto. Through this step, the ratio of the width W2 of the middle portion 116 of the protrusion 113 to the width W3 of the lower portion 117 is in the range of 50% to 70%. In addition, since the width of the protrusion 113 gradually decreases and then gradually increases from the upper portion 115 to the lower portion 117, the middle portion 116 of the protrusion 113 has an arc-shaped concave sidewall 118. In addition, through this step, the groove 114 can have a width W5 greater than the width W4 (see FIG. 3).

FIG. 5 is a partially enlarged three-dimensional view of the saddle fin 111 after the step of FIG. 4 is performed. Referring to FIG. 4 and FIG. 5 simultaneously, when the width W of the middle portion 116 of the protrusion 113 is reduced to the width W2, the saddle fin 111 at the bottom of the groove 114 is also etched synchronously, so that the saddle fin 111 has an arc-shaped surface 119. The arc-shaped surface 119 of the saddle fin 111 may include the top surface and the side wall of the saddle fin 111.

Referring to FIG. 6 , after the middle portion 116 of the protrusion 113 in FIG. 4 has a reduced width W2, a gate dielectric layer 120 can be formed on the substrate 110. The gate dielectric layer 120 is a coating layer and is disposed along the surface of the crown structure 112. Since the width W2 of the middle portion 116 of the protrusion 113 is smaller than the width W1 of the upper portion 115 and the width W3 of the lower portion 117, after the gate dielectric layer 120 is formed, the thickness t2 of the gate dielectric layer 120 in the middle portion 116 is greater than the thickness t1 of the upper portion 115 and the thickness t3 of the lower portion 117. The gate dielectric layer 120 may be formed by in-situ steam generation (ISSG) or a combination thereof with atomic layer deposition (ALD), but this is not intended to limit the present disclosure. In addition, through this step, the saddle fin 111 indicated by the dotted line in FIG. 6 is also covered by the gate dielectric layer 120.

Referring to FIG. 6 and FIG. 1 together, after the gate dielectric layer 120 is formed, the gate structure 130 can be formed in the trench 114 of the crown structure 112, respectively, so that the gate dielectric layer 120 is located between the gate structure 130 and the protrusion 113. Through this step, the gate structure 130 can cover the gate dielectric layer 120 and the saddle fin 111 thereunder.

In summary, since the width of the middle part of the crown structure of the semiconductor device is smaller than the width of the upper part and the width of the lower part of the protrusion, after the subsequent gate dielectric layer is formed, the thickness of the gate dielectric layer in the middle part of the protrusion will be greater than its thickness in the upper part and the thickness in the lower part of the protrusion. In this way, when the size of the semiconductor device is miniaturized, the gate dielectric layer in the middle part of the protrusion can still have a larger thickness, thereby improving the gate-induced drain leakage (GIDL), which can enhance the current driving capability and performance of the semiconductor device, and is beneficial to product design and competitiveness. In addition, since the saddle fin at the bottom of the trench can be etched synchronously when the width of the middle part of the convex part of the crown structure is reduced, the saddle fin can have a circular surface. In this way, the channel area of the semiconductor device is increased, so the subthreshold swing (SS) can be effectively reduced, which means that the switching characteristics between the on state and the off state of the device are better, which is beneficial to product design and competitiveness.

The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and/or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications here without departing from the spirit and scope of the present disclosure.

100: semiconductor device 110: substrate 111: saddle fin 112: crown structure 113: convex part 114: groove 115: upper part 116: middle part 117: lower part 118: concave sidewall 119: surface 120: gate dielectric layer 130: gate structure S1, S2, S3, S4: steps t1, t2, t3: thickness W, W1, W2, W3, W4, W5: width

The disclosure is best understood from the following embodiments when read in conjunction with the accompanying illustrations. Note that various features are not drawn to scale in accordance with standard practice in the industry. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion. FIG. 1 illustrates a cross-sectional view of a semiconductor device according to an embodiment of the disclosure. FIG. 2 illustrates a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the disclosure. FIG. 3, FIG. 4, and FIG. 6 illustrate cross-sectional views of intermediate steps of a method for manufacturing a semiconductor substrate according to an embodiment of the disclosure. FIG. 5 illustrates a partially enlarged stereoscopic view of a saddle fin after the step of FIG. 4 is performed.

Domestic storage information (please note in the order of storage institution, date, and number) None Foreign storage information (please note in the order of storage country, institution, date, and number) None

100:Semiconductor devices

110: Substrate

111: Saddle fin

112: Crown structure

113: convex part

114: Groove

115: Upper part

116: Middle part

117: Lower part

118: Concave side wall

119: Surface

120: Gate dielectric layer

130: Gate structure

t1, t2, t3: thickness

W1,W2,W3:Width

Claims (9)

A semiconductor device includes: a substrate having a crown structure, wherein the crown structure has a plurality of protrusions and a plurality of grooves, wherein each of the grooves is located between two adjacent protrusions, wherein each of the protrusions has an upper portion, a middle portion and a lower portion, and a width of the middle portion is smaller than a width of the upper portion and a width of the lower portion, and each of the protrusions has a width of The middle portion has an arc-shaped concave side wall; a gate dielectric layer is located on the substrate and arranged along the surface of the crown structure, wherein the thickness of the gate dielectric layer in the middle portion is greater than its thickness in the upper portion and the thickness in the lower portion; and a plurality of gate structures are respectively located in the trenches, wherein the gate dielectric layer is located between one of the gate structures and one of the protrusions. A semiconductor device as described in claim 1, wherein the top surfaces of the gate structures are lower than the upper portions of the protrusions and higher than the lower portions of the protrusions. A semiconductor device as described in claim 1, wherein the ratio of the width of the middle portion to the width of the lower portion of each of the protrusions is in the range of 50% to 70%. A semiconductor device as described in claim 1, wherein the bottom of each of the trenches has a saddle fin, the saddle fin has a circular arc surface, and the saddle fin is covered by one of the gate structures and the gate dielectric layer. A method for manufacturing a semiconductor device includes: forming a crown structure on a substrate, wherein the crown structure has a plurality of protrusions and a plurality of grooves, each of the grooves is located between two adjacent protrusions, and each of the protrusions has an upper portion, a middle portion, and a lower portion; reducing a width of the middle portion of each of the protrusions of the crown structure so that the width of the middle portion is smaller than that of the upper portion; A width of the upper portion and a width of the lower portion; forming a gate dielectric layer on the substrate, wherein the gate dielectric layer is disposed along the surface of the crown structure, and the thickness of the gate dielectric layer in the middle portion is greater than the thickness in the upper portion and the thickness in the lower portion; and forming a plurality of gate structures in the trenches respectively, so that the gate dielectric layer is located between one of the gate structures and one of the protrusions. The method for manufacturing a semiconductor device as described in claim 5, wherein the gate dielectric layer is formed on the substrate using an on-site vapor deposition method or a combination thereof with an atomic layer deposition method, and the crown structure is formed on the substrate using a dry etching method. A method for manufacturing a semiconductor device as described in claim 5, wherein the width of the middle portion of each of the protrusions of the crown structure is reduced by wet etching or a cleaning step. A method for manufacturing a semiconductor device as described in claim 5, wherein the width of the middle portion of each of the protrusions of the crown structure is reduced so that the ratio of the width of the middle portion to the width of the lower portion is in the range of 50% to 70%. A method for manufacturing a semiconductor device as described in claim 5, wherein the bottom of each of the grooves has a saddle-shaped fin, and the width of the middle portion of each of the protrusions of the crown structure is reduced so that the saddle-shaped fin has an arc-shaped surface.

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