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TWI725619B - 圖案化金屬層之方法 - Google Patents

圖案化金屬層之方法 Download PDF

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TWI725619B
TWI725619B TW108141301A TW108141301A TWI725619B TW I725619 B TWI725619 B TW I725619B TW 108141301 A TW108141301 A TW 108141301A TW 108141301 A TW108141301 A TW 108141301A TW I725619 B TWI725619 B TW I725619B
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layer
molybdenum
substrate
molybdenum layer
forming
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TW202025302A (zh
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歐卡藍 那拉馬蘇
魯多維 葛迪
王詣斐
晉欣 傅
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美商應用材料股份有限公司
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Abstract

本發明提供圖案化裝置(例如，半導體裝置)的金屬層的方法，以在互連層中形成特徵，此方法作為用於製造裝置的互連結構的處理的一部分。所揭示的方法說明具有改善選擇性之圖案化鉬層的處理。例如，本發明提供藉由退火或蝕刻改質與移除鉬層的區域之方法，而不損壞其他裝置結構或材料。

Description

圖案化金屬層之方法
本發明的實施例關於形成半導體裝置結構的方法。更具體地，本發明的實施例關於圖案化在基板上的金屬層之方法。
積體電路已經發展成在單一晶片上可包括數百萬之電晶體、電容器、及電阻器的複雜裝置。晶片設計的發展已經造成更大的電路密度以改善晶片的處理能力與速度。對於更快的處理能力與更大的電路密度的要求施加對應要求於用於製造此種積體電路的材料。尤其，當積體電路部件的尺寸縮減至次10 nm尺度時，低電阻導電材料及低介電常數絕緣材料用於從此種部件獲得合適電氣效能。
互連提供積體電路的各種電子部件之間的電氣連接及形成這些元件與用於將積體電路連接至其他電路的裝置的外部接觸元件(例如，銷)之間的連接。傳統上，銅已經是用於互連層的材料選擇。然而，在次10 nm尺度，習知銅互連顯現降低的傳導性，使得銅對於先進節點而言為非期望材料。最近，已在尋找替代材料以克服銅作為互連材料的缺點。一種此類材料為鉬。鉬互連甚至在次10 nm尺度顯現期望的電氣性質。然而，因為鉬是高硬度材料，鉬互連層在半導體裝置製造期間保持難以被圖案化。
因此，本領域中需要的是圖案化鉬層的改善方法。
在一實施例中，提供圖案化鉬互連層的方法。此方法包括在基板上形成鉬層。遮罩層接著在鉬層上方形成並圖案化以將鉬層的區域暴露至周圍。以氧改質鉬的暴露區域以形成鉬互連層的多個氧化鉬部分。在改質之後，鉬互連層的氧化鉬部分經由蝕刻處理從基板移除。
在一實施例中，提供在圖案化基板上形成金屬互連層的方法。此方法包括在圖案化基板上形成鉬層。遮罩層形成在鉬層上，圖案化遮罩層以將鉬層的不期望區域暴露至周圍。圖案化基板接著暴露至中性粒子束以移除鉬層的不期望區域。
在一實施例中，提供在基板上圖案化金屬互連層的方法。此方法包括在基板上形成鉬互連層。遮罩形成在鉬層上並圖案化以暴露鉬互連層的區域。基板接著放置進入基板處理腔室的基板處理區並暴露至在約20巴至約55巴的範圍內的分壓及約250°C至約550°C的範圍內的溫度之氣相H2 O，以移除鉬互連層的暴露區域。
本發明提供圖案化裝置(例如，半導體裝置)的金屬層以在互連層中形成特徵的方法，作為用於製造裝置的互連結構的處理的一部分。揭示的方法說明用於圖案化具有改善選擇性的鉬層的處理。例如，本發明提供藉由退火或蝕刻用於改質與移除鉬層的多個區域之方法，而不損傷其他裝置結構或材料。
圖1是根據一實施例之用於圖案化諸如半導體裝置的裝置之鉬層的方法100之流程圖。在某些實施例中，鉬層可直接沉積在基板表面上。在某些實施例中，鉬層可沉積在另一金屬層上，諸如阻障金屬層。在其他實施例中，鉬層可沉積在介電層上，諸如二氧化矽層。鉬層的圖案化可用於製造裝置的互連結構。圖案化方法100可執行在處理腔室中，諸如電漿處理腔室或其他合適處理腔室。接下來說明圖1的方法100，結合顯示在圖2A-2C中的視圖，其顯示在方法100的不同階段之包括鉬層的裝置。再者，雖然方法100在下方說明關於用於形成互連結構的鉬層，方法100也可有利地用於其他含金屬層與其他半導體裝置製造應用中。
在操作102，包括鉬層202的半導體裝置200(見圖2A)定位在電漿處理腔室中，例如，蝕刻處理腔室(未示出)。半導體裝置200在被製造的處理中或製造的各種階段中可包括一或多個半導體裝置。圖2A是根據一實施例之在移除安置在基板201上的一或多層的多個部分之前，包括鉬層202的半導體裝置200的一部分的圖解剖面視圖。圖2A中的視圖顯示在執行起始圖案化處理(例如，氧化處理)以改質鉬層202的多個部分之前的半導體裝置200。
半導體裝置200包括基板201。基板201可由任何合適材料形成，諸如矽、結晶矽、氧化矽、應變矽、矽鍺、摻雜或未摻雜的多晶矽、絕緣體上矽(SOI)、碳摻雜氧化矽、氮化矽、摻雜矽、鍺、砷化鎵、玻璃、或藍寶石、與其他材料。在某些實施例中，基板201是200 mm、300 mm、450 mm、或其他直徑的圓形基板。在其他實施例中，基板201是矩形基板或方形基板。在SOI用於基板201的一實施例中，基板201可進一步包括安置在矽結晶基板上的埋入介電層。
鉬層202安置在基板201上。在一實施例中，鉬層202直接安置在基板201上並接觸基板201。在其他實施例中，鉬層202可沉積在中間層(未示出)上，諸如介電層。在這些實施例中，中間層直接安置在基板201上並接觸基板201，而鉬層202安置在中間層上。鉬層202用於作為互連層以連接積體電路的多個元件或裝置。
半導體裝置200進一步包括在製造的一或多個階段期間之遮罩層203。遮罩層203可直接形成在鉬層202上或中間層(未示出)上，諸如介電層。在某些實施例中，遮罩層由不與溼式蝕刻溶液反應的材料形成。在某些實施例中，遮罩層由低硬度材料形成。在其他實施例中，遮罩層203是硬遮罩，諸如碳硬遮罩。可替代地或除了碳硬遮罩之外，遮罩層203可由其他高硬度材料形成。高硬度材料的實例包括但不限於碳化鎢(WC)、硼碳化鎢(WBC)、氮化鎢(WN)、硼化矽(SiBx )、碳化硼(BC)、非晶碳、氮化硼(BN)、氮化硼碳(BCN)、或其他類似材料。上述的遮罩層203材料可包含化合物(例如，等部分的鎢與碳的化學化合物、化學計量化合物、等等)或摻雜材料(例如，含有小百分比的碳之鎢層)。在可與本文所述的其他實施例結合的某些實施例中，遮罩層203是由光感材料形成的光阻，諸如重氮萘醌(naphtoquinone diazide (NQD))或其他合適光反應材料。在其他實施例中，
在某些實施例中，基板201是熱氧化基板。在包括熱氧化基板的實施例中，鉬層202可直接形成在基板201上。熱氧化基板包括在接觸鉬層202的表面處的氧。當如下所述之鉬層202的多個部分被移除以暴露熱氧化基板時，來自熱氧化基板的氧用於形成鈍化層(未示出)於半導體裝置200的暴露表面上。當蝕刻處理突破鉬層202時，鈍化層停止或實質上降低進一步蝕刻。例如，來自熱氧化基板的氧可與來自用以蝕刻鉬層202的含矽氣體的矽原子結合，以在半導體裝置202的多個暴露部分上形成氧化矽的鈍化層以停止蝕刻處理。雖然鈍化層在此說明為部分地藉由來自熱氧化基板的氧所形成，但是氧可來自直接在鉬層202下方的包括氧的層。
在某些實施例中，半導體裝置200可進一步包括阻障層(未示出)與低k絕緣介電層(未示出)。低k絕緣層安置在基板201上方，介於鉬層202與基板201之間。阻障層可安置在低k絕緣介電層上方，介於鉬層202與低k絕緣介電層之間。阻障層可由下列材料製造：氮化鉭(TaN)、氮化鈦(TiN)、氮化鋁(AIN)、氮化鉭矽(TaSiN)、氮化鈦矽(TiSiN)、氮化矽(SiN)、氧氮化矽(SiON)、碳化矽(SiC)、異腈矽(silicon isocyanide (SiNC))、氧碳化矽(SiOC)、或其他合適材料。再者，低k絕緣介電層可由下列材料形成：含SiO材料、含SiN材料、含SiOC材料、含SiC材料、碳基材料、或其他合適材料。
在操作104，移除遮罩層203的部分以形成鉬層202的暴露部分222，如圖2B所示。圖2B是根據一實施例之在移除安置在鉬層202上的遮罩203的部分之後，包括鉬層202的半導體裝置200的一部分的圖解剖面視圖。遮罩層203的這些部分的移除在遮罩層203中形成孔洞205，在圖2B中顯示為溝槽，藉由鉬層202的暴露部分222形成孔洞205的底部(即，圍住或部分地界定)。因此，遮罩層203的部分的移除暴露鉬層202的部分。
雖然上述用於遮罩層203的材料的使用(即，高硬度材料，諸如WC)可改善選擇性蝕刻鉬層202之上的特徵的處理，最終遮罩層203的部分或全部被移除以在裝置上形成特徵，諸如電晶體結構。
在操作106，改質鉬層202的暴露部分222。在一實施例中，氧化暴露部分222以形成氧化鉬部分223。圖2C是根據一實施例之在將鉬層202的暴露部分222氧化之後，包括鉬層202的半導體裝置200的一部分的圖解剖面視圖。
暴露部分222可藉由各種方法氧化，包括但不限於直接氧離子佈植或氧電漿摻雜。例如，佈植的氧離子可以實質上垂直路徑撞擊鉬層202的暴露表面222以穿入暴露部分222。佈植的離子可穿入暴露部分222至各種深度，取決於用於賦能予氧離子的功率與偏壓。例如，可以由約5 KeV至約30 KeV，諸如約10 KeV至約20 KeV的加速電壓賦能的氧離子，並以從約0.5E16 離子/cm2至約5E17 離子/cm2，諸如約1E16 離子/cm2至約1E17 離子/cm2的劑量佈植暴露部分222。例如，可以由10 KeV賦能的氧離子並以1E17 離子/cm2劑量佈植暴露部分222。
可藉由束線(beamline)或電漿佈植工具執行離子佈植。可按照本文的實施例有利地使用的合適商業上可獲得的處理平台是可由加州聖克拉拉的應用材料公司取得的VIISTA® PLADTM 平台。料想來自其他製造者的其他適合地設置的佈植技術平台也可按照本文的實施例使用。
在某些實施例中，在暴露部分222的氧離子佈植之後，退火半導體裝置200以形成氧化鉬部分223的多晶結構。半導體裝置200藉由各種方法退火，諸如爐退火或快速熱退火，例如燈系或雷射退火。在一實施例中，在約200 ºC與約600 ºC之間的溫度、約0.5巴至約75巴之間的壓力的水蒸汽、及約15分鐘至約2小時之間的持續期間退火裝置結構200。在某些實例中，在約250 ºC與約550 ºC之間的溫度退火裝置結構200，諸如約300 ºC與約500 ºC之間，諸如約350 ºC與約450 ºC之間。在某些實例中，在約25巴與約55巴之間的壓力退火裝置結構200，諸如約30巴與約50巴之間，諸如約35巴與約45巴之間。在某些實例中，退火裝置結構200持續約30分鐘與約1.5小時之間的期間，諸如45分鐘與75分鐘之間。在一實例中，在325 ºC與55巴持續約60分鐘的狀況下退火裝置結構200。
在某些實施例中，在高壓下並在處理氣體存在中執行熱退火，處理氣體諸如氫、氘、氟、氯、銨、或用於高壓氣體退火的其他合適氣體。在高壓程度下退火半導體裝置200促進甚至在低溫下(例如，小於350 ºC)的氧化鉬部分223的多晶結構的形成。
在操作108，從半導體裝置200移除氧化鉬部分223以形成圖案化鉬層204。圖2D是在移除氧化鉬部分223之後，包括圖案化鉬層204的基板201的一部分的圖剖面視圖。氧化鉬部分223的移除在圖案化鉬層204中形成孔洞205，在圖2D中顯示為溝槽，藉由基板201的頂表面207形成孔洞205的底部。
氧化鉬部分223可藉由對於氧化鉬為選擇性的任何合適蝕刻處理從基板201移除，包括溼式蝕刻或乾式蝕刻處理。例如，藉由以氨溶液的溼式蝕刻從基板201移除氧化鉬部分223。氨溶液對於氧化部分223為選擇性的。如此，移除氧化部分223，而非氧化的圖案化鉬層204不被氨溶液移除。氨溶液可包括氫氧化銨濃度為約26% w/w至約30% w/w，諸如約28% w/w。半導體裝置200可暴露至氨溶液，以蝕刻期望深度的氧化鉬部分223，諸如持續約2分鐘與約10分鐘之間的期間。
在可與本文所述的實例與實施例結合的另一實例中，藉由pH 10緩衝溶液的溼式蝕刻從半導體裝置200移除氧化鉬部分223。pH 10緩衝溶液包括鈉化合物，諸如四硼酸鈉或氫氧化鈉。半導體裝置200可暴露至pH 10緩衝溶液，以蝕刻期望深度的氧化鉬部分223，諸如持續約2分鐘與約10分鐘之間的期間。用於選擇性蝕刻氧化鉬部分223的氨溶液或pH 10緩衝溶液任一者的使用蝕刻氧化鉬部分223，而不損傷非氧化及圖案化鉬層204或其他材料層及半導體裝置200的裝置結構。
圖3是根據一實施例之藉由中性原子束蝕刻來圖案化諸如半導體裝置的裝置之鉬層的方法300的流程圖。類似於圖1與2中描繪的實施例，鉬層202可直接沉積在基板201上，或另一層上，諸如金屬層或介電層。根據當前實施例的鉬層202的圖案化可用於製造半導體裝置200的互連結構。圖案化方法300執行在處理腔室中，諸如電漿處理腔室或中性原子束蝕刻設備。接下來說明圖3的方法300，結合圖4A-4C中所示的視圖，其顯示在方法300的不同階段之包括鉬層202的圖2之半導體裝置200。再者，雖然方法300在下方說明關於利用以形成互連結構的鉬層202，但方法300也可用以助於不同於鉬的材料及在其他半導體裝置製造應用中。
在操作302，包括鉬層202的半導體裝置200(見圖4A)定位在電漿處理腔室中，例如蝕刻處理腔室(未示出)。半導體裝置200在製造的處理中或在製造的各種階段中可包括一或多個半導體裝置。圖4A是根據一實施例之在移除安置在基板201上的一或多層的部分之前，包括鉬層202的半導體裝置200的一部分的圖解剖面視圖。圖4A中的視圖顯示在執行圖案化處理(例如，中性束蝕刻)以改質鉬層202的部分之前的半導體裝置200。
在操作304，移除遮罩層203的部分以形成鉬層202的暴露部分222，如圖4B所示。圖4B是根據一實施例之在移除安置在鉬層202上遮罩層203的部分之後，包括鉬層202的半導體裝置200的一部分的圖解剖面視圖。遮罩層203的這些部分的移除形成遮罩層203中的孔洞205，如圖4B所示為溝槽，藉由鉬層202的暴露部分222形成孔洞205的底部(即，圍住或部分地界定)。因此，遮罩層203的部分的移除暴露鉬層202的部分。
在操作306，從半導體裝置200移除鉬層202的暴露部分以形成圖案化鉬層204。圖4C是在移除鉬層202的暴露部分222之後，包括圖案化鉬層204的半導體裝置200的一部分的圖解剖面視圖。暴露部分222的移除形成圖案化鉬層204中的孔洞205，在圖4C中顯示為溝槽，藉由基板201的頂表面形成孔洞205的底部。
在藉由圖3與4描繪的實施例中，鉬層202的暴露部分222可藉由加速原子束處理從半導體裝置200移除。可有利地按照本文所述的實施例利用的合適商業上可獲得的處理平台是可由麻薩諸塞州比爾里卡的Exogenesis公司取得的NanoAccelTM 平台。料想來自其他製造者的其他適當設置的加速原子束平台也可按照本文的實施例使用。
在一實例中，藉由氣體群集離子束(GCIB)蝕刻可移除鉬層202的暴露部分222。在鉬層202的GCIB蝕刻期間，加壓的惰性氣體可流動、膨脹、及加速朝向處理腔室內鉬層202的暴露部分222，傳遞能量至暴露部分222並致使暴露部分222的最外部原子的移除。在一實施例中，氣體群集離子束由氬氣體形成。在其他實施例中，額外氣體可與惰性氣體結合以形成氣體群集離子束，包括氧(O2 )、氮(N2 )、甲烷(CH4 )、及六氟化硫(SF6 )。
氣體群集離子束可以實質上垂直路徑引導穿過遮罩層203中的孔洞205，以穿入鉬層202的期望部分並形成圖案化鉬層204。因此，半導體裝置200上的其他裝置結構或材料層在氣體群集離子束蝕刻期間保持不受損。氣體群集離子束可加速至10 KeV至40 KeV的加速電壓，諸如15 KeV至35 KeV。例如，氣體群集離子束加速至25 KeV的加速電壓。半導體裝置200可暴露於氣體群集離子束持續任何合適劑量時間，諸如約0秒與約30秒之間，包括2-20秒之間。例如，半導體裝置200可暴露於氣體群集離子束持續6、8、10、14、或18秒的劑量時間。
在可與本文所述的實施例與實例結合的另一實例中，加速中性原子束(ANAB)蝕刻用以從半導體裝置200移除鉬層202的暴露部分222。類似於GCIB蝕刻，加速中性原子束蝕刻利用加速氣體群集離子的束，但在撞擊暴露部分222的表面之前，氣體群集被解離且電荷被移除。加速中性原子束以實質上垂直路徑引導穿過遮罩層203中的孔洞205，以便穿入鉬層202的期望部分。此外，中性原子束內的每個原子具有相對低能量，造成僅數原子層的受限表面改質，且因此顯著地降低或消除對於半導體裝置200的其他材料與層的蝕刻損傷。
加速中性原子束加速至10 KeV至40 KeV的加速電壓，諸如15 KeV至35 KeV。例如，加速中性原子束加速至25 KeV的加速電壓。半導體裝置200暴露至加速中性原子束持續任何合適劑量時間，諸如約0秒與約30秒之間，包括2-20秒之間。例如，半導體裝置200可暴露於加速中性原子束持續6、8、10、14、或18秒的劑量時間。諸如氬的惰性氣體可用於形成加速中性原子束。在某些實施例中，額外氣體可結合惰性氣體，包括氧(O2 )、氮(N2 )、甲烷(CH4 )、及六氟化硫(SF6 )。ANAB蝕刻可執行在任何合適蝕刻狀況。
圖5是根據一實施例之藉由高壓水退火來圖案化諸如半導體裝置的裝置之鉬層的方法500的流程圖。類似於圖1-4描繪的實施例，鉬層可直接沉積在基板表面上，或另一層上，諸如金屬層或介電層。根據可與本文所述的其他實施例和實例結合的當前實施例的鉬層的圖案化可用於製造裝置的互連結構。圖案化方法500執行在電漿處理腔室中，諸如蝕刻處理腔室或其他合適處理設備。雖然方法500在下方說明關於用於形成互連結構的鉬層，但方法500也可用於助於不同於鉬的材料和在其他半導體裝置製造應用中。
在操作302，包括鉬層的半導體裝置定位在電漿處理腔室中，諸如蝕刻處理腔室(未示出)。半導體裝置可包括在製造的處理中的一或多個半導體裝置。半導體裝置進一步包括基板、安置在基板上的鉬層、及遮罩層，例如，類似於關於圖2與圖4所述的基板201、鉬層202、及遮罩層203。半導體裝置也可包括安置在基板上的其他材料層，諸如阻障層或低k絕緣層。
在操作504，移除遮罩層的部分以形成鉬層的暴露部分。遮罩層的部分的移除形成遮罩層中的孔洞205，藉由鉬層的暴露部分形成孔洞205的底部。遮罩層的部分的移除暴露鉬層的部分。
在操作506，半導體裝置暴露於高壓水退火(HPWA)處理以從半導體裝置移除鉬層的暴露部分。雖然方法500說明利用水蒸汽以退火半導體裝置的高壓水退火，但料想到其他氣體可用於在高壓下退火半導體裝置。例如，在高壓下可使用氫、氘、氟、氯、銨、或其他合適氣體退火半導體裝置。在另一實例中，可使用包括氫、氘、氟、氯、銨、及其他合適氣體的氣體組合來退火半導體裝置。
在操作506，藉由從壓力腔室至處理腔室提供水蒸汽加壓處理腔室，接著熱退火裝置並藉由排空水蒸汽減壓處理腔室。熱退火執行在約250 ºC與約450 ºC之間的溫度，諸如約300 ºC與約400 ºC之間。例如，熱退火執行在約325 ºC與約375 ºC之間的溫度。此外，處理腔室加壓至約10巴與約75巴之間的壓力，諸如約20巴與約60巴之間。例如，處理腔室加壓至約30巴與約50巴之間的壓力。裝置暴露於高壓水蒸汽退火移除鉬層的暴露部分，因此形成圖案化鉬層，而不損傷其他裝置結構或材料層。
本發明的實施例包括圖案化裝置的金屬層以在互連層中形成特徵的方法，作為用於製造裝置的互連結構的處理的部分。具體地，揭示的方法說明改善選擇性之圖案化鉬層的處理。圖案化鉬層中增加的選擇性能夠形成互連結構及其他金屬層，而沒有關於圖案化高硬度材料的缺點，包括大的下切及對於堆疊在半導體裝置內的其他層與結構的損傷。因此，本文提供的方法使得鉬及其他高硬度材料對於諸如互連結構的裝置結構為變得更加符合期望並可實行的材料。
儘管前述關於發明的實施例，但在不背離本發明的基本範疇可構思出本發明的其他與進一步實施例，且本發明的範疇由之後的申請專利範圍所界定。
100:方法 102,104,106,108:操作 200:半導體裝置 201:基板 202:鉬層 203:遮罩層 204:圖案化鉬層 205:孔洞 207:頂表面 222:暴露部分 223:氧化鉬部分 300:方法 302,304,306:操作 500:方法 502,504,506:操作
為了可詳細理解本發明的上述特徵，藉由參照實施例，其中某些實施例繪示在隨附圖式中，可獲得簡短總結於上之本發明的更具體的說明。然而，將注意到隨附圖式僅繪示範例實施例且因而不當作限制本發明的範疇，且本發明的範疇可容許其他等效實施例。
圖1繪示根據本發明的一實施例之圖案化諸如半導體裝置的裝置之鉬互連層的方法的流程圖。
圖2A繪示根據本發明的一實施例之在移除基板上的一或多個層的多個部分之前，包括鉬層的半導體裝置的一部分的圖解剖面視圖。
圖2B繪示根據本發明的一實施例之在已經改質基板上的一或多個層的多個部分之後，包括鉬層的半導體裝置的一部分的圖解剖面視圖。
圖2C繪示根據本發明的一實施例之在已經改質基板上的一或多個層的多個部分之後，包括鉬層的半導體裝置的一部分的圖解剖面視圖。
圖2D繪示根據本發明的一實施例之在已經移除基板上的一或多個層的多個部分之後，包括鉬層的半導體裝置的一部分的圖解剖面視圖。
圖3繪示根據本發明的一實施例之圖案化諸如半導體裝置的裝置之鉬互連層的方法的流程圖。
圖4A繪示根據本發明的一實施例之在已經移除基板上的一或多個層的多個部分之前，包括鉬層的半導體裝置的一部分的圖解剖面視圖。
圖4B繪示根據本發明的一實施例之在已經移除基板上的一或多個層的多個部分之後，包括鉬層的半導體裝置的一部分的圖解剖面視圖。
圖4C繪示根據本發明的一實施例之在已經移除基板上的一或多個層的進一步多個部分之後，包括鉬層的半導體裝置的一部分的圖解剖面視圖。
圖5繪示根據本發明的一實施例之圖案化諸如半導體裝置的裝置之鉬互連層的方法的流程圖。
為了易於理解，儘可能已使用相同元件符號指代圖式中共通的相同元件。料想一實施例的元件與特徵可有利地併入其他實施例中，而不需進一步闡明。
國內寄存資訊 (請依寄存機構、日期、號碼順序註記) 無
國外寄存資訊 (請依寄存國家、機構、日期、號碼順序註記) 無
100:方法
102,104,106,108:操作

Claims (20)

  1. 一種形成一金屬互連層的方法，包含以下步驟：在一基板上形成一鉬層；在該鉬層上方形成一遮罩層；圖案化該遮罩層以暴露該鉬層的多個部分；以氧改質該鉬層的該等暴露部分，以形成該鉬層的多個氧化鉬部分；及從該基板移除該等氧化鉬部分。
  2. 如請求項1所述之方法，其中該鉬層的該等暴露部分藉由氧電漿摻雜而改質。
  3. 如請求項1所述之方法，其中該鉬層的該等暴露部分藉由直接氧佈植而改質。
  4. 如請求項3所述之方法，其中以約20KeV至約30KeV的一電壓執行該直接氧佈植。
  5. 如請求項1所述之方法，其中該鉬層的該等氧化鉬部分藉由一乾式蝕刻處理而移除。
  6. 如請求項1所述之方法，其中該鉬層的該等氧化鉬部分藉由一溼式蝕刻處理而移除。
  7. 如請求項6所述之方法，其中執行該溼式蝕刻持續約2分鐘與約10分鐘之間的一期間。
  8. 如請求項6所述之方法，其中藉由一pH 10緩衝溶液溼蝕刻該鉬層的該等氧化鉬部分。
  9. 如請求項8所述之方法，其中該緩衝溶液包含四硼酸鈉與氫氧化鈉。
  10. 如請求項7所述之方法，其中藉由一氨溶液溼蝕刻該鉬層的該等氧化鉬部分。
  11. 如請求項10所述之方法，其中該氨溶液包含一濃度為約28% w/w至約30% w/w的氫氧化銨。
  12. 如請求項1所述之方法，進一步包含以下步驟：在藉由蝕刻移除該鉬層的該等氧化鉬部分之前，退火該基板。
  13. 如請求項12所述之方法，其中該退火執行在約250℃與約550℃之間的一溫度及約25巴與約55巴之間的一壓力。
  14. 一種在一圖案化基板上形成一金屬互連層的方法，包含以下步驟：在該圖案化基板上形成一鉬層；在該鉬層上形成一遮罩層，該遮罩層圖案化以暴露該鉬層的多個部分；及將該圖案化基板暴露於一氣體群集離子束以移除該鉬層的該等暴露部分。
  15. 如請求項14所述之方法，其中該氣體群集離子束是藉由離子化及加速包含氬的一氣體群集所形 成的。
  16. 如請求項15所述之方法，其中以約20KeV至30KeV的一電壓加速該氣體群集。
  17. 如請求項15所述之方法，其中該氣體群集離子束進一步包含選自由氧、氮、六氟化硫及甲烷所構成之群組中之一或多種額外氣體。
  18. 一種在一圖案化基板上形成一金屬互連層的方法，包含以下步驟：在該圖案化基板上形成一鉬層；在該鉬層上形成一遮罩層，該遮罩層圖案化以暴露該鉬層的多個部分；及將該圖案化基板暴露於一加速中性原子束以移除該鉬層的該等暴露部分。
  19. 如請求項18所述之方法，其中該圖案化基板以0秒至約25秒的一劑量時間暴露於該中性原子束。
  20. 一種在一基板上圖案化一金屬互連層的方法，該方法包含以下步驟：在該基板上形成一鉬互連層；在該鉬互連層上形成一遮罩層；圖案化該遮罩層以暴露該鉬互連層的多個部分；及將該基板暴露於在約25巴與約55巴之間的一分壓 及約250℃與約550℃之間的一溫度的氣相H2O，以移除該鉬互連層的該等暴露部分。
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Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7570529B2 (ja) * 2021-02-24 2024-10-21 株式会社Ｓｃｒｅｅｎホールディングス モリブデンをエッチングする方法
US12243769B2 (en) 2022-05-03 2025-03-04 Nanya Technology Corporation Method for preparing semiconductor device structure using nitrogen-containing pattern
US20240038541A1 (en) * 2022-07-27 2024-02-01 Applied Materials, Inc. Methods for removing molybdenum oxides from substrates
JP2024018603A (ja) * 2022-07-29 2024-02-08 株式会社Ｓｃｒｅｅｎホールディングス 基板処理方法および基板処理装置
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWM286071U (en) * 2005-10-26 2006-01-21 Yun-Huei Wang Improved structure for distillation wine making machine
TW200706700A (en) * 2005-08-08 2007-02-16 Lg Philips Lcd Co Ltd Etchant composition, methods of patterning conductive layer and manufacturing flat panel display device using the same
TW200925324A (en) * 2007-12-07 2009-06-16 Nanya Technology Corp Etchant for metal alloy having hafnium and molybdenum, etching method using the etching solution and application therof
US20140273490A1 (en) * 2013-03-14 2014-09-18 Applied Materials, Inc. Method for improving cd micro-loading in photomask plasma etching
TW201841250A (zh) * 2017-01-20 2018-11-16 日商東京威力科創股份有限公司 電漿處理裝置

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04111312A (ja) * 1990-08-31 1992-04-13 Mitsubishi Electric Corp 微細加工装置及び方法
US5350484A (en) 1992-09-08 1994-09-27 Intel Corporation Method for the anisotropic etching of metal films in the fabrication of interconnects
JPH0897214A (ja) * 1994-09-29 1996-04-12 Nec Corp 半導体装置の製造方法
JPH08232083A (ja) * 1995-02-24 1996-09-10 Fuji Electric Co Ltd 表面弾性波デバイスの製造方法
US5972235A (en) * 1997-02-28 1999-10-26 Candescent Technologies Corporation Plasma etching using polycarbonate mask and low pressure-high density plasma
US8293430B2 (en) * 2005-01-27 2012-10-23 Applied Materials, Inc. Method for etching a molybdenum layer suitable for photomask fabrication
US20100320457A1 (en) * 2007-11-22 2010-12-23 Masahito Matsubara Etching solution composition
JP2010056541A (ja) * 2008-07-31 2010-03-11 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
JP2010165732A (ja) * 2009-01-13 2010-07-29 Hitachi Displays Ltd エッチング液及びこれを用いたパターン形成方法並びに液晶表示装置の製造方法
US8557710B2 (en) * 2011-09-01 2013-10-15 Tel Epion Inc. Gas cluster ion beam etching process for metal-containing materials
US20130335383A1 (en) * 2012-06-19 2013-12-19 Qualcomm Mems Technologies, Inc. Removal of molybdenum
CN105522684B (zh) * 2014-12-25 2018-11-09 比亚迪股份有限公司 一种金属-树脂复合体及其制备方法和一种电子产品外壳
EP3268505B1 (en) * 2015-03-11 2022-05-04 Exogenesis Corporation Method for neutral beam processing based on gas cluster ion beam technology
US9449843B1 (en) * 2015-06-09 2016-09-20 Applied Materials, Inc. Selectively etching metals and metal nitrides conformally

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200706700A (en) * 2005-08-08 2007-02-16 Lg Philips Lcd Co Ltd Etchant composition, methods of patterning conductive layer and manufacturing flat panel display device using the same
TWM286071U (en) * 2005-10-26 2006-01-21 Yun-Huei Wang Improved structure for distillation wine making machine
TW200925324A (en) * 2007-12-07 2009-06-16 Nanya Technology Corp Etchant for metal alloy having hafnium and molybdenum, etching method using the etching solution and application therof
US20140273490A1 (en) * 2013-03-14 2014-09-18 Applied Materials, Inc. Method for improving cd micro-loading in photomask plasma etching
TW201841250A (zh) * 2017-01-20 2018-11-16 日商東京威力科創股份有限公司 電漿處理裝置

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