TWI721756B - Array substrate, display panel and display device - Google Patents

Abstract

An array substrate defines a display area and a camera hole area surrounded by the display area. The camera hole area includes a light transmitting area and a routing area surrounding the light transmitting area. The array substrate includes a substrate, a first conductive layer, and a second conductive layer. The first conductive layer includes a plurality of first lines surrounding the light-transmitting area. The second conductive layer includes a plurality of second lines surrounding the light-transmitting area. The first conductive layer further includes a plurality of first capacitance compensation patterns. Each first capacitance compensation pattern is between adjacent two first lines. Along a thickness direction of the array substrate, a projection of each first capacitance compensation pattern on the substrate overlaps a projection of at least one second line. A display panel and a display device are also provided.

Description

Array substrate, display panel and display device

The present invention relates to the field of display technology, and in particular to an array substrate, a display panel using the array substrate, and a display device using the display panel.

Display devices such as mobile phones, tablet computers, etc., with the increasing demand for diversified functions of users, often need to combine components with other functions. Among them, display devices incorporating camera modules have been widely produced and applied.

Taking an array substrate including a plurality of wires in a display device as an example, the array substrate needs to be provided with a camera hole area that exposes the camera module. Of course, the camera hole area will affect the arrangement of the wires on the array substrate and even affect the performance of the electronic device.

One aspect of the present invention provides an array substrate, the array substrate defines a display area and a camera hole area surrounded by the display area, the camera hole area includes a light-transmitting area and a wiring area surrounding the light-transmitting area, The array substrate includes: a base; The first conductive layer is located on the substrate, the first conductive layer includes a plurality of first wires, each of the first wires is arranged around the light-transmitting area; the second conductive layer is located on the first conductive Layer away from the substrate, the second conductive layer includes a plurality of second wires, each of the second wires is arranged around the light-transmitting area; wherein, the first conductive layer also includes the A plurality of first capacitance compensation patterns arranged at intervals of the first wire insulation, each of the first capacitance compensation patterns is located between two adjacent first wires; along the thickness direction of the array substrate, each of the first capacitance compensation patterns The projection of the first capacitance compensation pattern on the substrate at least overlaps the projection of one of the second conductive lines.

In the above-mentioned array substrate, due to the arrangement of the first capacitance compensation pattern, the amount of capacitive coupling of the second wire overlapping with the first capacitance compensation pattern increases and the coupling voltage decreases, and the influence of the coupling voltage on the original voltage of the second wire is weakened. Therefore, the phenomenon that the wirings in the camera hole area of the array substrate are closely arranged, which results in a large parasitic capacitance between adjacent wirings, which affects the display effect.

Another aspect of the present invention provides a display panel including a color filter substrate, a liquid crystal layer, and an array substrate, the liquid crystal layer is sandwiched between the color filter substrate and the array substrate, and the array substrate is The above-mentioned array substrate.

The display panel uses the above-mentioned array substrate, which also improves the tight arrangement of the wiring in the camera hole area, resulting in a phenomenon that the parasitic capacitance between adjacent wirings is larger, which affects the display.

Another aspect of the present invention provides a display device, which includes: the above-mentioned display panel; a backlight module, the backlight module is located on the side of the display panel away from its display surface, the backlight module is defined through the A mounting hole of the backlight module, the mounting hole is aligned with the light-transmitting area; and The camera module is installed in the mounting hole and collects image information through the light-transmitting area.

The display device uses the above-mentioned display panel, which also improves the tight arrangement of the wiring in the camera hole area, which results in a larger parasitic capacitance between adjacent wirings, which affects the display.

10: Array substrate

A: Display area

B: Camera hole area

B1: Transmissive area

B2: Wiring area

X: first direction

Y: second direction

L1: the first axis of symmetry

L2: second axis of symmetry

AL: left area

AR: Right area

AT: Upper side area

AB: Lower area

12: Scan line

122: first scan line

124: second scan line

14: Data cable

142: The first data line

144: second data line

144a: auxiliary data line

144b: data line lead

146: third data line

148: The fourth data line

16: sub-pixel

162: Thin Film Transistor

GE: Gate

SE: Source

DE: Dip pole

164: pixel electrode

11: Base

13: The first conductive layer

120: first wire

110: The first capacitance compensation pattern

15: second conductive layer

140: second wire

130: second capacitance compensation pattern

17: Insulation layer

19: Via

20: Color filter substrate

30: liquid crystal layer

40: display panel

40a: display surface

50: camera module

60: Backlight module

60a: light emitting side

62: mounting hole

100: display device

FIG. 1 is a schematic top view of an array substrate according to an embodiment of the invention.

FIG. 2 is a schematic diagram of the wiring arrangement of the array substrate in FIG. 1.

FIG. 3 is a schematic cross-sectional view of the auxiliary data line and the data line lead in FIG. 2 at the connection position.

Fig. 4 is an enlarged schematic diagram of position IV in Fig. 2.

FIG. 5 is a schematic diagram of the projection of the first conductive layer of the array substrate in FIG. 2 on the base.

FIG. 6 is a schematic diagram of the projection of the second conductive layer of the array substrate in FIG. 2 on the base.

Fig. 7 is an enlarged schematic diagram of the position VII in Fig. 2.

FIG. 8 is an equivalent circuit diagram when the second compensation capacitor pattern and four first wires are stacked up and down in an embodiment of the present invention.

FIG. 9 is a schematic cross-sectional view of a display panel according to an embodiment of the invention.

FIG. 10 is a schematic cross-sectional view of a display device according to an embodiment of the invention.

As shown in FIG. 1, the array substrate 10 of the embodiment of the present invention defines a display area A and a camera hole area B surrounded by the display area A. The camera aperture area B defines a light-transmitting area B1 and a surrounding light-transmitting area B1 The routing area B2. The camera aperture area B is a light-transmitting area. In this embodiment, the camera aperture area B and the light-transmitting area B1 are approximately circular, and the wiring area B2 is a circular ring.

In other embodiments, the camera hole area B can also have other shapes. For example, the camera hole area B may also be elliptical, polygonal, or the like.

As shown in FIG. 2, the wiring area B2 has a first symmetry axis L1 and a second symmetry axis L2. Along the first direction X, the wiring area B2 is distributed axially symmetrically with respect to the second symmetry axis L2. Along the second direction Y, the wiring area B2 is distributed axially symmetrically with respect to the first symmetry axis L1. The second direction Y crosses the first direction X.

As shown in FIG. 2, along the first direction X, the display area A is divided by the second axis of symmetry L2 into a left area AL and a right area AR located on opposite sides of the second axis of symmetry L2, respectively. Along the second direction Y, the display area A is divided by the first symmetry axis L1 into an upper area AT and a lower area AB located on opposite sides of the first symmetry axis L1, respectively. That is, the left area AL and the right area AR constitute the entire display area A. The upper area AT and the lower area AB also constitute the entire display area A. The left area AL, the upper area AT, and the lower area AB all have an overlap area, and the right area AR domain has an overlap area between the upper area AT and the lower area AB. In one embodiment, the second direction Y is perpendicular to the first direction X.

As shown in FIG. 2, the array substrate 10 includes a base 11 and scan lines 12 and data lines 14 on the base 11.

As shown in FIG. 2, the scan line 12 includes a plurality of first scan lines 122. The plurality of first scan lines 122 extend across the wiring area B2 and are sequentially spaced along the second direction Y. A part of the first scan line 122 extends in the upper area AT and the wiring area B2, and another part of the first scan line 122 extends in the lower area AB and the wiring area B2. The plurality of first scan lines 122 are distributed axially symmetrically about the first symmetry axis L1. The portion of each first scan line 122 in the wiring area B2 is distributed axially symmetrically with respect to the second symmetry axis L2. Every The first scan line 122 extends along the first direction X in the left area AL to the routing area B2, and extends in the routing area B2 around the outer contour of the light-transmitting area B1, and then continues along the first direction in the right area AR X extension. That is, the arrangement of each first scan line 122 bypasses the light-transmitting area B1, crosses the wiring area B2, and extends along the first direction X in the display area A. Among them, the first scan line 122 located in the upper area AT and the wiring area B2 is bent and extended along the upper half of the transparent area B1, and the first scan line 122 located in the lower area AB and the wiring area B2 extends along the transparent area. The lower half of the light zone B1 is bent and extended.

Each first scan line 122 includes a straight line section extending along the first direction X in the left area AL, and a curved section extending around the outer contour of the light-transmitting area B1 in the routing area B2 (circle in FIG. 2). Arc) and a straight line segment extending in the first direction X in the right area AR. Wherein, the length of the curved portion of the first scan line 122 changes with the distance from the first axis of symmetry L1. The first scan line 122 that is closer to the first axis of symmetry L1 has a longer curve portion; the first scan line 122 that is farther away from the first axis of symmetry L1 has a shorter curve portion. In one embodiment, the plurality of first scan lines 122 are arranged at equal intervals.

As shown in FIG. 2, the data line 14 includes a plurality of first data lines 142 extending across the wiring area B2. The plurality of first data lines 142 are sequentially spaced along the first direction X. A part of the first data line 142 extends in the left area AL and the wiring area B2, and another part of the first data line 142 extends in the right area AR and the wiring area B2. The plurality of first data lines 142 are distributed axially symmetrically with respect to the second symmetry axis L2.

The portion of each first data line 142 in the wiring area B2 is axially symmetrical about the first symmetry axis L1. Each first data line 142 extends in the upper area AT along the second direction Y to the wiring area B2, and then extends in the wiring area B2 around the outer contour of the light-transmitting area B1, and then continues along the first data line in the lower area AB. Extend in two directions Y. That is, the arrangement of each first data line 142 bypasses the light-transmitting area B1, crosses the wiring area B2, and extends in the second direction Y in the display area A. Among them, located in the left area AL and routing area The first data line 142 in B2 bends and extends along the left half of the light-transmitting area B1, and the first data line 142 located in the right area AR and the wiring area B2 is bent and extends along the right half of the light-transmitting area B1.

Each first data line 142 includes a straight line portion extending in the second direction Y in the upper region AT, and a curved portion extending around the outer contour of the light-transmitting area B1 in the routing area B2 (circle in FIG. 2). Arc) and a straight line segment extending in the second direction Y in the lower region AB. The length of the curved portion of the first data line 142 changes with its distance from the second axis of symmetry L2. The first data line 142 that is closer to the second axis of symmetry L2 has a longer curve portion; the first data line 142 that is farther away from the first axis of symmetry L1 has a shorter curve portion. In one embodiment, the plurality of first data lines 142 are arranged at equal intervals.

As shown in FIG. 2, the data line 14 further includes a plurality of second data lines 144. The plurality of second data lines 144 extend across the wiring area B2. A part of the second data line 144 extends in the left area AL and the wiring area B2, and a part of the second data line 144 extends in the right area AR and the wiring area B2. The plurality of second data lines 144 are distributed axially symmetrically with respect to the second symmetry axis L2. The plurality of first data lines 142 and the plurality of second data lines 144 are arranged alternately in sequence along the first direction X as a first data line 142 and a second data line 144.

Each second data line 144 extends along the second direction Y in the upper area AT to the wiring area B2, and then bends and extends around the outer contour of the light-transmitting area B1 in the wiring area B2, and then continues along the lower area AB The second direction Y extends. That is, the arrangement of each second data line 144 bypasses the light-transmitting area B1, crosses the wiring area B2, and extends in the second direction Y in the display area A. The second data line 144 located in the left area AL and the wiring area B2 bends and extends along the left half of the light-transmitting area B1, and the second data line 144 located in the right area AR and the wiring area B2 is along the light-transmitting area B1 The right half is bent and extended.

Each second data line 144 includes a straight line section extending in the second direction Y in the upper area AT, and a curved section extending around the outer contour of the light-transmitting area B1 in the routing area B2 (circle in FIG. 2). Arc) and a straight line segment extending in the second direction Y in the lower region AB.

The curve portion defining each second data line 144 is an auxiliary data line 144a. Each auxiliary data line 144a is distributed axially symmetrically about the first symmetry axis L1. Each first data line 142 is located between two adjacent auxiliary data lines 144a, and there is an auxiliary data line 144a between two adjacent first data lines 142. The curved portions of the plurality of auxiliary data lines 144a and the plurality of first data lines 142 are one auxiliary data line 144a and one first data line 142 alternately arranged in the first direction X. The length of the plurality of auxiliary data lines 144a changes with the distance from the second axis of symmetry L2. The length of the auxiliary data line 144a that is closer to the second axis of symmetry L2 is longer; the length of the auxiliary data line 144a that is farther from the first axis of symmetry L1 is shorter.

The straight line segment defining each second data line 144 is a data line lead 144b. The plurality of data line leads 144b and the linear segments of the plurality of first data lines 142 are alternately arranged in the first direction X in sequence. In the second direction Y, the first scan line 122 is located on the side of the auxiliary data line 144a away from the light-transmitting area B1. The projection of each data line lead 144 b on the substrate 11 overlaps with all the first scan lines 122.

As shown in FIG. 3, the array substrate 10 includes a base 11, a first conductive layer 13 located on a surface of the base 11, a second conductive layer 15 located on the side of the first conductive layer 13 away from the base 11, and a first conductive layer 13 and the insulating layer 17 between the second conductive layer 15. The insulating layer 17 may be one layer or multiple layers. The first scan line 122 and the auxiliary data line 144a are defined by the first conductive layer 13. The first data line 142 and the data line lead 144b are defined by the second conductive layer 15. The auxiliary data line 144a and the data line lead 144b are The via 19 is electrically connected. That is, the auxiliary data line 144a and the first data line 142 are respectively located in different conductive layers.

Please refer to FIG. 2 again, the projection of each first data line 142 on the substrate 11 is located between two adjacent auxiliary data lines 144a, and there is an auxiliary data line 144a between the two adjacent first data lines 142 . Compared with the arrangement of adjacent conductive lines (for example, the first data line 142 and the second data line 144) in the same conductive layer, the adjacent conductive lines (for example, the first data line 142 and the second data line 144) in the wiring area B2 The auxiliary data lines 144a) of the two data lines 144 are located in different conductive layers, so that the wiring can be arranged more closely without short circuit, which is beneficial to reduce the wiring area of the wiring area B2.

Please continue to refer to FIG. 2, the data line 14 further includes a plurality of third data lines 146. The plurality of third data lines 146 extend across the wiring area B2 and are located on the side of the first data line 142 and the second data line 144 away from the light-transmitting area B1. The plurality of third data lines 146 are sequentially spaced along the first direction X. A part of the third data line 146 extends in the left area AL and the wiring area B2, and another part of the third data line 146 extends in the right area AR and the wiring area B2. The plurality of third data lines 146 are all distributed axially symmetrically about the second symmetry axis L2.

The portion of each third data line 146 in the wiring area B2 is axially symmetrical about the first symmetry axis L1. Each third data line 146 extends along the second direction Y in the upper area AT to the wiring area B2, and then extends in the wiring area B2 around the outer contour of the light-transmitting area B1 and then continues along the first area in the lower area AB. Extend in two directions Y. That is, the arrangement of each third data line 146 bypasses the light-transmitting area B1, crosses the wiring area B2, and extends in the second direction Y in the display area A. Among them, the first data line 142 located in the left area AL and the wiring area B2 extends along the left half of the light-transmitting area B1, and the first data line 142 located in the right area AR and the wiring area B2 extends along the light-transmitting area. The right half of the area B1 is bent and extended.

Each third data line 146 includes a straight line section extending in the second direction Y in the upper region AT, and a curved section extending around the outer contour of the light-transmitting region B1 in the routing region B2 (circle in FIG. 2). Arc) and a straight line segment extending in the second direction Y in the lower region AB. The length of the curved portion of the third data line 146 changes with the distance from the second axis of symmetry L2. The third data line 146 that is closer to the second axis of symmetry L2 has a longer curve portion; the third data line 146 that is farther away from the first axis of symmetry L1 has a shorter curve portion. In one embodiment, the plurality of third data lines 146 are arranged at equal intervals.

As shown in FIG. 2, the data line 14 extending across the wiring area B2 includes a first data line 142, a second data line 144, and a third data line 146. Along the first direction X, the arrangement of the data lines 14 in the routing area B2 is: a plurality of third data lines 146 (close to the left area AL), alternately arranged second data lines 144 and first data lines 142 , A plurality of third data lines 146 (near the right area AR). Among them, the data line 14 closest to the light-transmitting area B1 may be the first data line 142 or the second data line 144.

In one embodiment, the third data line 146 is defined by the second conductive layer 15. That is, the first data line 142, the data line lead 144b of the second data line 144, and the third data line 146 are all defined and formed with the same conductive layer. The auxiliary data line 144 a of the second data line 144 is formed by the first conductive layer 13 different from the second conductive layer 15. Preferably, the second data line 144 is adjacent to the third data line 146. In this way, in the data line 14 extending across the wiring area B2, at the junction of the different types of data lines 14, different conductive layers are used to make the wires more closely arranged without causing short circuits, which further reduces The difference between the inner and outer diameters of the small routing area B2.

Please continue to refer to FIG. 2, the data line 14 further includes a plurality of fourth data lines 148. The fourth data line 148 extends in the display area A, but does not extend to the wiring area B2. Part of the fourth data line 148 is located in the left area AL, and part of the fourth data line 148 is located in the right area AR. In the left area AL, the plural The four data lines 148 are sequentially arranged at intervals, and each fourth data line 148 extends along the second direction Y. In the right area AR, a plurality of fourth data lines 148 are sequentially arranged at intervals, and each fourth data line 148 extends along the second direction Y. In the lower area AB (or in the upper area AT), along the first direction X, the arrangement of the first data line 142, the second data line 144, the third data line 146, and the fourth data line 148 are: plural A fourth data line 148, a plurality of third data lines 146, a first data line 142 and a second data line 144 alternately arranged, a plurality of third data lines 146, and a plurality of fourth data lines 148.

Please continue to refer to FIG. 2, the scan line 12 also includes a plurality of second scan lines 124 only corresponding to the display area A. The second scan line 124 only extends in the display area A, and does not extend to the wiring area B2. Part of the second scan line 124 is located in the upper area AT, and part of the second scan line 124 is located in the lower area AB. In the upper area AT, a plurality of second scan lines 124 are sequentially arranged at intervals, and each second scan line 124 extends along the first direction X. In the lower region AB, a plurality of second scan lines 124 are sequentially arranged at intervals, and each second scan line 124 extends along the first direction X. Along the second direction Y, the arrangement of the first scan lines 122 and the second scan lines 124 are: a plurality of second scan lines 124 located in the upper area AT, a plurality of first scan lines 122 located in the upper area AT, A plurality of first scan lines 122 in the lower area AB and a plurality of second scan lines 124 in the lower area AB.

In one embodiment, the auxiliary data lines 144 a of the plurality of first scan lines 122, the plurality of second scan lines 124, and the plurality of second data lines 144 are defined by the first conductive layer 13. The plurality of first data lines 142, the data line leads 144 b of the plurality of second data lines 144, the plurality of third data lines 146 and the plurality of fourth data lines 148 are defined by the second conductive layer 15. That is, all the scan lines 12 are formed by the first conductive layer 13. Among all the data lines 14, the auxiliary data line 144 a excluding the second data line 144 is formed of the second conductive layer 15. The traces formed by the first conductive layer 13 (the first scan line 122, the second scan line 124, and the auxiliary data line 144a) are defined as the first conductive line 120. Define the traces formed by the second conductive layer 15 (the first A data line 142, a data line lead 144b, a third data line 146, and a fourth data line 148) are the second conductive lines 140.

Since the adjacent conductive lines (eg, the auxiliary data line 144a of the first data line 142 and the second data line 144, the third data line 146 and the auxiliary data line 144a of the second data line 144) are prepared by using different conductive layers , So that the adjacent wires can be arranged more densely without short circuit, which is beneficial to the narrow design of the wiring area B2. In addition, the auxiliary data line 144a is closer to the light-transmitting area B1 than the first scan line 122 made of the same conductive layer, without affecting the wiring of the first scan line 122.

Please refer to FIG. 2 again, all the scan lines 12 and all the data lines 14 are arranged to avoid the B domain of the camera hole area, so that the B domain of the camera hole area is transparent. At least a part of the first scan line 122, the first data line 142, the second data line 144, and the third data line 146 form a ring shape surrounding the light-transmitting area B1. All the portions of the scan lines 12 in the display area A extend along the first direction X, and all the portions of the data lines 14 in the display area A extend along the second direction Y. The projection of each data line 14 on the substrate 11 overlaps all the scan lines 12 up and down.

In one embodiment, the camera hole area B is not used for displaying images. Any two adjacent ones of the plurality of first scan lines 122 and the plurality of second scan lines 124 are connected to any of the plurality of first data lines 142, the plurality of second data lines 144, the plurality of third data lines 146, and the plurality of fourth data lines 148 Two adjacent two intersect in the display area A to define a sub-pixel 16.

As shown in FIG. 4, each sub-pixel 16 includes a thin film transistor 162 and a pixel electrode 164. The thin film transistor 162 includes a gate electrode GE, a source electrode SE, and a drain electrode DE. The gate GE is electrically connected to one of the first scan line 122 and the second scan line 124. The source electrode SE is electrically connected to one of the first data line 142, the second data line 144, the third data line 146, and the fourth data line 148, and the drain electrode DE is electrically connected to the pixel electrode 164.

It can be understood that although the arrangement of the scan lines 12 and the data lines 14 on the array substrate 10 is exemplarily described in this embodiment, it is not limited to the scan lines 12 and the data lines 14. In other embodiments, It is the arrangement of other wires on the array substrate 10 where the camera hole area B is defined. For example, it may be the arrangement of touch wires on the array substrate 10 as a touch panel avoiding the camera hole area B.

In one embodiment, the material of the substrate 11 is a transparent hard material, such as glass, quartz, or plastic. In other embodiments, the substrate 11 may be made of a flexible material, such as polyether ether (PES), polyethylene naphthalate (PEN), polyethylene (PE), polyimide (PI), One or more of polyvinyl chloride (PVC) and polyethylene terephthalate (PET). The material of the first conductive layer 13 and the second conductive layer 15 can be selected from at least aluminum, silver, gold, chromium, copper, indium, manganese, molybdenum, nickel, neodymium, palladium, platinum, titanium, tungsten, and zinc. One kind. The material of the insulating layer 17 can be selected from silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), and the like.

FIG. 5 is a schematic diagram of the projection of the first conductive layer 13 of the array substrate 10 on the base 11 in FIG. 2. As shown in FIG. 5, the first conductive layer 13 further includes a plurality of first capacitance compensation patterns 110 which are insulated and spaced apart from the first wire 120. Each of the first capacitance compensation patterns 110 is located between two adjacent first conductive lines 120. A part of the first capacitance compensation pattern 110 is located between the two adjacent first scan lines 122 and is located at a position where the wiring area B2 is close to the display area A. A part of the first capacitance compensation pattern 110 is located between two adjacent auxiliary data lines 144a and is located at a position of the wiring area B2 close to the light-transmitting area B1. In FIG. 5, the shape of the first capacitance compensation pattern 110 is approximately a hollow rectangle. In other embodiments, the shape of the first capacitance compensation pattern 110 is not limited.

FIG. 6 is a schematic diagram of the projection of the second conductive layer 15 of the array substrate 10 on the base 11 in FIG. 2. As shown in FIG. 6, the second conductive layer 15 further includes a plurality of second capacitance compensation patterns 130 arranged at an insulated interval from the second wire 140. Each of the second capacitance compensation patterns 130 is located at two adjacent Between the second wires 140. In the alignment area B2, one or a plurality of second data lines can be set between any two adjacent ones of the plurality of first data lines 142, the plurality of auxiliary data lines 144a, the plurality of third data lines 146, and the plurality of fourth data lines 148. Capacitance compensation pattern 130. That is, aligning the wiring area B2, between any two adjacent second conductive lines 140 (eg, between two adjacent first data lines 142, auxiliary data line 144a and the adjacent first data line 142 or between the third data line 146, between two adjacent third data lines 146, between the third data line 146 and the fourth data line 148 adjacent thereto) one or a plurality of second capacitance compensations can be set Pattern 130. The plurality of second capacitance compensation patterns 130 are located on the side of the wiring area B2 close to the display area A and approximately surround the light-transmitting area B1 in a circle.

In FIG. 6, the shape of the second capacitance compensation pattern 130 is approximately a hollow rectangle. In other embodiments, the second capacitance compensation pattern 130 may have other shapes, and among the plurality of second conductive lines 140, the second capacitance compensation pattern 130 may be partially disposed between two adjacent second conductive lines 140, and another part of the second conductive lines 140 may be provided with the second capacitance compensation pattern 130. The second capacitance compensation pattern 130 is not provided between two adjacent second conductive lines 140.

Fig. 7 is an enlarged schematic diagram of the position VII in Fig. 2. As shown in FIG. 7, along the thickness direction of the array substrate 10, the projection of each of the first capacitance compensation patterns 110 on the substrate 11 overlaps with the projection of at least one of the second conductive lines 140 for The signal compensation between adjacent first wires 120 is realized. Along the thickness direction of the array substrate 10, the projection of each of the second capacitance compensation patterns 130 on the substrate 11 overlaps with the projection of at least one of the first conductive lines 120, so as to realize the adjacent second Signal compensation between wires 140.

FIG. 8 is an equivalent circuit diagram when the second compensation capacitor pattern and the four first conductive lines 120 are stacked up and down in an embodiment of the present invention. As shown in FIG. 8, the parasitic capacitance between adjacent first wires 120 is C1, the original capacitance of the first wires 120 is Cs, and the four first wires 120 are affected by the second capacitance compensation pattern 130. Set the increased capacitive coupling amounts to Cp1, Cp2, Cp3, and Cp4, respectively, and the coupling voltage Vc1 of the first wire 120 is: Vc1=dV*(C1+Cp1*Cp2/(Cp1+Cp2))/(C1+Cs+Cp1 (Cp2+Cp3+Cp4)/(Cp1+Cp2+Cp3+Cp4)).

If the array substrate 10 is not provided with the second capacitance compensation pattern 130, the coupling voltage Vc2 of the first wire 120 is: Vc2=dV*C1/(C1+Cs).

It can be seen that when the first wire 120 and the second capacitance compensation pattern 130 project overlap, the coupling voltage Vc1 is less than the coupling voltage Vc2 when the second capacitance compensation pattern 130 is not provided. When the coupling voltage of the first wire 120 decreases, the coupling voltage The influence of the original voltage of the first wire 120 is weakened, thereby improving the tight arrangement of the wires (the first wire 120 and the second wire 140) on the array substrate 10, resulting in a larger parasitic capacitance between adjacent wires. Phenomena that affect the display effect.

It can be seen from the above formula that the influence of the second capacitance compensation pattern 130 on the original voltage of the first conductive line 120 is related to the number of the first conductive lines 120 that overlap each other. In one embodiment, the projection of each of the second capacitance compensation patterns 130 on the substrate 11 overlaps with the projections of the three first wires 120 to better reduce the parasitic capacitance on the first wires 120 The impact of the original voltage.

The principle of capacitance compensation when the first capacitance compensation pattern 110 and the second wire 140 are stacked up and down is similar to this, and will not be repeated here. Similarly, in an embodiment, the projection of each of the first capacitance compensation patterns 110 on the substrate 11 overlaps with the projections of the three second conductive lines 140, so as to better reduce the parasitic capacitance to the second The influence of the original voltage on the wire 140, thereby avoiding the close arrangement of the wires (the first wire 120 and the second wire 140) on the array substrate 10, resulting in a large parasitic capacitance between adjacent wires, affecting the display The effect of the phenomenon.

FIG. 9 is a cross-sectional view of a display panel 40 provided by an embodiment of the invention. As shown in FIG. 9, the display panel 40 includes an array substrate 10 and a color filter substrate 20 arranged opposite to each other, and a liquid crystal layer 30 sandwiched between the array substrate 10 and the color filter substrate 20.

The color filter substrate 20 includes a transparent substrate (not shown), a black matrix (not shown) disposed on the side of the substrate close to the liquid crystal layer 30, a filter layer (not shown), and a protective layer (not shown) Wait. The black matrix, filter layer, etc. of the light-transmitting area B1 corresponding to the camera aperture area B are removed. The liquid crystal layer 30 is arranged corresponding to the display area A and the camera aperture area B.

The array substrate 10 also includes a common electrode (not shown) provided corresponding to the display area A. An electric field is generated between the pixel electrode 164 and the common electrode to drive the liquid crystal molecules in the liquid crystal layer 30 to rotate, so that the image is displayed in the display area A, while the camera aperture area B does not display the image.

FIG. 10 is a cross-sectional view of a display device 100 provided by an embodiment of the invention. As shown in FIG. 10, the display device 100 includes a display panel 40, a backlight module 60 and a camera module 50. The display panel 40 is defined with a display surface 40a. The backlight module 60 and the camera module 50 are located on the side of the display panel 40 away from the display surface 40 a. The backlight module 60 is defined with a light emitting side 60a. The display panel 40 is located on the light emitting side 60 a of the backlight module 60. The camera module 50 is arranged corresponding to the camera hole area B to collect image information through the camera hole area B.

The backlight module 60 is a direct type backlight source. The backlight module 60 includes a light source (not shown in the figure), an optical film set (not shown in the figure), a back plate (not shown in the figure), and the like. The backlight module 60 defines a mounting hole 62 penetrating the backlight module 60 corresponding to the camera hole area B. The size of the mounting hole 62 is greater than or approximately equal to the size of the camera hole area B. The camera module 50 is disposed in the mounting hole 62. Since the camera module 50 is disposed corresponding to the camera hole area B surrounded by the display area A, the screen-to-body ratio of the display device 100 is increased compared to the manner in which the camera module 50 is disposed in the frame area surrounding the display area A. The display device 100 may be a mobile phone, a tablet computer, or the like.

The above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced. Without departing from the spirit and scope of the technical solution of the present invention.

A: Display area

B: Camera hole area

B1: Transmissive area

B2: Wiring area

X: first direction

Y: second direction

L1: the first axis of symmetry

L2: second axis of symmetry

AL: left area

AR: Right area

AT: Upper side area

AB: Lower area

12: Scan line

122: first scan line

124: second scan line

144a: auxiliary data line

11: Base

13: The first conductive layer

120: first wire

110: The first capacitance compensation pattern

Claims (9)

An array substrate is improved in that the array substrate defines a display area and a camera hole area surrounded by the display area, the camera hole area includes a light-transmitting area and a wiring area surrounding the light-transmitting area, so The array substrate includes: a base; a first conductive layer located on the base, the first conductive layer includes a plurality of first wires arranged around the light-transmitting area; a second conductive layer located on the first conductive Layer away from the substrate, the second conductive layer includes a plurality of second conductive lines arranged around the light-transmitting area; wherein, the first conductive layer further includes insulated and spaced apart from the first conductive line A plurality of first capacitance compensation patterns, each of the first capacitance compensation patterns is located between two adjacent first conductive lines; along the thickness direction of the array substrate, each of the first capacitance compensation patterns is located The projection on the substrate at least overlaps with the projection of one of the second wires; the second conductive layer further includes a plurality of second capacitance compensation patterns arranged at an insulating interval from the second wire, and each of the second capacitance compensation patterns The pattern is located between two adjacent second conductive lines; along the thickness direction of the array substrate, the projection of each second capacitance compensation pattern on the substrate is at least the same as the projection of one of the first conductive lines overlapping. The array substrate according to claim 1, wherein the first conductive line includes a plurality of first scan lines, and each of the first scan lines bypasses the light-transmitting area, straddles the wiring area, and spreads over the wiring area. The display area extends along a first direction; the first capacitance compensation pattern is arranged between two adjacent first scan lines. The array substrate according to claim 2, wherein the second conductive line includes a plurality of first data lines, and each of the first data lines bypasses the light-transmitting area, crosses the wiring area, and is connected to the wiring area. The display area extends along a second direction; the second direction crosses the first direction; the second capacitance compensation pattern is arranged between two adjacent first data lines. The array substrate according to claim 3, wherein the array substrate further includes a plurality of second data lines, and each of the second data lines bypasses the light-transmitting area, crosses the wiring area, and is connected to the wiring area. The display area extends along the second direction; in the first direction, the second data line and the first data line are alternately arranged in sequence; the first conductive line further includes a plurality of auxiliary data lines, so The second wire further includes a plurality of data line leads, each of the auxiliary data lines is located in the wiring area, and each of the data line leads is electrically connected to one of the auxiliary data lines and is connected between the wiring area and the wiring area. The display area extends along the second direction; each second data line includes one auxiliary data line and one data line lead. The array substrate according to claim 4, wherein the first capacitance compensation pattern is provided between two adjacent auxiliary data lines. The array substrate according to claim 5, wherein the second capacitance compensation pattern is provided between the adjacent first data line and the second data line. The array substrate according to claim 6, wherein the second conductive line further includes a plurality of third data lines; each of the third data lines bypasses the light-transmitting area, crosses the wiring area, and is located at the The display area extends along the second direction; In the first direction, the third data line is located on the side of the first data line and the second data line away from the light-transmitting area; one of the two adjacent third data lines The second capacitance compensation pattern is arranged in between. A display panel includes a color filter substrate, a liquid crystal layer, and an array substrate. The liquid crystal layer is sandwiched between the color filter substrate and the array substrate, wherein the array substrate is as claimed in claim 1. To the array substrate described in any one of 7. A display device, comprising: the display panel according to claim 8; a backlight module, the backlight module is located on the side of the display panel away from its display surface, the backlight module is defined to pass through the A mounting hole of the backlight module, the mounting hole is aligned with the light-transmitting area; and a camera module, the camera module being installed in the mounting hole and collecting image information through the light-transmitting area.

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