TWI718159B - OPTOELECTRONIC DETECTORS HAVING A DILUTE NITRIDE LAYER ON A SUBSTRATE WITH A LATTICE PARAMETER NEARLY MATCHING GaAs - Google Patents

Abstract

Optoelectronic detectors having one or more dilute nitride layers on substrates with lattice parameters matching or nearly matching GaAs are described herein. A semiconductor can include a substrate with a lattice parameter matching or nearly matching GaAs and a first doped III-V layer over the substrate. The semiconductor can also include an absorber layer over the first doped III-V layer, the absorber layer having a bandgap between approximately 0.7 eV and 0.95 eV and a carrier concentration less than approximately 1 x 10¹⁶ cm^-3 at room temperature. The semiconductor can also include a second doped III-V layer over the absorber layer.

Description

A photodetector with a dilute nitride layer on a substrate with lattice parameters almost matching GaAs

The present invention relates to a semiconductor including a substrate with lattice parameter matching or nearly matching GaAs.

III-V materials are selected materials for the manufacture of photoelectric transmitters and detectors for various applications. One of the reasons is that the band gap of the III-V material can be selected for the specific wavelength of interest. Due to the transmission characteristics of fiber optic systems, they usually use wavelengths of 1.33 μm (micrometers) and 1.50 μm.

Historically, the vast majority of 1.33μm and 1.50μm transmitters and detectors used indium gallium arsenide (InGaAs) alloy as the emission and detection medium. In order to produce the high-quality InGaAs required by the emitter or detector, it is preferable that the material is as free of crystalline defects as possible. The alloy composition and thickness of the InGaAs layer required for functional devices must be grown on an indium phosphide (InP) substrate because InP has the _{same in-plane lattice parameters as In 0.53} Ga _0.47 As (Eg=0.75 at 300 K) eV, which corresponds to a wavelength of 1.65μm).

From a cost point of view, it is better to grow the photodetector and emitter on a substrate that is cheaper than InP, such as gallium arsenide (GaAs), germanium (Ge), or silicon (Si). However, when grown thick enough to make a usable detector or emitter, the lattice mismatch between the cheaper substrate and the InGaAs alloy of the desired composition creates highly defective materials. The cost of the substrate is a significant part of the overall manufacturing cost. Therefore, it is found that the way to grow a material with a sufficient energy band gap on a cheaper substrate is quite technical and has practical benefits.

This article describes a photodetector with one or more diluted nitride layers on a substrate with lattice parameter matching or nearly matching GaAs. The semiconductor may include a substrate with lattice parameter matching or nearly matching GaAs and a first doped III-V layer on the substrate. The semiconductor may also include an absorber layer on the first doped III-V layer, the absorber layer having an energy band gap between about 0.7 eV and 0.95 eV and a carrier concentration at room temperature Less than about 1×10 ¹⁶ cm ^-3 . The semiconductor may also include a second doped III-V layer on the absorber layer.

x

1；0

y

1；0

z

1)。在一些實例中，x、y、及z在以下個別範圍內：(0

x

0.55；0

y

0.1；0

z

0.1)。 The absorber layer may include dilute nitride. The diluted nitride may include In _x Ga _1-x N _y As _1-yz Sb _z , where x, y, and z are within the following individual ranges: (0

x

1; 0

y

1; 0

z

1). In some instances, x, y, and z are in the following individual ranges: (0

x

0.55; 0

y

0.1; 0

z

0.1).

The carrier concentration of the absorbent layer may be less than about 5×10 ¹⁵ cm ^-3 , or it may be less than about 1×10 ¹⁵ cm ^-3 . The thickness of the absorbent layer can be between about 2 microns and about 10 microns, or it can be between about 3 microns and about 5 microns.

The semiconductor may further include a multiplication layer between the absorber layer and one of the first and second doped III-V layers.

One or more implementations can form a substrate with lattice parameter matching or nearly matching GaAs. The substrate may include GaAs. The substrate may include a silicon substrate and a designed lattice layer on the silicon substrate, wherein the surface of the designed lattice layer is opposite to the silicon substrate with lattice parameters matching or nearly matching GaAs. Designed lattice layer may include a Si _x Ge _1-x layer, x from the Si _x Ge _1-x layer closest to the surface of the silicon substrate Si _x Ge _1-x layer is a gradient of the silicon substrate opposite to the The surface is 0. The lattice engineered layer may include a rare earth-containing layer, wherein the rare earth-containing layer includes Sc, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and / Or one or more of Lu.

The first doped III-V layer may be n-type, and the second doped III-V layer may be p-type. The first doped III-V layer may be p-type, and the second doped III-V layer may be n-type.

100, 200, 300, 400, 160, 1700, 1800, 1600, 1630, 1660‧‧‧ Semiconductor

102,112,202,212‧‧‧III-V floor

106,206‧‧‧Dilute nitride layer

114,214,314,414,1636,1666‧‧‧Substrate

208,408‧‧‧Multiplication layer

302,402‧‧‧p-type GaAs layer

304,404‧‧‧p-type InGaNAsSb layer

306,406‧‧‧Intrinsic InGaNAsSb layer

310,312,410,412‧‧‧n-type GaAs layer 310

500,600,700,800,900,1000,1100,1200,1300,1400‧‧‧Figure

502,602,604,702,704,1402‧‧‧scan

504,506,508,510,606,608,610,706,708,710,1404‧‧peak

802,804,1002,1004,1006,1102,1104,1106,1202,1206,1208,1210,1212,1302,1306,1308,1310,1312‧‧‧Curve

902‧‧‧energy band gap curve

904‧‧‧PL intensity curve

1406‧‧‧Half height width

1500‧‧‧color map

1502‧‧‧Central location

1504‧‧‧Edge position

1602,1632,1662‧‧‧p-i-n diode

1606‧‧‧GaAs substrate

1634‧‧‧Si _x Ge _1-x layer

1635, 1665‧‧‧Si substrate

1664‧‧‧With RE layer

The above and other features of the present invention, including its nature and various advantageous advantages, will be more apparent when considering the following detailed description in conjunction with the accompanying drawings, in which: Figure 1 depicts a p-i-n diode according to an illustrative implementation 2 depicts a semiconductor including a pin diode and a multiplication layer according to an illustrative implementation; FIG. 3 depicts a semiconductor with a GaAs-based pin diode according to an illustrative implementation; FIG. 4 depicts a semiconductor including a pin diode according to an illustrative implementation GaAs-based pin diodes and multiplication layer semiconductors; FIG. 5 depicts a diagram showing the characteristics of the semiconductor shown in FIG. 3 by X-ray diffraction (XRD) according to an illustrative implementation; FIG. 6 depicts a diagram showing the characteristics of the semiconductor shown in FIG. 3 according to an illustrative implementation XRD scans of intrinsic InGaNAsSb layers with different thicknesses epitaxially formed on GaAs; FIG. 7 depicts XRD scans of InGaNAsSb layers grown on p-type and semi-insulating GaAs substrates according to an illustrative implementation; FIG. 8 depicts A graph showing the influence of the In/Sb ratio measured by the Hall effect according to an illustrative implementation on the carrier properties of InGaNAsSb; FIG. 9 depicts a graph showing the influence of the measured by photoluminescence (PL) according to an illustrative implementation A graph showing the influence of the In/Sb ratio on the optical properties of InGaNAsSb; FIG. 10 depicts a graph showing the influence of the growth temperature and As flux measured by the Hall effect on the carrier concentration of InGaNAsSb according to an illustrative implementation; FIG. 11 depicts Shows the light-induced emission according to the illustrative implementation A graph showing the influence of growth temperature and arsenic flux on the energy band gap of InGaNAsSb by optical measurement; FIG. 12 depicts the influence of rapid thermal annealing (RTA) measured by Hall effect on the carrier concentration of InGaNAsSb according to an illustrative implementation Figure 13 includes a graph showing the influence of RTA on the band gap of InGaNAsSb measured by photoluminescence according to an illustrative implementation; Figure 14 depicts a graph showing the effect of a 0.5μm InGaNAsSb layer grown on a GaAs substrate according to an illustrative implementation Figures of the photoluminescence spectra; Figure 15 includes a color map showing the cross-wafer variation of the energy band gap of a 0.5μm InGaNAsSb layer grown on a 150mm GaAs substrate according to an illustrative implementation; and Figure 16 illustrates an illustrative implementation according to an illustrative implementation There are several examples of pin diodes formed on substrates with lattice parameter matching or nearly matching GaAs.

The systems and methods described herein include methods for growing high-quality photodetectors on substrates with lattice parameter matching or nearly matching GaAs. The detector described herein uses a dilute nitride layer, usually an In _x Ga _1-x N _y As _1-yz Sb _z layer, as an absorbing medium, where x is in the range of 0 to 0.55 and y is in the range of 0 to 0.1 Range, and z is in the range of 0 to 0.1, hereinafter referred to as the InGaNAsSb layer. Diluted nitride is a III-V material that includes nitrogen at a low concentration (which is a low alloy level concentration and a concentration higher than the doping level concentration) nitrogen. The diluted nitride layer may have traces of dopants or contamination, but the amount will not hinder the function of the layer in the detector. In some instances, the photodetector uses a pin structure. In a typical pin, the absorbing medium is an intrinsic semiconductor (i), which is sandwiched between an n-type semiconductor and a p-type semiconductor. The n-type region has electrons as the main carrier, which is usually caused by doping with a donor dopant. The p-type region has holes as the main carrier, which is usually caused by doping with acceptor dopants. During operation, a reverse bias is applied to the diode, which is used to "sweep out" the carriers generated by photons with sufficient energy.

The substrate with lattice parameter matching or nearly matching GaAs may include a GaAs substrate, a Ge substrate, or a lattice designed substrate. Examples of lattice-designed substrates include a substrate including a graded SiGe layer on a Si handle wafer and a substrate including a rare earth-containing layer on a Si handle wafer. The lattice parameter is the unit cell size in the crystal lattice. The substrate with lattice parameter matching or nearly matching GaAs may have the same or slightly different lattice parameters with the lattice parameter of GaAs (5.65Å), but are similar enough to epitaxially grow high-quality GaAs on the substrate surface. High-quality GaAs may include a defect level equivalent to or lower than that of an _{In 0.53} Ga _{0.47 As layer grown on an InP substrate.} This means that the difference between the lattice parameter of the substrate and the lattice parameter of GaAs is less than or equal to 3%, less than 1%, or less than 0.5%.

The high-quality InGaNAsSb absorber layer can manufacture low-cost, high-performance detectors. One of the reasons for this is that the absorbent layer is grown coherently (that is, crystalline, non-relaxed, and has minimal defects) on a substrate with lattice parameter matching or almost matching GaAs. The composition of the InGaNAsSb layer can be fine-tuned so that the layer with the desired energy band gap and thickness can be Minimal defect epitaxial growth on substrates with lattice parameter matching or nearly matching GaAs. The energy band gap is the energy difference between the conduction band and the valence band of the material, and it can be direct (the electronic transition between the bands can only occur when photons are emitted or absorbed) or indirectly (the transition between the bands). In addition to photon emission or absorption, electronic transition also requires phonon emission or absorption). III-V materials have a direct energy band gap, but the layers described herein may have a direct or indirect energy band gap.

Figure 1 depicts a semiconductor 100 including a pin diode. The semiconductor 100 includes a substrate 114, an n ⁺ III-V layer 112 ^{epitaxially formed on the substrate 114, an intrinsically diluted nitride layer 106 epitaxially formed on the n +} III-V layer 112, and an intrinsically diluted nitride layer 106 formed epitaxially on the substrate 114, and ^{The p +} III-V layer 102 is epitaxially formed on the layer 106.

The III-V layers 102 and 112 may include any III-V materials, such as GaAs, InGaAs, AlGaAs, InGaP, InGaAsP, InGaAsN, InGaNAsSb, or other III-V materials. The substrate 114 may be a semiconductor, conductive, or insulating substrate. The upper surface of the substrate 114 has a lattice parameter matching or nearly matching GaAs. An example of the substrate 114 is described below with reference to FIG. 16. The diluted nitride layer 106 is an essential layer in the p-i-n diode and serves as an absorption medium. The terms absorber layer and absorption medium can be used to describe any layer that absorbs photons.

The diluted nitride layer 106 has lattice parameters compatible with the III-V layers 102 and 112. The diluted nitride layer 106 may be lattice-matched to the III-V layers 102 and 112, or it may have lattice parameters that are relatively close (nearly matched) to the III-V layers 102 and 112. In this way, the diluted nitride layer 106 has a sufficiently low defect level, and therefore has good optical performance. Such a sufficiently low defect level may include a defect level equal to or lower than that occurring in _{the In 0.53} Ga _{0.47 As layer grown on the InP substrate.} Each of the layers 102, 106, and 112 and the substrate 114 may include one or more layers that improve lattice matching, interface quality, electron transport, hole transport, and/or other optoelectronic properties.

Figure 2 depicts a semiconductor 200 with a pin diode and a multiplication layer. The semiconductor 200 is similar to the semiconductor 100 but includes a multiplication layer to amplify the photocurrent generated by the intrinsic layer of the pin diode. The structure of the semiconductor 200 can be described as an avalanche photodiode (APD) structure. In APD, adding a multiplication layer creates additional pin or pn junctions. This allows a higher reverse bias to be applied, resulting in carrier multiplication through the avalanche process. Therefore, the gain (number of electrons per photon) of the device (compared to the standard pin) increases. This results in a higher sensitivity device. The semiconductor 200 includes a substrate 214, an n ⁺ III-V layer 212 ^{epitaxially formed on the substrate 214, a p-type multiplication layer 208 formed on the n +} III-V layer 212, and an epitaxial layer on the p-type multiplication layer 208 The intrinsically diluted nitride layer 206 is formed, and the p ⁺ III-V layer 202 is epitaxially formed on the diluted nitride layer 206.

The III-V layers 202 and 212 may include any III-V materials, such as GaAs, InGaAs, AlGaAs, InGaP, InGaAsP, InGaAsN, InGaNAsSb, or other III-V materials. The substrate 214 may be a semiconductor, conductive, or insulating substrate. The upper surface of the substrate 214 has a lattice parameter that matches or nearly matches that of GaAs. An example of the substrate 214 is described below with reference to FIG. 16. The diluted nitride layer 206 is an essential layer in the p-i-n diode and serves as an optical absorber layer.

The diluted nitride layer 206 has lattice parameters compatible with the III-V layers 202 and 212. The diluted nitride layer 206 may be lattice-matched to the III-V layers 202 and 212, or it may have lattice parameters that are relatively close (nearly matched) to the III-V layers 202 and 212. In this way, the diluted nitride layer 206 has a sufficiently low defect level, and therefore has good optical performance. Such a sufficiently low defect level may include a defect level equal to or lower than that occurring in _{the In 0.53} Ga _{0.47 As layer grown on the InP substrate.} Each of the layers 202, 206, and 212 and the substrate 214 may include one or more layers that improve lattice matching, interface quality, electron transport, hole transport, and/or other optoelectronic properties.

The multiplication layer 208 may be a p-type III-V layer that amplifies the current generated by the diluted nitride layer 206 through avalanche multiplication. In this way, in terms of the respective carriers (electrons or holes) generated by the diluted nitride layer 206, the multiplication layer 208 generates one or more carriers through the avalanche effect. In this way, the multiplication layer 208 increases the total current generated by the semiconductor 200.

x

1；0

y

1；0

z

1)。莫耳分率x、y、及z可在不同層302及304中具有不同值。在一些實例中，x在0至0.55之範圍，y在0至0.1之範圍，且z在0至0.1之範圍。 Figure 3 depicts a semiconductor 300 with GaAs-based pin diodes. The semiconductor 300 includes a substrate 314 having a top surface with a lattice parameter that matches or nearly matches that of GaAs. The substrate 300 includes an n-type GaAs layer 312 epitaxially formed on the substrate 314 and an n-type GaAs layer 310 epitaxially formed on the GaAs layer 312. The GaAs layer 312 may be more heavily doped than the GaAs layer 310. The semiconductor 300 also includes an intrinsic InGaNAsSb layer 306 epitaxially formed on the GaAs layer 310, a p-type InGaNAsSb layer 304 epitaxially formed on the intrinsic InGaNAsSb layer 306, and a p-type GaAs epitaxially formed on the p-type InGaNAsSb layer 304层302. The p-type GaAs layer 302 may be more heavily doped than the p-type InGaNAsSb layer 304. The InGaNAsSb layer 304 and the InGaNAsSb layer 306 may each have a composition In _x Ga _1-x N _y As _1-yz Sb _z (0

x

1; 0

y

1; 0

z

1). The molar fractions x, y, and z may have different values in different layers 302 and 304. In some examples, x is in the range of 0 to 0.55, y is in the range of 0 to 0.1, and z is in the range of 0 to 0.1.

In some examples, the p-type GaAs layer 302 may have a thickness of about 0.2 μm, and may be doped with Be or C to form a free hole concentration of ^{about 1.5×10 19} cm ^−3. The p-type InGaNAsSb layer 304 may have a thickness of about 0.25 μm, and may be doped with Be or C to form a free hole concentration of ^{about 7×10 18} cm ^−3. The composition of the InGaNAsSb layer 304 can be selected to form an energy band gap of approximately 0.8 eV. The InGaNAsSb layer 306 may have a thickness of about 3 μm, and may be unintentionally doped (UID) with a free carrier concentration of ^{about 6×10 14} cm ^−3. The carrier concentration of a material is the number density of charge carriers (such as electrons or holes) in the material. The carrier concentration of a material is sometimes ^{expressed in units of electron-cm -3} , hole -cm ^-3 , or atom -cm ^-3 (called atomic dopant density), but it is more common to omit the particle name and The same number is indicated, and the carrier concentration is simply ^{expressed in cm -3} units. UID semiconductors do not have deliberately added dopants, but may include non-zero concentrations of impurities as dopants. The InGaNAsSb layer 306 can serve as an absorber layer to absorb incident photons. The InGaNAsSb layer 306 may mainly have holes as free carriers, making the layer 306 p-type. The composition of the InGaNAsSb layer 306 can also be selected to form an energy band gap of approximately 0.8 eV. The InGaNAsSb layer 306 may have an energy band gap between about 0.8 eV and about 0.95 eV, corresponding to a wavelength between 1.3 μm and 1.55 μm.

With proper In concentration, InGaAs alloy can have There is an energy band gap in the wavelength range of 1.3 to 1.55 μm. However, the lattice parameters of this InGaAs alloy are similar to those of InP, but not similar to those of GaAs or Si. As such, the InGaAs absorber is not easily compatible with epitaxial growth on GaAs or silicon substrates. However, adding N to InGaAs can reduce the energy band gap and at the same time form a lattice parameter that matches or nearly matches GaAs. The addition of Sb to InGaNAs results in improved crystallinity and lower background carrier concentration at a given energy band gap. Sb can migrate some types of defects or can be used as a surfactant to enhance device performance. Sb can improve the incorporation of N, allowing the use of lower N flux or flow rate to grow materials with a given N concentration and corresponding energy band gap, thereby reducing the background carrier concentration. Therefore, the energy band gap of InGaNAsSb can be set to an appropriate range while maintaining good crystallinity and lattice matching with GaAs.

The GaAs layer 310 may have a thickness of about 0.5 μm, and may be doped with silicon to form an n-type material with a free carrier concentration of ^{about 2×10 15} cm ^−3. The GaAs layer 312 may have a thickness of about 2.5 μm, and may be doped with silicon to form an n-type material with a free carrier concentration of ^{about 5×10 18} cm ^−3. The substrate 314 may include one or more layers, and the top surface of the substrate may have GaAs with matched or nearly matched lattice parameters. This forms a high-quality interface between the GaAs layer 312 and the substrate 314, and reduces the level of defects in the semiconductor 300. Some examples of the substrate 314 are described below with reference to FIG. 16. Therefore, the semiconductor 300 includes a GaAs-based pin diode that is optically active in the range of 1.3 to 1.55 μm and is formed on the top surface of a substrate having a lattice parameter that matches or nearly matches that of GaAs.

x

1；0

y

1；0

z

1)。莫耳分率x、y、及z可在不同層402及404中具有不同值。在一些實例中，x大約在0至0.55之範圍(包括端值)，y大約在0至0.1之範圍(包括端值)，且z大約在0至0.1之範圍(包括端值)。 FIG. 4 depicts a semiconductor 400 with a GaAs-based pin diode and a multiplication layer. The semiconductor 400 is similar to the semiconductor 300, but includes an avalanche multiplication layer to amplify the photocurrent generated by the intrinsic layer of the pin diode. The semiconductor 400 includes a substrate 414 having a top surface with a lattice parameter that matches or nearly matches that of GaAs. The substrate 400 includes an n-type GaAs layer 412 epitaxially formed on the substrate 414 and an n-type GaAs layer 410 epitaxially formed on the n-type GaAs layer 412. The GaAs layer 412 may be more heavily doped than the GaAs layer 410. The semiconductor 400 also includes a multiplying layer 408 epitaxially formed on the GaAs layer 410, an intrinsic InGaNAsSb layer 406 epitaxially formed on the multiplying layer 408, a p-type InGaNAsSb layer 404 epitaxially formed on the intrinsic InGaNAsSb layer 406, and The p-type GaAs layer 402 is epitaxially formed on the type InGaNAsSb layer 404. The p-type GaAs layer 402 may be more heavily doped than the p-type InGaNAsSb layer 404. The InGaNAsSb layer 404 and the InGaNAsSb layer 406 may each have a composition In _x Ga _1-x N _y As _1-yz Sb _z (0

x

1; 0

y

1; 0

z

1). The molar fractions x, y, and z may have different values in different layers 402 and 404. In some examples, x is approximately in the range of 0 to 0.55 (inclusive), y is approximately in the range of 0 to 0.1 (inclusive), and z is approximately in the range of 0 to 0.1 (inclusive).

In some examples, the p-type GaAs layer 402 may have a thickness of about 0.2 μm, and may be doped with Be or C to form a free hole concentration of ^{about 1.5×10 19} cm ^−3. The p-type InGaNAsSb layer 404 may have a thickness of about 0.25 μm, and may be doped with Be or C to form a free hole concentration of ^{about 7×10 18} cm ^−3. The composition of the InGaNAsSb layer 404 can be selected to form an energy band gap of approximately 0.8 eV. The InGaNAsSb layer 406 may have a thickness of about 3 μm, and may be unintentionally doped (UID) with a free carrier concentration of ^{about 6×10 14} cm ^−3. The InGaNAsSb layer 406 can serve as an absorber layer to absorb incident photons. The InGaNAsSb layer 406 may mainly have holes as free carriers, making the layer 406 p-type. The composition of the InGaNAsSb layer 406 can also be selected to form an energy band gap of approximately 0.8 eV. The InGaNAsSb layer 406 may have an energy band gap between about 0.8 eV and about 0.95 eV, corresponding to a wavelength between 1.3 μm and 1.55 μm.

With an appropriate In concentration, the InGaAs alloy may have an energy band gap in the wavelength range of 1.3 to 1.55 μm. However, the lattice parameters of this InGaAs alloy are similar to those of InP, but not similar to those of GaAs or Si. As such, the InGaAs absorber is not easily compatible with epitaxial growth on GaAs or silicon substrates. However, adding N to InGaAs can reduce the energy band gap and at the same time form a lattice parameter that matches or nearly matches GaAs. The addition of Sb to InGaNAs results in improved crystallinity and lower background carrier concentration at a given energy band gap. Sb can migrate some types of defects or can be used as a surfactant to enhance device performance. Sb can improve the incorporation of N, allowing the use of lower N flux or flow rate to grow materials with a given N concentration and corresponding energy band gap, thereby reducing the background carrier concentration. Therefore, the energy band gap of InGaNAsSb can be set to an appropriate range while maintaining good crystallinity and lattice matching with GaAs.

The GaAs layer 410 may have a thickness of about 0.5 μm, and may be doped with silicon to form an n-type material with a free carrier concentration of ^{about 2×10 15} cm ^−3. The GaAs layer 412 may have a thickness of about 2.5 μm, and may be doped with silicon to form an n-type material with a free carrier concentration of ^{about 5×10 18} cm ^−3. The substrate 414 may include one or more layers, and the top surface of the substrate may have GaAs with matched or nearly matched lattice parameters. This forms a high-quality interface between the GaAs layer 412 and the substrate 414, and reduces the level of defects in the semiconductor 400. Some examples of the substrate 414 are described below with reference to FIG. 16. Therefore, the semiconductor 400 includes a GaAs-based pin diode that is optically active in the range of 1.3 to 1.55 μm and is formed on the top surface of a substrate having a lattice parameter that matches or nearly matches that of GaAs.

The multiplication layer 408 may be a p-type III-V layer that amplifies the current generated by the diluted nitride layer 406 through avalanche multiplication. One of the examples of the p-type III-V layer is a p-type GaAs layer. Regarding the respective carriers (electrons or holes) generated by the diluted nitride layer 406, the multiplication layer 408 generates one or more carriers through the avalanche effect. In this way, the multiplication layer 408 increases the total current generated by the semiconductor 400.

In some examples, the band gap of one or more of the layers 106, 206, 304, 306, 404, and 406 is between 0.7 eV and 0.95 eV. In some examples, the band gap of one or more of layers 106, 206, 304, 306, 404, and 406 is 0.7 eV, 0.75 eV, 0.80 eV, 0.85 eV, 0.90 eV, or 0.95 eV. In some examples, one or more of layers 106, 206, 304, 306, 404, and 406 are up to 10 μm thick. In some examples, one or more of layers 106, 206, 304, 306, 404, and 406 are 0.001 to 1, 0.05 to 5, 0.5 to 5, 0.1 to 1, 1 to 10, 0.001 to 0.005, 0.005 to 0.01, 0.01 to 0.05, 0.05 to 0.1, 0.1 to 0.5, 0.5 to 1, 1 to 2, 2 to 3, 3 to 4, 4 to 5, 5 to 6, 6 to 7, 7 to 8, 8 to 9, 9 to 10, 2 to 10, 3 to 10, or 3 to 5 μm (micrometer) thick. The layers 106, 206, 306, and 406 have free carrier concentrations caused by unintentional dopants. The carrier concentration of one or more of the layers 106, 206, 306, and 406 at room temperature may be lower than about 1×10 ¹⁶ cm ^-3 , may be lower than about 5×10 ¹⁵ cm ^-3 , and may be lower than about 1×10 ¹⁵ cm ^-3 , and may be between approximately 1×10 ¹³ cm ^-3 and 5×10 ¹⁵ cm ^-3 . Room temperature may include the temperature range that layers 106, 206, 306, and 406 will experience during normal operation, such as about 20°C, between 15°C and 25°C, between 0°C and 30°C, and between Between -20°C and 50°C. Since the layers 106, 206, 306, and 406 are not deliberately doped, carrier freezing will occur at a higher temperature than a semiconductor with a higher doping level. Due to this freezing effect, a sample measured at a reduced temperature or low temperature will exhibit a lower carrier concentration than the same sample measured at room temperature. As such, as opposed to measuring carrier concentration at reduced or low temperatures, measuring carrier concentration at room temperature provides an accurate indication of the carrier concentration expected during device operation.

One or more of the layers 106, 206, 304, 306, 404, and 406 may have an Inmolar concentration between about 10% and about 20%, an N between about 3% and about 7%. Molar concentration, and Sb molar concentration between about 0.5% and about 5%.

FIG. 5 depicts a diagram 500 showing the characteristics of the semiconductor 300 by X-ray diffraction (XRD). Graph 500 includes scan 502 with peaks 504, 506, 508, and 510. Each peak corresponds to a different lattice parameter 的材料。 The material. The peak 504 corresponds to the intrinsic InGaNAsSb layer 306, and the peak 506 corresponds to the p-type InGaNAsSb layer 304. The p-type dopant adds tensile strain to layer 304, so peak 506 is shifted from peak 504 by approximately 26 arc seconds. The peak 508 may correspond to the GaAsSb that forms the interface between the p-type GaAs layer 302 and the p-type InGaNAsSb layer 304. The peak 510 corresponds to the substrate 314. The narrowness of the peaks 504, 506, 508, and 510 indicates that the epitaxial layers 302, 304, 306, 310, and 312 have high crystallinity and low defect levels.

FIG. 6 depicts an XRD scan 600 showing an intrinsic InGaNAsSb layer with different thicknesses formed by epitaxy on GaAs. These layers are grown using molecular beam epitaxy (MBE) at a growth temperature of 440°C and a ratio of group V elements to group III elements (V/III) of 42:1. The layers are epitaxially strained (non-relaxed) with an energy band gap as low as 0.78 eV. The graph 600 includes a scan 602 of the 4 μm InGaNAsSb layer and a scan 604 of the 0.5 μm InGaNAsSb layer. Scan 602 has two peaks (606 and 608), indicating that there are two different lattice parameters. The peak 608 corresponds to the GaAs substrate, and the peak 606 corresponds to the 4 μm InGaNAsSb layer. Peak 606 is offset from peak 608 by -114 arc seconds, indicating that the 4 μm InGaNAsSb layer is slightly more compressed than GaAs. Conversely, scan 604 has only one peak 610, indicating that there is only one lattice parameter. The XRD peaks from the 0.5μm InGaNAsSb layer and the GaAs substrate overlap, indicating that the InGaNAsSb layer and the GaAs substrate are lattice-matched or nearly matched. Furthermore, the narrowness of peaks 606, 608, and 610 indicates that the InGaNAsSb layer has high crystallinity and low defect levels.

FIG. 7 depicts an XRD scan 700 showing an InGaNAsSb layer grown on a p-type and semi-insulating GaAs substrate. Figure 700 is included in p A scan 702 of a 0.5 μm InGaNAsSb layer grown by MBE on a type GaAs substrate and a scan 704 of a 0.5 μm InGaNAsSb layer grown by MBE on a semi-insulating GaAs substrate.

When growing on a semi-insulating substrate, effective substrate temperature control can improve the quality of low energy band gap materials such as InGaNAsSb. When the temperature of the semiconductor substrate increases, heat generates free carriers and its absorption edge shifts to lower energy. This offset can be measured and used to calculate the substrate temperature.

Epitaxial growth systems often use radiant heaters that rely on the radiant absorption of the substrate to raise the temperature of the substrate. Absorption is related to both doping and band gap; as the band gap decreases and/or doping increases, more absorption occurs. The layer absorption is also scaled in proportion to the layer thickness. Therefore, the growth of a sufficiently thick low-energy band-gap material (InGaNAsSb) on a semi-insulating higher-energy band-gap material (such as a GaAs substrate) can form a state where the low-energy band-gap material dominates radiation absorption. The thickness of the low-energy band gap material changes to significantly affect the substrate temperature.

If a constant heater power that will form a constant equilibrium temperature of a semi-insulating substrate is maintained while a sufficiently thick low-energy band gap material is grown, the increase in substrate absorptivity will increase the amount of heat absorbed under constant heater power, resulting in an increase in substrate temperature. Therefore, when a sufficiently thick low-energy band gap material is grown on a semi-insulating substrate, both the open-loop temperature control and the closed-loop temperature control based on the indirect measurement of the substrate temperature will be inaccurate. When low-energy band gap materials are grown on more conductive substrates, these effects are not obvious. The reason is that the absorption of doped substrates is higher than that of semi-insulating substrates and often dominates radiation absorption.

The layer grown on the p-type substrate (scan 702) is grown using a thermocouple positioned to be sensitive to the backside of the substrate (opposite to the growth surface of the epitaxial layer) to simply adjust the temperature of the substrate holder by closed loop temperature control growth . However, the layer grown on the semi-insulating substrate (scan 704) is grown with modified closed loop control. The first anti-body loop uses the thermocouple and the first closed loop control algorithm to adjust the substrate temperature, but the temperature set point of the first closed loop control algorithm is adjusted by the second closed loop control algorithm. The second closed-loop control algorithm uses the temperature dependence of the optical absorption edge of the substrate to measure the substrate temperature, and then adjusts the temperature set point of the first closed-loop control algorithm to maintain a constant substrate temperature. In this way, the modified closed-loop control algorithm maintains a constant substrate temperature despite changes in the absorptivity of the substrate.

Scan 702 includes peak 710, and scan 704 includes peaks 706 and 708. Peaks 706 and 710 are aligned, indicating that the temperature is kept constant with effective closed loop control during the growth of the low-energy band gap InGaNAsSb material. The peak 708 is the second peak on the scan 704 and is caused by the composition change caused by the temperature change during the initial growth of the InGaNAsSb layer. However, scans 702 and 704 are very matched, indicating that under effective temperature control, high-quality InGaNAsSb can be grown on semi-insulating GaAs substrates.

FIG. 8 depicts a graph 800 showing the influence of the In/Sb ratio measured by the Hall effect on the carrier properties of InGaNAsSb. The graph 800 includes a carrier concentration curve 802 and a carrier mobility curve 804. The decrease in the In/Sb ratio during deposition below about 6 results in a higher carrier concentration, as shown by curve 802. Increasing the In/Sb during the deposition period above about 6 has no significant effect on the carrier concentration, which is also shown by the curve 802. However, measured by the Hall effect The hole mobility rate consistently increases as the In/Sb ratio during deposition increases from 2 to 14, as shown by curve 804.

FIG. 9 depicts a graph 900 showing the influence of the In/Sb ratio measured by photoluminescence (PL) on the optical properties of InGaNAsSb. The graph 900 includes an energy band gap curve 902 and a PL intensity curve 904. As the In/Sb ratio varies between 2 and 14, the energy band gap varies between approximately 0.811 eV and 0.803 eV, and the minimum energy band gap is when the In/Sb ratio is 10. The PL intensity varies with the In/Sb ratio between 2 and 14 rather than monotonously. The minimum value is when the In/Sb ratio is 2, and the maximum value is when the In/Sb ratio is 6. A higher PL intensity indicates a higher quality InGaNAsSb layer.

A lower In/Sb ratio results in a lower energy band gap, which may be desirable for certain applications. However, a decrease in the In/Sb ratio below about 6 will cause an increase in the background carrier concentration, which will cause an increase in the dark current. When InGaNAsSb materials are used for p-i-n diodes as light detectors, a higher dark current will increase the background noise level, thereby reducing the signal-to-noise level. Therefore, it is desirable to reduce the energy band gap while maintaining the background carrier concentration.

FIG. 10 depicts a graph 1000 showing the influence of the growth temperature and As flux on the carrier concentration of InGaNAsSb measured by the Hall effect. Graph 1000 includes curves 1002, 1004, and 1006, showing that the As flux increases by 25% and decreases by 25% at growth temperatures of 420°C, 440°C, and 460°C (ie, the substrate temperature during growth) for carrier concentration, respectively The impact. Higher growth temperature results in lower background carrier concentration. In this study, a growth temperature of 460°C resulted ^{in a background carrier concentration of approximately 4×10 15} cm ^-3 , as shown by curve 1006. The As flux has a small effect on the background carrier concentration, but generally, a lower As flux results in a lower background carrier concentration, as shown by curves 1004 and 1006.

FIG. 11 depicts a graph 1100 showing the influence of growth temperature and arsenic flux on the energy band gap of InGaNAsSb measured by photoluminescence. The graph 1100 includes curves 1102, 1104, and 1106, showing the effect of increasing the As flux by 25% and decreasing the As flux by 25% on the energy band gap at growth temperatures of 420°C, 440°C, and 460°C, respectively. The energy band gap of InGaNAsSb exhibits only a weak dependence on the growth temperature between 420°C and 460°C, ranging from as low as 0.79 eV to as high as 0.82 eV. The energy band gap of InGaNAsSb also exhibits a weak dependence on As flux, where an As flux of 1 (nominal value) usually forms the highest energy band gap in the flux range in this study.

FIG. 12 depicts a graph 1200 showing the effect of rapid thermal annealing (RTA) on the carrier concentration of InGaNAsSb measured by the Hall effect. The graph 1200 includes curves 1202 and 1206 corresponding to an RTA temperature of 780°C, a curve 1208 corresponding to an RTA temperature of 800°C, and curves 1210 and 1212 corresponding to an RTA temperature of 820°C. Generally, InGaNAsSb is briefly annealed at a lower temperature to form a lower background carrier concentration, which is within the RTA parameters examined in this study. For a given RTA temperature, a shorter RTA duration results in a lower carrier concentration, as shown by curves 1202, 1206, 1210, and 1212. For a given RTA duration, a lower RTA temperature results in a lower carrier concentration, as shown by curves 1202, 1206, 1210, and 1212. The carrier concentration decreases with RTA temperature especially obviously. Decreasing the RTA temperature from 820°C to 780°C reduced the carrier concentration from 3×10 ¹⁶ cm ^-3 (curve 1212) to 7×10 ¹⁴ cm ^-3 (curve 1202), a decrease of more than one order of magnitude.

FIG. 13 includes graphs 1300 showing the effect of RTA on the energy band gap of InGaNAsSb measured by photoluminescence. The graph 1300 includes curves 1302 and 1306 corresponding to an RTA temperature of 780°C, a curve 1308 corresponding to an RTA temperature of 800°C, and curves 1310 and 1312 corresponding to an RTA temperature of 820°C. The effect of RTA on the energy band gap is similar to the effect on carrier concentration. For a given RTA temperature, a shorter RTA duration results in a lower energy band gap, as shown by curves 1302, 1306, 1310, and 1312. For a given RTA duration, a lower RTA temperature results in a lower energy band gap, as shown by curves 1302, 1306, 1310, and 1312. Decreasing the RTA temperature from 820°C to 780°C reduces the energy band gap from approximately 0.81 eV (curve 1312) to approximately 0.797 eV (curve 1302).

FIG. 14 depicts a graph 1400 showing the photoluminescence spectrum of a 0.5 μm InGaNAsSb layer grown on a GaAs substrate. Graph 1400 includes a scan 1402 measured on a 0.5 μm InGaNAsSb layer grown on a GaAs substrate. Scan 1402 includes a peak 1404 with a wavelength of 1.5429 μm, which corresponds to an energy of 0.8036 eV. Scan 1402 includes a full width at half maximum 1406 of 121.3 nm, and a narrow width indicates good material quality.

Figure 15 includes a color map 1500 showing the cross-wafer variation of the energy band gap of a 0.5 μm InGaNAsSb layer grown on a 150mm GaAs substrate. The band gap range of this layer is between the minimum value of 0.799 eV at the center position 1502 and the maximum value of 0.813 eV at the edge position 1504. The average energy band gap is 0.806eV, and the standard deviation is 0.408%, or about 0.003eV. These variations can be caused by variations in precursor flow, substrate temperature, and/or other factors. However, these variations are relatively small and indicate good uniformity Great.

Figure 16 illustrates several examples of p-i-n diodes formed on a substrate with lattice parameter matching or nearly matching GaAs. FIG. 16 depicts semiconductors 1600, 1630, and 1660. The semiconductor 1600 includes a p-i-n diode 1602 epitaxially formed on a GaAs substrate 1606. The GaAs substrate 1606 thus provides an ideal substrate for homoepitaxial epitaxy of Ga-As-based p-i-n structures (such as p-i-n diode 1602). The substrate 1606 may include any of the substrates 114, 214, 314, and 414. The pin diode 1602 may include a pin diode including layers 102, 106, and 112; a pin diode including layers 202, 206, 208, and 212; a pin diode including layers 302, 304, 306, 310, and 312 pin diode; any one of the pin diodes including layers 402, 404, 406, 408, 410, and 412.

The semiconductors 1630 and 1660 each include a lattice designed layer on a silicon substrate. Each lattice designed layer has a first surface closest to the silicon substrate and a second (uppermost) surface opposite the silicon substrate. The first surface closest to the silicon substrate has a lattice parameter that matches or almost matches the lattice parameter of Si. This results in a low number of defects and/or dislocations in the lattice designed layer. The semiconductors 1630 and 1660 may include one or more layers (not shown) between the lattice designed layer and the silicon substrate. The second surface opposite to the silicon substrate has a lattice parameter that matches or nearly matches that of GaAs. When epitaxially grows a pin layer and/or a dilute nitride layer with a lattice constant that matches or nearly matches GaAs, this results in a low number of defects and/or dislocations. The low number of defects may include defects equivalent to or less than those that would occur in an _{In 0.53} Ga _{0.47 As layer grown on an InP substrate.}

x

1)層1634。漸變Si_xGe_1-x層1634為晶格經設計層。半導體1630亦包括在漸變Si_xGe_1-x層1634上磊晶形成之p-i-n二極體1632。漸變Si_xGe_1-x層1634之Si分率x通過其厚度從0變化至1。在與Si基板1635之界面，x=1且漸變Si_xGe_1-x層1634實質上僅含有Si。在與p-i-n二極體1632之界面，x=0且漸變Si_xGe_1-x層1634實質上僅含有Ge。如此，漸變Si_xGe_1-x層1634提供晶格參數從Si基板之晶格參數(5.43Å)至與GaAs之晶格參數(5.65Å)幾近匹配的Ge之晶格參數(5.66Å)的轉變。Ge及GaAs之晶格常數非常匹配，足以在Ge表面上磊晶生長高品質GaAs。如此，漸變Si_xGe_1-x層1634容許在Si基板上生長GaAs層。漸變Si_xGe_1-x層1634及矽基板1635一起包含具有晶格參數幾近匹配GaAs之頂表面的基板1636。基板1636可包括基板114、214、314、及414中任一者。p-i-n二極體1632可包括包含層102、106、及112之p-i-n二極體；包含層202、206、208、及212之p-i-n二極體；包含層302、304、306、310、及312之p-i-n二極體；包含層402、404、406、408、410、及412之p-i-n二極體中之任一者。 The semiconductor 1630 includes a graded Si _x Ge _1-x (0

x

1) Layer 1634. The graded Si _x Ge _1-x layer 1634 is a lattice designed layer. The semiconductor 1630 also includes a pin diode 1632 epitaxially formed _{on the graded Si x} Ge _{1-x layer 1634.} The Si fraction x of the graded Si _x Ge _1-x layer 1634 varies from 0 to 1 through its thickness. At the interface with the Si substrate 1635, x=1 and the graded Si _x Ge _1-x layer 1634 contains substantially only Si. At the interface with the pin diode 1632, x=0 and the graded Si _x Ge _1-x layer 1634 contains substantially only Ge. In this way, the graded Si _x Ge _1-x layer 1634 provides lattice parameters ranging from the lattice parameter of the Si substrate (5.43Å) to the lattice parameter of Ge (5.66Å) which almost matches the lattice parameter of GaAs (5.65Å). Change. The lattice constants of Ge and GaAs are very matched, enough to epitaxially grow high-quality GaAs on the Ge surface. As such, the graded Si _x Ge _1-x layer 1634 allows a GaAs layer to grow on the Si substrate. The graded Si _x Ge _1-x layer 1634 and the silicon substrate 1635 together include a substrate 1636 having a top surface with lattice parameters that almost match GaAs. The substrate 1636 may include any of the substrates 114, 214, 314, and 414. The pin diode 1632 may include a pin diode including layers 102, 106, and 112; a pin diode including layers 202, 206, 208, and 212; a pin diode including layers 302, 304, 306, 310, and 312 pin diode; any one of the pin diodes including layers 402, 404, 406, 408, 410, and 412.

The semiconductor 1660 includes a rare earth (RE)-containing layer 1664 formed epitaxially on a silicon substrate 1665. The RE-containing layer 1664 is a lattice designed layer. Rare earth elements are special types of elements on the periodic table (Sc, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu). The RE-containing layer may contain one or more rare earth elements. The semiconductor 1660 also includes a pin diode 1662 epitaxially formed on the RE-containing layer 1664. Generally, the RE-containing layer can be a rare earth oxide (REO), a rare earth silicide (RESi), or a phosphorous compound (RE-V, where V represents a group V element of the periodic table, in other words, N, P, As, Sb, or Bi) or any combination of REO, RESi, and/or phosphorous compounds. The composition of the RE-containing layer can be selected to match or nearly match the lattice parameters of GaAs at the interface between the RE-containing layer and the pin diode 1662. For example, the layer at the interface can be ErAs _x N _1-x , where x is about 0.9, which is lattice-matched or nearly matched with GaAs. The rare earth-containing layer may have a constant composition or be graded across its thickness. When gradual, the layer can be designed so that the part closest to Si is chemically and mechanically compatible with silicon. For example, gamma oxide can be used at or near the interface between silicon and the rare earth-containing layer due to its lattice parameters of silicon. Therefore, the RE-containing layer 1664 provides a template for epitaxial growth of the pin diode 1662. The RE-containing layer 1664 and the silicon substrate 1665 together include a substrate 1666 with a top surface that matches or almost matches GaAs with lattice parameters.

The substrate 1666 may include any of the substrates 114, 214, 314, and 414. The pin diode 1662 may include a pin diode including layers 102, 106, and 112; a pin diode including layers 202, 206, 208, and 212; a pin diode including layers 302, 304, 306, 310, and 312 pin diode; any one of the pin diodes including layers 402, 404, 406, 408, 410, and 412.

Figures 1 to 4 depict an n-type layer on the substrate, where the n The p-i-n structure of the optional multiplication layer on the type layer, the essential absorbent layer on the n-type layer or the optional multiplication layer, and the p-type layer on the essential absorbent layer. However, in some examples, the order of the layers may be different. For example, the p-type layer may be on the substrate, the intrinsic absorber layer may be on the p-type layer, and the n-type layer may be on the intrinsic absorber layer. In addition, a multiplication layer may be additionally included between the p-type layer and the intrinsic absorbent layer, or between the intrinsic absorbent layer and the n-type layer. The substrates depicted in Figures 1 to 4 and 16 can be n-type, p-type, highly doped, non-intentionally doped, insulating, conductive, or a combination of these.

The layers of semiconductors 100, 200, 300, 400, 1600, 1700, and 1800 can be epitaxially formed by semiconductor processing techniques such as molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), halide gas Phase epitaxy (HVPE), physical vapor deposition (PVD), and/or sputtering. All these layers of semiconductors can be formed in a single chamber, or different layers of semiconductors can be formed in different chambers. For example, the epitaxial layers of the substrates 114, 214, 314, 414, 1606, 1636, and 1666 may be formed in a different chamber from the epitaxial layer of the corresponding p-i-n diode. Then, the semiconductors 100, 200, 300, 400, 1600, 1700, and 1800 are laterally patterned using photolithography, etching, and metal deposition techniques to manufacture detectors.

From the above description of the method, it is clear that various techniques can be used to implement the method concept without violating its scope. The implementation aspects should be regarded as illustrative and non-limiting from all aspects. It should be understood that this method is not limited to the specific examples described herein, but can be implemented in other examples without departing from the scope of the patent application. Described in this article and/ Or the first layer depicted on the second layer may be immediately adjacent to the second layer, or there may be one or more intermediate layers between the first and second layers. Similarly, although the operations are depicted in a specific order in the drawings, it should be understood that these operations are required to be performed in the specific order shown or in a sequential order, or all the operations shown in the figures are performed to achieve the desired result.

100‧‧‧Semiconductor

102,112‧‧‧III-V floor

106‧‧‧Dilute nitride layer

114‧‧‧Substrate

Claims (28)

A semiconductor comprising: a substrate with lattice parameter matching or nearly matching GaAs; a first doped III-V layer on the substrate; an absorber layer on the first doped III-V layer , The absorbent layer has: diluted nitride, including In _x Ga _1-x N _y As _1-yz Sb _z (0

x

1; 0<y

1; 0<z

1); The In/Sb ratio is at least about 6; the band gap is between about 0.7eV and 0.95eV, and the carrier concentration at room temperature is less than about 1×10 ¹⁶ cm ^-3 ; and The second doped III-V layer on the absorber layer. For example, the semiconductor of item 1 in the scope of patent application, wherein the diluted nitride contains In _x Ga _1-x N _y As _1-yz Sb _z (0

x

0.55; 0<y

0.1; 0<z

0.1). Such as the semiconductor of item 1 in the scope of patent application, wherein the carrier concentration of the absorber layer is less than about 5×10 ¹⁵ cm ^-3 . For example, the semiconductor of item 1 in the scope of patent application, wherein the carrier concentration of the absorber layer is less than about 1×10 ¹⁵ cm ^-3 . Such as the semiconductor of the first item in the scope of patent application, wherein the thickness of the absorbent layer is between about 2 microns and about 10 microns. Such as the semiconductor of the first item of the patent application, wherein the thickness of the absorber layer is between about 3 microns and about 5 microns. For example, the semiconductor of item 1 in the scope of the patent application further includes a multiplication layer between the absorber layer and one of the first and second doped III-V layers. For example, the semiconductor of item 1 in the scope of patent application, wherein the substrate contains GaAs. For example, the semiconductor of the first item in the scope of patent application, wherein the substrate includes: a silicon substrate; and a lattice engineered layer on the silicon substrate, and the surface of the lattice engineered layer has lattice parameters and GaAs matched or nearly matched opposite to the silicon substrate. For example, the semiconductor of item 9 of the scope of patent application, wherein the lattice designed layer includes a Si _x Ge _1-x layer, and x is gradually changed from 1 on the surface _{of the Si x} Ge _1-x layer closest to the silicon substrate to The surface of the Si _x Ge _1-x layer opposite the silicon substrate is zero. Such as the semiconductor of item 9 in the scope of patent application, wherein the lattice designed layer includes a rare earth-containing layer, and the rare earth-containing layer includes Sc, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy One or more of, Ho, Er, Tm, Yb, and/or Lu. Such as the semiconductor of item 1 in the scope of patent application, wherein the first doped III-V layer is n-type and the second doped III-V layer is p-type. Such as the semiconductor of item 1 in the scope of patent application, wherein the first doped III-V layer is p-type and the second doped III-V layer is n-type. For example, the semiconductor of item 1 in the scope of patent application, where the absorber The layer is p-type. A method for forming a semiconductor, comprising: forming a first doped III-V layer on a substrate with lattice parameter matching or nearly matching GaAs; forming an absorber layer on the first doped III-V layer , The absorbent layer has: diluted nitride, including In _x Ga _1-x N _y As _1-yz Sb _z (0

x

1; 0<y

1; 0<z

1); The In/Sb ratio is at least about 6; the band gap is between about 0.7eV and 0.95eV, and the carrier concentration at room temperature is less than about 1×10 ¹⁶ cm ^-3 ; and A second doped III-V layer is formed on the absorber layer. Such as the method of item 15 in the scope of patent application, wherein the diluted nitride contains In _x Ga _1-x N _y As _1-yz Sb _z (0

x

0.55; 0<y

0.1; 0<z

0.1). Such as the method of item 15 in the scope of the patent application, wherein the carrier concentration of the absorbent layer is less than about 5×10 ¹⁵ cm ^-3 . Such as the method of item 15 in the scope of the patent application, wherein the carrier concentration of the absorbent layer is less than about 1×10 ¹⁵ cm ^-3 . Such as the method of claim 15, wherein the thickness of the absorbent layer is between about 2 micrometers and about 10 micrometers. Such as the method of claim 15, wherein the thickness of the absorbent layer is between about 3 micrometers and about 5 micrometers. Such as the method of claim 15, further comprising forming a multiplication layer between the absorber layer and one of the first and second doped III-V layers. Such as the method of claim 15 in which the substrate contains GaAs. For example, the method of claim 15, wherein the substrate includes: a silicon substrate; and a lattice designed layer on the silicon substrate, and the surface of the lattice designed layer has a lattice parameter that matches or is almost close to that of GaAs. Match the opposite side of the silicon substrate. Such as the method of item 23 in the scope of the patent application, wherein the lattice designed layer includes a Si _x Ge _1-x layer, and x is gradually changed from 1 on the surface _{of the Si x} Ge _1-x layer closest to the silicon substrate to at The surface of the Si _x Ge _1-x layer opposite the silicon substrate is zero. Such as the method of item 23 in the scope of the patent application, wherein the lattice designed layer includes a rare earth-containing layer, and the rare earth-containing layer includes Sc, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy One or more of, Ho, Er, Tm, Yb, and/or Lu. Such as the method of claim 15, wherein the first doped III-V layer is n-type and the second doped III-V layer is p-type. Such as the method of claim 15, wherein the first doped III-V layer is p-type and the second doped III-V layer is n-type. For example, the method of item 15 in the scope of patent application, wherein the absorbent The layer is p-type.

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