TWI714192B - Method for detecting operation state and obtaining operation current of flash memory - Google Patents

Abstract

A method for detecting operation state of flash memory is provided. The flash memory includes a plurality of blocks and each block includes a plurality of pages. The detecting method includes performing a specific operation on at least one page of the pages of the flash memory, generating a differential voltage corresponding to the at least one page of the pages, outputting a current value according to the differential voltage, and determining the operating state of the at least one page of the pages of the flash memory according to the current value. Herein, the specific operation is one of a block erase, a page program and a read operation, and the outputted current value corresponds to the specific operation on the at least one page of the pages. Therefore, it is instantly decided if the memory works properly.

Description

Method for detecting operating state of flash memory and method for obtaining operating current

The invention relates to a memory controller, particularly a NAND flash memory controller.

NAND Flash memory is mostly used in solid state drives (SSD), flash drives and memory cards based on its memory characteristics.

Each cell of the NAND flash memory represents its stored information according to its voltage level. Take the Triple-Level Cell (TLC) as an example. Each three-level storage cell can store 8 different contents, including: 111,011,001,101,100,000,010,110. Each of these 8 contents corresponds to an erase level (Erase State). ) And one of 7 programming levels (Program States). Specifically, when the recording voltage of a third-level storage unit falls at a certain level, it means that the content stored in the third-level storage unit is the content corresponding to the level.

NAND flash memory is to ensure the correctness of written data, after writing a storage unit, the controller inside the flash memory reads the voltage of the storage unit and determines whether the voltage reaches a predetermined voltage range (above Corresponding to the lower limit of the level), if it does not reach the predetermined voltage range, it will be written again until the voltage of the storage cell reaches the predetermined voltage range. This mechanism is generally referred to as verification. Therefore, for the storage unit with better characteristics or early life, its The operating voltage is low or the number of writes is still small; for the storage cells with poor characteristics or worn out, they may have been repeatedly written to form each storage cell, memory page, and memory block in the NAND flash memory The number of writes is different, and the number of flash memory programming and erasing directly affects its service life. In order to avoid a large amount of damage to the NAND flash memory in a short period of time, the industry has made several judgments. Whether the NAND flash memory is damaged.

One way is to judge the possible life of the NAND flash memory by monitoring whether the Error Correct Code (ECC) has an increasing trend. However, because the flash memory has the above verification mechanism, the ECC will not change significantly under normal operating conditions. Therefore, if you monitor the ECC, when you find that the ECC is so high, it is often the flash memory. A certain block is approaching the end of its life. Therefore, the method of monitoring ECC cannot effectively know the current life status of the flash memory.

One way is to use the cell voltage distribution graph (Cell Voltage Distribution) to make judgments. The threshold voltage distribution graph refers to plotting the recording voltage of each storage cell in the entire page or block on a graph , The horizontal axis of the graph is voltage, and the vertical axis is the number of storage cells. When the flash memory is in normal state, the voltage of each storage cell in the voltage distribution diagram will fall at the corresponding level. When the flash memory is in an abnormal state, the number of storage units falling at the corresponding level will be greatly reduced. As mentioned above, because the flash memory has the above-mentioned verification mechanism, when the threshold voltage distribution graph is abnormal, the flash memory is also near the end of its life. Therefore, this method is not effective in knowing the flash memory at the time. Life state.

The aforementioned method only has the ability to recognize that the flash memory is approaching the end of its life. The known method requires offline (removing the NAND flash memory from the storage device or system) to operate. For example, another way is through external circuits or external instruments (for example: high-order oscilloscope The device is equipped with a high-frequency current check table) and the solid state drive is connected to analyze whether it is abnormal. However, this method can only be operated and analyzed in an offline (offline) situation, and cannot meet the requirements of online analysis. As mentioned above, when an abnormality is found, the flash memory is also approaching the end of its life.

The aforementioned traditional methods only have the ability to recognize that the flash memory is approaching the end of its life, but do not have the ability to effectively and instantly know the current operating status of the flash memory.

Therefore, how to provide a detection system and method that can effectively and instantly know the current operating status of the flash memory has become an important issue in the industry.

In view of the above, this case proposes a method for detecting the operating status of the flash memory. Here, the flash memory includes a plurality of blocks, and each block includes a plurality of pages. The detection method includes: performing a specific operation on at least one of the plurality of pages of the flash memory, generating a differential voltage corresponding to the specific operation of at least one of the plurality of pages, and outputting a differential voltage according to the differential voltage. The current value and the operating state of at least one page among the plurality of pages of the flash memory are determined according to the current value. Wherein, the specific operation is at least one of a block erase (Block Erase), a page program (Page Program), and a read operation, and the output current value corresponds to at least one of the plurality of pages Specific operations.

This case also proposes a method for obtaining the operating current of the flash memory. Here, the flash memory includes a plurality of blocks, and each block includes a plurality of pages. The obtaining method includes: performing a specific operation on at least one of the plurality of pages in a flash memory, corresponding to the current generation during the specific operation of at least one of the plurality of pages in the flash memory A differential voltage, generating multiple levels based on a single-level signal, based on the sub-voltage and these bits A digital signal is output, and the current value is output based on the level signal and the digital signal. The specific operation is at least one of a block erase, a page programming, and a read operation, and the output current value corresponds to the specific operation of at least one of the plurality of pages.

To sum up, according to some embodiments, the flash memory controller can obtain the current value consumed by a specific page/block of the flash memory in real time, and determine the specific page/block of the flash memory accordingly Is it operating normally. According to some embodiments, the storage device with the flash memory controller can instantly determine whether a specific page/block of the flash memory is operating normally.

10: storage device

20: NAND flash memory

30: Voltage supply circuit

200: block

40: Flash memory controller

42: Flash control circuit

44: current sensing circuit

46: processor

440: Current to Voltage Circuit

441: resistor

442: sensing control circuit

444: level generating circuit

445a: adjustable current source

445b: resistor

446: Flash analog to digital circuit

448: M to N encoding circuit

447a, 447b, 447c, 447d: differential comparator

DI: Input pin

DO: output pin

PRG: Programming interval

Vip, Vin: differential voltage

Vrm,Vrm-1...,Vr1,Vr0: level

FIG. 1 is a schematic block diagram of the circuit of an embodiment of the storage device of the present invention.

FIG. 2 is a circuit block diagram of an embodiment of the current sensing circuit of the present application.

FIG. 3 is a circuit block diagram of an embodiment of the flash analog to digital circuit in this case.

FIG. 4 shows a schematic diagram of the current sensing result of an embodiment of the current sensing circuit in this case.

Fig. 5 is a partial enlarged schematic view of the position marked 5-5 in Fig. 4;

Please refer to FIG. 1. FIG. 1 is a circuit block diagram of an embodiment of the storage device of the present invention. The storage device 10 includes a NAND flash memory 20, a voltage supply circuit 30, and a flash memory controller 40.

The storage device 10 can be any storage device with a NAND flash memory 20. In some embodiments, the storage device 10 is a solid state drive (SSD), a flash drive, or a memory card.

The voltage supply circuit 30 is used to provide a current to the flash memory 20. Flash The memory controller 40 is suitable for the NAND flash memory 20 and the voltage supply circuit 30. The flash memory controller 40 controls the operation of the flash memory 20, which includes programming (Program), erasing (Erase) and reading Take, among them, programming and erasing can be collectively referred to as writing. The flash memory 20 includes a plurality of blocks (Block) 200, and each block 200 includes a plurality of pages (Page, not shown). When the flash memory 20 is erased, the block erase (Block) Erase); When the flash memory 20 is programmed, Page Program is used. When the flash memory 20 is programmed, erased, and read, the amount of current required is different, and this current is supplied by the voltage supply circuit 30.

The aforementioned flash memory controller 40 includes a flash control circuit 42, a current sensing circuit 44, and a processor 46. The flash control circuit 42 is used to control the writing of the flash memory 20. Specifically, the flash control circuit 42 controls the programming and erasing of the flash memory 20. In addition, the flash control circuit 42 also controls the reading of the flash memory 20 and other operations. The flash control circuit 42 is controlled by the processor 46, and the flash control circuit 42 controls the flash memory 20 to write or read.

The current sensing circuit 44 is used to measure the current of the flash memory 20. For example, the current sensing circuit 44 is used to measure the current of the flash memory 20 during the writing, and output a current value. Specifically, the current-to-voltage circuit 440 of the current sensing circuit 44 is connected between the voltage supply circuit 30 and the flash memory 20 (between the power supply lines), and the current-to-voltage circuit 440 has a current sensor. The current sensor is, for example, but not limited to, a resistor 441. When the voltage supply circuit 30 provides current to the flash memory 20 through the current-to-voltage circuit 440, a differential voltage (Vip ,Vin, Vip is called P potential, and Vin is called N potential), the current sensing circuit 44 divides the differential voltage (Vip, Vin) by the impedance of the current sensor (for example, but not limited to, the impedance of resistor 441) , You can get flash memory 20 in The current value consumed during the writing. Similarly, the current sensing circuit 44 can also be used to measure the current consumed by the flash memory 20 during the erasing or reading, and output a current value.

The processor 46 is used for outputting a control signal according to the current value. Specifically, the processor 46 receives the current value output by the current sensing circuit 44, and outputs a control signal according to the current value. In some embodiments, when the current value of the processor 46 exceeds the preset upper limit of the single programming current, the control signal output by the processor 46 is an abnormal signal, and the flash memory error location can be recorded. The foregoing upper limit of the single programming current may be the value of the abnormal current that the flash memory 20 consumes when performing a single programming.

Other embodiments in which the processor 46 outputs the control signal according to the current value will be described in detail later.

Therefore, it can be seen from the above description that the flash memory controller 40 can measure the current consumed by the flash memory 20 during programming, erasing, and reading operations in real time through the current sensing circuit 44. The processor 46 can determine whether the operating state of the flash memory 20 is maintained in a normal state according to the current value. In this real-time measurement, in addition to operating the flash memory 20, the processor 46 can know whether a page or a block is damaged in real time. The processor 46 can also collect a sufficient number of current values (according to the timing), A statistical method is used to predict the time when the flash memory 20 may be damaged, or the number of writes, erases, or reads that can be used.

Secondly, the current-to-voltage circuit 440 of the current sensing circuit 44 in FIG. 1 is located outside the flash memory controller 40, but in some embodiments, the current-to-voltage circuit 440 is built in the flash memory controller Within 40, the current output by the voltage supply circuit 30 is still transmitted to the flash memory 20 through the current-to-voltage circuit 440.

Please continue to refer to Figure 2. Figure 2 illustrates the circuit of an embodiment of the current sensing circuit in this case Block diagram. In some embodiments, the aforementioned current sensing circuit 44 includes a current to voltage circuit 440, a sensing control circuit 442, a level generating circuit 444, and a flash analog to digital circuit 446.

The current-to-voltage circuit 440 is connected between the voltage supply circuit 30 and the flash memory 20 and is used to convert the current into a differential input. The node A of the current-to-voltage circuit 440 in FIG. 2 is connected to the voltage supply circuit 30, and the node B is connected to flash memory 20. When the flash control circuit 42 controls the flash memory 20 to write (program or erase) or read, the current provided by the voltage supply circuit 30 passes through the resistor 441. The two ends (nodes) of the resistor 441 A, B) each has a P potential Vip and an N potential Vin, which means that the resistor 441 has a differential voltage (Vip, Vin) at both ends, and the current sensing circuit 44 uses the difference of the differential voltage (Vip -Vin) is divided by the impedance of the resistor 441 to obtain the current value.

The sensing control circuit 442 is used to generate a quasi signal. This level signal is related to the current value. When the level signal is higher, the range of the current value that can be measured is larger, and when the level signal is lower, the range of the current value that can be measured is smaller, which will be described later.

The level generating circuit 444 is used for generating a plurality of levels Vrm, Vrm-1..., Vr1, Vr0 according to the level signal. The number of the levels of the level generating circuit 444 is the resolution of the current sensing circuit 44. For example, if the level generating circuit 444 can generate 2 to 3 levels, the flash analog-to-digital circuit 446 is configured to express the output in two bits (2bits), that is, DO[1:0]. If the level generating circuit 444 can generate 4 to 7 levels, the flash analog-to-digital circuit 446 is configured to express the output in three bits (3 bits), that is, DO[2:0].

In some embodiments, the level generating circuit 444 includes an adjustable current source 445a and a plurality of resistors 445b. The adjustable current source 445a is used to generate correspondingly according to the level signal A reference current. The resistors 445b are connected in series in sequence, and the resistors 445b receive the reference current to generate the levels Vrm, Vrm-1..., Vr1, Vr0.

The aforementioned sensing control circuit 442 uses the level signal to control the magnitude of the reference current generated by the adjustable current source 445a. When the level signal is higher, the reference current is greater, and when the level signal is lower, the reference current is The smaller. When the reference current is larger, the voltage difference between the two ends of the resistors 445b in series is larger. Therefore, the level generating circuit 444 can generate the maximum voltage difference (Vrm-Vr0) at the same resolution. That is, the greater the difference (corresponding to the current value) of the differential voltage measured by the sensing control circuit 442 is greater. On the contrary, when the reference current is smaller, the voltage difference between the two ends of the resistors 445b in series is smaller. Therefore, the level generating circuit 444 can generate the maximum voltage difference (Vrm -Vr0) is smaller, the difference of the differential voltage measured by the sensing control circuit 442 is smaller.

The aforementioned flash analog to digital circuit 446 is used to output a digital signal according to the differential voltage (Vip-Vin) and the levels Vrm, Vrm-1,...,Vr0. In some embodiments, the flash analog to digital circuit 446 is the difference between the differential voltage (Vip, Vin) and the difference between the levels Vrm, Vrm-1,...,Vr0 (Vrm-Vr0, Vrm -1-Vr0,...,Vr1-Vr0, etc.) to obtain the level difference corresponding to the difference (Vip-Vin) of the differential voltage. The flash analog to digital circuit 446 will compare the corresponding The level difference value is converted into a binary value and the binary value is output as the digital signal. The digital signal corresponds to the level difference.

The sensing control circuit 442 outputs the current value according to the level signal and the digital signal, which will be described in detail later.

Please refer to FIG. 3 for reading. FIG. 3 shows a circuit block diagram of an embodiment of the flash analog-to-digital circuit in this case. The flash analog to digital circuit 446 includes a plurality of differential comparators 447a, 447b,...,447c, 447d and an M to N encoder logic 448 (M to N encoder logic), each of the differential comparators 447a, 447b,...,447c, 447d receives and compares the difference of the aforementioned differential voltage (Vip-Vin) and the corresponding level difference Vrm,Vrm-1...,Vr2,Vr1,Vr0, when the difference of the differential voltage (Vip-Vin) is greater than the corresponding level difference Vrm,Vrm-1 When ...,Vr2,Vr1,Vr0, the differential comparators 447a,447b,...,447c,447d output 1 (high level), otherwise, output 0 (low level). Therefore, when the difference (Vip-Vin) of the differential voltage falls between the levels Vrm and Vrm-1, the first differential comparator 447a outputs 0, and the remaining differential comparators 447b,...,447c, 447d output 1 .

The M-to-N encoding circuit 448 is used to encode the input signal, convert it into a binary value, and output the digital signal. Continuing with the above example, if the flash analog to digital circuit includes 4 differential comparators 447a, 447b, 447c, 447d, the first differential comparator 447a outputs 0, and the remaining differential comparators 447b, 447c, 447d output 1, this When the value received by the M-to-N encoding circuit 448 is 0,1,1,1 from top to bottom, the M-to-N encoding circuit 448 will encode it as DO[2:0]=011 (binary). The M-to-N encoding circuit 448 can be implemented by a logic circuit.

Please refer to FIG. 2 again, following the example of the flash analog to digital circuit 446, if the number of the resistors 445b is 4 and the resistance value of each resistor 445b is the same as 1k ohm, the output of the sensing control circuit 442 The level signal makes the reference current output by the adjustable current source 445a 10uA, and the level generated by the level generating circuit 444 is 0mV, 10mV, 20mV, 30mV and 40mV, and the voltage difference of these levels includes 10mV, 20mV, 30mV and 40mV, that is, the aforementioned differential comparators 447a, 447b, 447c, and 447d respectively receive level voltage differences of 40mV, 30mV, 20mV, and 10mV. When the digital signal output value is DO[2:0]=011 (binary), it means that the differential voltage output by the current-to-voltage circuit 440 is 30-40 corresponding to DO[2:0]=011 between mV. If the resistance of the resistor 441 is 0.5 ohm, the current of the flash memory during the writing is between 60-80 mA.

Following the example of the flash analog to digital circuit 446, if the number of the resistors 445b is 4 and the resistance value of each resistor 445b is the same as 1k ohm, the level signal output by the sensing control circuit 442 is such that The reference current output by the adjustable current source 445a is 20uA, and the levels generated by the level generating circuit 444 are 0mV, 20mV, 40mV, 60mV and 80mV, and the voltage difference of these levels includes 20mV, 40mV, 60mV and 80mV. That is, the aforementioned differential comparators 447a, 447b, 447c, and 447d respectively receive level voltage differences of 80mV, 60mV, 40mV, and 20mV. When the digital signal output value is DO[2:0]=011 (binary), it means that the differential voltage output by the current-to-voltage circuit 440 is between 60-80mV corresponding to DO[2:0]=011. If the resistance of the resistor 441 is 0.5 ohm, the current of the flash memory during the writing is between 120-160 mA.

It can be seen from the above two examples that the flash analog-to-digital circuit 446 outputs the same digital signal. The voltage value represented by the same digital signal is related to the aforementioned level. The higher the level (level voltage difference), the same digital signal The voltage value represented is greater; when the level (level voltage difference) is lower, the voltage value represented by the same digital signal is smaller. As mentioned above, these levels are determined by the level signal from the sensing control circuit 442. Therefore, the sensing control circuit 442 can obtain the corresponding voltage value and current value according to the level signal and the digital signal.

Secondly, during operation, the sensing control circuit 442 continuously obtains multiple current values. When the digital signal continuously received by the sensing control circuit 442 is the upper limit of the output of the flash analog to digital circuit 446 (in the foregoing example, The upper limit is DO[2:0]=100), which means that the continuously received differential voltage is higher than the highest level voltage difference generated by the level generating circuit 444 (Vrm-Vr0), therefore, the sensing control circuit 442 raises the level signal so that the current sensing circuit 44 can further measure the actual differential voltage value of the differential voltage; on the contrary, when the sensing control circuit 442 The continuously received digital signal is the lower limit of the output of the flash analog to digital circuit 446 (in the foregoing example, the lower limit of the output is DO[2:0]=000), which means that the continuously received differential voltage is all Is lower than the lowest level voltage difference (Vr1-Vr0) generated by the level generating circuit 444, therefore, the sensing control circuit 442 lowers the level signal so that the current sensing circuit 44 can further measure the difference The actual differential voltage value of the voltage.

It can be seen from the above description that the sensing control circuit 442 receives a plurality of the digital signals according to a time sequence, and adjusts the level signal according to the digital signals. Specifically, the sensing control circuit 442 determines the magnitude of the level signal output by the continuously obtained current value, so as to more accurately measure the current value consumed by the flash memory 20. When most of the digital signals continuously received by the sensing control circuit 442 (such as but not limited to 90% of the digital signals continuously received) are between the upper and lower output limits of the flash analog to digital circuit 446, it means that the current If the level signal is appropriate, the sensing control circuit 442 maintains the level signal. Secondly, when the flash memory controller 40 starts to operate, the sensing control circuit 442 can use a preset value as the level signal, and after a period of time adjustment of the level signal, the appropriate level can be obtained. Quasi-signal. The preset value can be designed or tested in the flash memory controller 40 and obtained by experiment.

The sampling frequency of the flash analog to digital circuit 446 is related to the time of a single programming, erasing, and reading of the flash memory 20. Take the time-current diagram of the flash memory 20 in FIG. 5 as an example (detailed later) ), the figure shows that a single programming time is about 5 microseconds (us). If you want to obtain 5 sampling points (to obtain 5 digital signals) within a single programming time, the sampling frequency of the flash analog to digital circuit 446 can be 1MHz.

In order to help understand some embodiments in which the processor 46 outputs a control signal according to the current value consumed by the flash memory 20, the time-current diagram drawn by the multiple current values received by the processor 46 will be described first. Please refer to FIG. 4 and FIG. 5 at the same time. FIG. 4 shows a schematic diagram of a current sensing result of an embodiment of the current sensing circuit of the present application. Fig. 5 is a partial enlarged schematic view of the position marked 5-5 in Fig. 4;

4 shows that according to some embodiments, when the processor 40 performs data programming operations on the flash memory 20 via the flash control circuit 42, the processor 46 continuously receives the current value output by the current sensing circuit 44 and plots it as Time-current graph, the horizontal axis is time (from 730 milliseconds (us) to 9.73 microseconds (ms)), and the vertical axis is the magnitude of current. The upper curve in the time-current graph represents the current value during programming, and the lower curve represents the ongoing program of the flash memory 20. For example, the time interval marked PRG in the figure indicates that the flash memory 20 is being programmed, and the time interval between two adjacent programming PRG intervals is for the flash control circuit 42 to transmit data to the flash memory 20 . Similarly, when the processor 46 performs data erasing operations on the flash memory 20 through the flash control circuit 42, the erasing time-current graph can also be obtained; when the processor 46 erases the flash memory 20 through the flash control circuit 42 When the memory 20 is performing a data reading operation, a time-current graph of reading can also be obtained.

As can be seen in Figure 5, the noise level current value is about 44.8mA. In the interval of 3.92ms to 4.42ms, the maximum current during programming is about 40mA (ie 84.8-44.8mA), and in the programming time interval, the lower current is about 5.2mA (ie 50-44.8mA). From the multiple current values in the PRG interval in Figure 5, it can be seen that most of the measured current values (called programming current values, which will be described later) are between 5.2mA and 40mA, and there is no excessive current value at the lower limit. Or upper limit, which means that the level signal output by the sensing control circuit 442 is appropriate, and there is no need to increase or decrease the level signal.

The single programming interval (PRG) in Figure 4 corresponds to the programming of a specific page (called page Programming), as shown in Figure 5, the time interval of 3.92-4.42ms corresponds to the "page programming" of a specific page. Each "page programming" includes multiple "programming tasks", that is, the peak value of each current in Figure 5 Each corresponds to a programming operation of the flash memory 20 for the page, and the current value measured during a single programming operation is called the programming current value. The aforementioned programming operation means that after the flash memory 20 receives the data to be written (including programming and erasing) from the flash control circuit 42 (the written data correspond to 111,011,001,010,100,000,101,110, and are divided into eight groups) , A programming operation (the first time) is performed on each memory cell (Cell) in the written page. In some embodiments, the programming pulse voltage (Program Pulse Voltage) used in the first programming operation is ) Is the lowest voltage level corresponding to the aforementioned 1 erase level (Erase State) and 7 programming levels (Program States). After the first programming operation is completed, it will be judged to write the lowest voltage level Whether the storage unit of the storage unit has the lowest voltage level (called Verification), if the lowest voltage level has been reached, the flash memory 20 will not perform the next (second) programming operation on these storage units The pre-program pulse voltage (Program Pulse) means that the flash memory 20 only performs programming operations corresponding to the next lower voltage level to the remaining storage cells; when the flash memory 20 completes this second programming operation, Verification will also be performed, and so on, until the programming operation corresponding to the highest voltage level is completed. In other words, each storage cell is applied with a program pulse voltage (Program Pulse) from 1 to N times (N is a positive integer greater than 1) according to the data content it wants to store.

As mentioned above, in the normal situation of the flash memory 20, the programming of each storage cell (Cell) will be successful if the programming pulse voltage is applied 1 to N times, which means that the storage cell is programmed N times, namely The recording voltage stored in the storage unit can be made to fall within the corresponding programming level interval. The high current value in Figure 4 and Figure 5 corresponds to the storage cell with a higher number of programming operations (its storage The programming level of the data is higher), and the lower current value corresponds to the programming operation of the storage cell with a lower number of programming operations (the programming level of the stored data is lower). Take a three-level storage cell as an example. The programming level of data 011 is lower than that of data 110. Therefore, when flash memory 20 programs a certain storage cell 011, the current required is lower than that of programming 110 .

On the contrary, when a storage cell has been excessively worn or is approaching the end of its life, the number of programming operations for the storage cell by the flash memory 20 will be higher than the normal number, so that the recording voltage stored in the storage cell can meet the corresponding programming bit Therefore, the overall current consumption for programming the storage cell will be greater than that of the normal storage cell. If the entire page or block contains more memory cells that have been excessively worn or are nearing the end of their life, the total current consumption of the corresponding page or the block will increase. Therefore, the processor 46 can set the page total current The sum of the value, the block and the threshold are used to determine whether the page or the block is abnormal or will be abnormal.

The following describes some embodiments in which the processor 46 outputs a control signal according to the current value consumed by the flash memory 20.

In some embodiments, the processor 46 determines whether a certain page or a certain area in the flash memory 20 is in a normal state according to the current value, and outputs a corresponding control signal. Specifically, when the processor 46 receives multiple current values corresponding to a certain page, it determines whether the current values are normal. When the current values are normal, the processor 46 outputs the control signal as a normal signal, and processes When the current values are abnormal, the control signal output by the device 46 is an abnormal signal. The aforementioned current value may be the current value during the page writing operation, the current value during the page programming operation, the current value during the page erasing operation, or the current value during the page reading operation.

In some embodiments, the aforementioned judgment method based on multiple current values is as follows: when the sum of the total current values corresponding to a page is greater than a page and a threshold, the page is abnormal; Otherwise, the page is normal. The aforementioned pages and thresholds refer to the total amount of current consumed cumulatively when a page is written (including programming and erasing) in the flash memory 20. In some embodiments, when the sum of the total programming current values corresponding to a page is greater than the programming and threshold of a page, the page is abnormal; otherwise, the page is normal. The total current of the aforementioned page can also be the total current of page erasing, and the page and the threshold correspond to the page erasing and threshold.

In some embodiments, the foregoing judgment method based on a plurality of the current values is as follows: when the programming current value in a page is greater than a programming current upper limit and the proportion of the total number is greater than 20%, the page is It is abnormal; otherwise, the page is normal. The aforementioned programming current value refers to the current value measured during each programming operation of the flash memory 20 during page programming (Program), such as each peak value in FIG. 5; the upper limit of the programming current refers to the flash memory During a single programming operation of the body 20, if its current is greater than the upper limit of the programming current, it means that most of the storage cells on the page are likely to be nearly damaged. Therefore, if the total number of programming current values greater than the upper limit of programming current accounts for more than 20% of the total number of programming operations (ie, the number of programming operations in page programming) during page programming, it is determined that the page is abnormal.

In some embodiments, when the sum of the total current values corresponding to a certain block is greater than one block and the threshold, the block is abnormal; otherwise, the block is normal. The aforementioned block total current value and block and threshold can also be changed to the block total current value and block and threshold for programming and erasing. In some embodiments, the aforementioned judgment method based on a plurality of the current values is: when the proportion of each programming current value in a certain block that is greater than a programming current upper limit to the total number is greater than 20%, the The block is abnormal; otherwise, the block is normal.

In some embodiments, when the processor 46 receives a plurality of the current values, the processor 46 compares the currents with a predetermined current template to determine whether the current values are normal. Place When the current values of the processor 46 are normal, the control signal output is a normal signal; when the current values are abnormal, the control signal output is an abnormal signal. Wherein, the predetermined current template is the upper limit of the slope between pages, and the processor 46 judges the multiple current values of multiple pages continuously received, for example, averages the 10% highest current value in each page, and The average values of the consecutive pages are operated on the approach line and the slope of the approach line is obtained. When the slope of the approach line is greater than the upper limit of the slope of the consecutive pages, the processor 46 determines that the pages are abnormal or the pages are located. The block is abnormal, and the output control signal is abnormal.

The aforementioned processor 46 judging that a certain page or a certain block is abnormal according to the current value does not mean that the page or block is damaged, but is probably close to damage. Therefore, the abnormality may mean that it is about to be damaged. The aforementioned processor 46 judges that a certain page or a certain block is normal according to the current value, which means that the judgment method is not abnormal, but it does not mean that the page or block will not be judged as abnormal due to other judgment methods (it may be about damage). When the processor 46 determines that a certain page or a certain block is normal according to a certain judgment method, it may not output the control signal.

When the control signal output by the processor 46 is abnormal, the processor 46 can further indicate that the page or block corresponding to the abnormality is damaged, so as to avoid errors in the information written to the page or block. The processor 46 can be used with a bad block management mechanism (Bad Block Management, BBM) to manage the bad blocks.

The pages and thresholds, page programming and thresholds, page erasing and thresholds, programming current upper limit, total page current value, block and threshold, and page slope upper limit described in some of the above embodiments can be obtained through experiments. For example, it is possible to perform an aging test on multiple flash memories 20, and continuously measure their consumption current values, and after statistics and consideration of safety factors, these thresholds, sums and upper limits can be obtained; or for the same flash memory Different pages and blocks in body 20 undergo aging test, or any These thresholds, sums, and upper limits can be obtained by statistical forecasting methods.

To sum up, according to some embodiments, the flash memory controller can obtain the current value consumed by the flash memory in real time and determine whether the flash memory is operating normally. According to some embodiments, the storage device with the flash memory controller can instantly determine whether the flash memory is operating normally.

10: storage device

20: NAND flash memory

30: Voltage supply circuit

200: block

40: Flash memory controller

42: Flash control circuit

44: current sensing circuit

46: processor

440: Current to Voltage Circuit

441: resistor

Vip, Vin: differential voltage

Claims (9)

A method for detecting the operating status of a flash memory. The flash memory includes a plurality of blocks, and each block includes a plurality of pages. The detection method includes: At least one of the plurality of pages performs a specific operation, where the specific operation is at least one of a block erase (Block Erase), a page program (Page Program), and a read operation; A differential voltage corresponding to the specific operation of the at least one page of the plurality of pages; a current value is output according to the differential voltage, wherein the current value corresponds to the at least one page of the plurality of pages Specific operation; and judging the operating state of the at least one page of the plurality of pages of the flash memory according to the current value, wherein the step of outputting the current value according to the differential voltage includes: generating a complex signal according to a one-level signal Digital level, where the voltage difference between the levels is related to the level signal; a digital signal is output according to the differential voltage and the levels; and the current is output according to the level signal and the digital signal value. The detection method according to claim 1, further comprising: performing bad block management on the flash memory according to the current value. The detection method according to claim 1, further comprising: using a statistical method to predict a possible damage time of the flash memory according to the current value. The detection method according to claim 1, wherein the step of outputting the current value according to the differential voltage further includes: receiving a plurality of the digital signals according to a time sequence; and adjusting the level signal according to the digital signals. The detection method according to claim 1, wherein the step of judging the operating state of the at least one page of the plurality of pages of the flash memory according to the current value includes: receiving a plurality of the current values of different timings , Wherein the current values correspond to the operation on the same part of the flash memory. The detection method according to claim 5, wherein the step of judging the operating state of the at least one page of the plurality of pages of the flash memory according to the current value further includes: when at least one of the following conditions is met, judging The same part is an abnormality: the sum of the current values is greater than a threshold; and the proportion of the current values greater than a programming current upper limit to the total number of operations is greater than 20%. The detection method according to claim 1, wherein the step of judging the operating state of the flash memory according to the current value includes: receiving a plurality of the current values of different timings, wherein the current values correspond to the flash memory The operation of a plurality of different parts of the flash memory; and judging the state of the parts according to the current values and a predetermined current template. A method for obtaining the operating current of a flash memory. The flash memory includes a plurality of blocks, and each block includes a plurality of pages. The obtaining method includes: Perform a specific operation on at least one of the plurality of pages in the flash memory, where the specific operation is at least one of a block erase, a page programming, and a read operation; correspondingly; The current of the at least one page of the plurality of pages during the specific operation generates a differential voltage; a plurality of levels are generated according to a one-level signal, wherein the voltage difference between the levels is the same as the level Signal-related; output a digital signal according to the differential voltage and the levels; and output a current value according to the level signal and the digital signal, wherein the current value corresponds to the at least one of the plurality of pages The specific operation. The obtaining method according to claim 8, further comprising: receiving a plurality of the digital signals in a time sequence; and adjusting the level signal according to the digital signals.

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