TWI713218B - Semiconductor devices - Google Patents

Abstract

A semiconductor device including a semiconductor layer disposed over a substrate; a doped region disposed in the semiconductor layer; a device region disposed on the doped region, including a source, a drain and a gate; a first isolation structure disposed in the semiconductor layer and surrounding the doped region; a second isolation structure surrounding the first isolation structure and spaced apart from the first isolation structure; and a terminal disposed between the first isolation structure and the second isolation structure, and being equipotential with the source.

Description

Semiconductor device

The present invention relates to semiconductor manufacturing technology, in particular to semiconductor-on-insulator devices.

Semiconductor devices include a substrate and circuit components disposed above the substrate, and have been widely used in various electronic products, such as personal computers, mobile phones, digital cameras, and other electronic devices. The evolution of semiconductor devices continues to influence and improve human life styles.

Semiconductor devices generally include isolation structures to electrically isolate devices formed on a semiconductor substrate. The isolation structure can be arranged by etching a trench in the semiconductor device, and then forming an insulating material in the trench. According to the depth of the trench, the isolation structure can be divided into Shallow Trench Isolation (STI) and Deep Trench Isolation (DTI). A shallow trench isolation structure with a shallow depth is often used to reduce parasitic capacitance and provide a lower level of voltage isolation between devices. On the other hand, the deep trench isolation structure has a deeper depth to provide isolation between different types of integrated circuits sharing the same semiconductor substrate.

However, although these isolation structures generally meet the requirements, they are still not satisfactory in every aspect, and may limit the performance of the semiconductor device in some cases. Therefore, it is necessary to further improve the semiconductor device and the isolation structure to make Therefore, semiconductor devices can have a wider range of applications.

According to some embodiments of the present invention, a semiconductor device is provided. The semiconductor device includes a semiconductor layer, which is disposed above a substrate; a doped region, which is disposed in the semiconductor layer; a device region, which is disposed on the doped region and includes a source electrode, a drain electrode and a gate electrode; a first isolation structure, which is disposed on the semiconductor layer In the layer and surrounding the doped region; a second isolation structure, surrounding the first isolation structure and separated from the first isolation structure; and a terminal, arranged between the first isolation structure and the second isolation structure and having the same potential as the source .

In some embodiments, the first isolation structure and the second isolation structure are separated by a portion of the semiconductor layer.

In some embodiments, the doped region includes a doped region of the first conductivity type adjacent to the terminal and a doped region of the second conductivity type far away from the terminal, wherein the doped region of the first conductivity type and the doped region of the second conductivity type have different Conductivity type.

In some embodiments, the source is disposed above the doped region of the first conductivity type, and the drain is disposed above the doped region of the second conductivity type.

In some embodiments, the semiconductor device further includes a plurality of first element regions disposed on the plurality of first doped regions; a plurality of first isolation structures disposed in the semiconductor layer, wherein each of the first isolation structures Each of these first doped regions is surrounded respectively.

In some embodiments, the second isolation structure surrounds the first isolation structures and is separated from each of the first isolation structures.

In some embodiments, the semiconductor device further includes an additional second isolation structure juxtaposed with the second isolation structure.

In some embodiments, the semiconductor device further includes a plurality of second device regions disposed on the plurality of second doped regions and surrounded by additional second isolation structures, wherein the second device regions and the first device regions have Different conductivity types.

In some embodiments, the semiconductor device further includes a plurality of terminals, which are respectively disposed in the additional second isolation structure and the second isolation structure.

In some embodiments, the semiconductor device further includes an insulating layer disposed between the substrate and the semiconductor layer, and the bottoms of the first isolation structure and the second isolation structure are in contact with the insulating layer.

100, 200, 300, 400, 500‧‧‧ Semiconductor device

102‧‧‧Base

104‧‧‧Insulation layer

106‧‧‧Semiconductor layer

108, 108A, 108B, 108C, 108D‧‧‧First conductivity type doped regions

109, 109A, 109B, 109C, 109D‧‧‧ doped area

110, 110A, 110B, 110C, 110D‧‧‧Second conductivity type doped regions

112‧‧‧Field Oxide

114‧‧‧Dip pole

116‧‧‧Source

118‧‧‧Body contact

120‧‧‧Gate Dielectric Layer

122‧‧‧Gate electrode layer

124, 124A, 124B, 124C, 124D‧‧‧Component area

126, 126A, 126B‧‧‧Terminal

130, 130A, 130B, 130C, 130D‧‧‧First isolation structure

140‧‧‧Second isolation structure

D1‧‧‧First pitch

D2‧‧‧Second pitch

D3‧‧‧third pitch

W1‧‧‧First width

W2‧‧‧Second width

A, B, C‧‧‧Arrow

The embodiments of the disclosure will be described in detail below in conjunction with the accompanying drawings. It should be noted that, according to industry standard practices, various features are not drawn to scale and are only used for illustration. In fact, it is possible to arbitrarily enlarge or reduce the size of the element to clearly show the features of the present disclosure.

1A to 1D are schematic cross-sectional diagrams illustrating various stages of manufacturing a semiconductor device according to some embodiments.

FIG. 1E is a schematic top view of a semiconductor device according to some embodiments.

2A to 2C are schematic cross-sectional views showing various stages of manufacturing a semiconductor device according to some other embodiments.

FIG. 2D is a schematic top view of a semiconductor device according to some other embodiments.

FIGS. 3 to 5 are schematic top views of semiconductor devices according to other embodiments.

Some embodiments are summarized below, so that persons with ordinary knowledge in the technical field of the present invention can understand the present invention more easily. However, these embodiments are only examples and are not used to limit the present invention. It can be understood that those with ordinary knowledge in the technical field of the present invention can adjust the embodiments described below according to requirements, such as changing the process sequence and/or including more or less steps than those described herein.

In addition, other elements may be added to the embodiments described below. For example, the description of "form the second element on the first element" may include an embodiment in which the first element is in direct contact with the second element, or may include other elements between the first element and the second element, so that the An embodiment where one element does not directly contact the second element, and the up-down relationship between the first element and the second element may change as the device is operated or used in different orientations.

Hereinafter, according to some embodiments of the present invention, a semiconductor device and a manufacturing method thereof will be described, and it is particularly suitable for a semiconductor device having an application of applying a back bias to a substrate. The present invention provides two isolation structures in the semiconductor device, and provides a terminal with the same potential as the source between the two isolation structures to eliminate the interference of the voltage applied outside the isolation structure to the internal components of the isolation structure, thereby improving reliability and safe operation Interval.

For the convenience of description, the invention will be described below with a Laterally Diffused Metal Oxide Semiconductor (LDMOS) device with a Semiconductor on Insulator (SOI) substrate, but the invention is not limited thereto. The present invention can also be applied to other types of metal oxide semiconductor devices, such as vertical diffusion metal An oxide semiconductor (Vertically Diffused Metal Oxide Semiconductor, VDMOS) device, an enhanced diffused metal oxide semiconductor (Extended-Drain Metal Oxide Semiconductor, EDMOS) device, or a similar metal oxide semiconductor device. In addition, the present invention can also be applied to other types of semiconductor devices, such as diodes, insulated gate bipolar transistors (Insulated Gate Bipolar Transistor, IGBT), and bipolar junction transistors (Bipolar Junction Transistor, BJT) or similar semiconductor devices.

1A to 1D are schematic cross-sectional views showing various stages of manufacturing the semiconductor device 100 according to some embodiments. As shown in FIG. 1A, the semiconductor device 100 includes a substrate 102. Any base material suitable for the semiconductor device 100 can be used. For example, the substrate 102 may be a bulk semiconductor substrate or a composite substrate formed of different materials, and the substrate 102 may be doped (for example, using p-type or n-type dopants) or undoped. In some embodiments, the substrate 102 may include an elemental semiconductor substrate, a compound semiconductor substrate, or an alloy semiconductor substrate. For example, the substrate 102 may include a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon carbide (SiC) substrate, an aluminum nitride (Aluminium Nitride, AlN) substrate, a gallium nitride (Gallium Nitride, GaN) substrate, Similar materials or a combination of the foregoing.

Then according to some embodiments, an insulating layer 104 is provided over the substrate 102 and a semiconductor layer 106 is provided over the insulating layer 104. In some embodiments, the formation of the substrate 102, the insulating layer 104, and the semiconductor layer 106 can be performed by a Separation by Ion Implantation of Oxygen (SIMOX) process, and Separation by Plasma (Separation by Plasma). Implantation of Oxygen (SPIMOX) process, wafer bonding process, epitaxial layer transfer (ELTRAN) process, similar processes or a combination of the foregoing.

In some embodiments of the SIMOX process, a high-energy oxygen ion beam is used to implant oxygen ions into the wafer to cause the oxygen ions to react with the wafer, and a high-temperature annealing (anneal) process An oxide layer, that is, an insulating layer 104, is formed in the wafer, in which a substrate 102 and a semiconductor layer 106 are formed under the insulating layer 104 and the portion of the wafer above the insulating layer 104, respectively. In some embodiments using the SPIMOX process, a method similar to the oxygen ion implantation process can be used, but plasma is used instead of the oxygen ion beam to increase yield and reduce cost.

In some embodiments using a wafer bonding process, the insulating layer 104 is directly bonded to the semiconductor layer 106, and then the two are bonded to the substrate 102, and the semiconductor layer 106 can be thinned before being bonded to the substrate 102.

In some embodiments using an epitaxial layer transfer (ELTRAN) process, a semiconductor layer 106 is epitaxially grown on a seed layer (not shown), and then the semiconductor layer 106 is oxidized to form the insulating layer 104. After bonding the insulating layer 104 to the substrate 102, the seed layer is removed.

In some embodiments, the insulating layer 104 may include a buried dielectric layer, such as buried oxide (BOX), buried silicon oxide (SiO ₂ ), buried silicon nitride (SiN), and the like的材料 or a combination of the foregoing.

In some embodiments, the semiconductor layer 106 may be doped with p-type or n-type dopants. For example, the p-type dopant may be boron, aluminum, gallium, BF ₂ , similar materials, or a combination of the foregoing, and the n-type dopant may be nitrogen, phosphorus, arsenic, antimony, a similar material, or a combination of the foregoing. In some embodiments, the semiconductor layer 106 can be doped by in-situ doping during epitaxial growth and/or by using p-type or n-type dopant implantation after epitaxial growth ( implanting).

Then, as shown in FIG. 1B, a doped region 109 is provided in the semiconductor layer 106, wherein the doped region 109 includes a first conductivity type doped region 108 and a second conductivity type doped region 110, and the first conductivity type is doped The region 108 and the second conductivity type doped region 110 have different conductivity types. In some embodiments, the laterally diffused metal oxide semiconductor device is p-type (LDPMOS), wherein the first conductivity type doped region 108 is n-type and the second conductivity type doped region 110 is p-type. In other embodiments, the laterally diffused metal oxide semiconductor device is n-type (LDNMOS), wherein the first conductivity type doped region 108 is p-type and the second conductivity type doped region 110 is n-type.

In some embodiments, a mask layer (not shown) may be formed and patterned before doping the first conductivity type doped region 108 and the second conductivity type doped region 110 to cover the semiconductor device 100 The area to be protected from implantation can achieve different implantation steps for the first conductivity type doped region 108 and the second conductivity type doped region 110. In some embodiments, the mask layer may be a photoresist, such as a positive photoresist or a negative photoresist. In other embodiments, the mask layer may be a hard mask, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbon nitride, similar materials, or a combination of the foregoing. In some embodiments, the formation of the mask layer may include spin-on coating, physical vapor deposition (Physical Vapor Deposition, PVD), chemical vapor deposition (Chemical Vapor Deposition, CVD), atomic layer deposition. Atomic Layer Deposition (ALD), a similar deposition process or a combination of the foregoing, and a suitable lithography technique can be used to pattern the mask layer.

Then, the portions of the semiconductor layer 106 that are not covered by the mask layer are implanted to form the first conductivity type doped regions 108 and the second conductivity type doped regions 110 respectively. The positions of the first conductivity type doped region 108 and the second conductivity type doped region 110 are adjusted according to the predetermined position of the device region. The doping concentration of the first conductivity type doping region 108 and the second conductivity type doping region 110 is higher than the doping concentration of the semiconductor layer 106. Then remove the mask layer.

Then, as shown in FIG. 1C, a source electrode 116 and a body contact 118 are provided in the first conductivity type doped region 108, and a field oxide layer 112 and a drain electrode 114 are provided in the second conductivity type doped region 110 . In some embodiments, the source 116, the drain 114, and the body contact 118 can be formed using an ion implantation process and a mask layer (not shown). The material and formation method of the mask layer can be as described above, but other materials and formation methods can also be used. In some embodiments, the source 116 and the drain 114 can be formed simultaneously by one ion implantation process, and the body contact 118 can be formed by another ion implantation process. In other embodiments, the source 116, the drain 114, and the body contact 118 may be formed by different ion implantation processes.

The source 116 and the drain 114 have the same conductivity type, and the body contact 118 has another conductivity type. In an embodiment where the laterally diffused metal oxide semiconductor device is p-type (LDPMOS), the source 116 and the drain 114 are p-type and the body contact 118 is n-type. In the embodiment where the laterally diffused metal oxide semiconductor device is n-type (LDNMOS), the source 116 and the drain 114 are n-type and the body contact 118 is p-type.

The doping concentration of the source electrode 116, the drain electrode 114 and the body contact 118 is greater than the doping concentration of the first conductivity type doped region 108 and the second conductivity type doped region 110.

Next, a field oxide layer 112 is provided on the second conductivity type doped region 110. In some embodiments, the formation of the field oxide layer 112 may use Thermal Oxidation or similar processes. In some other embodiments, the formation of the field oxide layer 112 may also use a shallow trench isolation (STI) process or similar processes. In some embodiments, the field oxide layer 112 abuts the source electrode 116, but the field oxide layer 112 may also have a gap with the source electrode 116. In addition, in some embodiments, the depth of the field oxide layer 112 is less than the depth of the source electrode 116, but the depth of the field oxide layer 112 may also be greater than or equal to the depth of the source electrode 116.

Then, a gate dielectric layer 120 is disposed between the field oxide layer 112 and the source electrode 116, and a gate electrode layer 122 is disposed above the field oxide layer 112 and the gate dielectric layer 120. In some embodiments, the material of the gate dielectric layer 120 may include silicon oxide, silicon nitride, silicon oxynitride, similar materials, or a combination of the foregoing. In some embodiments, the formation of the gate dielectric layer 120 may use an oxidation process, a deposition process, a similar process, or a combination of the foregoing. For example, the oxidation process includes a dry oxidation process or a wet oxidation process, and the deposition process includes a chemical deposition process. In some embodiments, the formation of the gate dielectric layer 120 may use a thermal oxidation method or a similar process.

In some embodiments, the material of the gate dielectric layer 120 may include a high-k dielectric material, that is, a dielectric material with a dielectric constant higher than 3.9. For example, the material of the gate dielectric layer 120 may include HfO ₂ , LaO ₂ , TiO ₂ , ZrO ₂ , Al ₂ O ₃ , Ta ₂ O ₃ , HfZrO, ZrSiO ₂ , HfSiO ₄ , similar high dielectric constant Material or a combination of the foregoing. The gate dielectric layer 120 can be formed by physical vapor deposition, chemical vapor deposition, atomic layer deposition, similar deposition processes, or a combination of the foregoing.

Then, a conductive material is deposited on the field oxide layer 112 and the gate dielectric layer 120, and a patterning process is performed on the deposited conductive material and the gate dielectric layer 120 to form a gate dielectric with a common sidewall at the desired position Layer 120 and gate electrode layer 122.

In some embodiments, the conductive material deposition process may include physical vapor deposition, chemical vapor deposition, atomic layer deposition, molecular beam epitaxy (MBE), and liquid phase epitaxy (LPE). , Vapor Phase Epitaxy (VPE), similar processes or a combination of the foregoing. In some embodiments, the conductive material may include metal, metal silicide, semiconductor material, similar materials, or a combination of the foregoing. For example, the metal can be gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al ), copper (Cu), similar materials, the foregoing alloys, the foregoing multilayer structure, or a combination of the foregoing, and the semiconductor material may include polycrystalline silicon (poly-Si) or polycrystalline germanium (poly-Ge).

Although the formation sequence of the field oxide layer 112, the source electrode 116, the drain electrode 114, the body contact 118, the gate dielectric layer 120 and the gate electrode layer 122 is described above, the present invention is not limited to this, and these elements can also be other elements. Formation order. In addition, the shape of the source electrode 116, the drain electrode 114, the body contact 118, the gate dielectric layer 120, and the gate electrode layer 122 is not limited to the vertical sidewalls in the figure, and may also be inclined. The sidewalls or sidewalls with other shapes. The upper surface of the gate electrode layer 122 is not limited to the stepped shape in the figure, and may also be a substantially flat upper surface or an upper surface with other topography.

Then, as shown in FIG. 1D, a first isolation structure 130 is provided. In some embodiments, the first isolation structure 130 may include a Deep Trench Isolation (DTI) structure. In some embodiments, a mask layer (not shown) is provided to expose a predetermined position of the first isolation structure 130, and the semiconductor layer 106 is etched out of trenches (not shown) by an etching process, and then by a deposition process An insulating material is deposited in the trench to form the first isolation structure 130. In some embodiments, the trench may pass through the semiconductor layer 106 and expose the insulating layer 104 so that the bottom of the first isolation structure 130 contacts the insulating layer 104 or is deep into the insulating layer 104.

The material and formation method of the mask layer can be as described above, but other materials and formation methods can also be used. In some embodiments, the etching process can use a dry etching process, a wet etching process, or a combination of the foregoing, such as reactive ion etching (RIE), inductively-coupled plasma (ICP) etching , Neutral Beam Etch (NBE), Electron Cyclotron Resonance (ERC) etching, similar etching process or a combination of the foregoing. In some embodiments, the deposition process may include Metal-Organic CVD (MOCVD), atomic layer deposition, molecular beam epitaxy, liquid phase epitaxy, similar processes, or a combination of the foregoing. In some embodiments, the insulating material may include an oxide such as silicon oxide, a nitride such as silicon nitride, similar materials, or a combination of the foregoing. In addition, the first isolation structure 130 is not limited to vertical sidewalls, and may also have inclined sidewalls or sidewalls with other shapes.

In some embodiments, the minimum distance between the first isolation structure 130 and the device region 124 (as shown in FIG. 1E) is the first distance D1. In some embodiments, as shown in FIG. 1D, the first distance D1 may be the distance between the first isolation structure 130 and the drain 114. However, the present invention is not limited to this, and the first distance D1 may also be the distance between the first isolation structure 130 and other components. For example, the first distance D1 may be the distance between the first isolation structure 130 and the body contact 118. If the first distance D1 is too small, the voltage applied outside the first isolation structure 130 may affect the device region 124 inside the first isolation structure 130. If the first distance D1 is too large, it will cause unnecessary space waste. The range of the first pitch D1 can be adjusted to reduce the interference received by the element region 124 and at the same time make the semiconductor device 100 have a smaller volume.

FIG. 1E is a schematic top view of the semiconductor device 100 according to some embodiments. As shown in FIG. 1E, the semiconductor device 100 includes a device region 124, wherein the device region 124 includes a field oxide layer 112, a source 116, a drain 114, a body contact 118, and a gate dielectric as shown in FIGS. 1C~1D. The electrical layer 120 and the gate electrode layer 122. In addition, the first isolation structure 130 surrounds the doped region 109 including the first conductivity type doped region 108 and the second conductivity type doped region 110, and is separated from the element region 124 by a part of the semiconductor layer 106.

Although the first isolation structure 130 is shown as a rectangle from the top view, the present invention is not limited to this. The first isolation structure 130 may also have other shapes, such as a circle, an ellipse, or other loop shapes.

When the semiconductor device 100 is used in applications such as ultrasonic medical applications, it is necessary to give the substrate 102 a back bias. However, this bias will couple additional charges on the surface of the insulating layer 104 on both sides of the first isolation structure 130, resulting in half guide The electric field distribution of the body device 100 changes, that is, the back side bias effect, as shown by arrows A and B. In addition, the first isolation structure 130 also has a lateral coupling effect (lateral coupling), as indicated by the arrow C, causing problems such as increased leakage current and deterioration of hot carrier injection, thereby limiting the safe operation range of the semiconductor device 100 . Therefore, the present invention further provides the following embodiments to improve the above problems.

2A to 2C are schematic cross-sectional views of the semiconductor device 200 according to some other embodiments. Figure 2A continues the process steps of Figure 1C. For simplicity, the same components are described below with the same symbols. The forming methods and materials of these elements are as described above, so they will not be repeated here. Compared with the embodiments in FIGS. 1A to 1E, the following embodiments will add additional components to improve the reliability of the semiconductor device.

As shown in FIG. 2A, a terminal 126 is provided in the semiconductor layer 106 of the semiconductor device 200. In some embodiments, the formation of the terminal 126 may use an ion implantation process with a mask layer (not shown). The material and formation method of the mask layer can be as described above, but other materials and formation methods can also be used.

In some embodiments, the terminal 126 may be provided when the source 116, the drain 114, and the body contact 118 are provided. For example, in some embodiments, the terminal 126, the source 116, and the drain 114 may be formed by one ion implantation process, and the body contact 118 may be formed by another ion implantation process. In other embodiments, the source 116 and the drain 114 may be formed by one ion implantation process, and the terminal 126 and the body contact 118 may be formed by another ion implantation process. However, the present invention is not limited to this, and the source 116, the drain 114, the body contact 118 and the terminal 126 can also be formed by a multi-channel ion implantation process. In again In other embodiments, after the source 116, the drain 114, the body contact 118, the field oxide layer 112, the gate dielectric layer 120, and the gate electrode layer 122 are formed, additional mask layers and ion patterns may be used. The implantation process forms the terminal 126. Other formation sequences can also be used.

The doping concentration of the terminal 126 is greater than the doping concentration of the first conductivity type doped region 108 and the second conductivity type doped region 110, and the doping concentration of the terminal 126 may be the same or different from the source 116, the drain 114, and the body. Doping concentration of contact 118. The doping concentration of the terminal 126 can be adjusted so that the terminal 126 has good electrical conductivity while keeping the influence of the dopants in the terminal 126 on surrounding components small. The width of the terminal 126 can be adjusted so that the terminal 126 can be well connected to the external conductive structure of the terminal 126 without increasing the volume of the semiconductor device 200.

As shown in FIG. 2A, in some embodiments, the terminal 126 is adjacent to the first conductivity type doped region 108 and away from the second conductivity type doped region 110. However, the present invention is not limited to this. In other embodiments, the terminal 126 may also be arranged adjacent to the second conductivity type doped region 110 and far away from the first conductivity type doped region 108 or arranged in other positions.

Then, as shown in FIG. 2B, a first isolation structure 130 and a second isolation structure 140 are provided in the semiconductor layer 106. In some embodiments, the first isolation structure 130 and the second isolation structure 140 may each independently include a deep trench isolation structure. As shown in FIG. 2B, the first isolation structure 130 and the second isolation structure 140 are separated by a portion of the semiconductor layer 106, and the terminal 126 is located on the semiconductor layer 106 between the first isolation structure 130 and the second isolation structure 140.

The material and formation method of the second isolation structure 140 can be selected as described above for the material and formation method of the first isolation structure 130, but the first isolation structure The structure 130 and the second isolation structure 140 can each independently use the same or different materials and formation methods. The width W1 of the first isolation structure 130 and the width W2 of the second isolation structure 140 may be the same or different. In some embodiments, the first isolation structure 130 and the second isolation structure 140 may be formed at the same time, and the first isolation structure 130 and the second isolation structure 140 have the same material. However, the present invention is not limited thereto, and the second isolation structure 140 may be formed before or after forming the first isolation structure 130. In addition, the first isolation structure 130 and the second isolation structure 140 are not limited to the vertical sidewalls in the drawings, but may also have inclined sidewalls or sidewalls with other shapes, and the first isolation structure 130 and the second isolation structure 140 may have the same or Different sidewalls.

As mentioned above, in some embodiments, the trenches used to form the first isolation structure 130 and the second isolation structure 140 may pass through the semiconductor layer 106 and expose the insulating layer 104, so that the first isolation structure 130 and the second isolation structure The bottom of the structure 140 can each independently contact the insulating layer 104 or go deep into the insulating layer 104.

In some embodiments, the first isolation structure 130 and the second isolation structure 140 may have the same or different pitches at different positions. The minimum distance between the first isolation structure 130 and the second isolation structure 140 is the second distance D2.

In some embodiments, the minimum distance between the first isolation structure 130 and the device region 124 (as shown in FIG. 2D) is the third distance D3. In some embodiments, as shown in FIG. 2B, the third distance D3 may be the distance between the first isolation structure 130 and the drain 114. However, the present invention is not limited to this, and the third distance D3 may also be the distance between the first isolation structure 130 and other elements. For example, the third distance D3 may be the distance between the first isolation structure 130 and the body contact 118.

As shown in FIG. 2C, the terminal 126 and the source 116 are connected in common so that the two are equal in potential. Since the terminal 126 and the source electrode 116 are respectively arranged on the inner and outer sides of the first isolation structure 130, setting the terminal 126 and the source electrode 116 to be equipotential can make the inner and outer sides of the first isolation structure 130 equipotential, thereby eliminating The voltage applied outside the first isolation structure 130 causes interference to the element region 124 inside the first isolation structure 130. Therefore, the leakage current can be reduced, the hot carrier injection effect can be improved, and the reliability and safe operating range of the semiconductor device 200 can be improved.

In addition, in the semiconductor device 100 having only the first isolation structure 130, in order to reduce the interference received by the device region 124, the first isolation structure 130 is separated from the device region 124. However, in the semiconductor device 200, the addition of the second isolation structure 140 and the source terminal 126 can reduce the interference received by the device region 124, and shorten the minimum distance between the first isolation structure 130 and the device region 124 (also That is, the third distance D3). In other words, compared to the semiconductor device 100 provided with only the first isolation structure 130, the semiconductor device 200 has the second isolation structure 140 and the terminal 126, and the third pitch D3 of the semiconductor device 200 may be smaller than the first pitch of the semiconductor device 200. D1.

In some embodiments, when the substrate 102 is biased at -180 volts (V), compared to not grounded, under the condition that the substrate 102 outside the first isolation structure 130 is grounded, the gate current (Ig) The maximum value can be reduced by about 37%, showing that the hot carrier injection effect has been significantly improved. In addition, in some embodiments, under the condition that the substrate 102 outside the first isolation structure 130 is grounded, the breakdown voltage in the on state can be increased by about 10-30V, and the safe operating interval of the display semiconductor device 200 is also improved.

FIG. 2D illustrates the semiconductor device 200 according to some embodiments Top view schematic. As shown in FIG. 2D, the first isolation structure 130 surrounds the doped region 109 including the first conductivity type doped region 108 and the second conductivity type doped region 110 and the device region 124, and the second isolation structure 140 surrounds the first The isolation structure 130, wherein the second isolation structure 140 and the first isolation structure 130 are separated by a portion of the semiconductor layer 106. Although the first isolation structure 130 and the second isolation structure 140 are rectangular in the top view, the present invention is not limited to this. The first isolation structure 130 and the second isolation structure 140 may also have other shapes, such as circular, Oval or other surrounding shapes, and the first isolation structure 130 and the second isolation structure 140 may have the same or different shapes.

In addition, the description of FIGS. 1A to 2D is that the isolation structure is set after the element is formed, that is, the formation sequence of the semiconductor devices 100 and 200 is to provide the substrate 102, the insulating layer 104 and the semiconductor layer 106, and then sequentially form the doped regions 109, The device region 124 and two isolation structures (the first isolation structure 130 and the second isolation structure 140), but the invention is not limited thereto. For example, components can also be arranged after the isolation structure is formed, that is, the substrate 102, the insulating layer 104 and the semiconductor layer 106 are provided, and then two isolation structures (the first isolation structure 130 and the second isolation structure 140) and doped Miscellaneous area 109 and element area 124.

The first isolation structure 130 and the second isolation structure 140 of the present invention can also be applied to a semiconductor device having multiple device regions. Hereinafter, an exemplary configuration of a semiconductor device having multiple element regions will be described according to some embodiments. For the sake of simplicity, the same components will be described with the same symbols, and the symbols of A, B, C and D will be added to some component symbols to distinguish them. The forming methods and materials of these elements are as described above, so they will not be repeated here.

FIG. 3 shows the top of the semiconductor device 300 according to some embodiments See schematic diagram. Figure 3 depicts an example configuration that includes element regions of the same conductivity type. In some embodiments, as shown in FIG. 3, the semiconductor device 300 includes element regions 124A and 124B having the same conductivity type. The device regions 124A and 124B can have the configuration of the device region 124 as described above. For example, the device regions 124A and 124B can include a field oxide layer 112, a source 116, a drain 114, a body contact 118, and a gate dielectric. The electrical layer 120 and the gate electrode layer 122, but the element regions 124A and 124B may have the same or different element configurations.

In some embodiments, the semiconductor device 300 includes doped regions 109A and 109B, wherein the doped region 109A includes a first conductivity type doped region 108A and a second conductivity type doped region 130A, and the doped region 109B includes a first conductivity type. The type doped region 108B and the second conductive type doped region 130B. In some embodiments, the element regions 124A and 124B are disposed above the doped regions 109A and 109B, respectively. In some embodiments, the semiconductor device 300 includes first isolation structures 130A and 130B to surround the doped regions 109A and 109B, respectively.

As mentioned above, in some embodiments, the element regions 124A and 124B have the same conductivity type, so a terminal 126 can be provided to connect the source electrodes in the element regions 124A and 124B at the same time, and a second isolation structure 140 can be provided to surround at the same time. The first isolation structures 130A and 130B are used to reduce manufacturing steps and reduce costs. However, the present invention is not limited to this. Two terminals 126 may be provided to respectively connect the source electrodes in the element regions 124A and 124B, and two second isolation structures 140 may be provided to surround the first isolation structures 130A and 130B, respectively.

According to some embodiments, as shown in FIG. 3, the terminal 126 is adjacent to the first isolation structure 130A, but the present invention is not limited to this. For example, the terminal 126 may also be disposed between the first isolation structure 130A and 130B or arranged as Near the first Isolation structure 130B. In addition, the doped regions 109A and 109B may also have the same or different configurations. For example, the first conductivity types 108A and 108B are located on different sides of the first isolation structures 130A and 130B.

FIG. 4 is a schematic top view of a semiconductor device 400 according to some embodiments. Figure 4 depicts an example configuration that includes element regions with different conductivity types. The configuration in Fig. 4 is similar to that in Fig. 3, but the element regions 124A and 124B in Fig. 4 have different conductivity types. For other elements, refer to Fig. 3 and related descriptions. The semiconductor device 400 includes two terminals 126A and 126B to connect the source electrodes in the element regions 124A and 124B, respectively, and the semiconductor device 400 includes two second isolation structures 140 juxtaposed, wherein the two terminals 126A and 126B are located in the two second isolation structures respectively. Two isolation structure 140.

According to some embodiments, as shown in FIG. 4, the terminals 126A and 126B are respectively located on the same side of the first isolation structure 130A and 130B, but the present invention is not limited to this. For example, the terminals 126A and 126B may be disposed on the first isolation structure. The isolation structures 130A and 130B or are respectively disposed on opposite sides of the first isolation structures 130A and 130B. In addition, the two second isolation structures 140 are not limited to being juxtaposed, and may also have gaps, and may have the same or different topography.

FIG. 5 is a schematic top view of a semiconductor device 500 according to some embodiments. Figure 5 depicts an example configuration that includes element regions with the same and different conductivity types. In some embodiments, the semiconductor device 500 includes first element regions (also referred to as element regions) 124A and 124B having the same conductivity type and second element regions (also referred to as element regions) 124C and 124C having different conductivity types. 124D, and includes two terminals 126A and 126B to connect the sources in the first element regions 124A and 124B and the sources in the second element regions 124C and 124D, respectively. In addition, the semiconductor device 500 includes two second isolation structures 140 juxtaposed, wherein two terminals 126A and 126B are respectively located in the two second isolation structures 140.

As described above, the element regions 124A, 124B, 124C and 124D, the terminals 126A and 126B, the doped regions 109A, 109B, 109C and 109D, the first conductivity type doped regions 108A, 108B, 108C and 108D, and the second conductivity type doped regions The configuration of the miscellaneous regions 110A, 110B, 110C, and 110D, and the first isolation structures 130A, 130B, 130C, and 130D is not limited to the exemplary shape and configuration of the semiconductor device 500, and these elements may also have different positions and shapes, and additional elements may be provided . For example, in some embodiments, four second isolation structures 140 may be used to separate the element regions 124A, 124B, 124C, and 124D, and four terminals may be provided to connect the element regions 124A, 124B, 124C, and 124D, respectively .

According to some embodiments of the present invention, the first isolation structure and the second isolation structure are provided in the semiconductor device, and a terminal common to the source is provided between the two, so that the inner and outer sides of the first isolation structure can be equipotential. This eliminates the interference caused by the voltage applied outside the first isolation structure to the components inside the first isolation structure, thereby reducing leakage current and improving the hot carrier injection effect, thereby enhancing the reliability of the semiconductor device and having greater safety Operating interval.

Although the present invention has been described above in terms of multiple embodiments, these embodiments are not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs should understand that they can make various changes, substitutions and substitutions based on the embodiments of the present invention to achieve the same purpose as the multiple embodiments described herein. And/or advantages. Those with general knowledge in the technical field of the present invention It can also be understood that such modifications or designs do not depart from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to those defined by the attached patent scope.

102‧‧‧Base

104‧‧‧Insulation layer

106‧‧‧Semiconductor layer

108‧‧‧First conductivity type doped region

109‧‧‧Doped area

110‧‧‧Second conductivity type doped region

112‧‧‧Field Oxide

114‧‧‧Dip pole

116‧‧‧Source

118‧‧‧Body contact

120‧‧‧Gate Dielectric Layer

122‧‧‧Gate electrode layer

126‧‧‧Terminal

130‧‧‧First isolation structure

140‧‧‧Second isolation structure

200‧‧‧Semiconductor device

Claims (10)

A semiconductor device includes: a semiconductor layer disposed above a substrate; a plurality of first doped regions disposed in the semiconductor layer; a plurality of first element regions are respectively disposed in each of the first doped regions One, wherein each of the first device regions includes a source, a drain, and a gate; a plurality of first isolation structures are disposed in the semiconductor layer, and each of the first isolation structures surrounds Each of the first doped regions; a second isolation structure surrounding the first isolation structures and spaced apart from each of the first isolation structures; a terminal disposed on the first isolation structures and The second isolation structure is located between the two of the first isolation structures, and is at the same potential as the source; and an insulating layer is disposed between the substrate and the semiconductor layer, wherein the insulating layer is from The second isolation structure extends away from a first side of the terminal to a second side of the second isolation structure adjacent to the terminal, and the bottom surface of the doped region entirely contacts the top surface of the insulating layer. According to the semiconductor device described in claim 1, wherein the first isolation structure and the second isolation structure are separated by a part of the semiconductor layer. According to the semiconductor device described in claim 1, wherein one of the first doped regions includes a doped region of the first conductivity type adjacent to the terminal and a doped region of the second conductivity type far away from the terminal, Where the first conductive type The type doped region and the second conductivity type doped region have different conductivity types, and the first conductivity type doped region contacts the second conductivity type doped region. The semiconductor device described in claim 3, wherein the source electrode is disposed above the first conductivity type doped region, and the drain electrode is disposed above the second conductivity type doped region. According to the semiconductor device described in claim 3, the first conductivity type doped region and the second conductivity type doped region respectively extend from the top surface of the semiconductor layer to the top surface of the insulating layer. In the semiconductor device described in item 3 of the scope of patent application, two sides of one of the first isolation structures respectively contact the first conductivity type doped region and the second conductivity type doped region. The semiconductor device described in item 1 of the scope of the patent application further includes an additional second isolation structure juxtaposed with the second isolation structure. The semiconductor device described in item 7 of the scope of the patent application further includes a plurality of second element regions disposed on the plurality of second doped regions and surrounded by the additional second isolation structure, wherein the second element regions It has a different conductivity type from the first element regions. According to the semiconductor device described in item 7 of the scope of patent application, the semiconductor device further includes a plurality of terminals disposed in the additional second isolation structure and the second isolation structure, respectively. According to the semiconductor device described in claim 1, wherein the bottoms of the first isolation structure and the second isolation structure are in contact with the insulating layer.

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