TWI713155B - Memory device - Google Patents

Abstract

A memory device includes a channel element, a memory element, and an electrode element. The channel element has an open ring shape. A memory cell is defined in the memory element between the channel element and the electrode element.

Description

Memory device

The present invention relates to a memory device.

As the critical size of components in integrated circuits gradually shrinks to the perceptible limit of the process technology, designers have begun to look for technologies that can achieve greater memory density, thereby achieving lower costs per bit.

The invention relates to a memory device.

According to one aspect of the present invention, a memory device is provided. The memory device includes channel elements, memory elements, and electrode elements. The channel element has an open loop shape. The memory cell is defined in the memory element between the channel element and the electrode element.

According to another aspect of the present invention, a memory device is provided. The memory device includes channel elements, memory elements, and electrode elements. The memory element has an open loop shape. The memory cell is defined in the memory element between the channel element and the electrode element.

According to yet another aspect of the present invention, a memory device is provided. The memory device includes a memory element, a source-side element, a drain-side element, a channel element, an insulating element, and an electrode element. The channel element is electrically connected between the source-side element and the drain-side element. The channel element, the source-side element and the drain-side element are respectively in the insulating element The opposite side of the piece. The memory cell is defined in the memory element between the channel element and the electrode element.

In order to have a better understanding of the above and other aspects of the present invention, the following specific examples are given in conjunction with the accompanying drawings to describe in detail as follows:

100: memory element

110: Concave side wall memory surface

120: Convex side wall memory surface

130: Sidewall memory plane

200: channel element

210: Concave curved side wall channel surface

217: sidewall channel surface

220: Convex side wall channel surface

242: Source-side components

244: Drain side component

245: Convex side wall surface

300: Electrode element

310: sidewall electrode surface

400: insulating element

410: Flat sidewall insulation surface

420: convex curved sidewall insulation surface

500: insulating layer

650: Base

651: Stacked Structure

652: material film

654, 674: insulating film

656: hole

657: sidewall surface

658: Insulating material film

660: insulating material layer

662, 671: groove

664: Notch

666: metal silicide layer

673: Slit

676: Material Components

678: first conductive via

680: second conductive via

D1: First direction

D2: second direction

D3: Third party

K1, K2: size

M1: The first metal layer

M2: second metal layer

P-P, Q-Q: Section line

Figure 1 is a cross-sectional view of a memory device according to an embodiment.

Figure 2 is a cross-sectional view of a memory device of another embodiment.

3A to 14 illustrate a method of manufacturing a memory device according to an embodiment.

Figure 15 is a cross-sectional view of a memory device according to an embodiment.

Figure 16 is a cross-sectional view of a memory device according to an embodiment.

Fig. 17 is a cross-sectional view of a memory device according to an embodiment.

Some examples are described below. It should be noted that this disclosure does not show all possible embodiments, and other implementation aspects not mentioned in this disclosure may also be applicable. Furthermore, the size ratios in the drawings are not drawn in proportion to the actual products. Therefore, the contents of the description and illustrations are only used to describe the embodiments, rather than to limit the protection scope of this disclosure. In addition, the descriptions in the embodiments, such as detailed structure, process steps, material applications, etc., are for illustrative purposes only, and are not intended to limit the scope of the disclosure. The respective details of the steps and structures of the embodiments can be added according to the needs of the actual application process without departing from the spirit and scope of this disclosure Change and modification. In the following description, the same/similar symbols represent the same/similar elements.

Please refer to FIG. 1, which shows a cross-sectional view of a memory device according to an embodiment. The memory device includes a memory element 100, a channel element 200, and an electrode element 300.

The memory element 100 has an open loop shape. The memory element 100 includes a concave curved sidewall memory surface 110, a convex curved sidewall memory surface 120, and a sidewall memory plane 130. The sidewall memory plane 130 is between the concave curved sidewall memory surface 110 and the convex curved sidewall memory surface 120.

The channel element 200 has an open loop shape. The channel element 200 has a concave curved sidewall channel surface 210 and a convex curved sidewall channel surface 220 opposite to each other. The channel element 200 is electrically connected between the source-side element 242 and the drain-side element 244. The channel element 200 may include a source-side element 242 and a drain-side element 244. The source-side element 242 and the drain-side element 244 have a convex curved sidewall surface 245 opposite to the convex curved sidewall channel surface 220 of the channel element 200. The channel element 200 may be located between the source-side element 242, the drain-side element 244 and the memory element 100. In one embodiment, the channel element 200 is on the concave curved sidewall memory surface 110 of the memory element 100, and the source side element 242 and the drain side element 244 respectively extend from opposite ends of the channel element 200 beyond the sidewall memory plane of the memory element 100 130.

In the embodiment, the size K1 of the channel element 200 is smaller than the size K2 of the source-side element 242 and the drain-side element 244. The dimension K1 of the channel element 200 can be defined between the concave curved sidewall channel surface 210 and the convex curved sidewall channel surface 220 The dimensions such as thickness. The dimension K2 of the source-side element 242 and the drain-side element 244 may be the maximum distance between the convex curved sidewall surface 245.

The channel element 200, the source-side element 242, and the drain-side element 244 may include semiconductor materials, such as polysilicon, single crystal silicon, and so on. The dopant concentration of the source-side element 242 and the drain-side element 244 may be different from the dopant concentration of the channel element 200. The conductivity of the source-side element 242 and the drain-side element 244 may be greater than the conductivity of the channel element 200. The dopant concentration of the source-side element 242 and the drain-side element 244 may be greater than the dopant concentration of the channel element 200. For example, the source-side element 242 and the drain-side element 244 may include N-type heavily doped semiconductor materials (such as monocrystalline silicon or polysilicon, etc.), and the channel element 200 may include undoped or N-type lightly doped semiconductors. Material (such as monocrystalline silicon or polycrystalline silicon, etc.). But this disclosure is not limited to this.

The electrode element 300 has a sidewall electrode surface 310. The sidewall electrode surface 310 of the electrode element 300 and the sidewall memory plane 130 of the memory element 100 may be coplanar. The electrode element 300 is on the memory surface 120 of the convex curved sidewall of the memory element 100.

The channel element 200 and the source-side element 242 and the drain-side element 244 are respectively on opposite sides of the insulating element 400. The insulating element 400 has an adjacent planar side wall insulating surface 410 and a convex curved side wall insulating surface 420. The convex curved sidewall insulation surface 420 may be opposite to the planar sidewall insulation surface 410. The channel element 200 may abut the convex curved sidewall insulating surface 420. The source side element 242 and the drain side element 244 extend from the channel element 200 beyond the planar sidewall insulation surface 410. The source side element 242 and the drain side element 244 may be on the planar sidewall insulating surface 410.

The insulating layer 500 is adjacent to the source-side element 242 and the drain-side element 244. The insulating element 400 is between the insulating layer 500 and the channel element 200. Specifically, the insulating layer 500 may be located on the sidewall electrode surface 310 of the electrode element 300, the sidewall memory plane 130 of the memory element 100, the convex curved sidewall surface 245 of the source side element 242 and the drain side element 244, and the insulating element 400 On the insulating surface 410 of the planar sidewall.

In this embodiment, the planar sidewall insulating surface 410 of the insulating element 400 is not aligned with the sidewall memory plane 130 of the memory element 100, nor is it aligned with the sidewall electrode surface 310 of the electrode element 300.

In an embodiment, a metal silicide layer (not shown) may be disposed on the sidewall surfaces of the source side element 242 and the drain side element 244 opposite to the channel element 200. Specifically, the metal silicide layer may be disposed on the convex curved sidewall surface 245 of the source side element 242 and the drain side element 244 that is not in contact with the insulating element 400 and the channel element 200.

In one embodiment, the source-side element 242 and the drain-side element 244 function as a source electrode and a drain electrode, respectively. The electrode element 300 functions as a gate electrode, for example, functions as a word line. The memory cell is defined in the memory element 100 between the channel element 200 and the electrode element 300.

According to the configuration profile of the channel element 200 (which may include the source-side element 242 and the drain-side element 244) and the memory element 100 as shown in FIG. 1, the memory element can have a smaller cell size, and the memory device can be improved The density of the memory cell array. The source-side element 242 and the drain-side element 244 have a larger size than the channel element 200, so the process alignment of the upper conductive element (such as the first conductive via 678 shown in FIG. 14) can be improved and have good electrical properties. Sexual connection, the process operation window (process window) is large and improves product yield.

In an embodiment, FIG. 1 may be a cross-sectional view of the memory device on a plane formed by the first direction D1 and the second direction D2. The first direction D1 is different from the second direction D2. In an embodiment, the first direction D1 is substantially perpendicular to the second direction D2. For example, the first direction D1 is the X direction, and the second direction D2 is the Y direction.

Please refer to FIG. 2, which shows a cross-sectional view of a memory device according to another embodiment. In this embodiment, the planar sidewall insulating surface 410 of the insulating element 400 can be substantially aligned with the sidewall memory plane 130 of the memory element 100 and can be aligned with the sidewall electrode surface 310 of the electrode element 300. According to the configuration outlines of the channel element 200, the source-side element 242, the drain-side element 244, and the memory element 100 as shown in FIG. 2, the memory component can have a smaller cell size and improve the memory of the memory device Cell array density. The source-side element 242 and the drain-side element 244 have a larger size than the channel element 200, so the process alignment of the upper conductive element (such as the first conductive via 678 shown in FIG. 14) can be improved and have good electrical properties. Sexual connection relationship, large process operation window, and improve product yield.

3A to 14 illustrate a method of manufacturing a memory device according to an embodiment.

Please refer to Figure 3A and Figure 3B. Figure 3A is a longitudinal cross-sectional view of the memory device, which can be drawn along the PP section line shown in Figure 3B. Figure 3B is a transverse cross-sectional view of the memory device, which can be drawn along the QQ section line shown in Figure 3A. A stacked structure 651 is formed on the substrate 650. The stacked structure 651 includes a material film 652 and an insulating film 654 stacked alternately. The material of the material film 652 is different from The material of the insulating film 654. In one embodiment, the material film 652 includes nitride such as silicon nitride. The insulating film 654 includes oxide such as silicon oxide. However, the present disclosure is not limited to this. The insulating film 654 can use other suitable insulating materials, and the material film 652 can use other suitable materials such as dielectric materials or conductive materials. The hole 656 can be formed in the stacked structure 651 using the yellow light lithography etching technique.

The memory element 100 may be formed in the hole 656 and on the upper surface of the stacked structure 651. The memory device 100 may include any charge trapping structure, such as an oxide-nitride-oxide (ONO) structure or an oxide-nitride-oxide-nitride-oxide (BE-SONOS) structure. For example, the charge trapping layer can use nitrides such as silicon nitride, or other similar high dielectric constant materials including metal oxides, such as aluminum oxide (Al ₂ O ₃ ), zirconium oxide (HfO ₂ ), etc. . The channel element 200 may be formed on the memory element 100. The channel element 200 may include undoped or doped semiconductor materials such as polysilicon, single crystal silicon, etc.). The insulating material film 658 may be formed on the channel member 200. In an embodiment, the insulating material film 658 may include oxide such as silicon oxide, but is not limited to this, and it may also include nitride such as silicon nitride, or other suitable insulating materials.

Please refer to Figure 4A and Figure 4B. FIG. 4A is a longitudinal sectional view of the memory device, which can be drawn along the PP section line shown in FIG. 4B. Figure 4B is a transverse cross-sectional view of the memory device, which can be drawn along the QQ section line shown in Figure 4A. An etch-back step may be performed to remove the memory element 100, the channel element 200, and the insulating material film 658 on the upper surface of the stacked structure 651 and the portion at the bottom of the hole 656. In one embodiment, an anisotropic etching step can be used to remove The portion of the insulating material film 658 on the upper surface of the stacked structure 651 and the portion at the bottom of the hole 656 and the portion on the sidewall surface of the channel element 200 are left. Then, another etching step is used to remove the channel element 200 and the memory. The part of the element 100 that is not shielded by the insulating material film 658. An insulating material layer 660 may be formed to fill the hole 656 and on the upper surface of the stacked structure 651. In one embodiment, the insulating material layer 660 may include oxide such as silicon oxide, but is not limited to this, and it may also include nitride such as silicon nitride, or other suitable insulating materials. The insulating element 400 may include an insulating material film 658 and an insulating material layer 660.

As shown in FIG. 4B, the insulating element 400 may have a solid circular shape. The channel element 200 may have a closed ring shape or a hollow circular shape, surrounding the insulating element 400. The memory element 100 may have a closed ring shape or a hollow circular shape surrounding the channel element 200. In one embodiment, trenches 662 may be formed in the structures shown in FIGS. 4A and 4B to form the structures shown in FIGS. 5A, 5B, and 5C. Figures 5A and 5B are longitudinal cross-sectional views of the memory device. Figure 5A can be drawn along the PP profile line shown in Figure 5C, and Figure 5B can be drawn along the EE profile line shown in Figure 5C. . FIG. 5C is a transverse cross-sectional view of the memory device, which can be drawn along the QQ section line shown in FIG. 5A and FIG. 5B.

As shown in FIG. 5C, the insulating element 400 is patterned into a solid semicircular shape by the trench 662. The channel element 200 is patterned into an open loop shape by the groove 662. The memory device 100 is patterned into an open loop shape by the groove 662. The planar sidewall insulation surface 410 of the insulating element 400, the sidewall channel surface 217 of the channel element 200, the sidewall memory plane 130 of the memory element 100, and the material film 652 The sidewall surface 657 may be coplanar.

Please refer to Figure 6A, Figure 6B and Figure 6C. Figures 6A and 6B are longitudinal cross-sectional views of the memory device. Figure 6A can be drawn along the PP profile line shown in Figure 6C, and Figure 6B can be drawn along the EE profile line shown in Figure 6C. . Figure 6C is a transverse cross-sectional view of the memory device, which can be drawn along the QQ section line shown in Figure 6A and Figure 6B. The planar sidewall insulating surface 410 of the insulating element 400 exposed from the trench 662 undergoes an etch-back step, so that the planar sidewall insulating surface 410 moves inwardly of the insulating element 400 and forms a recess 664. The notch 664 exposes the concave curved sidewall channel surface 210 of the channel element 200. Then, a deposition method can be used to form the source side as shown in FIGS. 7A and 7B on the surface of the channel element 200 where the recess 664 and the trench 662 are exposed (including the concave curved sidewall channel surface 210 and the sidewall channel surface 217). Element 242 and drain-side element 244. FIG. 7A is a longitudinal cross-sectional view of the memory device, which can be drawn along the PP cross-section line shown in FIG. 7B. FIG. 7B is a transverse cross-sectional view of the memory device, which can be drawn along the QQ section line shown in FIG. 7A. In one embodiment, the source-side element 242 and the drain-side element 244 formed by epitaxial growth have convex curved sidewall surfaces 245.

Please refer to Figure 8A and Figure 8B. FIG. 8A is a longitudinal sectional view of the memory device, which can be drawn along the PP section line shown in FIG. 8B. FIG. 8B is a transverse cross-sectional view of the memory device, which can be drawn along the QQ section line shown in FIG. 8A. The metal silicide layer 666 may be formed on the exposed surfaces (including the convex curved sidewall surface 245) of the source side element 242 and the drain side element 244. The metal silicide layer 666 may include nickel silicide (NiSi), platinum silicide (PtSi), titanium silicide (TiSi2), tungsten silicide (WSi2), cobalt silicide (CoSi2) and so on.

Please refer to Figure 9A, Figure 9B and Figure 9C. Figures 9A and 9B are longitudinal cross-sectional views of the memory device. Figure 9A can be drawn along the PP profile line shown in Figure 9C, and Figure 9B can be drawn along the EE profile line shown in Figure 9C. . FIG. 9C is a transverse cross-sectional view of the memory device, which can be drawn along the QQ section line shown in FIGS. 9A and 9B. The insulating layer 500 may be formed to fill the recess 664 and the trench 662 and on the upper surface of the stacked structure 651. The insulating layer 500 may include oxide such as silicon oxide, nitride such as silicon nitride, or other suitable insulating materials.

Please refer to Figure 10A and Figure 10B. FIG. 10A is a longitudinal sectional view of the memory device, which can be drawn along the EE section line shown in FIG. 10B. FIG. 10B is a transverse cross-sectional view of the memory device, which can be drawn along the QQ section line shown in FIG. 10A. The trench 671 can be formed in the stacked structure 651 using a yellow light photolithography etching process. The trench 671 can expose the insulating film 654 and the material film 652 of the stacked structure 651. An etching step can be used to remove the material film 652 (that is, as a sacrificial layer) exposed by the trench 671 to form the slit 673 as shown in FIGS. 11A, 11B, and 11C. Figures 11A and 11B are longitudinal cross-sectional views of the memory device. Figure 11A can be drawn along the PP profile line shown in Figure 11C, and Figure 11B can be drawn along the EE profile line shown in Figure 11C. . FIG. 11C is a transverse cross-sectional view of the memory device, which can be drawn along the QQ section line shown in FIGS. 11A and 11B. The slit 673 can expose the convex curved sidewall memory surface 120 of the memory device 100 and the upper surface/lower surface of the insulating film 654.

Please refer to Figure 12A, Figure 12B and Figure 12C. Figures 12A and 12B are longitudinal cross-sectional views of the memory device. Figure 12A can be drawn along the PP profile line shown in Figure 12C, and Figure 12B can be drawn along the EE profile line shown in Figure 12C. . Figure 12C is a transverse cross-sectional view of the memory device, which can be drawn along the QQ cross-sectional line shown in Figures 12A and 12B. The electrode element 300 may be formed in the slit 673. The electrode element 300 may include a metal layer such as tungsten (W) or the like. The electrode element 300 may also include a barrier layer with conductive properties, and the metal layer is formed on the barrier layer. The barrier layer may include, for example, tantalum nitride (TaN), titanium nitride (TiN), or the like. In an embodiment, the electrode element 300 may be formed on the dielectric film after the dielectric film is formed. The dielectric film may include high K materials, such as aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), and other suitable dielectric materials. The electrode elements 300 are separated from each other by the insulating film 654 in the third direction D3 and are arranged on the sidewall memory surface of the memory element 100 (ie, the convex curved sidewall memory surface 120). The third direction D3 is different from the first direction D1 and the second direction D2. In an embodiment, the third direction D3 may be substantially perpendicular to the first direction D1 and the second direction D2. The third direction D3 may be the Z direction, for example, a direction perpendicular to the upper surface of the substrate 650.

In one embodiment, the structure constituting the memory cell may be similar to the structure shown in Figure 1. The electrode element 300 is a gate electrode element and serves as a word line. The memory cell is defined in the memory element 100 between the channel element 200 and the electrode element 300. In the third direction D3, memory cells of different levels are electrically connected in parallel between the source-side element 242 and the drain-side element 244. The memory device may include an AND type memory device. The manufacturing method according to the embodiment can form the memory device in a self-aligned manner, and the method is simple And can reduce costs.

Please refer to Figure 13A and Figure 13B. FIG. 13A is a longitudinal sectional view of the memory device, which can be drawn along the EE section line shown in FIG. 13B. FIG. 13B is a transverse cross-sectional view of the memory device, which can be drawn along the QQ section line shown in FIG. 13A. An insulating film 674 may be formed in the trench 671. The insulating film 674 may include oxide such as silicon oxide, or nitride such as silicon nitride, or other suitable insulating materials. The insulating film 674 can be formed by a suitable method such as physical vapor deposition or chemical vapor deposition. A material element 676 can be formed on the insulating film 674 and fill the trench 671. In one embodiment, the material element 676 is a conductive element, which can be electrically insulated from the electrode element 300 in the stacked structure by the insulating film 674. In this example, a bias voltage can be applied to the material element 676 to inject current to perform joule heat on the memory cell, thereby improving the performance of the memory cell such as endurance and data retention. In another embodiment, the material element 676 is an insulating material, such as an oxide such as silicon oxide, etc., which can be used as a bypass element together with the insulating film 674.

Please refer to the longitudinal sectional view of the memory device shown in Figure 14. The first conductive via 678 may be formed on the source side element 242 and the drain side element 244. The first metal layer M1 may be formed on the first conductive via 678. The second conductive via 680 may be formed on the first metal layer M1. The second metal layer M2 may be formed on the second conductive via 680.

In another embodiment, the manufacturing process described with reference to FIGS. 3A and 3B is to omit the step of forming the memory element 100, and referring to FIGS. 11A and 11B. After the step of forming the slit 673 described in FIG. and FIG. 11C, the memory element 100 is formed on the surface of the channel surface 220 and the insulating film 654 of the convex sidewall of the channel element 200 exposed by the slit 673. Then, steps similar to those described with reference to FIGS. 12A, 12B, and 12C to form the electrode element 300 in the slit 673 are performed. Through this modification, a memory device as shown in FIG. 15 can be formed, in which the memory element 100 is located on the upper electrode surface, the lower electrode surface, and the sidewall electrode surface of the electrode element 300.

In an embodiment, the step of etching back/forming the notch 664 of the insulating element 400 described with reference to FIGS. 6A, 6B, and 6C may be omitted. Through this change, a memory device as shown in Figure 2 can be formed.

The source-side element 242 and the drain-side element 244 formed by the epitaxial method described with reference to FIGS. 7A and 7B are not limited to the outline shown in FIG. 7B. The source-side element 242 and the drain-side element 244 may have other profiles due to the selected epitaxial process parameters, for example, as shown in FIGS. 16 and 17. The source-side element 242 and the drain-side element 244 of any contour grown from the surface of the channel element 200 by epitaxial method are all within the concept of the present disclosure.

According to the above disclosure, the memory device of the embodiment can have an improved memory cell array density.

In summary, although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Those who have ordinary knowledge in the technical field to which the present invention belongs can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to those defined by the attached patent application scope.

100: memory element

110: Concave side wall memory surface

120: Convex side wall memory surface

130: Sidewall memory plane

200: channel element

210: Concave curved side wall channel surface

220: Convex side wall channel surface

242: Source-side components

244: Drain side component

245: Convex side wall surface

300: Electrode element

310: sidewall electrode surface

400: insulating element

410: Flat sidewall insulation surface

420: convex curved sidewall insulation surface

500: insulating layer

D1: First direction

D2: second direction

D3: Third party

K1, K2: size

Claims (9)

A memory device includes: a channel element having an open-loop shape; a memory element; an electrode element, wherein a memory cell is defined in the memory element between the channel element and the electrode element; an insulating element having An adjacent convex curved sidewall insulation surface and a planar sidewall insulation surface; a source side element; and a drain side element, wherein the channel element is electrically connected to the source side element and the drain side element In between, the channel element is adjacent to the convex curved sidewall insulation surface, and the source side element and the drain side element extend from the channel element beyond the planar sidewall insulation surface. The memory device described in claim 1, wherein the channel element has a concave curved side wall channel surface and a convex curved side wall channel surface opposite to each other. In the memory device described in claim 1, wherein the size of the channel element is smaller than the size of the source-side element, and the size of the channel element is smaller than the size of the drain-side element. A memory device includes: a channel element; a memory element having an open loop shape; An electrode element, in which a memory cell is defined in the memory element between the channel element and the electrode element; an insulating element having an adjacent convex curved sidewall insulating surface and a planar sidewall insulating surface; a source A pole-side element; and a drain-side element, wherein the channel element is electrically connected between the source-side element and the drain-side element, the channel element is adjacent to the insulating surface of the convex curved sidewall, the source-side element The drain side element extends from the channel element beyond the insulating surface of the planar sidewall. The memory device according to claim 4, wherein the memory element includes a concave curved sidewall memory surface and a convex curved sidewall memory surface opposite to each other, and a sidewall memory plane is formed between the concave curved sidewall memory surface and the convex Between the curved sidewall memory surfaces. The memory device described in claim 5, wherein the channel element is on the memory surface of the concave curved side wall, and the electrode element is on the memory surface of the convex curved side wall. The memory device according to claim 4, wherein the channel element is disposed between the source-side element, the drain-side element, and the memory element. A memory device includes: a memory element; a source side element; a drain side element; A channel element is electrically connected between the source side element and the drain side element; an insulating element has an adjacent convex curved sidewall insulating surface and a flat sidewall insulating surface, wherein the channel element and The source-side element and the drain-side element are respectively on opposite sides of the insulating element, the channel element is adjacent to the convexly curved sidewall insulating surface, and the source-side element and the drain-side element extend beyond the channel element The planar sidewall insulating surface; and an electrode element, in which a memory cell is defined in the memory element between the channel element and the electrode element. The memory device described in one of items 1 to 8 of the scope of the patent application includes a plurality of the electrode elements separately arranged in a vertical direction on a memory surface of a convex sidewall of the memory element, wherein most One of the memory cells is defined in the memory element between the electrode elements and the channel element.

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