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TWI710527B - Oxide dielectric and manufacturing method thereof, and solid-state electronic device and manufacturing method thereof - Google Patents

Oxide dielectric and manufacturing method thereof, and solid-state electronic device and manufacturing method thereof Download PDF

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TWI710527B
TWI710527B TW105139027A TW105139027A TWI710527B TW I710527 B TWI710527 B TW I710527B TW 105139027 A TW105139027 A TW 105139027A TW 105139027 A TW105139027 A TW 105139027A TW I710527 B TWI710527 B TW I710527B
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TW201741245A (en
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下田達也
井上聰
有賀智紀
竹內慎治
瀨川茂俊
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國立大學法人北陸先端科學技術大學院大學
日商安達滿納米奇精密寶石有限公司
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Abstract

本發明之1種由氧化物介電質所構成之氧化物層30係具有燒綠石型結晶構造之結晶相,含有由鉍(Bi)與鈮(Nb)與鈦(Ti)所構成之氧化物(可含無法避免的雜質),當該鉍(Bi)之原子數為1之時,該鈮(Nb)之原子數為0.5以上~未達1.7,且當該鉍(Bi)之原子數為1之時,該鈦(Ti)之原子數為超過0~未達1.3。 An oxide layer 30 composed of an oxide dielectric substance of the present invention has a pyrochlore-type crystal structure of the crystal phase, and contains oxides composed of bismuth (Bi), niobium (Nb) and titanium (Ti) (It may contain unavoidable impurities). When the number of atoms of bismuth (Bi) is 1, the number of atoms of niobium (Nb) is 0.5 to less than 1.7, and when the number of atoms of bismuth (Bi) When it is 1, the number of atoms of the titanium (Ti) is more than 0 to less than 1.3.

Description

氧化物介電質及其製造方法、以及固態電子裝置及其製造方法 Oxide dielectric and manufacturing method thereof, and solid-state electronic device and manufacturing method thereof

本發明係關於一種氧化物介電質及其製造方法、以及固態電子裝置及其製造方法。 The present invention relates to an oxide dielectric and a manufacturing method thereof, and a solid-state electronic device and a manufacturing method thereof.

以往以開發出由具備機能性之各種組成所構成之氧化物層。此外,做為具備該氧化物層之固態電子裝置之一例,已開發出具備有可期待高速動作之強介電質薄膜的裝置。此外,固態電子裝置所使用之介電質材料在不含鉛(Pb)且能以相對低溫燒成的氧化物層方面已開發了BiNbO4。關於此BiNbO4,已有報告指出利用固相成長法所形成之BiNbO4的介電特性(非專利文獻1)。此外,專利文獻中也揭示了1kHz之相對介電係數為60以上、亦即相對介電係數相對高的由鉍(Bi)與鈮(Nb)所構成之氧化物層(專利文獻1~3)。 In the past, oxide layers composed of various functional compositions have been developed. In addition, as an example of a solid-state electronic device provided with this oxide layer, a device with a ferroelectric thin film that can be expected to operate at high speed has been developed. In addition, the dielectric materials used in solid-state electronic devices have developed BiNbO 4 in terms of oxide layers that do not contain lead (Pb) and can be fired at a relatively low temperature. Regarding this BiNbO 4 , there have been reports indicating the dielectric properties of BiNbO 4 formed by the solid-phase growth method (Non-Patent Document 1). In addition, patent literature also discloses an oxide layer composed of bismuth (Bi) and niobium (Nb) with a relative permittivity of 60 or more at 1 kHz, that is, a relatively high relative permittivity (Patent Documents 1 to 3) .

先前技術文獻 Prior art literature 專利文獻 Patent literature

專利文獻1國際公開第WO2013/069470號 Patent Document 1 International Publication No. WO2013/069470

專利文獻2國際公開第WO2013/069471號 Patent Document 2 International Publication No. WO2013/069471

專利文獻3日本特開2015-67475號公報 Patent Document 3 JP 2015-67475 A

非專利文獻 Non-patent literature

非專利文獻1 Effect of phase transition on the microwave dielectric properties of BiNbO4,Eung Soo Kim,Woong Choi,Journal of the European Ceramic Society 26(2006)1761-1766 Non-Patent Document 1 Effect of phase transition on the microwave dielectric properties of BiNbO 4 , Eung Soo Kim, Woong Choi, Journal of the European Ceramic Society 26(2006)1761-1766

產業界中,為了實現capacitor或是condenser(以下,總稱為「capacitor」;電容器)這類半導體裝置或是包含微電機系統等之固態電子裝置的高性能化,而需要不僅具備高相對介電係數且具備低介電損耗(tanδ)之電氣特性的氧化物介電質以及氧化物介電質之層。進而,若具有此種特性之氧化物介電質的製造程序中特別是關於加熱溫度之自由度可提高,則可更安定且可實現高可靠性的氧化物介電質之製造將成為可能。 In the industry, in order to achieve high performance of semiconductor devices such as capacitors or condensers (hereinafter collectively referred to as "capacitors"; capacitors) or solid-state electronic devices including micro-motor systems, it is necessary not only to have high relative permittivity And has low dielectric loss (tanδ) electrical characteristics of oxide dielectric and oxide dielectric layer. Furthermore, if the degree of freedom regarding the heating temperature in the manufacturing process of an oxide dielectric with such characteristics can be increased, it will be possible to manufacture an oxide dielectric that is more stable and can achieve high reliability.

此外,即使是其他固態電子裝置例如包含高頻濾波器、貼片天線、半導體裝置、微電機系統、或是RCL當中至少2個的複合元件,更低介電損耗(tanδ)的實現為重要技術課題之一。 In addition, even for other solid-state electronic devices such as high-frequency filters, patch antennas, semiconductor devices, micro-motor systems, or composite components of at least two of RCL, the realization of lower dielectric loss (tanδ) is an important technology One of the topics.

此外,以往技術中,由於一般為真空程序、使用光微影法之程序等需要相對長時間以及/或是昂貴的設備之程序,故原材料、製造能量之使用效率非常地差。當採用上述製造方法的情況,為了製造固態電子裝置需要許多的處理與長時間,故從工業性乃至於量產性之觀點非所喜好者。此外,以往技術尚存在著大面積化相對困難的問題。 In addition, in the prior art, the use efficiency of raw materials and manufacturing energy is very poor due to the relatively long and/or expensive equipment procedures, such as vacuum procedures and procedures using photolithography. When the above-mentioned manufacturing method is adopted, a lot of processing and a long time are required to manufacture a solid-state electronic device, so it is not preferred from the viewpoint of industrialization and mass production. In addition, the previous technology still has the problem that it is relatively difficult to enlarge the area.

本發明係藉由解決上述諸多問題之至少1者來實現以氧化物做為至少介電質或是絕緣體(以下總稱為「介電質」)來使用之固態電子裝置之高性能化、或是此種固態電子裝置之製造程序的簡潔化與節能化。其結果,本發明對於在工業性乃至於量產性上優異之氧化物介電質、以及具備該氧化物介電質之固態電子裝置之提供上做出重大貢獻。 The present invention solves at least one of the above-mentioned problems to achieve high performance of solid-state electronic devices using oxide as at least a dielectric or an insulator (hereinafter collectively referred to as "dielectric"), or Simplification and energy saving of the manufacturing process of such solid-state electronic devices. As a result, the present invention has made a significant contribution to the provision of an oxide dielectric that is excellent in terms of industriality and mass productivity, and solid-state electronic devices equipped with the oxide dielectric.

本案發明者針對到目前為止之介電係數相對高的由鉍(Bi)與鈮(Nb)所構成之氧化物(以下也稱為「BNO氧化物」)之各種特性的改善或是提高,不斷地進行致力檢討與分析。但是,發明者思考到不光是著重於BNO氧化物,也將其他元素納入考慮,來實現氧化物介電質之電氣特性進一步的提高(尤其是非常低的介電損耗)也為重要者。 The inventors of this case have been aiming to improve or improve various characteristics of oxides composed of bismuth (Bi) and niobium (Nb) (hereinafter also referred to as "BNO oxides"), which have relatively high dielectric constants so far. Conduct dedicated review and analysis. However, the inventor considers that not only the BNO oxide is emphasized, but also other elements are taken into consideration to achieve further improvement of the electrical properties of the oxide dielectric (especially very low dielectric loss) is also important.

是以,發明者進行試誤而不斷進行詳細分析與想法轉換的結果,發現到諸多元素之組合當中,由鉍(Bi)與鈮(Nb)與鈦(Ti)所構成之氧化物在目前時點可實現極低之介電損耗值。再者令人玩味的是,得知具有前述組成之氧化物即使經過對於BNO氧化物而言是無法想像的高溫加熱處理,仍可發 現燒綠石型結晶構造之結晶相。其結果,所製造的氧化物可一面保持高的相對介電係數、一面實現極低之介電損耗值。 Therefore, as a result of the inventor’s trial and error and continuous detailed analysis and conversion of ideas, he discovered that among the combinations of many elements, the oxide composed of bismuth (Bi) and niobium (Nb) and titanium (Ti) is at the present time. A very low dielectric loss value can be achieved. What's more interesting is that even if the oxides with the aforementioned composition undergo high-temperature heating treatment that is unimaginable for BNO oxides, they can still generate The present pyrochlore crystal structure is the crystalline phase. As a result, the manufactured oxide can maintain a high relative permittivity while achieving a very low dielectric loss value.

此外,發明者發現在該氧化物介電質之製造方法中,藉由採用無須高真空狀態之方法,可實現廉價且簡便的製造製程。此種製造製程當中代表性者為網版印刷法或是也被稱為「奈米壓印」之「壓模」加工法。發明者也同時發現該氧化物介電質所構成之氧化物層能藉由廉價且簡便的前述各方法來圖案化。其結果,發明者獲得如下見解:藉由可實現高性能之氧化物且相較於以往可大幅簡潔化或是節能化以及易於大面積化的程序,使得該氧化物介電質之形成、乃至於具備此等氧化物介電質之固態電子裝置的製造成為可能。本發明係基於上述各觀點所創出者。 In addition, the inventor found that in the manufacturing method of the oxide dielectric, a cheap and simple manufacturing process can be achieved by using a method that does not require a high vacuum state. The representative of this type of manufacturing process is the screen printing method or the "compression mold" processing method also known as "nanoimprint". The inventors also discovered that the oxide layer composed of the oxide dielectric can be patterned by the aforementioned various methods that are inexpensive and simple. As a result, the inventors have obtained the following insights: the formation of oxide dielectrics, and even the formation of oxide dielectrics, through procedures that can achieve high-performance oxides and which can be greatly simplified or energy-saving and easy to increase in area compared to the past It is possible to manufacture solid-state electronic devices with these oxide dielectrics. The present invention is based on the above viewpoints.

本發明之一種氧化物介電質,具有燒綠石型結晶構造之結晶相,含有由鉍(Bi)與鈮(Nb)與鈦(Ti)所構成之氧化物(可含無法避免的雜質);當該鉍(Bi)之原子數為1之時,該鈮(Nb)之原子數為0.5以上~未達1.7,且當該鉍(Bi)之原子數為1之時,該鈦(Ti)之原子數為超過0~未達1.3。 An oxide dielectric of the present invention has a pyrochlore-type crystal structure in the crystalline phase, and contains oxides composed of bismuth (Bi), niobium (Nb) and titanium (Ti) (may contain unavoidable impurities) ; When the number of atoms of the bismuth (Bi) is 1, the number of atoms of the niobium (Nb) is 0.5 to less than 1.7, and when the number of atoms of the bismuth (Bi) is 1, the titanium (Ti The number of atoms in) is more than 0 to less than 1.3.

此氧化物介電質可在保持著相對高的相對介電係數之下,實現非常低的介電損耗(tanδ)值(代表性為頻率1kHz時未達0.001)。另一方面,此氧化物介電質中由鉍(Bi)與鈮(Nb)與鈦(Ti)所構成之氧化物(可含無法避免的雜質。以下針對本案中全部的氧化物相同)具有燒綠石型結晶構造之結晶相。進而,藉由採用上述原子組成比之範圍,則前述氧化物即使以高溫(例如600℃以上~800℃以下,代表性為超過620℃~800℃以下)來加熱,仍可抑制使用CuKα特性X射線之XRD測定中出現β-BiNbO4型結晶構造。此外,該氧化物介電質中至少鈦(Ti)的存在被認為是扮演創造出前述結晶構造之特異性的功用。 This oxide dielectric can achieve a very low dielectric loss (tanδ) value (typically less than 0.001 at a frequency of 1kHz) while maintaining a relatively high relative permittivity. On the other hand, this oxide dielectric consists of bismuth (Bi) and niobium (Nb) and titanium (Ti) oxides (may contain unavoidable impurities. The following is the same for all oxides in this case) The crystalline phase of the pyrochlore crystal structure. Furthermore, by adopting the above-mentioned range of atomic composition ratio, even if the aforementioned oxide is heated at a high temperature (for example, 600°C or higher to 800°C or lower, typically more than 620°C to 800°C or lower), the use of CuKα characteristics can be suppressed. X Β-BiNbO 4 -type crystal structure appeared in XRD measurement of X-ray. In addition, the presence of at least titanium (Ti) in the oxide dielectric is believed to play a specific role in creating the aforementioned crystal structure.

另一方面,上述鈮(Nb)之原子數與上述鈦(Ti)之原子數之和為1以上~2.6以下,由於能以更高確實度來實現一種氧化物介電質,其一面保持相對高的相對介電係數,一面實現極低之介電損耗值,故為適宜的一態樣。 On the other hand, the sum of the number of atoms of the above-mentioned niobium (Nb) and the above-mentioned titanium (Ti) is 1 to 2.6, and since an oxide dielectric can be realized with higher reliability, one side remains relatively High relative permittivity, while achieving extremely low dielectric loss value, is a suitable aspect.

此外,本發明之一種氧化物介電質之製造方法,包含下述製程:藉由將以含鉍(Bi)之前驅體、含鈮(Nb)之前驅體以及含鈦(Ti)之前驅體為溶質之前驅體溶液做為起始材之前驅體層在含氧雰圍中進行加熱的加熱處理,來 形成氧化物介電質之層,該氧化物介電質具有燒綠石型結晶構造之結晶相,含有由鉍(Bi)與鈮(Nb)與鈦(Ti)所構成之氧化物(可含無法避免的雜質),當該鉍(Bi)之原子數為1之時,該鈮(Nb)之原子數為0.5以上~未達1.7,且當該鉍(Bi)之原子數為1之時,該鈦(Ti)之原子數為超過0~未達1.3。 In addition, the method for manufacturing an oxide dielectric of the present invention includes the following process: by using a precursor containing bismuth (Bi), a precursor containing niobium (Nb), and a precursor containing titanium (Ti) The solute precursor solution is used as the starting material, and the precursor layer is heated in an oxygen-containing atmosphere to A layer of oxide dielectric is formed. The oxide dielectric has a pyrochlore-type crystal structure and contains an oxide composed of bismuth (Bi) and niobium (Nb) and titanium (Ti) (may contain Inevitable impurity), when the number of atoms of the bismuth (Bi) is 1, the number of atoms of the niobium (Nb) is 0.5 to less than 1.7, and when the number of atoms of the bismuth (Bi) is 1 , The number of atoms of this titanium (Ti) is more than 0 to less than 1.3.

依據此氧化物介電質之製造方法,所製造出的氧化物介電質可在保持著相對高的相對介電係數之下,實現非常低的介電損耗(tanδ)值(代表性為於頻率1kHz時未達0.001)。另一方面,此製造方法所製造之氧化物介電質,由鉍(Bi)與鈮(Nb)與鈦(Ti)所構成之氧化物(可含無法避免的雜質。以下針對本案中全部的氧化物相同)具有燒綠石型結晶構造之結晶相。進而,藉由採用上述之原子組成比的範圍,則前述氧化物即使以高溫(例如600℃以上~800℃以下,代表性為超過620℃~800℃以下)來加熱,仍可抑制使用CuKα特性X射線之XRD測定中出現β-BiNbO4型結晶構造。此外,該氧化物介電質中至少鈦(Ti)的存在被認為是扮演創造出前述結晶構造之特異性的功用。 According to the manufacturing method of this oxide dielectric, the manufactured oxide dielectric can maintain a relatively high relative permittivity and achieve a very low dielectric loss (tanδ) value (typically in Less than 0.001 when the frequency is 1kHz). On the other hand, the oxide dielectric produced by this manufacturing method is an oxide composed of bismuth (Bi), niobium (Nb) and titanium (Ti) (may contain unavoidable impurities. The following is for all of the materials in this case) The same oxide) has a pyrochlore-type crystal structure in a crystalline phase. Furthermore, by adopting the above-mentioned range of atomic composition ratio, even if the aforementioned oxide is heated at high temperature (for example, 600°C or higher to 800°C or lower, typically more than 620°C to 800°C or lower), the use of CuKα characteristics can be suppressed The β-BiNbO 4 -type crystal structure appeared in X-ray XRD measurement. In addition, the presence of at least titanium (Ti) in the oxide dielectric is believed to play a specific role in creating the aforementioned crystal structure.

另一方面,上述鈮(Nb)之原子數與上述鈦(Ti)之原子數之和為1以上~2.6以下,由於能以更高確實度來製造一種氧化物介電質,其一面保持相對高的相對介電係數、一面實現極低之介電損耗值,故為適宜的一態樣。 On the other hand, the sum of the number of atoms of niobium (Nb) and the number of atoms of titanium (Ti) is 1 to 2.6, and since it is possible to produce an oxide dielectric with higher reliability, one side remains relatively The high relative permittivity and the extremely low dielectric loss value at the same time are suitable.

此外,上述氧化物介電質之製造方法可藉由不使用光微影法之相對簡潔的處理(例如噴墨法、網版印刷法、凹版/凸版印刷法、或是奈米壓印法)來形成氧化物層。藉此,諸如使用真空程序之程序般需要相對長時間以及/或是昂貴設備的程序將不需要。其結果,上述各氧化物層之製造方法在工業性或是量產性上優異。 In addition, the above-mentioned oxide dielectric manufacturing method can be achieved by a relatively simple process (such as inkjet, screen printing, gravure/relief printing, or nanoimprinting) without using photolithography. To form an oxide layer. Thereby, procedures such as those using vacuum procedures that require a relatively long time and/or procedures that require expensive equipment will not be required. As a result, the manufacturing method of each oxide layer described above is excellent in industriality or mass productivity.

具體的一例中,上述製造方法之發明,於形成上述氧化物介電質之層之前,在含氧雰圍中以80℃以上~250℃以下來加熱上述前驅體層之狀態下施行壓模加工,藉此形成該前驅體之壓模構造,基於無須使用真空程序之程序般需要相對長時間以及/或是昂貴設備之程序的觀點為可採用之適宜的一態樣。 In a specific example, the invention of the above-mentioned manufacturing method, before forming the above-mentioned oxide dielectric layer, is subjected to compression molding while heating the above-mentioned precursor layer at a temperature above 80°C to below 250°C in an oxygen-containing atmosphere, by The mold structure for forming the precursor is a suitable aspect that can be adopted based on the viewpoint that a procedure that does not require a vacuum procedure requires a relatively long time and/or a procedure of expensive equipment.

此外,本申請案中所說的「含氧雰圍中」係指氧雰圍中或是大氣中。此外,本申請案中之「層」係不單指層也包含膜的概念。反過來說,本申請案中的「膜」不單指膜也包含層的概念。 In addition, the "in an oxygen-containing atmosphere" in this application refers to an oxygen atmosphere or the atmosphere. In addition, the "layer" in this application not only refers to the concept of a layer but also a film. Conversely speaking, the "film" in this application not only refers to the concept of a film but also a layer.

本發明之1種氧化物介電質,可在保持著相對高的相對介電係數之下實現非常低的介電損耗(tanδ)值。 The oxide dielectric of the present invention can achieve a very low dielectric loss (tanδ) value while maintaining a relatively high relative permittivity.

此外,依據本發明之1種氧化物介電質之製造方法,所製造出的氧化物介電質可在保持著相對高的相對介電係數之下實現非常低的介電損耗(tanδ)值。 In addition, according to the method for manufacturing an oxide dielectric of the present invention, the manufactured oxide dielectric can achieve a very low dielectric loss (tanδ) value while maintaining a relatively high relative permittivity. .

10‧‧‧基板 10‧‧‧Substrate

20,320‧‧‧下部電極層 20,320‧‧‧Lower electrode layer

220a,220b,220c,220d,220e‧‧‧電極層 220a, 220b, 220c, 220d, 220e‧‧‧electrode layer

221a‧‧‧電極層用前驅體層 221a‧‧‧Precursor layer for electrode layer

320a‧‧‧下部電極層用前驅體層 320a‧‧‧Precursor layer for lower electrode layer

30,230a,330‧‧‧氧化物層(氧化物介電質之層) 30,230a,330‧‧‧Oxide layer (oxide dielectric layer)

30a,330a‧‧‧前驅體層 30a,330a‧‧‧Precursor layer

340a‧‧‧上部電極層用前驅體層 340a‧‧‧Precursor layer for upper electrode layer

40,340‧‧‧上部電極層 40,340‧‧‧Upper electrode layer

100,300‧‧‧固態電子裝置一例之薄膜電容器 100,300‧‧‧Film capacitor as an example of solid-state electronic device

200‧‧‧固態電子裝置一例之積層電容器 200‧‧‧Multilayer capacitors as an example of solid-state electronic devices

400‧‧‧固態電子裝置一例之薄膜電晶體 400‧‧‧Thin Film Transistor of an Example of Solid State Electronic Device

444‧‧‧通道 444‧‧‧channel

456‧‧‧汲極電極 456‧‧‧Drain electrode

458‧‧‧源極 458‧‧‧Source

M1‧‧‧下部電極層用模具 M1‧‧‧Mould for lower electrode layer

M2‧‧‧介電質層用模具 M2‧‧‧Dielectric layer mold

M3‧‧‧上部電極層用模具 M3‧‧‧Mould for upper electrode layer

圖1係顯示本發明之第1實施形態中固態電子裝置一例之薄膜電容器之全體構成圖。 FIG. 1 is a diagram showing the overall structure of a film capacitor as an example of a solid-state electronic device in the first embodiment of the present invention.

圖2係顯示本發明之第1實施形態中薄膜電容器之製造方法之一過程的截面示意圖。 2 is a schematic cross-sectional view showing a process of the method of manufacturing the film capacitor in the first embodiment of the present invention.

圖3係顯示本發明之第1實施形態中薄膜電容器之製造方法之一過程的截面示意圖。 3 is a schematic cross-sectional view showing a process of the method of manufacturing a film capacitor in the first embodiment of the present invention.

圖4係顯示本發明之第1實施形態中薄膜電容器之製造方法之一過程的截面示意圖。 4 is a schematic cross-sectional view showing a process of the method of manufacturing a film capacitor in the first embodiment of the present invention.

圖5係顯示本發明之第1實施形態中薄膜電容器之製造方法之一過程的截面示意圖。 Fig. 5 is a schematic cross-sectional view showing a process of a method of manufacturing a film capacitor in the first embodiment of the present invention.

圖6係顯示參考例中由鉍(Bi)與鈮(Nb)與鈦(Ti)所構成之氧化物之加熱溫度差異以及燒成時間差異所致顯示該氧化物之結晶構造之X射線繞射(XRD)之測定結果變化圖。 Figure 6 shows the X-ray diffraction of the oxides composed of bismuth (Bi), niobium (Nb) and titanium (Ti) in the reference example due to the difference in heating temperature and the difference in firing time showing the crystal structure of the oxide (XRD) measurement result change graph.

圖7係顯示本發明之第1實施形態中氧化物之加熱溫度差異以及燒成時間差異所致顯示該氧化物之結晶構造之X射線繞射(XRD)之測定結果變化圖。 FIG. 7 is a graph showing the change of X-ray diffraction (XRD) measurement results showing the crystal structure of the oxide due to the difference in heating temperature and the difference in firing time in the first embodiment of the present invention.

圖8係顯示本發明之第1實施形態中氧化物之加熱溫度差異以及燒成時間差異所致顯示該氧化物之結晶構造之X射線繞射(XRD)之測定結果變化圖。 FIG. 8 is a graph showing the change of X-ray diffraction (XRD) measurement results showing the crystal structure of the oxide due to the difference in heating temperature and the difference in firing time in the first embodiment of the present invention.

圖9係顯示本發明之第1實施形態中氧化物、參考例以及比較例之加熱溫度與介電損耗(tanδ)之相關性之圖。 9 is a graph showing the correlation between the heating temperature and the dielectric loss (tan δ) of the oxide, the reference example, and the comparative example in the first embodiment of the present invention.

圖10係顯示本發明之第1實施形態中氧化物、參考例以及比較例之加熱溫度與相對介電係數之相關性之圖。 10 is a graph showing the correlation between the heating temperature and the relative permittivity of the oxide, the reference example, and the comparative example in the first embodiment of the present invention.

圖11係顯示本發明之第1實施形態中其他氧化物之加熱溫度與介電損耗(tanδ)之相關性之圖。 FIG. 11 is a graph showing the correlation between the heating temperature of other oxides and the dielectric loss (tanδ) in the first embodiment of the present invention.

圖12係顯示本發明之第1實施形態中其他氧化物之加熱溫度與相對介電係數之相關性之圖。 Fig. 12 is a graph showing the correlation between heating temperature and relative permittivity of other oxides in the first embodiment of the present invention.

圖13係顯示本發明之第2實施形態中固態電子裝置一例之積層電容器之全體構成圖。 13 is a diagram showing the overall configuration of a multilayer capacitor as an example of a solid-state electronic device in the second embodiment of the present invention.

圖14係顯示本發明之第2實施形態中固態電子裝置一例之積層電容器之製造方法之一過程的截面示意圖。 14 is a schematic cross-sectional view showing a process of a manufacturing method of a multilayer capacitor as an example of a solid-state electronic device in the second embodiment of the present invention.

圖15係顯示本發明之第2實施形態中固態電子裝置一例之積層電容器之製造方法之一過程的截面示意圖。 15 is a schematic cross-sectional view showing a process of a manufacturing method of a multilayer capacitor as an example of a solid-state electronic device in the second embodiment of the present invention.

圖16係顯示本發明之第2實施形態中固態電子裝置一例之積層電容器之製造方法之一過程的截面示意圖。 16 is a schematic cross-sectional view showing a process of a manufacturing method of a multilayer capacitor as an example of a solid-state electronic device in the second embodiment of the present invention.

圖17係顯示本發明之第2實施形態中固態電子裝置一例之積層電容器之製造方法之一過程的截面示意圖。 17 is a schematic cross-sectional view showing a process of a manufacturing method of a multilayer capacitor as an example of a solid-state electronic device in the second embodiment of the present invention.

圖18係顯示本發明之第2實施形態中固態電子裝置一例之積層電容器之製造方法之一過程的截面示意圖。 18 is a schematic cross-sectional view showing a process of a manufacturing method of a multilayer capacitor as an example of a solid-state electronic device in the second embodiment of the present invention.

圖19係顯示本發明之第3實施形態中固態電子裝置一例之薄膜電容器之全體構成圖。 19 is a diagram showing the overall structure of a film capacitor as an example of a solid-state electronic device in the third embodiment of the present invention.

圖20係顯示本發明之第3實施形態中固態電子裝置一例之薄膜電容器之製造方法之一過程的截面示意圖。 20 is a schematic cross-sectional view showing a process of a method for manufacturing a thin film capacitor as an example of a solid-state electronic device in the third embodiment of the present invention.

圖21係顯示本發明之第3實施形態中固態電子裝置一例之薄膜電容器之製造方法之一過程的截面示意圖。 21 is a schematic cross-sectional view showing a process of a method of manufacturing a film capacitor as an example of a solid-state electronic device in the third embodiment of the present invention.

圖22係顯示本發明之第3實施形態中固態電子裝置一例之薄膜電容器之製造方法之一過程的截面示意圖。 22 is a schematic cross-sectional view showing a process of a method of manufacturing a film capacitor as an example of a solid-state electronic device in the third embodiment of the present invention.

圖23係顯示本發明之第3實施形態中固態電子裝置一例之薄膜電容器之製造方法之一過程的截面示意圖。 23 is a schematic cross-sectional view showing a process of a method of manufacturing a thin film capacitor as an example of a solid-state electronic device in the third embodiment of the present invention.

圖24係顯示本發明之第3實施形態中固態電子裝置一例之薄膜電容器之製造方法之一過程的截面示意圖。 24 is a schematic cross-sectional view showing a process of a method of manufacturing a film capacitor as an example of a solid-state electronic device in the third embodiment of the present invention.

圖25係顯示本發明之第3實施形態中固態電子裝置一例之薄膜電容器之製造方法之一過程的截面示意圖。 25 is a schematic cross-sectional view showing a process of a method of manufacturing a film capacitor as an example of a solid-state electronic device in the third embodiment of the present invention.

圖26係顯示本發明之第3實施形態中固態電子裝置一例之薄膜電容器之製造方法之一過程的截面示意圖。 26 is a schematic cross-sectional view showing a process of a method of manufacturing a thin film capacitor as an example of a solid-state electronic device in the third embodiment of the present invention.

圖27係顯示本發明之第3實施形態中固態電子裝置一例之薄膜電容器之製造方法之一過程的截面示意圖。 27 is a schematic cross-sectional view showing a process of a method for manufacturing a thin film capacitor as an example of a solid-state electronic device in the third embodiment of the present invention.

圖28係顯示本發明之第3實施形態中固態電子裝置一例之薄膜電容器之製造方法之一過程的截面示意圖。 28 is a schematic cross-sectional view showing a process of a method of manufacturing a thin film capacitor as an example of a solid-state electronic device in the third embodiment of the present invention.

圖29係顯示本發明之第3實施形態中固態電子裝置一例之薄膜電容器之製造方法之一過程的截面示意圖。 29 is a schematic cross-sectional view showing a process of a method of manufacturing a thin film capacitor as an example of a solid-state electronic device in the third embodiment of the present invention.

圖30係顯示本發明之其他實施形態之薄膜電晶體之全體構成圖。 Fig. 30 is a diagram showing the overall structure of a thin film transistor according to another embodiment of the present invention.

針對本發明之實施形態之固態電子裝置基於所附圖式來詳細描述。此外,說明過程中,全部的圖在未特別提到的前提下針對共通部分係賦予共通之參見符號。此外,圖中本實施形態之要素未必彼此保持縮尺來記載。再者,為便於觀看各圖式有可能省略一部分的符號。 The solid-state electronic device according to the embodiment of the present invention is described in detail based on the drawings. In addition, in the description process, all the drawings are given common reference symbols for the common parts without special mention. In addition, the elements of the present embodiment in the figure are not necessarily described with each other on a scale. Furthermore, some symbols may be omitted in order to facilitate the viewing of the drawings.

<第1實施形態> <First Embodiment>

1.本實施形態之薄膜電容器之全體構成 1. The overall structure of the film capacitor of this embodiment

圖1係顯示本實施形態中固態電子裝置一例之薄膜電容器100之全體構成圖。如圖1所示般,薄膜電容器100於基板10上從基板10之側依序具備下部電極層20、氧化物介電質之層(以下也簡稱為「氧化物層」。以下相同)30以及上部電極層40。 FIG. 1 is a diagram showing the overall structure of a film capacitor 100 as an example of a solid-state electronic device in this embodiment. As shown in FIG. 1, the film capacitor 100 is provided with a lower electrode layer 20 and an oxide dielectric layer (hereinafter also referred to as "oxide layer". The same hereinafter) 30 and The upper electrode layer 40.

基板10可使用各種絕緣性基材,包含例如高耐熱玻璃、SiO2/Si基板、氧化鋁(Al2O3)基板、STO(SrTiO)基板、於Si基板表面上經由SiO2層以及 Ti層而形成有STO(SrTiO)層之絕緣性基板等;於Si基板表面上依序積層有SiO2層以及TiOX層之絕緣性基板、半導體基板(例如Si基板、SiC基板、Ge基板、樹脂製基板等)。 The substrate 10 can use various insulating substrates, including, for example, high heat-resistant glass, SiO 2 /Si substrate, alumina (Al 2 O 3 ) substrate, STO (SrTiO) substrate, and SiO 2 layer and Ti layer on the surface of Si substrate. Insulating substrates with STO (SrTiO) layer formed, etc.; insulating substrates with SiO 2 layers and TiO X layers laminated on the surface of Si substrates, semiconductor substrates (such as Si substrates, SiC substrates, Ge substrates, resin-made substrates) Substrate, etc.).

下部電極層20以及上部電極層40之材料係使用鉑、金、銀、銅、鋁、鉬、鈀、釕、銥、鎢等高熔點金屬或是其合金等的金屬材料。 The lower electrode layer 20 and the upper electrode layer 40 are made of high melting point metals such as platinum, gold, silver, copper, aluminum, molybdenum, palladium, ruthenium, iridium, and tungsten, or metal materials such as alloys thereof.

本實施形態中,氧化物介電質之層(氧化物層30)係將以含鉍(Bi)之前驅體、含鈮(Nb)之前驅體以及含鈦(Ti)之前驅體為溶質之前驅體溶液做為起始材之前驅體在含氧雰圍中進行加熱所形成(以下,本製程之製造方法也稱為「溶液法」)。此外,本實施形態中前驅體溶液中的溶質可採用例如,2-乙基己酸鉍、2-乙基己酸鈮、以及2-乙基己酸鈦。 In this embodiment, the oxide dielectric layer (oxide layer 30) will be based on a precursor containing bismuth (Bi), a precursor containing niobium (Nb), and a precursor containing titanium (Ti) as the solute. The driver solution is used as the starting material and the precursor is heated in an oxygen-containing atmosphere (hereinafter, the manufacturing method of this process is also referred to as "solution method"). In addition, as the solute in the precursor solution in this embodiment, for example, bismuth 2-ethylhexanoate, niobium 2-ethylhexanoate, and titanium 2-ethylhexanoate can be used.

藉由採用上述以前驅體溶液做為起始材之前驅體之層(也簡稱為「前驅體層」),得到由鉍(Bi)與鈮(Nb)與鈦(Ti)所構成之氧化物30。更具體而言,如後述般,以至少800℃以下(更佳為700℃以下)做加熱處理所得之本實施形態之氧化物層30係包含燒綠石型結晶構造之結晶相所構成之氧化物。此是基於藉由X射線繞射(XRD)測定氧化物層30未觀測到源自β-BiNbO4型結晶構造之波峰此一令人玩味的分析結果所得見地。此外,本實施形態之氧化物層30可包含微結晶相。 By using the aforementioned precursor solution as the starting material precursor layer (also referred to as "precursor layer"), an oxide composed of bismuth (Bi), niobium (Nb) and titanium (Ti) is obtained. . More specifically, as will be described later, the oxide layer 30 of the present embodiment obtained by heating at least 800°C or less (more preferably 700°C or less) is an oxide composed of a pyrochlore-type crystal structure. Things. This is based on the interesting analysis result that the oxide layer 30 is measured by X-ray diffraction (XRD), and no peak derived from the β-BiNbO 4 crystal structure is observed. In addition, the oxide layer 30 of this embodiment may include a microcrystalline phase.

此外,到目前為止所知一般的燒綠石型結晶構造為在由鉍(Bi)與鈮(Nb)與鋅(Zn)所構成之氧化物中所觀察到的構造,但本發明者所得分析結果為:由鉍(Bi)與鈮(Nb)與鈦(Ti)所構成之本實施形態之氧化物層30具有燒綠石型結晶構造。為何氧化物層30會發現燒綠石型結晶構造目前不明。但是,如後述般,已獲知具有燒綠石型結晶構造之結晶相係和做為薄膜電容器之介電質層、積層電容器之介電質層、或是其他各種固態電子裝置(例如半導體裝置或是微電機系統)之絕緣層所需良好的介電特性(尤其是非常低的介電損耗)相關。 In addition, the general pyrochlore-type crystal structure known so far is the structure observed in oxides composed of bismuth (Bi), niobium (Nb), and zinc (Zn), but the inventors have obtained the analysis As a result, the oxide layer 30 of the present embodiment composed of bismuth (Bi), niobium (Nb), and titanium (Ti) has a pyrochlore type crystal structure. It is currently unknown why the oxide layer 30 has a pyrochlore crystal structure. However, as described later, it is known that the crystalline phase system with a pyrochlore-type crystal structure and the dielectric layer as a thin film capacitor, the dielectric layer of a multilayer capacitor, or other various solid-state electronic devices (such as semiconductor devices or It is related to the good dielectric properties (especially very low dielectric loss) required for the insulating layer of the micro-motor system.

此外,確認了本實施形態之氧化物層30依組成比以及/或是加熱溫度除了上述第1結晶相以及/或是第2結晶相也具有非晶質相以及Bi3NbO7型結晶構造之結晶相(第3結晶相)(但是富含Nb之氧化物層之情況則未發現Bi3NbO7型結晶)。如此般,存在著各種結晶相與非晶質相一事,從高機率 防止無謂的晶界形成所致電氣特性的劣化乃至於變動的觀點為適切的一態樣。 In addition, it was confirmed that the oxide layer 30 of this embodiment has, depending on the composition ratio and/or heating temperature, in addition to the first crystal phase and/or the second crystal phase, it also has an amorphous phase and a Bi 3 NbO 7 type crystal structure. Crystal phase (third crystal phase) (However, in the case of the Nb-rich oxide layer, no Bi 3 NbO 7 type crystal was found). In this way, there are various crystalline phases and amorphous phases, and it is appropriate from the viewpoint of preventing the deterioration and fluctuation of electrical properties caused by unnecessary grain boundary formation with a high probability.

此外,本實施形態不限定於圖1所示構造。此外,為簡化圖式,針對來自各電極層之引出電極層的圖案化之記載加以省略。 In addition, this embodiment is not limited to the structure shown in FIG. 1. In addition, in order to simplify the drawing, the description of the patterning of the lead electrode layer from each electrode layer is omitted.

2.薄膜電容器100之製造方法 2. Manufacturing method of film capacitor 100

其次說明薄膜電容器100之製造方法。此外,本專利申請之溫度顯示係表示加熱器之設定溫度。圖2乃至圖5分別為薄膜電容器100之製造方法一過程的截面示意圖。如圖2所示般,首先,於基板10上形成下部電極層20。其次,於下部電極層20上形成氧化物層30,之後,於氧化物層30上形成上部電極層40。 Next, the method of manufacturing the film capacitor 100 will be described. In addition, the temperature display of this patent application indicates the set temperature of the heater. FIG. 2 and FIG. 5 are cross-sectional schematic diagrams of a process of manufacturing the film capacitor 100 respectively. As shown in FIG. 2, first, the lower electrode layer 20 is formed on the substrate 10. Next, an oxide layer 30 is formed on the lower electrode layer 20, and then, an upper electrode layer 40 is formed on the oxide layer 30.

(1)下部電極層之形成 (1) Formation of the lower electrode layer

圖2顯示下部電極層20之形成過程圖。本實施形態中,舉出薄膜電容器100之下部電極層20由鉑(Pt)所形成之例來說明。下部電極層20係藉由周知的濺鍍法在基板10上形成由鉑(Pt)所構成之層(例如200nm厚)。 FIG. 2 shows a process diagram of the formation of the lower electrode layer 20. In this embodiment, an example in which the lower electrode layer 20 of the film capacitor 100 is formed of platinum (Pt) will be described. The lower electrode layer 20 is formed by forming a layer (for example, 200 nm thick) made of platinum (Pt) on the substrate 10 by a well-known sputtering method.

(2)做為絕緣層之氧化物層的形成 (2) Formation of oxide layer as insulating layer

其次,於下部電極層20上形成氧化物層30。氧化物層30係以(A)前驅體層之形成以及預備燒成之製程、(B)正式燒成之製程的順序來形成。圖3以及圖4係顯示氧化物層30之形成過程之圖。本實施形態中,薄膜電容器100之製造製程的氧化物層30係舉出具有燒綠石型結晶構造之結晶相、由鉍(Bi)與鈮(Nb)與鈦(Ti)所構成之氧化物所形成之例來說明。 Next, an oxide layer 30 is formed on the lower electrode layer 20. The oxide layer 30 is formed in the order of (A) precursor layer formation and preliminary firing process, and (B) formal firing process. 3 and 4 are diagrams showing the formation process of the oxide layer 30. In this embodiment, the oxide layer 30 of the manufacturing process of the film capacitor 100 is a pyrochlore crystal structure with a crystal phase, an oxide composed of bismuth (Bi), niobium (Nb) and titanium (Ti) The examples formed to illustrate.

(A)前驅體層之形成以及預備燒成 (A) Formation of precursor layer and preparation for firing

如圖3所示般,於下部電極層20上,藉由周知的旋塗法來形成以含鉍(Bi)之前驅體(也稱為前驅體A)、含鈮(Nb)之前驅體(也稱為前驅體B)、以及含鈦(Ti)之前驅體(也稱為前驅體C)為溶質之前驅體溶液(以下簡稱為「前驅體溶液」)做為起始材之前驅體層(也稱為「前驅體層」)30a。 As shown in FIG. 3, on the lower electrode layer 20, a bismuth (Bi)-containing precursor (also referred to as precursor A) and a niobium (Nb)-containing precursor ( Also called precursor B), and titanium (Ti)-containing precursor (also called precursor C) is the solute precursor solution (hereinafter referred to as the ``precursor solution'') as the starting material precursor layer ( Also called "precursor layer") 30a.

此處,氧化物層30所需前驅體A之例除了上述2-乙基己酸鉍以外,尚可採用辛基酸鉍、氯化鉍、硝酸鉍、或是各種鉍烷氧化物(例如異丙氧化鉍、丁氧化鉍、乙氧化鉍、甲氧基乙氧化鉍)。此外,本實施形態中前驅體B之例除了上述2-乙基己酸鈮以外,尚可採用辛基酸鈮、氯化鈮、硝酸鈮、 或是各種鈮烷氧化物(例如異丙氧化鈮、丁氧化鈮、乙氧化鈮、甲氧基乙氧化鈮)。此外,本實施形態中前驅體C之例除了上述2-乙基己酸鈦以外,尚可採用辛基酸鈦、氯化鈦、硝酸鈦、或是各種鈦烷氧化物(例如異丙氧化鈦、丁氧化鈦、乙氧化鈦、甲氧基乙氧化鈦)。 Here, examples of the precursor A required for the oxide layer 30 in addition to the above-mentioned bismuth 2-ethylhexanoate, bismuth octylate, bismuth chloride, bismuth nitrate, or various bismuth alkoxides (such as Bismuth propoxide, bismuth butoxide, bismuth ethoxide, bismuth methoxyethoxide). In addition, in the example of the precursor B in this embodiment, in addition to the above 2-ethylhexanoate niobium, niobium octylate, niobium chloride, niobium nitrate, Or various niobium alkoxides (for example, niobium isopropoxide, niobium butoxide, niobium ethoxide, niobium ethoxylate). In addition, in the example of the precursor C in this embodiment, in addition to the above-mentioned titanium 2-ethylhexanoate, titanium octylate, titanium chloride, titanium nitrate, or various titanium alkoxides (such as titanium isopropoxide) , Titanium butoxide, titanium ethoxide, titanium methoxyethoxide).

此外,前驅體溶液之溶媒以選自乙醇、丙醇、丁醇、2-甲氧基乙醇、2-乙氧基乙醇、以及2-丁氧基乙醇之群中至少1種的醇溶媒、或是選自乙酸、丙酸、辛酸、以及2-乙基己酸之群中至少1種的羧酸溶媒為佳。從而,在前驅體溶液之溶媒方面,上述2種以上之醇溶媒的混合溶媒、上述2種以上羧酸之混合溶媒也為可採用之一態樣。 In addition, the solvent of the precursor solution is at least one alcohol solvent selected from the group consisting of ethanol, propanol, butanol, 2-methoxyethanol, 2-ethoxyethanol, and 2-butoxyethanol, or It is preferably at least one carboxylic acid solvent selected from the group of acetic acid, propionic acid, caprylic acid, and 2-ethylhexanoic acid. Therefore, regarding the solvent of the precursor solution, a mixed solvent of the above-mentioned two or more kinds of alcohol solvents and a mixed solvent of the above-mentioned two or more kinds of carboxylic acids can also be adopted.

此外,本實施形態之前驅體溶液係將下述之(1)所示第1溶液、下述之(2)所示第2溶液、下述之(3)所示第3溶液加以混合來製造。 In addition, the precursor solution of this embodiment is produced by mixing the first solution shown in (1) below, the second solution shown in (2) below, and the third solution shown in (3) below. .

(1)將2-乙基己酸鉍經1-丁醇所稀釋後之溶液與2-乙基己酸鉍經2-甲氧基乙醇所稀釋後之溶液加以混合而得之第1溶液、或是2-乙基己酸鉍經2-乙基己酸所稀釋後之第1溶液 (1) The first solution obtained by mixing the solution of bismuth 2-ethylhexanoate diluted with 1-butanol and the solution of bismuth 2-ethylhexanoate diluted with 2-methoxyethanol, Or the first solution of bismuth 2-ethylhexanoate diluted with 2-ethylhexanoic acid

(2)將2-乙基己酸鈮經1-丁醇所稀釋後之溶液與2-乙基己酸鈮經2-甲氧基乙醇所稀釋後之溶液加以混合而得之第2溶液、或是鈮乙氧化物經2-乙基己酸所稀釋後之第2溶液 (2) The second solution obtained by mixing the solution of niobium 2-ethylhexanoate diluted with 1-butanol and the solution of niobium 2-ethylhexanoate diluted with 2-methoxyethanol, Or the second solution of niobium ethoxide diluted with 2-ethylhexanoic acid

(3)將2-乙基己酸鈦經1-丁醇所稀釋後之溶液與2-乙基己酸鈦經2-甲氧基乙醇所稀釋後之溶液加以混合而得之第3溶液、或是2-乙基己酸鈦經2-乙基己酸所稀釋後之第3溶液 (3) The third solution obtained by mixing the solution of titanium 2-ethylhexanoate diluted with 1-butanol and the solution of titanium 2-ethylhexanoate diluted with 2-methoxyethanol, Or the third solution of titanium 2-ethylhexanoate diluted with 2-ethylhexanoic acid

此外,本實施形態中,以當鉍(Bi)之原子數為1.5之時,鈮(Nb)之原子數為1~2、以及鈦(Ti)之原子數為0.5~1.5的方式來調製前驅體溶液。 In addition, in this embodiment, when the number of atoms of bismuth (Bi) is 1.5, the number of atoms of niobium (Nb) is 1 to 2, and the number of atoms of titanium (Ti) is 0.5 to 1.5, the precursor is prepared. Body solution.

之後,做為預備燒成,在含氧雰圍中以既定時間、於80℃以上~250℃以下之溫度範圍進行預備燒成。預備燒成中,係使得前驅體層30a中之溶媒(代表性的為主溶媒)充分蒸發,並形成未來可呈現出塑性變形特性之較佳的凝膠狀態(被認為於熱分解前處於殘存著有機鏈之狀態)。形成如此狀態之凝膠狀態,使得後述成膜製程之一做法亦即壓模加工法或是網版印刷法所進行之成膜更為容易。此外,為了以更高確實度來實現前述觀點,預備燒成溫度以80℃以上、250℃以下為佳。此外,藉由使得前述旋塗法所做前驅 體層30a之形成以及預備燒成反覆進行複數次,可得到氧化物層30之所希望之厚度。 After that, as a preliminary firing, the preliminary firing is carried out in an oxygen-containing atmosphere for a predetermined time at a temperature ranging from 80°C to 250°C. In the preliminary firing, the solvent (typically the main solvent) in the precursor layer 30a is fully evaporated, and a better gel state that can exhibit plastic deformation characteristics in the future is formed (it is considered that it remains in the residual state before thermal decomposition). The state of the organic chain). The formation of the gel state in such a state makes it easier to form a film by the compression molding method or the screen printing method, which is one of the film forming processes described later. In addition, in order to realize the aforementioned viewpoint with higher reliability, the preliminary firing temperature is preferably 80°C or higher and 250°C or lower. In addition, by making the aforementioned spin coating method a precursor The formation of the bulk layer 30a and the preliminary firing are repeated several times to obtain the desired thickness of the oxide layer 30.

(B)正式燒成 (B) Formal firing

之後,於本實施形態,做為正式燒成所需加熱製程,係使得前驅體層30a在氧雰圍中(例如100體積%,但不限定於此)、以既定時間(例如20分鐘)、550℃以上~800℃以下之範圍的溫度(第1溫度)做加熱而進行的加熱製程。其結果,如圖4所示般,於電極層上形成由鉍(Bi)與鈮(Nb)與鈦(Ti)所構成之氧化物層(氧化物層30)(例如170nm厚)。 Then, in this embodiment, as the heating process required for the main firing, the precursor layer 30a is exposed to an oxygen atmosphere (for example, 100% by volume, but not limited to this) for a predetermined time (for example, 20 minutes), at 550°C The heating process is carried out by heating at a temperature (the first temperature) in the range above to below 800℃. As a result, as shown in FIG. 4, an oxide layer (oxide layer 30) composed of bismuth (Bi), niobium (Nb) and titanium (Ti) (for example, 170 nm thick) is formed on the electrode layer.

此外,氧化物層30之膜厚範圍以30nm以上為佳。若氧化物層30之膜厚未達30nm,伴隨膜厚減少造成漏電流以及介電損耗之增加,則適用於固態電子裝置時不符實用而非所喜好者。 In addition, the thickness range of the oxide layer 30 is preferably 30 nm or more. If the film thickness of the oxide layer 30 is less than 30 nm, the leakage current and the dielectric loss increase due to the decrease of the film thickness, which is not suitable for practical use but not preferred when applied to solid-state electronic devices.

(3)上部電極層之形成 (3) Formation of the upper electrode layer

其次,於氧化物層30上形成上部電極層40。圖5係顯示上部電極層40之形成過程圖。本實施形態中,係舉出薄膜電容器100之上部電極層40由鉑(Pt)所形成之例來說明。上部電極層40和下部電極層20同樣地係藉由周知之濺鍍法於氧化物層30上形成由鉑(Pt)所構成之層(例如150nm厚)。藉由此上部電極層40之形成,製造圖1所示薄膜電容器100。 Next, an upper electrode layer 40 is formed on the oxide layer 30. FIG. 5 is a diagram showing the formation process of the upper electrode layer 40. In this embodiment, an example in which the upper electrode layer 40 of the film capacitor 100 is formed of platinum (Pt) will be described. The upper electrode layer 40 and the lower electrode layer 20 are similarly formed with a platinum (Pt) layer (for example, 150 nm thick) on the oxide layer 30 by a well-known sputtering method. With the formation of the upper electrode layer 40, the film capacitor 100 shown in FIG. 1 is manufactured.

另一方面,本實施形態中雖將形成氧化物層30之際的正式燒成溫度(第1溫度)設定在550℃以上、800℃以下,但第1溫度不限定於前述溫度範圍。另一方面,相當值得玩味的是,發明者發現若在550℃以上~800℃以下之溫度範圍、尤其是在600℃以上~800℃以下(代表性為超過620℃~800℃以下、或是650℃以上~800℃以下)之溫度範圍來變化正式燒成之溫度或是加熱溫度,不僅可變化由鉍(Bi)與鈮(Nb)與鈦(Ti)所構成之氧化物之相對介電係數之值、也可變化其介電損耗。 On the other hand, in the present embodiment, the main firing temperature (first temperature) when forming the oxide layer 30 is set at 550°C or higher and 800°C or lower, but the first temperature is not limited to the aforementioned temperature range. On the other hand, it is quite interesting that the inventor found that if the temperature range is above 550℃~800℃, especially above 600℃~800℃ (typically more than 620℃~800℃, or 650℃~800℃ below) to change the formal firing temperature or heating temperature, not only can change the relative dielectric of oxides composed of bismuth (Bi) and niobium (Nb) and titanium (Ti) The value of the coefficient can also change its dielectric loss.

此外,若採用本實施形態之氧化物層之製造方法,由於無需使用真空程序只要在含氧雰圍中來加熱氧化物層之前驅體溶液即可,故相較於以往之濺鍍法可容易達成大面積化,且可特別提高工業性或是量產性。 In addition, if the oxide layer manufacturing method of this embodiment is used, since there is no need to use a vacuum process as long as the oxide layer precursor solution is heated in an oxygen-containing atmosphere, it can be easily achieved compared to the conventional sputtering method. Large area, and can especially improve industrial or mass production.

3.薄膜電容器100之電氣特性 3. Electrical characteristics of film capacitor 100

依據本發明者之研究與分析,發現上述加熱製程中若為使得前驅體層30a成為氧化物層30所進行之加熱的溫度(正式燒成溫度)愈從550℃往800℃上升,此外,若至少於既定時間帶之範圍內的加熱時間愈長,則愈清楚顯現出燒綠石型結晶構造之結晶相。再者,令人玩味的是,發現了在藉由590℃以上之加熱處理所形成之BNO氧化物之情況下原確認其存在之β-BiNbO4之結晶構造,在藉由600℃以上~800℃以下、尤其是650℃以上~800℃以下之加熱處理所形成之本實施形態之氧化物層30中並未出現。 According to the research and analysis of the present inventors, it is found that if the precursor layer 30a becomes the oxide layer 30 in the above heating process, the heating temperature (main firing temperature) increases from 550°C to 800°C. In addition, if at least The longer the heating time within the predetermined time zone, the more clearly the pyrochlore-type crystal structure of the crystal phase appears. In addition, it is interesting that the crystal structure of β-BiNbO 4 , which was originally confirmed to exist in the case of the BNO oxide formed by the heat treatment above 590℃, was found to be above 600℃~800 It does not appear in the oxide layer 30 of the present embodiment formed by heat treatment at temperatures below 650°C and above 800°C.

再者,確認了本實施形態之氧化物層30尤其如後述般當滿足(X1)以及(Y1)所示條件其中1者的情況,可實現非常低的介電損耗值。 Furthermore, it was confirmed that the oxide layer 30 of the present embodiment can achieve a very low dielectric loss value especially when one of the conditions shown in (X1) and (Y1) is satisfied as described later.

以下更詳細說明本發明者之分析結果。 The analysis results of the inventors are described in more detail below.

<X射線繞射(XRD)之測定結果> <X-ray diffraction (XRD) measurement results>

圖6~圖8顯示本實施形態中因由鉍(Bi)與鈮(Nb)與鈦(Ti)所構成之氧化物(氧化物層30)之加熱溫度差異以及燒成時間差異所得該氧化物之結晶構造,顯示使用CuKα特性X射線之X射線繞射(XRD)之測定結果變化圖。此外,圖6~圖8(a)係顯示在正式燒成方面以第1溫度進行20分鐘加熱後所測定之結果。此外,圖6~圖8(b)係顯示於正式燒成後,進而在後退火(post-annealing)處理方面以相同溫度對氧化物層30追加20分鐘的加熱後所測定之結果。此外,圖7以及圖8係揭示本實施形態之例,圖6係揭示參考例。 6 to 8 show the difference in heating temperature and firing time of the oxide (oxide layer 30) composed of bismuth (Bi), niobium (Nb) and titanium (Ti) in this embodiment. The crystal structure shows the change in the measurement result of X-ray diffraction (XRD) using CuKα characteristic X-rays. In addition, Fig. 6 to Fig. 8(a) show the results measured after heating at the first temperature for 20 minutes in terms of main firing. In addition, FIG. 6 to FIG. 8(b) show the results of the measurement after the post-annealing treatment is added to the oxide layer 30 at the same temperature for 20 minutes after the main firing. In addition, FIGS. 7 and 8 show examples of this embodiment, and FIG. 6 shows a reference example.

此外,圖6~圖8所採用之氧化物30(成為測定對象之試料)的鉍(Bi)、鈮(Nb)、以及鈦(Ti)之原子數比係如以下之(試料a)~(試料c)所示。 In addition, the atomic ratios of bismuth (Bi), niobium (Nb), and titanium (Ti) of the oxide 30 (the sample to be measured) used in FIGS. 6 to 8 are as follows (Sample a)~( Sample c) as shown.

(試料a)關於圖6,鉍(Bi):鈮(Nb):鈦(Ti)=1.5:2:0.5 (Sample a) Regarding Figure 6, bismuth (Bi): niobium (Nb): titanium (Ti) = 1.5: 2: 0.5

(試料b)關於圖7,鉍(Bi):鈮(Nb):鈦(Ti)=1.5:1.5:1 (Sample b) Regarding Figure 7, bismuth (Bi): niobium (Nb): titanium (Ti) = 1.5: 1.5:1

(試料c)關於圖8,鉍(Bi):鈮(Nb):鈦(Ti)=1.5:1:1.5 (Sample c) Regarding Figure 8, bismuth (Bi): niobium (Nb): titanium (Ti) = 1.5:1: 1.5

首先,如圖6~圖8所示般,即使是僅進行了正式燒成之加熱處理的情況,只要加熱溫度在至少600℃以上,會出現源自燒綠石型結晶構造之結晶相的在X軸之2θ值為28°~30°附近之波峰(圖中Q所示波峰)。從而,可知即便在基於周知情報對於BNO氧化物而言無法想像的高溫(600℃以上~800℃以下(代表性為超過620℃~800℃以下、或是650℃以上~800℃以下))下進 行加熱處理,也可發現燒綠石型結晶構造之結晶相。此意涵著關於具有燒綠石型結晶構造之結晶相(顯示相對高的相對介電係數)之氧化物之製造製程,可特別提高加熱處理之溫度範圍的自由度。 First of all, as shown in Figures 6 to 8, even in the case where only the heat treatment for main firing is performed, as long as the heating temperature is at least 600°C or higher, the pyrochlore-type crystal structure of the crystalline phase will appear. The 2θ value of the X axis is a peak near 28°~30° (the peak is shown by Q in the figure). Therefore, it can be seen that even at high temperatures (600°C or higher to 800°C or lower (typically exceeding 620°C to 800°C or lower, or 650°C to 800°C or lower)) that is unimaginable for BNO oxides based on public information Advance Heat treatment can also find the pyrochlore crystal structure crystal phase. This means that the manufacturing process of oxides with a pyrochlore-type crystal structure (showing a relatively high relative permittivity) crystal phase can particularly increase the degree of freedom in the temperature range of the heat treatment.

此外,尤其在採用了試料b以及試料c之情況的550℃進行加熱之正式燒成後與在同溫度下經過追加性加熱之後退火處理後的關係中所顯著顯示,若加熱時間變長,會見到新出現圖中Q所示波峰的現象、或是該波峰強度變大之現象。從而,可知即便是未變化加熱溫度之狀態,藉由拉長加熱時間,能以更高確實度地於氧化物30內發現燒綠石型結晶構造之結晶相。 In addition, especially in the case of using sample b and sample c, the relationship between the main firing after heating at 550°C and the annealing treatment after additional heating at the same temperature is clearly shown. When the phenomenon of the peak shown in Q in the figure appears newly, or the phenomenon that the intensity of the peak increases. Therefore, it can be seen that even in a state where the heating temperature is not changed, by extending the heating time, the crystal phase of the pyrochlore-type crystal structure can be found in the oxide 30 with higher certainty.

另一方面,如圖6所示般,當採用試料a之情況,不論是以550℃進行加熱之正式燒成後、或是以相同溫度進行追加性加熱之後退火處理後之任一情況,均未見到源自燒綠石型結晶構造之結晶相的X軸之2θ值在28°~30°附近的波峰。 On the other hand, as shown in Fig. 6, when sample a is used, either after the main firing by heating at 550°C or after the annealing treatment after additional heating at the same temperature. No peaks with the 2θ value of the X axis derived from the pyrochlore crystal structure in the vicinity of 28°-30° are seen.

另一方面,例如若如本案發明者之一部分發明者所揭示做為以往發明之專利文獻3之圖9中顯示600℃之圖所示般,觀察X軸之2θ值在13°附近之波峰,將會成為出現β-BiNbO4之結晶構造之結晶相。但是,令人玩味的是,不論是圖6~圖8之任一圖,並未出現源自β-BiNbO4之結晶構造之X軸之2θ值在13°附近的波峰。從而,即使在高溫(600℃以上~800℃以下(代表性為超過620℃~800℃以下、或是650℃以上~800℃以下))下進行了加熱處理之情況,未觀測到源自β-BiNbO4型結晶構造的波峰乃為一特徴性的事實。此意涵著於包含正式燒成之氧化物30之製造製程中,抑制或是防止顯示相對低的相對介電係數之β-BiNbO4之結晶構造之出現將可特別擴張發現燒綠石型結晶構造之溫度範圍。 On the other hand, for example, as shown in the graph of 600°C shown in Figure 9 of Patent Document 3, which is part of the inventors of the present invention, as a prior invention, observe the peak of the 2θ value of the X axis near 13°, It will become the crystalline phase where the crystalline structure of β-BiNbO 4 appears. However, what is interesting is that no matter it is in any of the graphs of Figs. 6-8, there is no peak of the 2θ value of the X-axis derived from the crystal structure of β-BiNbO 4 near 13°. Therefore, even if heat treatment is performed at high temperature (600°C or higher to 800°C or less (typically exceeding 620°C to 800°C or lower, or 650°C or higher to 800°C or lower)), no β-derived from β is observed. -The peak of the BiNbO 4 -type crystal structure is a characteristic fact. This means that during the manufacturing process including the formally fired oxide 30, suppressing or preventing the appearance of the β-BiNbO4 crystal structure, which exhibits a relatively low relative permittivity, will allow the discovery of the pyrochlore-type crystal structure in particular. The temperature range.

<介電損耗(tanδ)以及相對介電係數之測定結果> <Measurement results of dielectric loss (tanδ) and relative permittivity>

圖9係關於進行了正式燒成與後退火處理之後之上述試料a、試料b、以及試料c之顯示介電損耗(tanδ)值與加熱溫度(℃)之相關性之圖。此外,圖10係關於進行了正式燒成與後退火處理之後之試料a、試料b、以及試料c之顯示相對介電係數與加熱溫度(℃)之相關性之圖。此外,比較例係採用了相對高的相對介電係數之BNO氧化物,具體而言係採用當鉍(Bi)之原子數為1之時,鈮(Nb)之原子數為約1.7之BNO氧化物。此外,圖9以及 圖10中,試料a係顯示參考例,試料b係顯示實施例1,試料c係顯示實施例2。進而,圖9以及圖10中,正式燒成以及後退火處理之加熱溫度相同。 9 is a graph showing the correlation between the dielectric loss (tanδ) value and the heating temperature (°C) of the above-mentioned sample a, sample b, and sample c after the main firing and post-annealing treatments. In addition, FIG. 10 is a graph showing the correlation between the relative permittivity and the heating temperature (°C) of the sample a, the sample b, and the sample c after the main firing and post-annealing treatment. In addition, the comparative example uses BNO oxide with a relatively high relative permittivity. Specifically, when the number of atoms of bismuth (Bi) is 1, and the number of atoms of niobium (Nb) is about 1.7 Things. In addition, Figure 9 and In FIG. 10, the sample a shows the reference example, the sample b shows the example 1, and the sample c shows the example 2. Furthermore, in FIGS. 9 and 10, the heating temperature of the main firing and the post-annealing treatment is the same.

此外,相對介電係數係藉由對下部電極層與上部電極層之間施加0.1V之電壓、1kHz之交流電壓來測定。此測定中係使用東陽技術公司製1260-SYS型寬區介電係數測定系統。此外,介電損耗(tanδ)係於室溫下對下部電極層與上部電極層之間施加0.1V之電壓、1kHz之交流電壓來進行測定。此測定係使用東陽技術公司製1260-SYS型寬區介電係數測定系統。 In addition, the relative permittivity was measured by applying a voltage of 0.1V and an AC voltage of 1kHz between the lower electrode layer and the upper electrode layer. For this measurement, the Toyo Technology Co., Ltd. 1260-SYS wide-area permittivity measurement system was used. In addition, the dielectric loss (tanδ) was measured by applying a voltage of 0.1V and an AC voltage of 1kHz between the lower electrode layer and the upper electrode layer at room temperature. This measurement uses the Toyo Technology Corporation 1260-SYS wide-area permittivity measurement system.

如圖9所示般,可知實施例1以及實施例2之介電損耗(tanδ)值不受加熱溫度影響而為極低值(代表性為0.001以下)。另一方面,確認了比較例之介電損耗(tanδ)值超過0.01之條件。基於上述結果以及本案發明者之分析得到了下述見地:只要可滿足選自下述(X1)以及(Y1)所示條件之群中至少1者,即可實現極低之介電損耗(tanδ)。 As shown in FIG. 9, it can be seen that the dielectric loss (tan δ) values of Example 1 and Example 2 are extremely low values (typically 0.001 or less) regardless of the heating temperature. On the other hand, it was confirmed that the dielectric loss (tanδ) value of the comparative example exceeds 0.01. Based on the above results and the analysis of the inventor of the present case, the following insights are obtained: as long as at least one of the following conditions (X1) and (Y1) can be satisfied, extremely low dielectric loss (tanδ) can be achieved. ).

(X1)當鉍(Bi)之原子數為1.5之時,鈮(Nb)之原子數為1以上~未達2,或是當鉍(Bi)之原子數為1.5之時,鈦(Ti)之原子數為超過0.5~1.5以下。 (X1) When the number of atoms of bismuth (Bi) is 1.5, the number of atoms of niobium (Nb) is 1 to less than 2, or when the number of atoms of bismuth (Bi) is 1.5, titanium (Ti) The number of atoms is more than 0.5 to 1.5.

此外,X1之條件中,除了上述條件,該鈮(Nb)之原子數與該鈦(Ti)之原子數之和在1.5以上~3.9以下為更適宜的條件。 In addition, in the conditions of X1, in addition to the above-mentioned conditions, a more suitable condition is that the sum of the number of atoms of the niobium (Nb) and the number of atoms of the titanium (Ti) is 1.5 to 3.9.

(Y1)當鉍(Bi)之原子數為1.5之時,鈮(Nb)之原子數為1以上~2以下、以及鈦(Ti)之原子數為0.5以上~1.5以下,且當鈦(Ti)為1之時,鈮(Nb)未達4。 (Y1) When the number of atoms of bismuth (Bi) is 1.5, the number of atoms of niobium (Nb) is 1 to 2 and the number of atoms of titanium (Ti) is 0.5 to 1.5, and when titanium (Ti) When) is 1, niobium (Nb) is less than 4.

此外,基於可同時得到更高的相對介電係數與低的介電損耗值之觀點,關於上述(X1)以及(Y1)之各數值範圍,滿足當鉍(Bi)之原子數為1.5之時,鈮(Nb)之原子數為1以上~1.9以下之條件以及/或是當鉍(Bi)之原子數為1.5之時,鈦(Ti)之原子數為0.6以上~1.4以下之條件為適宜的一態樣。 In addition, based on the viewpoint that a higher relative permittivity and a lower dielectric loss value can be obtained at the same time, the numerical ranges of (X1) and (Y1) above are satisfied when the atomic number of bismuth (Bi) is 1.5 , The condition that the number of atoms of niobium (Nb) is from 1 to 1.9 and/or when the number of atoms of bismuth (Bi) is 1.5, the condition that the number of atoms of titanium (Ti) is from 0.6 to 1.4 is suitable The same state.

另一方面,雖參考例之介電損耗(tanδ)值較實施例1以及實施例2之各值來得差,但由於參考例之介電損耗(tanδ)值在600℃以上為未達0.01,故此參考例之介電損耗(tanδ)值也可說是良好的數值。 On the other hand, although the dielectric loss (tanδ) value of the reference example is inferior to the values of Example 1 and Example 2, but because the dielectric loss (tanδ) value of the reference example does not reach 0.01 at 600°C or higher, Therefore, the dielectric loss (tanδ) value of this reference example can also be said to be a good value.

此外,如圖10所示般,可知關於所有的試料以及比較例,藉由至少600℃以上之加熱處理可得到相對高的相對介電係數。尤其,關於實施例1以 及實施例2,確認了藉由550℃以上之加熱處理可得到相對高的相對介電係數。 In addition, as shown in FIG. 10, it can be seen that, for all samples and comparative examples, a relatively high relative permittivity can be obtained by heat treatment at least 600°C or higher. In particular, regarding Example 1 And in Example 2, it was confirmed that relatively high relative permittivity can be obtained by heat treatment at 550°C or higher.

從而,依據圖6~圖10可得到下述見地:尤其當滿足選自上述(X1)以及(Y1)所示條件群中至少1者的情況,可一面保持相對高的相對介電係數、一面實現非常低的介電損耗值。此外,上述(X1)可改寫為下述(X2)。 Therefore, according to Figs. 6-10, the following insights can be obtained: especially when at least one of the condition groups selected from the above (X1) and (Y1) is satisfied, a relatively high relative permittivity and a Achieve very low dielectric loss values. In addition, the above (X1) can be rewritten as the following (X2).

(X2)當鉍(Bi)之原子數為1之時,鈮(Nb)之原子數為0.666以上~1.333以下;或是當鉍(Bi)之原子數為1之時,鈦(Ti)之原子數為0.334以上~1以下。 (X2) When the number of atoms of bismuth (Bi) is 1, the number of atoms of niobium (Nb) is from 0.666 to 1.333; or when the number of atoms of bismuth (Bi) is 1, titanium (Ti) is The number of atoms is 0.334 or more to 1 or less.

此外,X2之條件中,除了上述條件,該鈮(Nb)之原子數與該鈦(Ti)之原子數之和在1以上~2.6以下為更適宜的條件。 In addition, in the conditions of X2, in addition to the above-mentioned conditions, a more suitable condition is that the sum of the number of atoms of the niobium (Nb) and the number of atoms of the titanium (Ti) is 1 to 2.6.

此外,即便是關於上述以外試料之氧化物30(成為測定對象之試料),經發明者研究與分析的結果,確認了可發揮介電損耗值非常低的效果。 In addition, even with respect to the oxide 30 (the sample to be measured) of the sample other than the above, the inventors' research and analysis confirmed that the effect of very low dielectric loss value can be exerted.

代表性而言,顯示鉍(Bi)、鈮(Nb)以及鈦(Ti)之原子數比為以下所示條件之(試料d-1)以及(試料d-2)之例。 Representatively, the atomic ratios of bismuth (Bi), niobium (Nb), and titanium (Ti) are shown as examples of (sample d-1) and (sample d-2) under the conditions shown below.

(試料d-1)鉍(Bi):鈮(Nb):鈦(Ti)=1.5:1.5:0.5 (Sample d-1) Bismuth (Bi): Niobium (Nb): Titanium (Ti) = 1.5: 1.5: 0.5

(試料d-2)鉍(Bi):鈮(Nb):鈦(Ti)=1.5:1.5:0.12 (Sample d-2) Bismuth (Bi): Niobium (Nb): Titanium (Ti) = 1.5: 1.5: 0.12

尤其,上述試料d-2,當該鉍(Bi)之原子數為1之時,即便該鈦(Ti)之原子數為0.08(亦即未達0.1)此一小值,在維持著相對高的相對介電係數(例如190以上)的情況下實現低的介電損耗值(例如於頻率1kHz為0.002以下)一事為相當令人玩味之發現。 In particular, for the sample d-2, when the number of atoms of the bismuth (Bi) is 1, even if the number of atoms of the titanium (Ti) is 0.08 (that is, less than 0.1), the small value remains relatively high. In the case of relative permittivity (for example, 190 or more), achieving a low dielectric loss value (for example, 0.002 or less at a frequency of 1kHz) is a very interesting discovery.

圖11係關於進行了正式燒成與後退火處理之後之上述試料d之顯示介電損耗(tanδ)值與加熱溫度(℃)之相關性之圖。此外,圖12係關於進行了正式燒成與後退火處理之後之試料d之顯示相對介電係數與加熱溫度(℃)之相關性之圖。此外,圖11以及圖12中,試料d顯示做為實施例3。此外,測定條件和(試料a)~(試料c)之條件相同。 Fig. 11 is a graph showing the correlation between the dielectric loss (tanδ) value and the heating temperature (°C) of the sample d after the main firing and post-annealing treatments. In addition, FIG. 12 is a graph showing the correlation between the relative permittivity and the heating temperature (°C) of the sample d after the main firing and post-annealing treatment. In addition, in FIGS. 11 and 12, sample d is shown as Example 3. In addition, the measurement conditions are the same as those of (sample a) to (sample c).

如圖11所示般,可知實施例3之介電損耗(tanδ)值尤其藉由採用700℃以上之加熱溫度會成為極低之值(代表性為0.002以下)。從而,當滿足選自上述(X1)以及(Y1)所示條件之群中至少1者的情況,可實現極低之介電損耗(tanδ)。 As shown in FIG. 11, it can be seen that the dielectric loss (tanδ) value of Example 3 becomes extremely low (typically 0.002 or less) especially by using a heating temperature of 700°C or higher. Therefore, when at least one member selected from the group of the conditions shown in (X1) and (Y1) is satisfied, extremely low dielectric loss (tanδ) can be achieved.

此外,如圖12所示般,可知實施例3同樣地藉由至少600℃以上之加熱處理可得到相對高的相對介電係數。 In addition, as shown in FIG. 12, it can be seen that in Example 3, a relatively high relative permittivity can be obtained by a heat treatment of at least 600°C or higher.

此外,在其他實施例方面,顯示了鉍(Bi)、鈮(Nb)以及鈦(Ti)之原子數比為以下所示條件之(試料e)之例。 In addition, in other examples, it is shown that the atomic ratio of bismuth (Bi), niobium (Nb), and titanium (Ti) is under the conditions shown below (Sample e).

(試料e)鉍(Bi):鈮(Nb):鈦(Ti)=1.5:2:1.2 (Sample e) Bismuth (Bi): Niobium (Nb): Titanium (Ti) = 1.5: 2: 1.2

關於進行了正式燒成與後退火處理之後之上述試料e之介電損耗(tanδ)值與加熱溫度(℃)之相關性、以及相對介電係數與加熱溫度(℃)之相關性,於和(試料a)~(試料c)之條件為相同測定條件下進行調查的結果,得到了以下(X3)以及(Y3)所示見解。 Regarding the correlation between the dielectric loss (tanδ) value and the heating temperature (℃) of the above sample e after the main firing and post-annealing treatment, and the correlation between the relative dielectric coefficient and the heating temperature (℃), and The conditions of (sample a) to (sample c) are the results of investigation under the same measurement conditions, and the following findings (X3) and (Y3) were obtained.

(X3)至少於600℃~800℃之加熱溫度,介電損耗(tanδ)值為0.005以下。(尤其,於約700℃,介電損耗(tanδ)值為0.001以下。) (X3) The heating temperature is at least 600℃~800℃, and the dielectric loss (tanδ) value is less than 0.005. (In particular, the dielectric loss (tanδ) value is 0.001 or less at about 700°C.)

(Y3)至少於600℃~800℃之加熱溫度,相對介電係數為120以上。(尤其,約700℃,相對介電係數成為160以上。) (Y3) The heating temperature is at least 600℃~800℃, and the relative permittivity is above 120. (In particular, at about 700°C, the relative permittivity becomes 160 or more.)

再者依據發明者之檢討與分析,若當鉍(Bi)之原子數為1之時,該鈮(Nb)之原子數為0.5以上~未達1.7,且當該鉍(Bi)之原子數為1之時,該鈦(Ti)之原子數為超過0~未達1.3(較佳為0.08以上~未達1.3,更佳為0.3以上~未達1.3),可製造出一種可保持相對高的相對介電係數、並實現極低之介電損耗值的氧化物(或是氧化物介電質)。再者較佳為,若該鈮(Nb)之原子數與該鈦(Ti)之原子數之和成為1以上~2.6以下,可更高確實度地製造一種保持相對高的相對介電係數、並實現極低之介電損耗值的氧化物(或是氧化物介電質)。此外,尤其,雖該鈮(Nb)之原子數與該鈦(Ti)之原子數之和的值對於本實施形態之氧化物之物性(亦即相對介電係數以及介電損耗)並非支配性因素,但當其和的值未達1之情況、或是超過2.6之情況,被認為難以高確實度地獲得一種保持相對高的相對介電係數、並實現極低之介電損耗值的氧化物(或是氧化物介電質)。 Furthermore, according to the inventor’s review and analysis, if the atomic number of bismuth (Bi) is 1, the atomic number of niobium (Nb) is 0.5 to less than 1.7, and when the atomic number of bismuth (Bi) When it is 1, the number of atoms of the titanium (Ti) is more than 0 to less than 1.3 (preferably more than 0.08 to less than 1.3, more preferably more than 0.3 to less than 1.3), which can be manufactured to maintain a relatively high The relative permittivity of the oxide (or oxide dielectric) with extremely low dielectric loss value. More preferably, if the sum of the number of atoms of the niobium (Nb) and the number of atoms of the titanium (Ti) becomes 1 or more to 2.6 or less, a relatively high relative permittivity can be manufactured with higher certainty. And to achieve extremely low dielectric loss value oxide (or oxide dielectric). In addition, in particular, although the value of the sum of the number of atoms of the niobium (Nb) and the number of atoms of the titanium (Ti) is not dominating the physical properties of the oxide of this embodiment (that is, the relative permittivity and the dielectric loss) However, when the sum is less than 1 or exceeds 2.6, it is considered difficult to obtain an oxidation that maintains a relatively high relative permittivity and achieves a very low dielectric loss value with high certainty. Substance (or oxide dielectric).

此外,圖6~圖12中,如上述般,顯示了施行過後退火處理之例,但為了達成本實施形態之效果,未必要進行後退火處理。但是,進行後退火處理為可採用的適宜態樣。例如,可進行壓模加工並結束了圖案化之後,再進行後退火處理。 In addition, in FIGS. 6 to 12, as described above, an example of performing post-annealing treatment is shown, but in order to achieve the effect of the embodiment, post-annealing treatment is not necessary. However, post-annealing treatment is a suitable aspect that can be adopted. For example, after stamping and patterning are completed, post-annealing treatment can be performed.

於更具體的後退火一例中,第1實施形態之氧化物層30藉由第1溫度(一例為650℃)之正式燒成製程所形成後,進而花約20分鐘於含氧雰圍中以第1溫度以下之第2溫度(代表性為350℃以上~650℃以下)進行加熱來形成。其結果,如圖6~圖8所示般,可更高確實度地發現薄膜電容器100中之氧化物30內的燒綠石型結晶構造之結晶相。此外,可創造出進而提高氧化物層30與其底層(亦即下部電極層20)以及/或是上部電極層40之密合性的效果。 In a more specific example of post-annealing, the oxide layer 30 of the first embodiment is formed by a formal firing process at a first temperature (an example is 650°C), and then it takes about 20 minutes to perform the first annealing in an oxygen-containing atmosphere. It is formed by heating at a second temperature below 1 temperature (typically 350°C or higher to 650°C or lower). As a result, as shown in FIGS. 6 to 8, the crystal phase of the pyrochlore type crystal structure in the oxide 30 in the film capacitor 100 can be found with higher certainty. In addition, an effect of further improving the adhesion between the oxide layer 30 and the bottom layer (ie, the lower electrode layer 20) and/or the upper electrode layer 40 can be created.

另一方面,後退火處理之第2溫度較佳為第1溫度以下之溫度。此乃由於,若第2溫度高於第1溫度,第2溫度對於氧化物層30a之物性造成影響之可能性會變高之故。從而,第2溫度以選擇對於氧化物層30a之物性不會成為支配性因素的溫度為佳。另一方面,後退火處理中第2溫度之下限值如上述般,係基於進而提高相對於底層(亦即下部電極層20)以及/或是上部電極層40之密合性的觀點來決定。 On the other hand, the second temperature of the post-annealing treatment is preferably a temperature below the first temperature. This is because if the second temperature is higher than the first temperature, the possibility that the second temperature will affect the physical properties of the oxide layer 30a will increase. Therefore, the second temperature is preferably a temperature that does not become a dominant factor for the physical properties of the oxide layer 30a. On the other hand, the second lower temperature limit in the post-annealing process is determined based on the viewpoint of further improving the adhesion to the bottom layer (ie, the lower electrode layer 20) and/or the upper electrode layer 40 as described above. .

<漏電流之測定結果> <Measurement result of leakage current>

發明者進而對於以700℃加熱做為正式燒成所得氧化物層30在施加50kV/cm時的漏電流值進行了調查。其結果,漏電流值係得到了可做為電容器使用之特性。代表性結果之一例,上述試料b之漏電流值為10-8A/cm2~10-7A/cm2。此外,此漏電流係對下部電極層與上部電極層之間施加上述電壓來測定電流。此外,此測定中係使用了安捷倫科技(Agilent Technologies)公司製4156C型儀器。進而,至少正式燒成之溫度於600℃~800℃之範圍內,可得到和前述代表性漏電流值的結果為相同程度之低漏電流值。此外,關於漏電流值,至少試料c可達成和試料b相同程度之效果。 The inventors further investigated the leakage current value of the oxide layer 30 obtained by heating at 700°C as the main firing when 50 kV/cm is applied. As a result, the leakage current value can be used as a capacitor. An example of a representative result, the leakage current value of the above sample b is 10 -8 A/cm 2 ~10 -7 A/cm 2 . In addition, this leakage current is measured by applying the above voltage between the lower electrode layer and the upper electrode layer. In addition, the 4156C instrument manufactured by Agilent Technologies was used in this measurement. Furthermore, at least the main firing temperature is within the range of 600°C to 800°C, and a low leakage current value that is the same level as the result of the aforementioned representative leakage current value can be obtained. In addition, with regard to the leakage current value, at least sample c can achieve the same effect as sample b.

如上述般,本實施形態之由鉍(Bi)與鈮(Nb)與鈦(Ti)所構成之氧化物(氧化物層30)藉由採用既定範圍之原子數比,可一面保持相對高的相對介電係數、一面實現低的介電損耗值。從而,確認了尤其特別適用於各種固態電子裝置(例如電容器、半導體裝置、或是微電機系統、或是包含高頻濾波器、貼片天線以及RCL當中至少2個的複合元件)。 As described above, the oxide (oxide layer 30) composed of bismuth (Bi) and niobium (Nb) and titanium (Ti) in this embodiment can maintain a relatively high atomic ratio by adopting a predetermined range of atomic ratios. Relative dielectric coefficient, one side realizes low dielectric loss value. Therefore, it has been confirmed that it is particularly suitable for various solid-state electronic devices (such as capacitors, semiconductor devices, or micro-motor systems, or composite components including at least two of high-frequency filters, patch antennas, and RCL).

<第2實施形態> <Second Embodiment>

於本實施形態中,針對固態電子裝置一例之積層電容器200來說明。 此外,積層電容器200之至少一部分的層係藉由網版印刷法所形成。此外,本實施形態中,形成積層電容器200之材料當中由鉍(Bi)與鈮(Nb)與鈦(Ti)所構成之氧化物係和第1實施形態之氧化物層30相同。從而,和第1實施形態重複之說明得以省略。 In this embodiment, a multilayer capacitor 200 as an example of a solid-state electronic device will be described. In addition, at least a part of the layers of the multilayer capacitor 200 are formed by a screen printing method. In addition, in this embodiment, the oxide system composed of bismuth (Bi), niobium (Nb) and titanium (Ti) among the materials forming the multilayer capacitor 200 is the same as the oxide layer 30 of the first embodiment. Therefore, the description overlapping with the first embodiment is omitted.

〔積層電容器200之構造〕 [Structure of multilayer capacitor 200]

圖13係顯示本實施形態中積層電容器200之構造的截面示意圖。如圖13所示般,本實施形態之積層電容器200中部分具備有由合計5層之電極層與合計4層之介電質層所交互積層而得之構造。此外,非電極層與介電質層所交互積層之部分係以下層側之電極層(例如第1段之電極層220a)與上層側之電極層(例如第5段之電極層220e)以電性連接的方式來形成各電極層。此外,各電極層220a、220b、220c、220d、220e之材料乃至於組成、以及各介電質層之氧化物層230a、230b、230c、230d之材料乃至於組成係揭示於後述本實施形態之積層電容器200之製造方法之說明中。 FIG. 13 is a schematic cross-sectional view showing the structure of the multilayer capacitor 200 in this embodiment. As shown in FIG. 13, the multilayer capacitor 200 of this embodiment has a structure in which a total of 5 electrode layers and a total of 4 dielectric layers are alternately laminated. In addition, the alternately laminated part of the non-electrode layer and the dielectric layer is the electrode layer on the lower layer side (for example, the electrode layer 220a of the first stage) and the electrode layer on the upper layer side (for example, the electrode layer 220e of the fifth stage). Each electrode layer is formed by means of sexual connection. In addition, the material and composition of each electrode layer 220a, 220b, 220c, 220d, 220e, and the material and composition of the oxide layer 230a, 230b, 230c, 230d of each dielectric layer are disclosed in the following description of this embodiment In the description of the manufacturing method of the multilayer capacitor 200.

圖14乃至圖18係積層電容器200之製造方法之一過程的截面示意圖。此外,圖14、圖15、圖16、圖17以及圖18為了方便說明起見係將圖13所示積層電容器200之一部分構造抽出表示。此外,本申請案之溫度顯示係表示加熱器之設定溫度。 14 and 18 are schematic cross-sectional views of one process of the manufacturing method of the multilayer capacitor 200. In addition, FIG. 14, FIG. 15, FIG. 16, FIG. 17, and FIG. 18 show a part of the structure of the multilayer capacitor 200 shown in FIG. 13 for convenience of description. In addition, the temperature display in this application indicates the set temperature of the heater.

(1)第1段之電極層220a之形成 (1) Formation of the electrode layer 220a in the first stage

本實施形態中,首先,如圖14所示般,和第1實施形態同樣地,於基板10上藉由網版印刷法來形成電極層用前驅體層221a(係以含鑭(La)之前驅體以及含鎳(Ni)之前驅體為溶質之前驅體溶液(稱為電極層用前驅體溶液。以下對於第1段乃至第5段之電極層用前驅體之溶液相同)做為起始材)。之後,做為預備燒成係以約5分鐘、150℃以上~250℃以下進行加熱。此外,此預備燒成係在含氧雰圍下進行。 In this embodiment, first, as shown in FIG. 14, as in the first embodiment, a precursor layer 221a for an electrode layer (a precursor containing lanthanum (La)) is formed on the substrate 10 by screen printing. The precursor and the precursor containing nickel (Ni) are the solute precursor solution (called the precursor solution for the electrode layer. The following is the same as the solution of the precursor for the electrode layer in the first to fifth paragraphs) as the starting material ). After that, as a preliminary firing system, heating is carried out for about 5 minutes at 150°C or higher to 250°C or lower. In addition, this preliminary firing is performed in an oxygen-containing atmosphere.

此外,藉由此預備燒成可將電極層用前驅體層221a中之溶媒(代表性為主溶媒)充分蒸發,並可形成未來可呈現出塑性變形特性之較佳的凝膠狀態(被認為於熱分解前處於殘存著有機鏈之狀態)。以更高確實度地實現前述觀點之觀點而言,預備燒成溫度以80℃以上~250℃以下為佳。其結果,形成層厚為約2μm~約3μm之第1段之電極層用前驅體層221a。此外,不限於 第1段之電極層220a,即使是後述各層之網版印刷,也可適宜採用周知材料(乙基纖維素等)來調整網版印刷性(黏度等)。 In addition, by this preliminary firing, the solvent (typically the main solvent) in the electrode layer precursor layer 221a can be fully evaporated, and a better gel state that can exhibit plastic deformation characteristics in the future can be formed (it is considered to be It is in a state where organic chains remain before thermal decomposition). From the viewpoint of achieving the aforementioned viewpoints with higher certainty, the pre-firing temperature is preferably 80°C or higher to 250°C or lower. As a result, the first-stage electrode layer precursor layer 221a having a layer thickness of about 2 μm to about 3 μm is formed. In addition, not limited to Even if the electrode layer 220a of the first stage is screen printing of each layer described later, a well-known material (ethyl cellulose, etc.) can be suitably used to adjust the screen printing properties (viscosity, etc.).

之後,做為正式燒成,係將第1段之電極層用前驅體層221a在氧雰圍中以約15分鐘、580℃進行加熱,而如圖15所示般,於基板10上形成由鑭(La)與鎳(Ni)所構成之第1段之電極層用氧化物層(其中可含無法避免的雜質。以下相同。此外,也僅稱為「第1段之電極層」)220a。此外,由鑭(La)與鎳(Ni)所構成之電極用氧化物層(不僅是第1段之電極用氧化物層,也包含其他電極用氧化物層)也稱為LNO層。 After that, as the main firing, the electrode layer precursor layer 221a of the first stage is heated in an oxygen atmosphere at 580°C for about 15 minutes, and as shown in FIG. 15, a lanthanum ( An oxide layer for the electrode layer of the first stage composed of La) and nickel (Ni) (which may contain unavoidable impurities. The following is the same. In addition, it is also only referred to as the "first stage electrode layer") 220a. In addition, an electrode oxide layer composed of lanthanum (La) and nickel (Ni) (not only the first stage electrode oxide layer, but also other electrode oxide layers) is also referred to as an LNO layer.

此外,本實施形態中用於第1段之電極層220a的含鑭(La)之前驅體之例為乙酸鑭。其他例可採用硝酸鑭、氯化鑭、或是各種鑭烷氧化物(例如異丙氧化鑭、丁氧化鑭、乙氧化鑭、甲氧基乙氧化鑭)。此外,本實施形態中用於第1段之電極層220a的含鎳(Ni)之前驅體之例為乙酸鎳。其他例可採用硝酸鎳、氯化鎳、或是各種鎳烷氧化物(例如異丙氧化鎳、丁氧化鎳、乙氧化鎳、甲氧基乙氧化鎳)。 In addition, an example of a lanthanum (La)-containing precursor used in the electrode layer 220a of the first stage in this embodiment is lanthanum acetate. In other examples, lanthanum nitrate, lanthanum chloride, or various lanthanum alkoxides (such as lanthanum isopropoxide, lanthanum butoxide, lanthanum ethoxide, lanthanum methoxyethoxide) can be used. In addition, an example of the nickel (Ni)-containing precursor used in the electrode layer 220a of the first stage in this embodiment is nickel acetate. Other examples can be nickel nitrate, nickel chloride, or various nickel alkoxides (such as nickel isopropoxide, nickel butoxide, nickel ethoxide, nickel methoxyethoxide).

進而,本實施形態中,雖採用由鑭(La)與鎳(Ni)所構成之第1段之電極層220a,但第1段之電極層220a不限定於此組成。例如,也可採用由銻(Sb)與錫(Sn)所構成之第1段之電極層(其中可含無法避免的雜質。以下相同)。於該情況,做為含銻(Sb)之前驅體的例可採用乙酸銻、硝酸銻、氯化銻、或是各種銻烷氧化物(例如異丙氧化銻、丁氧化銻、乙氧化銻、甲氧基乙氧化銻)。此外,做為含錫(Sn)之前驅體之例可採用乙酸錫、硝酸錫、氯化錫、或是各種錫烷氧化物(例如異丙氧化錫、丁氧化錫、乙氧化錫、甲氧基乙氧化錫)。此外,可採用由銦(In)與錫(Sn)所構成之氧化物(其中可含無法避免的雜質。以下相同)。於該情況,含銦(In)之前驅體之例可採用乙酸銦、硝酸銦、氯化銦、或是各種銦烷氧化物(例如異丙氧化銦、丁氧化銦、乙氧化銦、甲氧基乙氧化銦)。此外,含錫(Sn)之前驅體之例和前述例相同。 Furthermore, in this embodiment, although the first-stage electrode layer 220a composed of lanthanum (La) and nickel (Ni) is used, the first-stage electrode layer 220a is not limited to this composition. For example, a first-stage electrode layer composed of antimony (Sb) and tin (Sn) (which may contain unavoidable impurities. The same applies below). In this case, as examples of antimony (Sb)-containing precursors, antimony acetate, antimony nitrate, antimony chloride, or various antimony alkoxides (such as antimony isopropoxide, antimony butoxide, antimony ethoxide, Antimony ethoxylate). In addition, as an example of the precursor containing tin (Sn), tin acetate, tin nitrate, tin chloride, or various tin alkoxides (such as tin isopropoxide, tin butoxide, tin ethoxide, methoxy Ethoxylate). In addition, an oxide composed of indium (In) and tin (Sn) (which may contain unavoidable impurities. The same applies below). In this case, examples of indium (In)-containing precursors can be indium acetate, indium nitrate, indium chloride, or various indium alkoxides (such as indium isopropoxide, indium butoxide, indium ethoxide, methoxy Indium ethoxylate). In addition, the example of the precursor containing tin (Sn) is the same as the previous example.

(2)第1段之介電質層(氧化物層)230a之形成 (2) The formation of the dielectric layer (oxide layer) 230a of the first stage

之後,如圖16所示般,於基板10以及第1段之電極層220a上,藉由網版印刷法來形成以含鉍(Bi)之前驅體、含鈮(Nb)之前驅體以及含鈦(Ti)之前驅體為溶質之前驅體溶液做為起始材之經圖案化的前驅體層。之後,在 預備燒成方面係以約5分鐘於250℃進行加熱。此外,此預備燒成係以含氧雰圍來進行。 Afterwards, as shown in FIG. 16, on the substrate 10 and the electrode layer 220a of the first stage, a bismuth (Bi)-containing precursor, a niobium (Nb)-containing precursor, and a bismuth (Nb)-containing precursor are formed by a screen printing method. The titanium (Ti) precursor is a patterned precursor layer with a solute precursor solution as a starting material. After In terms of preliminary firing, heating is performed at 250°C for about 5 minutes. In addition, this preliminary firing is performed in an oxygen-containing atmosphere.

此外,藉由此預備燒成,可將前驅體層中之溶媒(代表性為主溶媒)充分蒸發,並可形成未來可呈現出塑性變形特性之較佳的凝膠狀態(被認為於熱分解前處於殘存著有機鏈之狀態)。基於以更高確實度高來實現前述觀點的觀點,預備燒成溫度以80℃以上~250℃以下為佳。本實施形態中,為了得到做為介電質層之氧化物層230a的充分厚度(例如約2μm~約3μm),係藉由前述網版印刷法來進行前驅體層之形成與預備燒成。 In addition, through this preliminary firing, the solvent (typically the main solvent) in the precursor layer can be fully evaporated, and a better gel state that can exhibit plastic deformation characteristics in the future can be formed (it is considered to be before thermal decomposition). In a state where the organic chain remains). From the viewpoint of realizing the aforementioned viewpoints with higher reliability, the pre-firing temperature is preferably from 80°C to 250°C. In this embodiment, in order to obtain a sufficient thickness (for example, about 2 μm to about 3 μm) of the oxide layer 230a as a dielectric layer, the formation of the precursor layer and the preliminary firing are performed by the aforementioned screen printing method.

之後,做為正式燒成之加熱製程,係將氧化物層230a之前驅體層於氧雰圍中以既定時間(例如約20分鐘)、650℃進行加熱,而如圖16所示般,於基板10以及第1段之電極層220a上形成由鉍(Bi)與鈮(Nb)與鈦(Ti)所構成之經圖案化之氧化物層(氧化物層230a)。此處,藉由於前述條件下進行正式燒成、或是進行正式燒成以及第1實施形態所示後退火處理,可製造出保持相對高的相對介電係數、並實現極低之介電損耗值的氧化物層230a。 After that, as a heating process for the formal firing, the precursor layer of the oxide layer 230a is heated in an oxygen atmosphere for a predetermined time (for example, about 20 minutes) at 650°C, and as shown in FIG. 16, the substrate 10 And a patterned oxide layer (oxide layer 230a) composed of bismuth (Bi), niobium (Nb) and titanium (Ti) is formed on the electrode layer 220a of the first stage. Here, by performing the main firing under the aforementioned conditions, or performing the main firing, and the post-annealing treatment shown in the first embodiment, it is possible to produce a relatively high relative permittivity and achieve extremely low dielectric loss. Value of the oxide layer 230a.

(3)第2段以後之電極層以及介電質層之形成 (3) The formation of electrode layer and dielectric layer after the second stage

之後,使用到目前為止所說明過之電極層(第1段之電極層220a)以及介電質層之氧化物層230a之製造製程,藉由網版印刷法使得經圖案化之電極層以及介電質層來交互積層。 After that, using the manufacturing process of the electrode layer (the electrode layer 220a of the first stage) and the oxide layer 230a of the dielectric layer described so far, the patterned electrode layer and the dielectric layer are made by screen printing. The electrical layer is alternately stacked.

具體而言,於第1段之氧化物層230a經圖案化後,於氧化物層230a以及第1段之電極層220a上,藉由網版印刷法使得經圖案化之第2段之電極層用前驅體層來和第1段之電極層用前驅體層221a同樣地形成。之後,如圖17所示般,形成經圖案化之第2段之電極層220b。 Specifically, after the first-stage oxide layer 230a is patterned, the second-stage electrode layer is patterned by screen printing on the oxide layer 230a and the first-stage electrode layer 220a The precursor layer is formed in the same manner as the electrode layer precursor layer 221a of the first stage. Thereafter, as shown in FIG. 17, the patterned second-stage electrode layer 220b is formed.

之後,如圖18所示般,於第2段之電極層220b以及第1段之介電質層的氧化物層230a上,藉由網版印刷法來形成經圖案化之第2段之介電質層230b。 Then, as shown in FIG. 18, on the second-stage electrode layer 220b and the first-stage dielectric layer oxide layer 230a, a patterned second-stage dielectric is formed by screen printing. The dielectric layer 230b.

如此般,藉由網版印刷法來交互地積層經圖案化之電極層以及介電質層,最終來製造圖13所示積層電容器200。 In this way, the patterned electrode layer and the dielectric layer are alternately laminated by the screen printing method, and finally the multilayer capacitor 200 shown in FIG. 13 is manufactured.

如上述般,本實施形態之積層電容器200,各電極層以及各介電質層(氧化物層)皆由金屬氧化物所形成這點特別值得一提。進而,本實施形態中, 由於各電極層以及各介電質層(氧化物層)皆為將各種前驅體溶液在含氧雰圍中加熱來形成,故相較於以往之方法,可容易大面積化,且可特別提高工業性乃至於量產性。 As described above, in the multilayer capacitor 200 of this embodiment, each electrode layer and each dielectric layer (oxide layer) are formed of metal oxide, which is particularly worth mentioning. Furthermore, in this embodiment, Since each electrode layer and each dielectric layer (oxide layer) are formed by heating various precursor solutions in an oxygen-containing atmosphere, compared with the conventional method, it is easy to increase the area, and can improve the industrial Sex and even mass production.

此外,藉由知悉本申請案內容而使得上述各電極層以及各介電質層(氧化物層)之形成製程進而交互反覆進行來往上方堆疊一事係業界人士所能理解者。 In addition, by knowing the content of the present application, the formation process of each electrode layer and each dielectric layer (oxide layer) described above and then alternately and repeatedly stacked up and down is understood by those in the industry.

<第3實施形態> <The third embodiment>

1.本實施形態之薄膜電容器之全體構成 1. The overall structure of the film capacitor of this embodiment

本實施形態中,在固態電子裝置一例之薄膜電容器所有層之形成過程中施以壓模加工。本實施形態中固態電子裝置一例之薄膜電容器300之全體構成顯示於圖19。本實施形態中,下部電極層、氧化物層以及上部電極層除了被施以壓模加工以外係和第1實施形態相同。從而,省略和第1實施形態為重複之說明。 In this embodiment, a compression molding process is applied during the formation of all layers of a thin film capacitor as an example of a solid-state electronic device. The overall structure of a film capacitor 300 as an example of a solid-state electronic device in this embodiment is shown in FIG. 19. In this embodiment, the lower electrode layer, the oxide layer, and the upper electrode layer are the same as in the first embodiment except that they are stamped. Therefore, the overlapping description with the first embodiment is omitted.

如圖19所示般,本實施形態之薄膜電容器300和第1實施形態同樣地係形成於基板10上。此外,薄膜電容器300係從基板10側起具備有下部電極層320、由鉍(Bi)與鈮(Nb)與鈦(Ti)所構成之氧化物而成的氧化物層330、以及上部電極層340。 As shown in FIG. 19, the film capacitor 300 of this embodiment is formed on the substrate 10 in the same manner as in the first embodiment. In addition, the film capacitor 300 is provided with a lower electrode layer 320 from the side of the substrate 10, an oxide layer 330 made of an oxide composed of bismuth (Bi), niobium (Nb) and titanium (Ti), and an upper electrode layer 340.

2.薄膜電容器300之製造製程 2. Manufacturing process of film capacitor 300

其次,說明薄膜電容器300之製造方法。圖20至圖29分別為薄膜電容器300之製造方法之一過程的截面示意圖。於薄膜電容器300之製造之際,首先,於基板10上形成被施以了壓模加工之下部電極層320。其次,於下部電極層320上形成被施以了壓模加工之氧化物層330。之後,於氧化物層330上形成被施以了壓模加工之上部電極層340。薄膜電容器300之製造製程和第1實施形態為重複的說明予以省略。 Next, the manufacturing method of the film capacitor 300 will be described. 20 to 29 are schematic cross-sectional views of one process of the manufacturing method of the film capacitor 300, respectively. When the film capacitor 300 is manufactured, first, the lower electrode layer 320 subjected to compression molding is formed on the substrate 10. Next, an oxide layer 330 subjected to compression molding is formed on the lower electrode layer 320. After that, the upper electrode layer 340 subjected to compression molding is formed on the oxide layer 330. The description of the manufacturing process of the film capacitor 300 and the first embodiment is repeated and omitted.

(1)下部電極層之形成 (1) Formation of the lower electrode layer

於本實施形態中係說明薄膜電容器300之下部電極層320是由鑭(La)與鎳(Ni)所構成之導電用氧化物層所形成之例。下部電極層320係以(A)前驅體層之形成以及預備燒成之製程、(B)壓模加工之製程、(C)正式燒成之製程的順序來形成。 In this embodiment, an example is described in which the lower electrode layer 320 of the film capacitor 300 is formed of a conductive oxide layer composed of lanthanum (La) and nickel (Ni). The lower electrode layer 320 is formed in the order of (A) precursor layer formation and preliminary firing process, (B) stamper processing process, and (C) formal firing process.

(A)前驅體層之形成以及預備燒成之製程 (A) Precursor layer formation and preparation process for firing

首先,於基板10上以周知的旋塗法來形成以含鑭(La)之前驅體以及含鎳(Ni)之前驅體為溶質之下部電極層用前驅體溶液做為起始材之下部電極層用前驅體層320a。 First, a well-known spin coating method is used to form a lower electrode layer with a precursor containing lanthanum (La) and a precursor containing nickel (Ni) as the solute on the substrate 10, and the lower electrode layer with the precursor solution as the starting material. The layer precursor layer 320a.

之後,在預備燒成方面,係於含氧雰圍中以既定時間,將下部電極層用前驅體層320a以80℃以上~250℃以下之溫度範圍來加熱。此外,藉由使得前述旋塗法所進行之下部電極層用前驅體層320a之形成以及預備燒成反覆進行複數次,可得到下部電極層320之所希望之厚度。 After that, in terms of preliminary firing, the lower electrode layer precursor layer 320a is heated in a temperature range of 80°C or higher to 250°C or lower in an oxygen-containing atmosphere for a predetermined time. In addition, by repeating the formation of the precursor layer 320a for the lower electrode layer by the aforementioned spin coating method and the preliminary firing multiple times, the desired thickness of the lower electrode layer 320 can be obtained.

(B)壓模加工 (B) Die processing

其次,為了進行下部電極層用前驅體層320a之圖案化,如圖20所示般,在80℃以上~300℃以下之範圍內加熱之狀態下,使用下部電極層用模具M1,以0.1MPa以上~20MPa以下之壓力來施行壓模加工。壓模加工中之加熱方法之例有:藉由腔室、爐等來成為既定溫度雰圍之狀態的方法;將載置基板之基台從下部以加熱器來加熱之方法;或是,使用事先加熱至80℃以上~300℃以下之模具來施行壓模加工之方法等。於此情況,併用基台從下部以加熱器來加熱之方法與使用事先加熱至80℃以上~300℃以下之模具的方法,在加工性方面更佳。 Next, in order to pattern the precursor layer 320a for the lower electrode layer, as shown in FIG. 20, use the mold M1 for the lower electrode layer under the condition of heating in the range of 80°C or higher to 300°C or less, and the pressure is 0.1MPa or higher. ~20MPa pressure below to perform compression molding processing. Examples of heating methods in the molding process include: a method of using a chamber, a furnace, etc. to achieve a predetermined temperature atmosphere; a method of heating the substrate on which the substrate is placed from below with a heater; or, using a prior Heat the mold above 80°C to below 300°C for compression molding. In this case, combining the method of heating the base with a heater from the bottom and the method of using a mold that has been heated to a temperature above 80°C and below 300°C are better in terms of workability.

此外,上述模具之加熱溫度之所以定為80℃以上~300℃以下係基於以下理由。當壓模加工時之加熱溫度未達80℃之情況,起因於下部電極層用前驅體層320a之溫度降低會造成下部電極層用前驅體層320a之塑性變形能力降低,而會欠缺壓模構造之成型時的成型實現性、或是成型後之可靠性或是安定性。此外,當壓模加工時之加熱溫度超過300℃之情況,由於會進行成為塑性變形能力之根源的有機鏈之分解(氧化熱分解),故塑性變形能力會降低。再者,從前述觀點來說,下部電極層用前驅體層320a於壓模加工之際在100℃以上~250℃以下之範圍內進行加熱為更佳的態樣。 In addition, the reason why the heating temperature of the mold is set to 80°C or higher to 300°C or lower is based on the following reasons. When the heating temperature of the stamper processing is less than 80°C, the lower electrode layer precursor layer 320a will have a lower plastic deformation ability due to the decrease in temperature of the lower electrode layer precursor layer 320a, and the molding of the stamper structure will be lacking. Realization of molding, or reliability or stability after molding. In addition, when the heating temperature during the molding process exceeds 300°C, the decomposition of the organic chain (oxidative thermal decomposition) that is the source of the plastic deformability will progress, and the plastic deformability will be reduced. Furthermore, from the foregoing viewpoint, it is more preferable to heat the precursor layer 320a for the lower electrode layer in the range of 100°C or higher to 250°C or lower during the compression molding process.

此外,壓模加工之壓力只要是在0.1MPa以上~20MPa以下之範圍內的壓力,則下部電極層用前驅體層320a可跟隨模具之表面形狀來變形,能以高精度形成所希望之壓模構造。此外,被施以壓模加工之際,所施加的壓 力係設定為0.1MPa以上~20MPa以下(尤其是未達1MPa)此一低壓力範圍。其結果,施行壓模加工之際不易損傷模具,且有利於大面積化。 In addition, as long as the pressure of the press molding is within the range of 0.1 MPa to 20 MPa, the precursor layer 320a for the lower electrode layer can be deformed following the surface shape of the mold, and the desired press mold structure can be formed with high precision. . In addition, the pressure applied when the die is applied The force system is set to a low pressure range of 0.1MPa or more to 20MPa or less (especially less than 1MPa). As a result, the mold is less likely to be damaged when the press molding is performed, and it is advantageous to increase the area.

之後,對下部電極層用前驅體層320a進行全面性蝕刻。其結果,如圖21所示般,從對應於下部電極層之區域以外的區域來完全去除下部電極層用前驅體層320a(對下部電極層用前驅體層320a之全面的蝕刻製程)。 After that, the precursor layer 320a for the lower electrode layer is etched all over. As a result, as shown in FIG. 21, the lower electrode layer precursor layer 320a is completely removed from the area other than the area corresponding to the lower electrode layer (the entire etching process of the lower electrode layer precursor layer 320a).

此外,上述壓模加工中,事先對於會成為壓模面所接觸之各前驅體層之表面施行脫模處理以及/或是對該模具之壓模面施行脫模處理,之後,對各前驅體層施行壓模加工為佳。藉由施行此種處理,可降低各前驅體層與模具之間的摩擦力,而可對各前驅體層施行精度更高之壓模加工。此外,可用於脫模處理之脫模劑可例示出界面活性劑(例如氟系界面活性劑、矽系界面活性劑、非離子系界面活性劑等)、含氟類鑽石碳等。 In addition, in the above-mentioned stamping process, the surface of each precursor layer that will be the surface of the stamper is subjected to mold release treatment and/or the stamper surface of the mold is subjected to release treatment beforehand, and then each precursor layer is applied Die processing is better. By performing such a treatment, the friction between each precursor layer and the mold can be reduced, and higher precision compression molding processing can be performed on each precursor layer. In addition, the mold release agent that can be used for mold release treatment includes surfactants (for example, fluorine-based surfactants, silicon-based surfactants, non-ionic surfactants, etc.), fluorine-containing diamond carbon, and the like.

(C)正式燒成 (C) Formal firing

其次,對下部電極層用前驅體層320a在大氣中進行正式燒成。正式燒成之際的加熱溫度為550℃以上~650℃以下。其結果,如圖22所示般,於基板10上形成由鑭(La)與鎳(Ni)所構成之下部電極層320(其中,可含無法避免的雜質。以下相同)。 Next, the precursor layer 320a for the lower electrode layer is subjected to main firing in the atmosphere. The heating temperature during the main firing is 550°C or higher to 650°C or lower. As a result, as shown in FIG. 22, a lower electrode layer 320 composed of lanthanum (La) and nickel (Ni) is formed on the substrate 10 (which may contain unavoidable impurities. The same applies below).

(2)成為介電質層之氧化物層之形成 (2) Formation of the oxide layer that becomes the dielectric layer

其次,於下部電極層320上形成成為介電質層之氧化物層330。氧化物層330係以(A)前驅體層之形成以及預備燒成之製程、(B)壓模加工之製程、(C)正式燒成之製程的順序所形成。圖23乃至圖26係顯示氧化物層330之形成過程圖。 Next, an oxide layer 330 that becomes a dielectric layer is formed on the lower electrode layer 320. The oxide layer 330 is formed in the order of (A) precursor layer formation and preliminary firing process, (B) compression molding process, and (C) formal firing process. FIG. 23 and FIG. 26 are diagrams showing the formation process of the oxide layer 330.

(A)由鉍(Bi)與鈮(Nb)與鈦(Ti)所構成之氧化物之前驅體層之形成以及預備燒成 (A) Formation and preliminary firing of oxide precursor layer composed of bismuth (Bi), niobium (Nb) and titanium (Ti)

如圖23所示般,於基板10以及經圖案化之下部電極層320上,和第2實施形態同樣地形成以含鉍(Bi)之前驅體、含鈮(Nb)之前驅體以及含鈦(Ti)之前驅體為溶質之前驅體溶液做為起始材之前驅體層330a。之後,於本實施形態中,係在含氧雰圍中在加熱至80℃以上~250℃以下之狀態下進行預備燒成。此外,依據發明者之研究,本實施形態中藉由將前驅體層330a以80℃以上~250℃以下之範圍內進行加熱,則前驅體層330a之塑性變形能力 會變高,且可充分去除溶媒(代表性為主溶媒)。 As shown in FIG. 23, a bismuth (Bi)-containing precursor, a niobium (Nb)-containing precursor, and a titanium-containing precursor are formed on the substrate 10 and the patterned lower electrode layer 320 in the same manner as in the second embodiment. The (Ti) precursor is a solute precursor solution as the starting material precursor layer 330a. After that, in the present embodiment, preliminary firing is performed in a state of heating to 80°C or higher to 250°C or lower in an oxygen-containing atmosphere. In addition, according to the inventor’s research, in this embodiment, by heating the precursor layer 330a in the range of 80°C or higher to 250°C or lower, the plastic deformability of the precursor layer 330a Will become higher, and the solvent can be fully removed (typically the main solvent).

(B)壓模加工 (B) Die processing

本實施形態中,如圖24所示般,對於僅進行了預備燒成之前驅體層330a施以壓模加工。具體而言,為了進行氧化物層之圖案化,在加熱至80℃以上~250℃以下之狀態下,使用介電質層用模具M2,以0.1MPa以上~20MPa以下之壓力來施行壓模加工。 In this embodiment, as shown in FIG. 24, the precursor layer 330a that has only undergone preliminary firing is subjected to compression molding. Specifically, in order to pattern the oxide layer, the die M2 for the dielectric layer is used to perform compression molding with a pressure of 0.1 MPa to 20 MPa under the state of heating to 80°C or higher to 250°C or lower .

之後,將前驅體層330a做全面蝕刻。其結果,如圖25所示般,從對應於氧化物層330之區域以外的區域來完全去除前驅體層330a(對前驅體層330a全面之蝕刻製程)。此外,本實施形態之前驅體層330a之蝕刻製程雖使用了未採真空程序之濕式蝕刻技術來進行,但藉由使用了電漿之所謂的乾式蝕刻技術來蝕刻也無妨。 After that, the precursor layer 330a is fully etched. As a result, as shown in FIG. 25, the precursor layer 330a is completely removed from the area other than the area corresponding to the oxide layer 330 (the entire precursor layer 330a is etched). In addition, although the etching process of the precursor layer 330a of the present embodiment is performed using a wet etching technique without a vacuum process, it may be etched by a so-called dry etching technique using plasma.

(C)正式燒成 (C) Formal firing

之後,和第2實施形態同樣地對前驅體層330a進行正式燒成。此外,可視必要性來追加性地進行第1實施形態所示後退火處理。其結果,如圖26所示般,於下部電極層320上形成成為介電質層之氧化物層330(其中,可含無法避免的雜質。以下相同)。在正式燒成所需加熱製程方面,係將前驅體層330a在氧雰圍中以既定時間(例如約20分鐘)、650℃進行加熱。 After that, the precursor layer 330a is subjected to main firing in the same manner as in the second embodiment. In addition, the post-annealing treatment shown in the first embodiment may be additionally performed depending on necessity. As a result, as shown in FIG. 26, an oxide layer 330 that becomes a dielectric layer is formed on the lower electrode layer 320 (which may contain unavoidable impurities. The same applies below). Regarding the heating process required for the main firing, the precursor layer 330a is heated in an oxygen atmosphere for a predetermined time (for example, about 20 minutes) at 650°C.

此處,藉由在前述條件下進行正式燒成、或是藉由進行正式燒成以及第1實施形態所示後退火處理,可製造出氧化物層230a,其可保持相對高的相對介電係數,並可實現極低之介電損耗值。 Here, by performing the main firing under the aforementioned conditions, or by performing the main firing and the post-annealing treatment shown in the first embodiment, the oxide layer 230a can be manufactured, which can maintain a relatively high relative dielectric. Coefficient, and can achieve extremely low dielectric loss value.

此外,也可在正式燒成後進行對於前驅體層330a全面之蝕刻製程,但如前述般,於壓模製程與正式燒成之製程之間包含將前驅體層全體加以蝕刻之製程,為更佳的一態樣。此乃由於相較於在正式燒成後蝕刻各前驅體層可更容易去除不要區域之前驅體層。 In addition, the overall etching process for the precursor layer 330a can also be performed after the formal firing. However, as described above, it is more preferable to include a process of etching the entire precursor layer between the compression molding process and the formal firing process. One way. This is because it is easier to remove the unwanted area precursor layer than etching each precursor layer after the formal firing.

(3)上部電極層之形成 (3) Formation of the upper electrode layer

之後,和下部電極層320同樣地,於氧化物層330上以周知的旋塗法來形成以含鑭(La)之前驅體以及含鎳(Ni)之前驅體為溶質之前驅體溶液做為起始材之上部電極層用前驅體層340a。之後,對上部電極層用前驅體層340a在含氧雰圍中以80℃以上~250℃以下之溫度範圍做加熱來進行預備燒成。 After that, similar to the lower electrode layer 320, a well-known spin coating method is used to form a precursor solution containing lanthanum (La) and nickel (Ni) as the solute on the oxide layer 330. The precursor layer 340a for the upper electrode layer of the starting material. After that, the upper electrode layer precursor layer 340a is heated in an oxygen-containing atmosphere in a temperature range of 80° C. or higher to 250° C. or lower to perform preliminary firing.

接著,如圖27所示般,為了對於經過預備燒成之上部電極層用前驅體層340a進行圖案化,而在上部電極層用前驅體層340a被加熱至80℃以上~300℃以下的狀態下,使用上部電極層用模具M3來對於上部電極層用前驅體層340a以0.1MPa以上~20MPa以下之壓力施行壓模加工。之後,對上部電極層用前驅體層340a進行全面蝕刻,而如圖28所示般,從對應於上部電極層340之區域以外的區域來完全去除上部電極層用前驅體層340a。 Next, as shown in FIG. 27, in order to pattern the upper electrode layer precursor layer 340a after preliminary firing, the upper electrode layer precursor layer 340a is heated to 80°C or higher to 300°C or lower, The upper electrode layer mold M3 is used to perform compression molding on the upper electrode layer precursor layer 340a at a pressure of 0.1 MPa to 20 MPa. After that, the upper electrode layer precursor layer 340a is completely etched, and as shown in FIG. 28, the upper electrode layer precursor layer 340a is completely removed from the area other than the area corresponding to the upper electrode layer 340.

之後,如圖29所示般,做為正式燒成係於氧雰圍中將上部電極層用前驅體層340a以既定時間於520℃至600℃進行加熱,而於氧化物層330上形成由鑭(La)與鎳(Ni)所構成之上部電極層340(其中,可含無法避免的雜質。以下相同)。 After that, as shown in FIG. 29, as the main firing system, the upper electrode layer precursor layer 340a is heated at 520°C to 600°C for a predetermined time in an oxygen atmosphere, and lanthanum ( The upper electrode layer 340 is composed of La) and nickel (Ni) (which may contain unavoidable impurities. The same applies below).

另一方面,本實施形態之薄膜電容器300係於基板10上從基板10側起具備下部電極層320、做為絕緣層之氧化物層330、以及上部電極層340。此外,前述各層係藉由施行壓模加工來形成壓模構造。其結果,真空程序、使用光微影法之程序、或是紫外線之照射程序等需要相對長時間以及/或是昂貴設備的程序將成為不需要。進而,電極層以及氧化物層均可簡便地圖案化。從而,本實施形態之薄膜電容器300在工業性或是量產性極為優異。 On the other hand, the thin film capacitor 300 of the present embodiment is provided with a lower electrode layer 320, an oxide layer 330 as an insulating layer, and an upper electrode layer 340 on the substrate 10 from the substrate 10 side. In addition, each of the aforementioned layers forms a stamper structure by performing stamping processing. As a result, procedures requiring relatively long time and/or expensive equipment such as vacuum procedures, procedures using photolithography, or ultraviolet irradiation procedures will become unnecessary. Furthermore, both the electrode layer and the oxide layer can be easily patterned. Therefore, the film capacitor 300 of this embodiment is extremely excellent in industriality or mass production.

此外,做為本實施形態之變形例,於基板10上形成由下部電極層320之前驅體層亦即下部電極層用前驅體層320a、氧化物層330之前驅體層亦即前驅體層330a、以及上部電極層340之前驅體層亦即上部電極層用前驅體層340a所得之積層體後,對此積層體施行壓模加工也為可採用的一態樣。之後,進行正式燒成。若採用如此之方法,則此態樣中雖不同於薄膜電容器300,無法針對各層單體來形成個別的壓模構造,但可降低壓模加工製程的次數。 In addition, as a modification of this embodiment, a precursor layer for the lower electrode layer 320, which is a precursor layer for the lower electrode layer 320a, a precursor layer for the oxide layer 330, which is a precursor layer for the oxide layer 330, and an upper electrode are formed on the substrate 10. After the layer 340 is a precursor layer, that is, a laminate obtained by using a precursor layer 340a for the upper electrode layer, it is also possible to apply compression molding to the laminate. After that, the formal firing is carried out. If such a method is adopted, although this aspect is different from the film capacitor 300, it is impossible to form an individual stamper structure for each layer of monomer, but the number of stamper processing processes can be reduced.

<其他實施形態(1)> <Other embodiments (1)>

此外,上述各實施形態中氧化物層適合於以低驅動電壓來控制大電流之各種固態電子裝置。做為具備上述各實施形態中之氧化物層的固態電子裝置,除了上述薄膜電容器以外,也可適用於許多裝置上。例如,也可將上述各實施形態中之氧化物層適用於電容可變薄膜電容器等各種電容器、金屬氧化物半導體接合電場效應電晶體(MOSFET)、非揮發性記憶體等半導 體裝置、或是以微TAS(Total Analysis System)、微化學晶片、DNA晶片等MEMS(microelectromechanical system)或是NEMS(nanoelectromechanical system)為代表之微電機系統的元件、其他尚有包含高頻濾波器、貼片天線或是RCL當中至少2種的複合元件。 In addition, the oxide layer in each of the above embodiments is suitable for various solid-state electronic devices that use a low driving voltage to control a large current. As the solid-state electronic device provided with the oxide layer in each of the above embodiments, it can be applied to many devices in addition to the above-mentioned film capacitor. For example, the oxide layer in each of the above embodiments can also be applied to various capacitors such as variable capacitance film capacitors, metal oxide semiconductor junction field effect transistors (MOSFET), non-volatile memory and other semiconductors. Body devices, or MEMS (microelectromechanical systems) such as micro-TAS (Total Analysis System), micro-chemical chips, DNA chips, etc., or components of micro-motor systems represented by NEMS (nanoelectromechanical system), and others that include high-frequency filters , Patch antennas or composite components of at least 2 types of RCL.

以下,針對固態電子裝置一例之薄膜電晶體400之構造來說明。 The following describes the structure of a thin film transistor 400 as an example of a solid-state electronic device.

<本實施形態之薄膜電晶體之全體構成> <The overall structure of the thin film transistor of this embodiment>

圖30係顯示薄膜電晶體400之全體構成圖。如圖30所示般,本實施形態中之薄膜電晶體400係於基板10上從下層起依序積層下部電極層(閘極)320、氧化物層(閘極絕緣層)330、通道444、源極458以及汲極456。下部電極層(閘極)320以及氧化物層(閘極絕緣層)330之製造方法係和第3實施形態個別的製造方法相同故加以省略。 FIG. 30 is a diagram showing the overall structure of the thin film transistor 400. As shown in FIG. 30, the thin film transistor 400 in this embodiment is laminated on the substrate 10 from the lower layer to a lower electrode layer (gate) 320, an oxide layer (gate insulating layer) 330, channels 444, Source 458 and drain 456. The manufacturing methods of the lower electrode layer (gate) 320 and the oxide layer (gate insulating layer) 330 are the same as the individual manufacturing methods of the third embodiment, so they are omitted.

此外,薄膜電晶體400係採用所謂的底部閘極構造,但本實施形態不限定於此構造。此外,和第1實施形態同樣地,為了簡化圖式,針對來自各電極之引出電極的圖案化之記載予以省略。 In addition, the thin film transistor 400 adopts a so-called bottom gate structure, but this embodiment is not limited to this structure. In addition, as in the first embodiment, in order to simplify the drawing, the description of the patterning of the lead electrode from each electrode is omitted.

本實施形態之通道444係由含銦(In)、鋅(Zn)以及鋯(Zr)之通道用氧化物所構成。此外,本實施形態中,也可採用其他周知的通道材料。此外,通道444之厚度為5nm以上~80nm以下,通道444之厚度為5nm以上~80nm以下之薄膜電晶體基於可高確實度覆蓋氧化物層(閘極絕緣層)等之觀點以及使得通道之導電性的調變成為容易之觀點為適宜的一態樣。 The channel 444 of this embodiment is composed of channel oxides containing indium (In), zinc (Zn), and zirconium (Zr). In addition, in this embodiment, other well-known channel materials may also be used. In addition, the thickness of the channel 444 is from 5nm to 80nm, and the thickness of the channel 444 is from 5nm to 80nm. The thin film transistor is based on the viewpoint that it can cover the oxide layer (gate insulating layer) with high reliability and make the channel conductive Sexual tune becomes an easy point of view as an appropriate aspect.

此外,本實施形態之源極458以及汲極電極456係由ITO(Indium Tin Oxide)所構成。 In addition, the source 458 and the drain electrode 456 of this embodiment are made of ITO (Indium Tin Oxide).

此外,於固態電子裝置一例之薄膜電晶體400中,做為發揮氧化物層(閘極絕緣層)330以外之功用的絕緣層也可利用由鉍(Bi)與鈮(Nb)與鈦(Ti)所構成之氧化物。 In addition, in the thin-film transistor 400 of an example of a solid-state electronic device, an insulating layer that performs functions other than the oxide layer (gate insulating layer) 330 can also be made of bismuth (Bi) and niobium (Nb) and titanium (Ti). ) Formed by the oxide.

<其他實施形態(2)> <Other embodiments (2)>

此外,上述實施形態,在施行壓模加工之態樣中之所以將壓模加工時之壓力定在「0.1MPa以上~20MPa以下」之範圍內係基於以下之理由。首先,當該壓力未達1MPa之情況,會有壓力過低而無法對各前驅體層進行壓模之情況。另一方面,只要壓力達20MPa即可充分地對前驅體層進行壓模, 而無須施加更高的壓力。從前述觀點而言,壓模製程中以0.1MPa以上~10MPa以下之範圍內的壓力來施行壓模加工為更佳。 In addition, in the above-mentioned embodiment, the reason why the pressure during the compression molding process is set within the range of "0.1 MPa or more to 20 MPa or less" in the state where the compression molding process is performed is based on the following reasons. First, when the pressure is less than 1 MPa, the pressure may be too low to be able to compression mold each precursor layer. On the other hand, as long as the pressure reaches 20MPa, the precursor layer can be fully compression molded. There is no need to apply higher pressure. From the foregoing point of view, it is better to perform compression molding with a pressure in the range of 0.1 MPa to 10 MPa in the compression molding process.

如以上所述,上述各實施形態之揭示係用以說明此等實施形態而記載者,並非用以限定本發明之記載。進而,包含各實施形態之其他組合的本發明之範圍內所存在之變形例也包含於申請專利範圍中。 As described above, the disclosure of each of the above-mentioned embodiments is described for describing these embodiments, and is not intended to limit the description of the present invention. Furthermore, modifications that exist within the scope of the present invention including other combinations of the respective embodiments are also included in the scope of patent applications.

10‧‧‧基板 10‧‧‧Substrate

20‧‧‧下部電極層 20‧‧‧Lower electrode layer

30‧‧‧氧化物層(氧化物介電質之層) 30‧‧‧Oxide layer (oxide dielectric layer)

40‧‧‧上部電極層 40‧‧‧Upper electrode layer

100‧‧‧固態電子裝置一例之薄膜電容器 100‧‧‧Film capacitors as an example of solid-state electronic devices

Claims (13)

一種氧化物介電質,具有燒綠石型結晶構造之結晶相,含有由鉍(Bi)與鈮(Nb)與鈦(Ti)所構成之氧化物(可含無法避免的雜質);當該鉍(Bi)之原子數為1之時,該鈮(Nb)之原子數為0.5以上~未達1.7,且當該鉍(Bi)之原子數為1之時,該鈦(Ti)之原子數為超過0~未達1.3。 An oxide dielectric with a pyrochlore-type crystal structure in the crystalline phase, containing oxides composed of bismuth (Bi), niobium (Nb) and titanium (Ti) (may contain unavoidable impurities); When the number of atoms of bismuth (Bi) is 1, the number of atoms of niobium (Nb) is 0.5 to less than 1.7, and when the number of atoms of bismuth (Bi) is 1, the atoms of titanium (Ti) The number is over 0 to less than 1.3. 如申請專利範圍第1項之氧化物介電質,其中該鈮(Nb)之原子數與該鈦(Ti)之原子數之和為1以上~2.6以下。 For example, the oxide dielectric of item 1 in the scope of patent application, wherein the sum of the number of atoms of the niobium (Nb) and the number of atoms of the titanium (Ti) is 1 to 2.6. 如申請專利範圍第1或2項之氧化物介電質,其中於25℃利用X射線繞射(XRD)測定該氧化物介電質,並未出現源自β-BiNbO4型結晶構造的波峰。 For example, the oxide dielectric of item 1 or 2 in the scope of patent application, in which the oxide dielectric is measured by X-ray diffraction (XRD) at 25°C, there is no peak derived from the β-BiNbO 4 crystal structure . 如申請專利範圍第1或2項之氧化物介電質,進而當該鉍(Bi)之原子數為1之時,該鈮(Nb)之原子數為0.666以上~1.334以下,或是當該鉍(Bi)之原子數為1之時,該鈦(Ti)之原子數為0.333以上~1以下。 For example, the oxide dielectric of item 1 or 2 of the patent application, and when the number of atoms of the bismuth (Bi) is 1, the number of atoms of the niobium (Nb) is from 0.666 to 1.334, or when the When the number of atoms of bismuth (Bi) is 1, the number of atoms of this titanium (Ti) is 0.333 or more and 1 or less. 如申請專利範圍第1或2項之氧化物介電質,其中當以700℃加熱後,利用X射線繞射(XRD)測定該氧化物介電質,會出現源自燒綠石型結晶構造的波峰,且未出現源自β-BiNbO4型結晶構造的波峰。 For example, the oxide dielectric of item 1 or 2 in the scope of patent application, when heated at 700°C, the oxide dielectric is measured by X-ray diffraction (XRD), and the pyrochlore-type crystal structure appears The peak of β-BiNbO 4 type crystal structure does not appear. 一種固態電子裝置,係具備有如申請專利範圍第1至5項中任一項之氧化物介電質。 A solid-state electronic device is provided with an oxide dielectric as in any one of items 1 to 5 in the scope of the patent application. 如申請專利範圍第6項之固態電子裝置,其中該固態電子裝置係選自由電容器、半導體裝置、以及微電機系統所構成群中之1種。 For example, the solid-state electronic device of the sixth item of the scope of patent application, wherein the solid-state electronic device is selected from one of the group consisting of capacitors, semiconductor devices, and micro-motor systems. 一種氧化物介電質之製造方法,包含下述製程:藉由將以含鉍(Bi)之前驅體、含鈮(Nb)之前驅體以及含鈦(Ti)之前驅體為溶質之前驅體溶液做為起始材之前驅體層在含氧雰圍中進行加熱的加熱處理,來形成氧化物介電質之層,該氧化物介電質具有燒綠石型結晶構造之結晶相,含有由鉍(Bi)與鈮(Nb)與鈦(Ti)所構成之氧化物(可含無法避免的雜質),當該鉍(Bi)之原子數為1之時,該鈮(Nb)之原子數為0.5以上~未達1.7,且當該鉍(Bi)之原子數為1之時,該鈦(Ti)之原子數為超過0~未達1.3。 A manufacturing method of an oxide dielectric, including the following process: by using a bismuth (Bi)-containing precursor, a niobium (Nb)-containing precursor, and a titanium (Ti)-containing precursor as the solute precursor The solution is used as the starting material, and the precursor layer is heated in an oxygen-containing atmosphere to form an oxide dielectric layer. The oxide dielectric has a pyrochlore-type crystal structure of the crystal phase, containing bismuth (Bi) and niobium (Nb) and titanium (Ti) composed of oxides (may contain unavoidable impurities). When the number of atoms of bismuth (Bi) is 1, the number of atoms of niobium (Nb) is 0.5 or more to less than 1.7, and when the number of atoms of the bismuth (Bi) is 1, the number of atoms of the titanium (Ti) is more than 0 to less than 1.3. 如申請專利範圍第8項之氧化物介電質之製造方法,其中形成該氧化物介電質之層之製程進而為形成該鈮(Nb)之原子數與該鈦(Ti)之原子數之和為1以上~2.6以下之該氧化物介電質之層之製程。 For example, the method for manufacturing an oxide dielectric in the scope of patent application, wherein the process of forming the oxide dielectric layer is further to form the number of atoms of the niobium (Nb) and the number of atoms of the titanium (Ti) The manufacturing process of the oxide dielectric layer whose sum is above 1 to below 2.6. 如申請專利範圍第8或9項之氧化物介電質之製造方法,其中藉由以700℃進行加熱之該加熱處理所形成之該氧化物介電質之層,利用X射線繞射(XRD)測定該氧化物介電質,會出現源自燒綠石型結晶構造的波峰,且未出現源自β-BiNbO4型結晶構造的波峰。 For example, the method for manufacturing an oxide dielectric of item 8 or 9 in the scope of the patent application, wherein the oxide dielectric layer formed by the heating treatment at 700°C uses X-ray diffraction (XRD) ) When the oxide dielectric is measured, a peak derived from the pyrochlore type crystal structure appears, and no peak derived from the β-BiNbO 4 type crystal structure appears. 如申請專利範圍第8或9項之氧化物介電質之製造方法,其中形成該氧化物介電質之層之製程進而為形成當該鉍(Bi)之原子數為1之時,該鈮(Nb)之原子數為0.666以上~1.334以下,或是當該鉍(Bi)之原子數為1之時,該鈦(Ti)之原子數為0.333以上~1以下之該氧化物介電質之層之製程。 For example, the method for manufacturing an oxide dielectric of item 8 or 9 of the scope of patent application, wherein the process of forming the oxide dielectric layer is further to form when the number of atoms of the bismuth (Bi) is 1, the niobium The number of atoms of (Nb) is from 0.666 to 1.334, or when the number of atoms of bismuth (Bi) is 1, the number of atoms of titanium (Ti) is from 0.333 to less than 1 The manufacturing process of the layers. 如申請專利範圍第8或9項之氧化物介電質之製造方法,其中於形成該氧化物介電質之層之前,在含氧雰圍中以80℃以上~250℃以下來加熱該前驅體層之狀態下施行壓模加工,以形成該前驅體層之壓模構造。 For example, the method for manufacturing an oxide dielectric of item 8 or 9 of the scope of patent application, wherein before forming the oxide dielectric layer, the precursor layer is heated at a temperature above 80°C to below 250°C in an oxygen-containing atmosphere In this state, compression molding is performed to form a compression molding structure of the precursor layer. 一種固態電子裝置之製造方法,具有下述製程:製造具備氧化物介電質之固態電子裝置,該氧化物介電質係藉由如申請專利範圍第8至12項中任一項之氧化物介電質之製造方法所形成者。 A method for manufacturing a solid-state electronic device has the following manufacturing process: manufacturing a solid-state electronic device with an oxide dielectric, the oxide dielectric is made of an oxide as in any one of the patent applications 8-12 Formed by the manufacturing method of the dielectric.
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