TWI709218B - Chip package structure and manufacturing method thereof - Google Patents

Abstract

A chip package structure includes at least one chip, at least one thermally conductive element, a molding compound and a redistribution layer. Each chip has an active surface and a back surface opposite to each other and a plurality of electrodes disposed on the active surface. The thermally conductive element is disposed on the back surface of each chip. The molding compound encapsulates the chip and the thermally conductive element and has an upper surface and a lower surface opposite to each other. A bottom surface of each of the electrodes of each chip is aligned with the lower surface of the molding compound. The molding compound exposes a top surface of each thermally conductive element. The redistribution layer is disposed on the lower surface of the molding compound and electrically connected to the electrodes of each chip.

Description

Chip packaging structure and manufacturing method thereof

The invention relates to a packaging structure and a manufacturing method thereof, and more particularly to a chip packaging structure and a manufacturing method thereof.

The use of fan-out multi-band antenna wafer-level packaging design can miniaturize electronic circuits and greatly reduce electrical insertion loss. In the future, as the transmission frequency and operation speed of electronic products become faster and faster, the accompanying heat dissipation problem of the chip becomes more and more important. However, in the fabrication of the aforementioned fan-out multi-band antenna wafer-level package, the active surface of the chip is face-up and back bonded to the first reconfiguration circuit layer as the antenna ground pattern, and then the A second reconfiguration circuit layer electrically connected with the solder balls is formed on the active surface of the chip. Therefore, it is impossible to add heat sinks or heat sink fins to dissipate heat from the chip in the above-mentioned manufacturing method, and thus cannot solve the heat dissipation problem of fan-out multi-band antenna wafer-level packaging.

The present invention provides a chip packaging structure, which can have better heat dissipation effects.

The present invention provides a manufacturing method of a chip package structure for manufacturing the above-mentioned chip package structure.

The chip packaging structure of the present invention includes at least one chip, at least one heat-conducting element, a packaging compound, and a reconfiguration circuit layer. Each chip has an active surface and a back surface opposite to each other, and a plurality of electrodes arranged on the active surface. The heat conducting element is arranged on the back of each chip. The packaging glue covers the chip and the heat-conducting element, and has an upper surface and a lower surface opposite to each other. A bottom surface of each electrode of each chip is cut in line with the bottom surface of the packaging compound. The encapsulant exposes a top surface of each thermal element. The reconfiguration circuit layer is disposed on the lower surface of the packaging glue and electrically connected to the electrodes of each chip.

In an embodiment of the present invention, the aforementioned chip package structure further includes at least one conductive via, at least one first pad, and at least one second pad. The conductive through hole penetrates the packaging compound and connects the upper surface and the lower surface. The first pad is disposed on the upper surface of the packaging compound and is electrically connected to a first end of each conductive via. The second pad is configured on the lower surface of the packaging compound and is electrically connected to a second end of each conductive via, wherein the reconfiguration circuit layer is electrically connected to the second pad.

In an embodiment of the present invention, the above-mentioned chip package structure further includes an antenna structure layer, which is disposed on the upper surface of the packaging compound, and includes a dielectric layer and a plurality of antenna patterns. The dielectric layer has at least one opening exposing the heat-conducting element, and the dielectric layer covers the upper surface of the packaging compound and the first pad. The antenna pattern is buried in the dielectric layer and is aligned with a surface of the dielectric layer that is relatively far away from the packaging compound. The antenna pattern is electrically connected to the first pad.

In an embodiment of the present invention, the aforementioned at least one chip is at least one radio frequency chip.

In an embodiment of the present invention, the aforementioned at least one chip includes a first chip and a second chip, and the antenna pattern is arranged corresponding to the first chip.

In an embodiment of the present invention, the aforementioned first chip is a radio frequency chip, and the second chip is a baseband chip.

In an embodiment of the present invention, the aforementioned at least one chip is at least one baseband chip.

In an embodiment of the present invention, the above-mentioned chip package structure further includes a plurality of solder balls, which are arranged on the plurality of fan-out pads of the redistributed circuit layer and are electrically connected to the redistributed circuit layer.

In an embodiment of the present invention, the orthographic projection area of each of the above-mentioned heat-conducting elements on the back surface of each chip is smaller than the area of the back surface.

In an embodiment of the present invention, the aforementioned chip package structure further includes at least one thermal interface material disposed between the thermally conductive element and the chip. The thermally conductive element is fixed on the chip through the thermal interface material.

The manufacturing method of the chip package structure of the present invention includes the following steps. Provide a carrier with an adhesive layer formed. At least one chip and at least one heat conducting element are provided. Each chip has an active surface and a back surface opposite to each other, and a plurality of electrodes arranged on the active surface. Each heat conducting element is arranged on the back of each chip. The chips are bonded on the carrier, and the electrodes of each chip directly contact the adhesive layer. A encapsulant is formed on the carrier to cover the adhesive layer and cover the chip and the heat-conducting element. Remove part of the encapsulant so that the encapsulant exposes a top surface of each thermal element. The carrier board and the adhesive layer are removed, and the electrodes of each chip and the lower surface of the packaging glue are exposed. A bottom surface of each electrode of each chip is cut in line with the bottom surface of the packaging compound. A reconfiguration circuit layer is formed on the lower surface of the encapsulant. The reconfiguration circuit layer is electrically connected to the electrodes of each chip.

In an embodiment of the present invention, after the carrier board and the adhesive layer are removed, and before the reconfiguration circuit layer is formed, the following steps are further included. At least one conductive through hole is formed to penetrate through the packaging glue and connect an upper surface and a lower surface of the packaging glue with respect to the lower surface. At least one first pad is formed on the upper surface of the packaging compound, wherein the first pad is electrically connected to a first end of each conductive via. At least one second pad is formed on the lower surface of the encapsulant, wherein the second pad is electrically connected to a second end of each conductive via.

In an embodiment of the present invention, before forming the reconfiguration circuit layer, it further includes forming an antenna structure layer on the upper surface of the packaging compound. The antenna structure layer includes a dielectric layer and a plurality of antenna patterns. The dielectric layer has at least one opening exposing the heat-conducting element, and the dielectric layer covers the upper surface of the packaging compound and the first pad. The antenna pattern is buried in the dielectric layer and is aligned with a surface of the dielectric layer that is relatively far away from the packaging compound. The antenna pattern is electrically connected to the first pad.

In an embodiment of the present invention, the aforementioned at least one chip is at least one radio frequency (RF) chip.

In an embodiment of the present invention, the aforementioned at least one chip includes a first chip and a second chip. The antenna pattern is arranged corresponding to the first chip.

In an embodiment of the present invention, the above-mentioned first chip is a radio frequency chip, and the second chip is a baseband chip.

In an embodiment of the present invention, the aforementioned at least one chip is at least one baseband chip.

In an embodiment of the present invention, after forming the reconfiguration circuit layer, it further includes: forming a plurality of solder balls on the plurality of fan-out pads of the reconfiguration circuit layer, wherein the solder balls are electrically connected to the reconfiguration circuit layer .

In an embodiment of the present invention, the orthographic projection area of each of the above-mentioned heat-conducting elements on the back surface of each chip is smaller than the area of the back surface.

In an embodiment of the present invention, the manufacturing method of the above-mentioned chip package structure further includes providing at least one thermal interface material between the thermally conductive element and the chip, wherein the thermally conductive element is fixed on the chip through the thermal interface material.

Based on the above, in the design of the chip package structure of the present invention, a thermally conductive element is arranged on the back of the chip, and the top surface of the thermally conductive element is exposed by the packaging glue. Thereby, the heat generated by the chip can be quickly transferred to the outside through the heat-conducting element, so that the chip package structure of the present invention can have a better heat dissipation effect. In addition, the reconfiguration circuit layer is disposed on the lower surface of the packaging compound and electrically connected to the electrodes of the chip, so that the chip packaging structure of the present invention can have better electrical performance. In short, the chip package structure of the present invention can take into account both electrical and heat dissipation performance, and can maintain the function of the chip without overheating, thereby effectively extending the service life of the chip package structure.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

1A to 1J are schematic cross-sectional diagrams of a manufacturing method of a chip package structure according to an embodiment of the present invention. FIG. 2 is a schematic top view of the chip package structure of FIG. 1J. Regarding the manufacturing method of the chip package structure of this embodiment, first, referring to FIG. 1A, a carrier 10 having an adhesive layer 12 formed thereon is provided. Here, the adhesive layer 12 is, for example, a double-sided thermal release tape (thermal release tape), but it is not limited thereto.

Next, referring to FIG. 1B, at least one chip (schematically shows a chip 110) and at least one heat-conducting element (schematically shows a heat-conducting element 120) is provided. Each chip 110 has an active surface 111 and a back surface 113 opposite to each other, and a plurality of electrodes 112 disposed on the active surface 111. Each heat conducting element 120 is disposed on the back surface 113 of each chip 110. Furthermore, at least one thermal interface material (TIM) (a thermal interface material 125 is schematically shown) can be provided between the thermally conductive element 120 and the chip 110, wherein the thermally conductive element 120 can penetrate the thermal interface material 125 It is fixed on the chip 110. As shown in FIG. 1B, the orthographic projected area of the heat conducting element 120 on the back surface 113 of the wafer 110 is smaller than the area of the back surface 113. Here, the chip 110 is embodied as a radio frequency (RF) chip, and the thermally conductive element 120 is, for example, a heat spreader (Heat Spreader), but not limited to this.

Next, referring to FIG. 1C, the chip 110 is bonded on the carrier 10, and the electrode 112 of each chip 110 directly contacts the adhesive layer 12. Here, the chip 110 and the thermal conductive element 120 thereon are bonded to the adhesive layer 12 of the carrier board 10 in a face-down manner with the active surface 111 facing down.

Next, referring to FIG. 1D, an encapsulant 130 a is formed on the carrier board 10 to cover the adhesive layer 12 and cover the chip 110 and the thermally conductive element 120. At this time, the encapsulant 130a completely covers the chip 110 and the thermally conductive element 120, which means that a top surface 122 of the thermally conductive element 120 is also covered by the encapsulant 130.

Next, referring to FIG. 1D and FIG. 1E at the same time, a part of the encapsulant 130 a is removed by, for example, grinding, so that the encapsulant 130 exposes the top surface 122 of the thermally conductive element 120. Here, the top surface 122 of the heat-conducting element 120 is substantially flush with an upper surface 132 of the packaging compound 130.

Next, referring to FIG. 1E and FIG. 1F at the same time, the carrier 10 and the adhesive layer 12 are removed, and the electrode 112 of the chip 110 and the lower surface 134 of the encapsulant 130 relative to the upper surface 132 are exposed. Here, a bottom surface 115 of each electrode 112 of the chip 110 is substantially aligned with the bottom surface 134 of the packaging compound 130.

Next, referring to FIGS. 1G and 1H at the same time, a through hole is formed in the packaging compound 130 by means of, for example, laser drilling, and at least one conductive through hole is formed by means of electroplating and filling of holes (two are shown schematically) Conductive vias 140) to penetrate the encapsulant 130, form at least one first pad (schematically show two first pads 150) on the upper surface 132 of the encapsulant 130, and form at least one second pad ( Two second pads 155) are schematically shown on the lower surface 134 of the encapsulant 140. The conductive via 140 is connected to the upper surface 132 and the lower surface 134, the first pad 150 is electrically connected to a first end 142 of each conductive via 140, and the second pad 155 is electrically connected to each conductive via 140 The one second end 144. Here, the material of the conductive via 140, the material of the first pad 150, and the material of the second pad 155 are the same, such as copper, but not limited to this.

After that, referring to FIGS. 1I and 2 at the same time, an antenna structure layer 160 is formed on the upper surface 132 of the packaging compound 130. The antenna structure layer 160 includes a dielectric layer 162 and a plurality of antenna patterns 164. The dielectric layer 162 has at least one opening (one opening 163 is schematically shown) exposing the heat-conducting element 120, and the dielectric layer 162 covers the upper surface 132 of the encapsulant 130 and the first pad 150. Here, the dielectric layer 162 is, for example, a photosensitive dielectric layer (Photo-Imageable Dielectric layer), and the opening 163 is formed by, for example, etching, but is not limited thereto. The antenna pattern 164 is embedded in the dielectric layer 162 and is aligned with a surface 165 of the dielectric layer 162 that is relatively far away from the packaging compound 130, wherein the antenna pattern 164 is electrically connected to the first pad 150. Here, the antenna pattern 164 includes, for example, a plurality of patch antennas 164a and a plurality of dipole antennas 164b, and the material of the antenna pattern 164 is, for example, copper, but it is not limited thereto.

Finally, referring to FIG. 1J, a reconfiguration circuit layer 170 is formed on the lower surface 134 of the encapsulant 130, wherein the reconfiguration circuit layer 170 is electrically connected to the electrode 112 of the chip 110. Since the orthographic projection area of the patterned circuit 172 of the reconfiguration circuit layer 170 on the packaging glue 130 is larger than the orthographic projection area of the chip 110 on the packaging glue 130, the patterned circuit 172 can be regarded as a fan-out circuit. Next, a plurality of solder balls 180 are formed on the plurality of fan-out pads 174 of the redistributed circuit layer 170, wherein the solder balls 180 and the redistributed circuit layer 170 are electrically connected. Finally, a singulation process can be used to form at least one chip package structure 100a as shown in FIG. 1J to complete the fabrication of the chip package structure 100a.

In terms of structure, please refer to FIG. 1J again. The chip package structure 100 a of this embodiment includes a chip 110, a thermally conductive element 120, an encapsulant 130 and a reconfiguration circuit layer 170. The chip 110 is, for example, a radio frequency chip, and it has an active surface 111 and a back surface 113 opposite to each other, and an electrode 112 disposed on the active surface 111. The thermally conductive element 120 can be disposed through the thermal interface material 125 and fixed on the back 113 of the chip 110, wherein the orthographic area of the thermally conductive element 120 on the back 113 of the chip 110 is smaller than the area of the back 113. The encapsulant 130 covers the chip 110 and the heat conducting element 120 and has an upper surface 132 and a lower surface 134 opposite to each other. The top surface 122 of the thermally conductive element 120 is aligned with the top surface 132 of the packaging glue 130. The bottom surface 115 of the electrode 112 of the chip 110 is aligned with the bottom surface 134 of the encapsulant 130. The reconfiguration circuit layer 170 is disposed on the lower surface 134 of the packaging glue 130 and is electrically connected to the electrode 112 of the chip 110.

Furthermore, the chip package structure 100a of this embodiment further includes conductive vias 140, first pads 150, and second pads 155. The conductive via 140 penetrates the encapsulant 130 and connects the upper surface 132 and the lower surface 134. The first pad 150 is disposed on the upper surface 132 of the encapsulant 130 and is electrically connected to the first end 142 of each conductive via 140. The second pad 155 is disposed on the lower surface 134 of the encapsulant 130 and is electrically connected to the second end 144 of each conductive via 140, wherein the patterned circuit layer 172 of the reconfiguration circuit layer 170 is electrically connected to the second terminal Pad 155.

In addition, the chip package structure 100 a of the present embodiment further includes an antenna structure layer 160, which is disposed on the upper surface 132 of the encapsulant 130, and includes a dielectric layer 162 and an antenna pattern 164. The dielectric layer 162 has an opening 163 exposing the thermal conductive element 120, and the dielectric layer 162 covers the upper surface 132 of the packaging compound 130 and the first pad 150. The antenna pattern 164 is buried in the dielectric layer 162 and is aligned with the surface 165 of the dielectric layer 162 that is relatively far away from the packaging compound 130, and the antenna pattern 164 is electrically connected to the first pad 150. In addition, the chip package structure 100a of this embodiment further includes solder balls 180, which are disposed on the fan-out pads 174 of the redistributed circuit layer 170 and are electrically connected to the redistributed circuit layer 170.

Compared with the conventional face-up manufacturing method of the chip, the chip 110 and the thermally conductive element 120 thereon are bonded with the active surface 111 facing down (face-down) in this embodiment. A thermally conductive element 120 is disposed on the adhesive layer 12 of the carrier 10 and the back 113 of the chip 110, wherein the encapsulant 130 and the opening 163 of the dielectric layer 162 of the antenna structure layer 160 both expose the top surface 122 of the thermally conductive element 120. Thereby, the heat generated by the chip 110 can be quickly transferred to the outside through the heat conducting element 120, so that the chip package structure 100a of this embodiment can have a better heat dissipation effect. In addition, the reconfiguration circuit layer 170 is disposed on the lower surface 134 of the encapsulant 130 and electrically connected to the electrode 112 of the chip 110, and the conductive via 140, the first pad 150 and the second pad 155 are electrically connected to the antenna structure The layer 160 and the reconfiguration circuit layer 170 enable the chip package structure 100a of this embodiment to have better electrical performance. In short, the chip package structure 100a of this embodiment can take into account both electrical and heat dissipation performance, can maintain the function of the chip 110 without overheating, maintain the radiation intensity and gain of the antenna pattern 164, and effectively extend the chip package structure 100a life span. In other words, the chip package structure 100a of this embodiment can be regarded as a chip package structure of a heat dissipation enhanced fan-out antenna package.

It must be noted here that the following embodiments use the element numbers and part of the content of the foregoing embodiments, wherein the same numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, and the following embodiments will not be repeated.

3 is a schematic cross-sectional view of a chip package structure according to an embodiment of the invention. 1J and 3 at the same time, the chip package structure 100b of this embodiment is similar to the chip package structure 100a of FIG. 1J, and the difference between the two is that the heat conducting element of this embodiment includes a first heat conducting element 120a and a second heat conducting element 120a. Thermally conductive element 120b. The first heat-conducting element 120a is fixed on the back surface 113 of the chip 110 through the thermal interface material 125, wherein the first heat-conducting element 120a is, for example, a heat sink. The second heat conducting element 120b is fixed on the first heat conducting element 120a through the thermal interface material 127, wherein the second heat conducting element 120b is, for example, a heat dissipation fin. Here, the first heat conducting element 120a is located between the thermal interface material 125 and the thermal interface material 127, and the thermal interface material 127 is coplanar with the upper surface 132 of the encapsulant 130, but not limited to this. Since the chip package structure 100b of the present embodiment includes a first heat conduction element 120a and a second heat conduction element 120b, they can be matched on a high-performance chip 110 to improve the heat dissipation effect of the overall chip package structure 100b.

4 is a schematic cross-sectional view of a chip package structure according to another embodiment of the invention. 1J and 4 at the same time, the chip package structure 100c of this embodiment is similar to the chip package structure 100a of FIG. 1J. The difference between the two is: the chip package structure 100c of this embodiment does not have an antenna structure layer 160, and The chip 110a of the embodiment is embodied as a baseband-chip. The thermally conductive element 120 is fixed on the back surface 113a of the chip 110a through the thermal interface material 125.

In the manufacturing process, after the step of FIG. 1F, the carrier 10 and the adhesive layer 12 are removed, and the electrode 112 of the chip 110 and the lower surface 134 of the encapsulant 130 relative to the upper surface 132 are exposed, directly follow the step of FIG. 1J The steps include forming the reconfiguration circuit layer 170 on the lower surface 134 of the encapsulant 130, forming the solder balls 180 on the fan-out pad 174 of the reconfiguration circuit layer 170, and performing the singulation process.

5 is a schematic cross-sectional view of a chip package structure according to another embodiment of the invention. 1J and FIG. 5 at the same time, the chip package structure 100d of this embodiment is similar to the chip package structure 100a of FIG. 1J. The difference between the two is that at least one chip of this embodiment includes a chip 110 (which can be regarded as a first chip). ) And the chip 110a (can be regarded as the second chip), and the antenna pattern 164 is arranged corresponding to the chip 110. For example, the antenna pattern 164 is arranged around the chip 110; or, the orthographic projection of the antenna pattern 164 on the upper surface 132 of the encapsulant 130 completely overlaps or partially overlaps the chip 110 on the upper surface 132 of the encapsulant 130 Orthographic projection. The orthographic projection of the antenna pattern 164 on the upper surface 132 of the packaging compound 130 does not overlap with the orthographic projection of the chip 110 a on the upper surface 132 of the packaging compound 130. Here, the chip 110 is a radio frequency chip, and the chip 110a is a base frequency chip. That is, the antenna pattern 164 is not provided at the corresponding baseband chip.

In addition, the heat-conducting element of this embodiment includes a first heat-conducting element 120a and a second heat-conducting element 120b. The first heat-conducting element 120a is fixed on the back surfaces 113, 113a of the chips 110, 110a through the thermal interface material 125, wherein the first heat-conducting element 120a is, for example, a heat sink. The second heat conducting element 120b is fixed on the first heat conducting element 120a through the thermal interface material 127, wherein the second heat conducting element 120b is, for example, a heat dissipation fin. Here, the first heat conducting element 120a is located between the thermal interface material 125 and the thermal interface material 127, and the thermal interface material 127 is coplanar with the upper surface 132 of the encapsulant 130, but not limited to this. Since the chip package structure 100d of the present embodiment includes a first heat-conducting element 120a and a second heat-conducting element 120b, they can be matched with high-performance chips 110 and 110a to improve the heat dissipation effect of the overall chip package structure 100d.

To sum up, in the design of the chip package structure of the present invention, a heat-conducting element is arranged on the back of the chip, and the top surface of the heat-conducting element is exposed by the encapsulant. Thereby, the heat generated by the chip can be quickly transferred to the outside through the heat-conducting element, so that the chip package structure of the present invention can have a better heat dissipation effect. In addition, the reconfiguration circuit layer is disposed on the lower surface of the packaging compound and electrically connected to the electrodes of the chip, so that the chip packaging structure of the present invention can have better electrical performance. In short, the chip package structure of the present invention can take into account both electrical and heat dissipation performance, and can maintain the function of the chip without overheating, thereby effectively extending the service life of the chip package structure.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

10: Carrier board 12: Adhesive layer 100a, 100b, 100c, 100d: chip package structure 110, 110a: chip 111: active surface 112: Electrode 113, 113a: back 115: bottom surface 120, 120a, 120b: thermally conductive elements 122: top surface 125, 127: Thermal interface materials 130, 130a: Encapsulation gel 132: upper surface 134: lower surface 140: conductive via 142: first end 144: second end 150: first pad 155: second pad 160: antenna structure layer 162: Dielectric layer 163: open 164: Antenna pattern 164a: Patch antenna 164b: dipole antenna 165: Surface 170: reconfiguration line layer 172: Patterned circuit layer 174: Fan Out Pad 180: solder ball

1A to 1J are schematic cross-sectional diagrams of a manufacturing method of a chip package structure according to an embodiment of the present invention. FIG. 2 is a schematic top view of the chip package structure of FIG. 1J. 3 is a schematic cross-sectional view of a chip package structure according to an embodiment of the invention. 4 is a schematic cross-sectional view of a chip package structure according to another embodiment of the invention. 5 is a schematic cross-sectional view of a chip package structure according to another embodiment of the invention.

100a: Chip package structure

110: chip

111: active surface

112: Electrode

113: Back

115: bottom surface

120: Thermal element

122: top surface

125: Thermal interface material

130: Encapsulation colloid

132: upper surface

134: lower surface

140: conductive via

142: first end

144: second end

150: first pad

155: second pad

160: antenna structure layer

162: Dielectric layer

163: open

164: Antenna pattern

165: Surface

170: reconfiguration line layer

172: Patterned circuit layer

174: Fan Out Pad

180: solder ball

Claims (18)

A chip packaging structure includes: at least one chip, each chip having an active surface and a back surface opposite to each other, and a plurality of electrodes arranged on the active surface; at least one heat conducting element arranged on the back surface of each chip An encapsulant, covering the at least one chip and the at least one heat-conducting element, and having an upper surface and a lower surface opposite to each other, wherein a bottom surface of each electrode of each of the chips is aligned with the lower surface, and The packaging compound exposes a top surface of each of the thermally conductive elements; a reconfiguration circuit layer is disposed on the lower surface of the packaging compound and electrically connected to the electrodes of each chip; at least one conductive through hole penetrates the The encapsulant is connected to the upper surface and the lower surface; at least one first pad is disposed on the upper surface of the encapsulant and is electrically connected to a first end of each conductive via; at least one second contact A pad is disposed on the lower surface of the encapsulant and is electrically connected to a second end of each of the conductive vias, wherein the reconfiguration circuit layer is electrically connected to the at least one second pad; and an antenna structure layer , Disposed on the upper surface of the encapsulant, and including a dielectric layer and a plurality of antenna patterns, wherein the dielectric layer has at least one opening exposing the at least one thermally conductive element, and the dielectric layer covers the package The upper surface of the colloid and the at least one first pad, and the antenna patterns are embedded in the dielectric layer and are aligned with the The dielectric layer is relatively far away from a surface of the packaging compound, and the antenna patterns are electrically connected to the at least one first pad. According to the chip package structure described in claim 1, wherein the at least one chip is at least one radio frequency chip. According to the chip package structure described in claim 1, wherein the at least one chip includes a first chip and a second chip, and the antenna pattern is arranged corresponding to the first chip. According to the chip package structure described in claim 3, the first chip is a radio frequency chip, and the second chip is a baseband chip. According to the chip package structure described in claim 1, wherein the at least one chip is at least one baseband chip. The chip package structure described in item 1 of the scope of patent application further includes a plurality of solder balls, which are arranged on a plurality of fan-out pads of the redistributed circuit layer and are electrically connected to the redistributed circuit layer. According to the chip package structure described in claim 1, wherein the orthographic projected area of each thermal element on the back surface of each chip is smaller than the area of the back surface. The chip package structure described in claim 1 further includes: at least one thermal interface material disposed between the at least one thermally conductive element and the at least one chip, wherein the at least one thermally conductive element passes through the at least one thermal interface The material is fixed on the at least one chip. A method for manufacturing a chip packaging structure includes: A carrier board having an adhesive layer formed thereon is provided; at least one chip and at least one heat-conducting element are provided, each chip has an active surface and a back surface opposite to each other, and a plurality of electrodes arranged on the active surface, each of the heat-conducting elements Arranged on the back surface of each of the chips; bonding the at least one chip to the carrier, wherein the electrodes of each of the chips directly contact the adhesive layer; forming an encapsulant on the carrier to cover the adhesive layer And encapsulate the at least one chip and the at least one heat-conducting element; remove part of the encapsulant so that the encapsulant exposes a top surface of each of the heat-conducting elements; remove the carrier board and the adhesive layer to expose The electrodes of each chip and the lower surface of the encapsulation body, wherein a bottom surface of each electrode of each chip is aligned with the lower surface of the encapsulation body; and a reconfiguration circuit layer is formed on the lower surface of the encapsulation body On the bottom surface, the reconfiguration circuit layer is electrically connected to the electrodes of each chip. According to the method for manufacturing a chip package structure according to claim 9, after removing the carrier and the adhesive layer, and before forming the reconfiguration circuit layer, it further comprises: forming at least one conductive via to Pass through the encapsulant and connect an upper surface of the encapsulant relative to the lower surface and the lower surface; form at least one first pad on the upper surface of the encapsulant, wherein the at least one first pad is electrically conductive Connected to a first end of each of the conductive vias; and At least one second pad is formed on the lower surface of the encapsulant, wherein the at least one second pad is electrically connected to a second end of each of the conductive vias. According to the method for manufacturing a chip package structure described in claim 10, before the reconfiguration circuit layer is formed, it further includes: forming an antenna structure layer on the upper surface of the packaging compound, wherein the antenna structure layer Comprising a dielectric layer and a plurality of antenna patterns, the dielectric layer has at least one opening exposing the at least one thermally conductive element, and the dielectric layer covers the upper surface of the encapsulant and the at least one first pad, The antenna patterns are embedded in the dielectric layer and are aligned with a surface of the dielectric layer that is relatively far away from the packaging compound, and the antenna patterns are electrically connected to the at least one first pad. According to the manufacturing method of the chip package structure described in claim 11, the at least one chip is at least one radio frequency chip. According to the manufacturing method of the chip package structure described in claim 11, the at least one chip includes a first chip and a second chip, and the antenna pattern is arranged corresponding to the first chip. According to the manufacturing method of the chip package structure described in claim 13, wherein the first chip is a radio frequency chip, and the second chip is a baseband chip. According to the manufacturing method of the chip package structure described in item 9 of the scope of patent application, the at least one chip is at least one baseband chip. According to the manufacturing method of the chip package structure described in item 9 of the scope of patent application, after forming the reconfiguration circuit layer, it further includes: A plurality of solder balls are formed on the fan-out pads of the redistributed circuit layer, wherein the solder balls are electrically connected to the redistributed circuit layer. According to the manufacturing method of the chip package structure described in claim 9, wherein the orthographic projected area of each of the thermally conductive elements on the back surface of each chip is smaller than the area of the back surface. The manufacturing method of the chip package structure according to claim 9 further includes: providing at least one thermal interface material between the at least one thermally conductive element and the at least one chip, wherein the at least one thermally conductive element passes through the at least one The thermal interface material is fixed on the at least one chip.

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