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TWI799588B - 積和運算裝置、積和運算電路、積和運算系統及積和運算方法 - Google Patents

積和運算裝置、積和運算電路、積和運算系統及積和運算方法 Download PDF

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Publication number
TWI799588B
TWI799588B TW108117978A TW108117978A TWI799588B TW I799588 B TWI799588 B TW I799588B TW 108117978 A TW108117978 A TW 108117978A TW 108117978 A TW108117978 A TW 108117978A TW I799588 B TWI799588 B TW I799588B
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TW
Taiwan
Prior art keywords
sum operation
product sum
product
circuit
operation device
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TW108117978A
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English (en)
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TW202006611A (zh
Inventor
森江隆
山口正登志
岩元剛毅
田向権
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日商索尼股份有限公司
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Publication of TW202006611A publication Critical patent/TW202006611A/zh
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Publication of TWI799588B publication Critical patent/TWI799588B/zh

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443—Sum of products
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/049—Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06G—ANALOGUE COMPUTERS
    • G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
    • G06G7/12—Arrangements for performing computing operations, e.g. operational amplifiers
    • G06G7/16—Arrangements for performing computing operations, e.g. operational amplifiers for multiplication or division
    • G06G7/161—Arrangements for performing computing operations, e.g. operational amplifiers for multiplication or division with pulse modulation, e.g. modulation of amplitude, width, frequency, phase or form
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06G—ANALOGUE COMPUTERS
    • G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
    • G06G7/12—Arrangements for performing computing operations, e.g. operational amplifiers
    • G06G7/18—Arrangements for performing computing operations, e.g. operational amplifiers for integration or differentiation; for forming integrals
    • G06G7/184—Arrangements for performing computing operations, e.g. operational amplifiers for integration or differentiation; for forming integrals using capacitive elements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/048—Activation functions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G06N3/065—Analogue means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01728—Modifications for accelerating switching in field-effect transistor circuits in synchronous circuits, i.e. by using clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/0806—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using charge transfer devices (DTC, CCD)
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/48—Indexing scheme relating to groups G06F7/48 - G06F7/575
    • G06F2207/4802—Special implementations
    • G06F2207/4814—Non-logic devices, e.g. operational amplifiers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Biomedical Technology (AREA)
  • Biophysics (AREA)
  • Software Systems (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Computer Hardware Design (AREA)
  • Data Mining & Analysis (AREA)
  • Evolutionary Computation (AREA)
  • General Health & Medical Sciences (AREA)
  • Molecular Biology (AREA)
  • Artificial Intelligence (AREA)
  • Computational Linguistics (AREA)
  • Power Engineering (AREA)
  • Neurology (AREA)
  • Complex Calculations (AREA)
  • Analogue/Digital Conversion (AREA)
  • Amplifiers (AREA)
  • Logic Circuits (AREA)
TW108117978A 2018-07-13 2019-05-24 積和運算裝置、積和運算電路、積和運算系統及積和運算方法 TWI799588B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2018-133750 2018-07-13
JP2018133750 2018-07-13

Publications (2)

Publication Number Publication Date
TW202006611A TW202006611A (zh) 2020-02-01
TWI799588B true TWI799588B (zh) 2023-04-21

Family

ID=69141673

Family Applications (1)

Application Number Title Priority Date Filing Date
TW108117978A TWI799588B (zh) 2018-07-13 2019-05-24 積和運算裝置、積和運算電路、積和運算系統及積和運算方法

Country Status (6)

Country Link
US (1) US12008338B2 (zh)
EP (1) EP3822843B1 (zh)
JP (1) JP7283477B2 (zh)
CN (1) CN112384927B (zh)
TW (1) TWI799588B (zh)
WO (1) WO2020013069A1 (zh)

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* Cited by examiner, † Cited by third party
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US12299556B2 (en) * 2020-06-02 2025-05-13 University Of Louisiana At Lafayette Method for pulse-based convolution for near-sensor processing
KR102840449B1 (ko) * 2020-06-24 2025-07-29 삼성전자주식회사 회로를 이용하여 소정의 연산을 수행하는 장치 및 방법
CN115769221A (zh) * 2020-07-17 2023-03-07 株式会社半导体能源研究所 半导体装置及电子设备
US20230049032A1 (en) * 2021-08-02 2023-02-16 Silicon Storage Technology, Inc. Output circuitry for analog neural memory in a deep learning artificial neural network
JP7694246B2 (ja) * 2021-08-06 2025-06-18 日本電気株式会社 演算装置、ニューラルネットワークシステム、ニューロンモデル装置、演算方法およびプログラム
JP7725928B2 (ja) * 2021-08-06 2025-08-20 日本電気株式会社 演算装置、ニューラルネットワークシステム、ニューロンモデル装置、演算方法およびプログラム
US11789857B2 (en) * 2021-08-11 2023-10-17 International Business Machines Corporation Data transfer with continuous weighted PPM duration signal
JP7697516B2 (ja) * 2021-09-03 2025-06-24 日本電気株式会社 演算装置、ニューラルネットワークシステム、ニューロンモデル装置、演算方法および学習済みモデル生成方法
US20230376736A1 (en) * 2022-05-23 2023-11-23 International Business Machines Corporation Neuron circuits for spiking neural networks
US20230386566A1 (en) * 2022-05-25 2023-11-30 Stmicroelectronics International N.V. Bit line voltage clamping read circuit for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (sram)
US12469545B2 (en) * 2022-05-25 2025-11-11 Stmicroelectronics International N.V. Bit line read current mirroring circuit for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)

Citations (4)

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Publication number Priority date Publication date Assignee Title
JPH07141313A (ja) * 1993-11-18 1995-06-02 Fujitsu Ltd 神経回路素子
JP2010061428A (ja) * 2008-09-04 2010-03-18 Yazaki Corp 掛算回路
US20180101359A1 (en) * 2016-10-12 2018-04-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and system using the same
US20180181708A1 (en) * 2013-01-17 2018-06-28 Edico Genome Corporation Bioinformatics systems, apparatuses, and methods executed on an integrated circuit processing platform

Family Cites Families (6)

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Publication number Priority date Publication date Assignee Title
JP4620944B2 (ja) 2003-10-16 2011-01-26 キヤノン株式会社 積和演算回路及びその方法
JP4272967B2 (ja) 2003-10-16 2009-06-03 キヤノン株式会社 演算回路およびその動作制御方法
JP6501146B2 (ja) * 2014-03-18 2019-04-17 パナソニックＩｐマネジメント株式会社 ニューラルネットワーク回路およびその学習方法
EP3502950B1 (en) * 2016-08-19 2021-02-03 Sony Corporation Multiplier-accumulator
US9779355B1 (en) * 2016-09-15 2017-10-03 International Business Machines Corporation Back propagation gates and storage capacitor for neural networks
US11315009B2 (en) * 2017-03-03 2022-04-26 Hewlett Packard Enterprise Development Lp Analog multiplier-accumulators

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07141313A (ja) * 1993-11-18 1995-06-02 Fujitsu Ltd 神経回路素子
JP2010061428A (ja) * 2008-09-04 2010-03-18 Yazaki Corp 掛算回路
US20180181708A1 (en) * 2013-01-17 2018-06-28 Edico Genome Corporation Bioinformatics systems, apparatuses, and methods executed on an integrated circuit processing platform
US20180101359A1 (en) * 2016-10-12 2018-04-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and system using the same

Also Published As

Publication number Publication date
US20210294573A1 (en) 2021-09-23
EP3822843B1 (en) 2024-10-16
CN112384927B (zh) 2024-09-13
JP7283477B2 (ja) 2023-05-30
US12008338B2 (en) 2024-06-11
WO2020013069A1 (ja) 2020-01-16
EP3822843A4 (en) 2021-09-01
EP3822843A1 (en) 2021-05-19
JPWO2020013069A1 (ja) 2021-08-02
TW202006611A (zh) 2020-02-01
CN112384927A (zh) 2021-02-19

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