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TWI799427B - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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Publication number
TWI799427B
TWI799427B TW107121415A TW107121415A TWI799427B TW I799427 B TWI799427 B TW I799427B TW 107121415 A TW107121415 A TW 107121415A TW 107121415 A TW107121415 A TW 107121415A TW I799427 B TWI799427 B TW I799427B
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TW
Taiwan
Prior art keywords
semiconductor device
semiconductor
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Application number
TW107121415A
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English (en)
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TW201921623A (zh
Inventor
森山卓史
利根川丘
Original Assignee
日商瑞薩電子股份有限公司
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Application filed by 日商瑞薩電子股份有限公司 filed Critical 日商瑞薩電子股份有限公司
Publication of TW201921623A publication Critical patent/TW201921623A/zh
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Publication of TWI799427B publication Critical patent/TWI799427B/zh

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    • H—ELECTRICITY
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes)
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes) consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
TW107121415A 2017-06-29 2018-06-22 半導體裝置 TWI799427B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2017127570A JP6872991B2 (ja) 2017-06-29 2017-06-29 半導体装置およびその製造方法
JP2017-127570 2017-06-29

Publications (2)

Publication Number Publication Date
TW201921623A TW201921623A (zh) 2019-06-01
TWI799427B true TWI799427B (zh) 2023-04-21

Family

ID=64734953

Family Applications (1)

Application Number Title Priority Date Filing Date
TW107121415A TWI799427B (zh) 2017-06-29 2018-06-22 半導體裝置

Country Status (4)

Country Link
US (1) US10504861B2 (zh)
JP (1) JP6872991B2 (zh)
CN (1) CN109216307B (zh)
TW (1) TWI799427B (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019114750A (ja) * 2017-12-26 2019-07-11 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US11404310B2 (en) * 2018-05-01 2022-08-02 Hutchinson Technology Incorporated Gold plating on metal layer for backside connection access
JP7379845B2 (ja) * 2019-03-28 2023-11-15 セイコーエプソン株式会社 半導体装置、半導体装置の製造方法、電子デバイス、電子機器および移動体
US11088141B2 (en) 2019-10-03 2021-08-10 Nanya Technology Corporation Semiconductor device and method for fabricating the same
JP7465120B2 (ja) * 2020-03-10 2024-04-10 キヤノン株式会社 半導体装置、その製造方法及び機器
JPWO2022064551A1 (zh) * 2020-09-23 2022-03-31
JP7760308B2 (ja) * 2021-09-27 2025-10-27 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
CN117542817B (zh) * 2024-01-05 2024-03-29 江苏中科智芯集成科技有限公司 半导体封装结构及其制造方法

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US5930664A (en) * 1997-07-24 1999-07-27 Taiwan Semiconductor Manufacturing Company, Ltd. Process for preventing corrosion of aluminum bonding pads after passivation/ARC layer etching
US6218732B1 (en) * 1998-09-15 2001-04-17 Texas Instruments Incorporated Copper bond pad process
US6800555B2 (en) * 2000-03-24 2004-10-05 Texas Instruments Incorporated Wire bonding process for copper-metallized integrated circuits
JP2017069381A (ja) * 2015-09-30 2017-04-06 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置の製造方法

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