TWI798805B - Semiconductor package substrate and manufacturing method thereof - Google Patents

Abstract

A semiconductor package substrate and its manufacturing method includes at least a conductive pillar layer and at least a patterned circuit layer. The conductive pillar layer includes a plurality of conductive pillars, and a first insulating material covering the conductive pillars. The conductive pillar has a first end surface and a second end surface, and the first insulating material has a first surface and a second surface. The first end surface of the conductive pillar is exposed on and flush with the first surface of the first insulating material, and the second end surface of the conductive pillar is exposed on the second surface of the first insulating material. The patterned circuit layer includes a patterned circuit layout and a second insulating material covering the patterned circuit layout. The patterned circuit layout is erected on the first end surface of the conductive pillar and the first surface of the first insulating material. The line width at the overlap of the patterned circuit layout and the conductive pillar is equal to or less than the pillar width of the conductive pillar.

Description

Semiconductor package substrate and manufacturing method thereof

The invention relates to a semiconductor package carrier board and a manufacturing method thereof, in particular to a semiconductor package carrier board capable of increasing circuit density and a manufacturing method thereof.

Please refer to Fig. 1A, Fig. 1B and Fig. 1C at the same time, wherein Fig. 1B is a cross-sectional view along line AA' in Fig. 1A, and Fig. 1C is a cross-sectional view along line BB' in Fig. 1A. A conventional semiconductor package substrate 10 includes a substrate 11 , a conductive via 12 , a connection pad 13 and a conductive circuit 14 . The conductive vias 12 and the connection pads 13 are formed on the substrate 11 after being drilled with a drilling device, and then combined with dry film photoresist and electroplating techniques. The conductive circuit 14 is formed by using the connection pad 13 as an alignment reference, using dry film photoresist and electroplating technology.

The above-mentioned conventional semiconductor package substrate 10 may include the following defects, for example, in the process of forming the conductive via 12 and the connection pad 13, the normal situation will be the conductive via 12a and the connection pad 13a in the figure, but some film light When the resistive alignment is shifted, it may cause edge defects 15 such as the conductive via 12b and the connection pad 13b. In addition, in order to avoid dislocation between the conductive circuit 14 and the connection pad 13 and lead to failure of conduction, the size of the connection pad 13 and the line width of the conductive circuit 14 must be larger than the diameter of the conductive via 12 to ensure that the complete conductive via 12 can be covered.

Generally speaking, the diameter of the conductive via 12 is about 50 micrometers (μm), the diameter of the connection pad 13 is about 100 μm, and the distance between adjacent connection pads 13 must be 25 μm to avoid electrical short circuit. Accordingly, it can be known that the distance between adjacent conductive vias 12a, 12b is about 75 μm. The layout of the line will also be limited by this spacing, and the line density cannot be increased.

In addition, the through holes on the substrate can also be formed by laser drilling in addition to the aforementioned drilling equipment. As shown in Figure 2, if the size of the connection pad 13' When the size is not large enough, as mentioned above, it may cause the edge defect 15' of the conductive via 12'.

In response to the problems existing in the above-mentioned conventional technologies, it is necessary to provide a semiconductor packaging substrate and its manufacturing method. In addition to avoiding the fear of misalignment and causing electroplating errors, it can also reduce the distance between the connection pads to increase the circuit density. One of the current important issues.

In view of the above, an object of the present invention is to provide a semiconductor package substrate and a manufacturing method thereof, which can reduce the distance between metal circuits, thereby increasing circuit density.

To achieve the above purpose, the present invention provides a semiconductor packaging substrate, which includes at least one conductive column layer and at least one patterned circuit layer. The conductive pillar layer includes a plurality of pillar-shaped conductive pillars and a first insulating material covering the conductive pillars. The conductive post has a first end surface and a second end surface as electrical connection pads, and the first insulating material has a first surface and a second surface. The first end surface of the conductive column is exposed on the first surface of the first insulating material and is flush with it, and the second end surface of the conductive column is exposed on the second surface of the first insulating material. The patterned circuit layer includes a patterned circuit layout and a second insulating material covering the patterned circuit layout, wherein the patterned circuit layout is erected on the first end surface of the conductive column and the first surface of the first insulating material . Wherein the line width of the overlapped portion of the patterned circuit layout and the conductive column is equal to or smaller than the column width of the conductive column, and part of the surface of the patterned circuit layout is exposed on the surface of the second insulating material.

In one embodiment, the minimum distance between the conductive pillars in the conductive pillar layer is between 25 microns and 50 microns.

In one embodiment, the patterned circuit layout of the patterned circuit layer includes a plurality of conductive bumps that can be connected to electronic components. The electronic components include active components or passive components, and the conductive bumps include metal bumps or solder bumps.

In one embodiment, the second end surface of the conductive pillar of the conductive pillar layer can be connected with a conductive element to be combined with a circuit board, and the conductive element includes a solder ball.

In one embodiment, the first insulating material includes photosensitive dielectric material, non-photosensitive dielectric material, organic dielectric material, ABF, prepreg with or without glass fiber, molding compound, epoxy molding resin, or primer.

In one embodiment, the second insulating material includes photosensitive dielectric material, non-photosensitive dielectric material, organic dielectric material, ABF, prepreg with or without glass fiber, molding compound, epoxy molding resin , Primer coatings, welding resist materials, or photosensitive inks.

To achieve the above purpose, the present invention provides a method for manufacturing a semiconductor package substrate, which includes the following steps. Step 1 is to form a plurality of conductive pillars with a first end surface and a second end surface by patterned exposure, development and electroplating on a temporary substrate, wherein the first end surface and the second end surface are used as electrical connection pads. Step 2 is to form a first insulating material with a first surface and a second surface on the temporary substrate to cover the conductive column, wherein the first end surface of the conductive column is exposed on the first surface of the first insulating material and is flush . Step 3 is to form a patterned circuit layout by patterned exposure, development and electroplating on the first end surface of the conductive pillar and the first surface of the first insulating material, wherein the overlap between the patterned circuit layout and the first end surface of the conductive pillar The line width is equal to or smaller than the column width of the conductive column. Step four is to form a second insulating material on the first surface of the first insulating material to cover the patterned circuit layout, and part of the surface of the patterned circuit layout is exposed on the surface of the second insulating material. Step 5 is removing the temporary substrate, so that the second end surface of the conductive column is exposed on the second surface of the first insulating material.

Based on the above, the present invention discloses a semiconductor packaging substrate and its manufacturing method, which can greatly reduce the line pitch, because there is no need for a conventional connection pad as a bridge between the conductive column and the metal circuit layer, according to this It will be possible to increase the line density. In addition, in terms of manufacturing process, because the process steps of the connection pad are eliminated, the manufacturing process can be simplified, which can effectively increase the manufacturing yield and reduce the cost.

11: Substrate

12, 12', 12a, 12b: Conductive vias

13,13’,13a,13b: connection pads

14: Conductive circuit

15,15': Edge blemishes

10,20: Semiconductor package substrate

21: Conductive column layer

211a, 211b, 211c, 311a, 311b, 411a, 411b: conductive pillars

2111a, 2111b, 2111c, 3111a, 3111b, 4111a, 4111b: first end face

2112a, 2112b, 2112c, 3112a, 3112b, 4112a, 4112b: second end face

212,412: first insulating material

2121, 3121, 4121: first surface

2122, 3122, 4122: second surface

22: Patterned circuit layer

221,321,421: patterned line layout

222,422: Second insulating material

2211, 2221, 4211: surface

312: The first photosensitive dielectric material

313a, 313b, 481a, 481b: straight perforation

322: Second photosensitive dielectric material

323a, 323b, 482a, 482b: concave hole

324,424: Conductive treatment layer

39,49: Temporary substrate

391,491: Metal surfaces

481: The first photosensitive dry film

482: Second photosensitive dry film

51,61: Electronic components

52,62: molding layer

S01~S05, S11~S18, S21~S32: steps

[FIG. 1A] is a schematic top view showing a conventional semiconductor package substrate.

[Fig. 1B] is a schematic cross-sectional view along line AA' of Fig. 1A.

[Fig. 1C] is a schematic cross-sectional view along line BB' of Fig. 1A.

[FIG. 2] is a schematic cross-sectional view showing another conventional semiconductor package substrate.

[FIG. 3A] is a schematic top view showing a semiconductor packaging substrate according to a preferred embodiment of the present invention.

[Fig. 3B] is a sectional view showing a line CC' in Fig. 3A.

[Fig. 3C] is a sectional view showing a line DD' in Fig. 3A.

[FIG. 4] is a flow chart showing a manufacturing method of a semiconductor package substrate according to a preferred embodiment of the present invention.

[FIG. 5A] to [FIG. 5I] are schematic diagrams showing the correspondence and packaging of the semiconductor package substrate corresponding to each step of the first manufacturing method.

[FIG. 6A] to [FIG. 6M] are schematic diagrams showing the correspondence and packaging of the semiconductor package substrate corresponding to each step of the second manufacturing method.

In order to enable those skilled in the art to understand the contents of the present invention and realize the contents of the present invention accordingly, appropriate embodiments and drawings are described below.

Please refer to Fig. 3A, Fig. 3B and Fig. 3C at the same time, wherein Fig. 3B is a sectional view along line CC' in Fig. 3A, and Fig. 3C is a sectional view along DD' line among Fig. 3A. As shown in FIG. 3A and FIG. 3B , a semiconductor package substrate 20 according to a preferred embodiment of the present invention includes a conductive column layer 21 and a patterned circuit layer 22 .

The conductive column layer 21 includes a plurality of conductive columns 211 a , 211 b , 211 c and a first insulating material 212 . The conductive pillars 211a, 211b, 211c are respectively columnar, and respectively have a first end surface 2111a, 2111b, 2111c and a second end surface 2112a, 2112b, 2112c. Wherein at least part of the first end surface and/or the second end surface of the conductive pillar can be used as an electrical connection pad.

The first insulating material 212 covers the conductive columns 211 a , 211 b , 211 c , and the first insulating material 212 has a first surface 2121 and a second surface 2122 . The first end surfaces 2111a, 2111b, 2111c of the conductive pillars 211a, 211b, 211c are respectively exposed on the first surface 2121 of the first insulating material 212, and the first end surfaces 2111a, 2111b, 2111c are flush with the first surface 2121. In addition, the second end surfaces 2112a , 2112b , 21112c of the conductive pillars 211a , 211b , 211c are respectively exposed on the second surface 2122 of the first insulating material 212 .

In addition, the material of the first insulating material 212 includes photosensitive dielectric material, non-photosensitive dielectric material, organic dielectric material, ABF, prepreg with or without glass fiber, molding compound, epoxy molding resin or primer, but not limited thereto.

In this embodiment, the second end surfaces 2112a, 2112b, 21112c of the conductive pillars 211a, 211b, 211c exposed on the second surface 2122 of the first insulating material 212 can be used as electrical connection pads for connecting with other electronic components. Or the circuit board is electrically connected, so the second end surfaces 2112 a , 2112 b , 2112 c can be flush with the second surface 2122 , and of course they can also be retracted into the second surface 2122 of the first insulating material 212 . To further illustrate, the second end surfaces 2112a, 2112b, 2112c of the conductive pillars 211a, 211b, 211c can respectively be connected with a conductive element, and then electrically connected to a circuit board or an electronic element (not shown). The conductive elements are, for example, solder balls.

The patterned circuit layer 22 includes a patterned circuit layout 221 and a second insulating material 222 . The patterned circuit layout 221 is erected (as shown in FIG. 3C ) on the first end surfaces 2111 a , 2111 b , 2111 c of the conductive pillars 211 a , 211 b , 211 c and the first surface 2121 of the first insulating material 212 . The second insulating material 222 covers the patterned circuit layout 221 , and a part of the surface 2211 of the patterned circuit layout 221 is exposed on a surface 2221 of the second insulating material 222 (as shown in FIG. 3B ).

The patterned circuit layout 221 may also include a plurality of conductive bumps, which may include but not limited to metal bumps or solder bumps. The conductive bumps can be used to electrically connect to electronic components, and the electronic components include but not limited to active components or passive components.

The line width of the overlap between the patterned circuit layout 221 and the first end surfaces 2111a, 2111b, 2111c of the conductive pillars 211a, 211b, 211c is equal to or smaller than the column width of the conductive pillars 211a, 211b, 211c. In detail, for example, if the column width of the conductive column 211a is 50 μm, the maximum line width of the patterned circuit layout 221 can also be 50 μm, and the line width of the patterned circuit layout 221 in this embodiment is 25 μm as an example. It is also worth mentioning that since no additional electrical connection pads are required, the minimum distance between the conductive pillars 211a and 211b can be between 25 microns and 50 microns, so that the semiconductor package substrate 20 has a thin line width, It also has the advantage of fine pitch, which can increase the overall circuit density to cope with the increasingly large-scale integrated circuit layout.

Moreover, the material of the conductive pillars 211a, 211b, 211c and the patterned circuit layout 221 is, for example but not limited to, copper, copper alloy or other metals and alloys suitable for electroplating process.

Next, please refer to Figure 4 to illustrate the preferred embodiment of the present invention A method of manufacturing a semiconductor package carrier.

Step S01 is to form a plurality of conductive pillars with a first end surface and a second end surface by patterned exposure, development and electroplating on a temporary substrate. Wherein, the first end surface and the second end surface of the conductive column are used as electrical connection pads.

In step S02 , a first insulating material is formed on the temporary substrate to cover the conductive pillars. Wherein the first insulating material has a first surface and a second surface, and the first end surface of the conductive column is exposed on the first surface of the first insulating material, and the first end surface of the conductive column is flush with the first end surface of the first insulating material. a surface.

Step S03 , forming a patterned circuit layout by patterned exposure, development, and electroplating on the first end surface of the conductive pillar and the first surface of the first insulating material. Wherein, the line width of the lap joint between the patterned circuit layout and the first end surface of the conductive column is equal to or smaller than the column width of the conductive column.

Step S04 , forming a second insulating material on the first surface of the first insulating material to cover the patterned circuit layout. Part of the surface of the patterned circuit layout is exposed on the surface of the second insulating material.

Step S05 is removing the temporary substrate, so that the second end surface of the conductive pillar is exposed on the second surface of the first insulating material, so as to form the semiconductor packaging substrate of the present invention.

The following are two embodiments based on the aforementioned semiconductor package carrier to further illustrate the manufacturing method of the semiconductor package carrier. 5A to 5I are schematic diagrams corresponding to the manufacturing method and packaging of the semiconductor package substrate of the first embodiment, which include steps S11 to S18.

As shown in FIG. 5A , step S11 is to form a first photosensitive dielectric material 312 on a temporary substrate 39 . The temporary substrate 39 has a metal surface 391 . It is worth mentioning that the temporary substrate 39 can be a metal substrate, or a substrate with a metal cladding layer formed on the surface.

As shown in FIG. 5B , step S12 is to form a plurality of straight through holes 313 a and 313 b in the first photosensitive dielectric material 312 by exposure and development.

As shown in FIG. 5C , step S13 is to form conductive pillars 311 a , 311 b in the straight through holes 313 a , 313 b by electroplating.

In this embodiment, the conductive pillars 311a, 311b have a first end surface 3111a, 3111b and a second end surface 3112a, 3112b respectively, wherein the first end surfaces 3111a, 3111b are exposed on the first photosensitive dielectric material 312. A surface 3121 and flush (can be done by leveling). It is also worth mentioning that the first photosensitive dielectric material 312 can be compared with the first insulating material 212 described in the foregoing embodiments.

As shown in FIG. 5D , step S14 is to form a second photosensitive dielectric material 322 on the first photosensitive dielectric material 312 . Specifically, the second photosensitive dielectric material 322 is formed on the first surface 3121 of the first photosensitive dielectric material 312 and the first end surfaces 3111a, 3111b of the conductive pillars 311a, 311b.

As shown in FIG. 5E , step S15 is to form a plurality of concave holes 323 a, 323 b in the second photosensitive dielectric material 322 by exposure and development.

As shown in FIG. 5F , step S16 is to form a conductive processing layer 324 in the concave holes 323 a and 323 b.

As shown in FIG. 5G , in step S17 , a patterned circuit layout 321 is formed by electroplating on the conductive treatment layer 324 in the concave holes 323 a and 323 b. In this embodiment, the patterned circuit layout 321 is formed on the first end surfaces 3111 a , 3111 b of the conductive pillars 311 a , 311 b and the first surface 3121 of the first photosensitive dielectric material 312 . Wherein, the line width of the overlap between the patterned circuit layout 321 and the first end surfaces 3111a, 3111b of the conductive pillars 311a, 311b is equal to or smaller than the pillar width of the conductive pillars 311a, 311b. The patterned circuit layout 321 further includes a plurality of conductive bumps or conductive stubs for electrical connection with electronic components.

As shown in FIG. 5H , step S18 is to remove the temporary substrate 39 so that the second end surfaces 3112 a , 3112 b of the conductive pillars 311 a , 311 b are exposed on the second surface 3122 of the first photosensitive dielectric material 312 . It should be noted that the metal surface 391 is removed at the same time as the temporary substrate 39 .

In other embodiments, after step S17, a photosensitive dielectric material or solder resist material can be formed on the second photosensitive dielectric material 322 and the patterned circuit layout 321, and part of the patterned circuit layout 321 is exposed. surface.

As shown in Figure 5I, it is a schematic diagram of the application of the semiconductor packaging substrate of the present invention to package electronic components, wherein it can be seen that the electronic component 51 is connected to the substrate in a flip-chip manner. The patterned circuit layout 321 is placed on the conductive bumps or conductive stubs, and a molding layer 52 is used to cover the electronic component 51 and the patterned circuit layout 321 exposed on the surface.

Next, FIG. 6A to FIG. 6M are schematic diagrams corresponding to the manufacturing method and packaging of the semiconductor package substrate of the second embodiment, which include steps S21 to S32.

As shown in FIG. 6A , step S21 is to form a first photosensitive dry film 481 on a temporary substrate 49 . The temporary substrate 49 has a metal surface 491 . It is worth mentioning that the temporary substrate 49 can be a metal substrate, or a substrate with a metal cladding layer formed on its surface.

As shown in FIG. 6B , step S22 is to form a plurality of straight perforations 481 a and 481 b in the first photosensitive dry film 481 by exposure and development.

As shown in FIG. 6C , step S23 is to form conductive pillars 411 a , 411 b in the straight through holes 481 a , 481 b by electroplating.

As shown in FIG. 6D , step S24 is to chemically remove the first photosensitive dry film 481 .

As shown in FIG. 6E , in step S25 , the metal surface 491 on the temporary substrate 49 without the conductive pillars 411 a and 411 b is removed by etching.

As shown in FIG. 6F , step S26 is to form a first insulating material 412 on the temporary substrate 49 to cover the conductive pillars 411 a and 411 b.

In this embodiment, the conductive pillars 411a, 411b have a first end surface 4111a, 4111b and a second end surface 4112a, 4112b respectively, wherein the first end surfaces 4111a, 4111b are exposed on a first surface 4121 of the first insulating material 412 And flush with it (can be done by leveling).

As shown in FIG. 6G , in step S27 , a second photosensitive dry film 482 is formed on the first insulating material 412 , and a plurality of concave holes 482 a and 482 b are formed on the second photosensitive dry film 482 by exposure and development.

As shown in FIG. 6H , step S28 is to form a conductive processing layer 424 in the concave holes 482a, 482b.

As shown in FIG. 6I , in step S29 , a patterned circuit layout 421 is formed by electroplating on the conductive treatment layer 424 inside the concave holes 482 a and 482 b. In this embodiment, the patterned circuit layout 421 is formed on the first end surfaces 4111a, 4111b of the conductive pillars 411a, 411b. 4111b and the first surface 4121 of the first insulating material 412 . Wherein, the line width of the overlap between the patterned circuit layout 421 and the first end surfaces 4111a, 4111b of the conductive pillars 411a, 411b is equal to or smaller than the pillar width of the conductive pillars 411a, 411b. The patterned circuit layout 421 further includes a plurality of conductive bumps or conductive stubs for electrical connection with electronic components.

As shown in FIG. 6J , step S30 is to chemically remove the second photosensitive dry film 482 .

As shown in FIG. 6K , step S31 is to form a second insulating material 422 on the first insulating material 412 to cover the patterned circuit layout 421 and expose part of the surface of the patterned circuit layout 421 to the second insulating material 421. One surface 4211.

As shown in FIG. 6L , step S32 is to remove the temporary substrate 49 and the metal surface 491 , so that the second end surfaces 4112 a , 4112 b of the conductive pillars 411 a , 411 b are exposed on the second surface 4122 of the first insulating material 412 .

As shown in FIG. 6M, it is a schematic diagram of the application of the semiconductor packaging substrate of the present invention to package electronic components, wherein it can be seen that the electronic component 61 is connected to the conductive bump or conductive stub of the patterned circuit layout 421 in a flip-chip manner. Furthermore, a molding layer 62 is used to cover the electronic component 61 and the pattern circuit layout 421 exposed on the surface.

It is worth mentioning that in the above two examples, it is mentioned that the photosensitive dielectric material or photosensitive dry film is used to make the semiconductor package carrier, but in other embodiments, the insulating material (photosensitive dielectric material) is also Can be formed by molding techniques. In addition, since the end faces of the conductive pillars are flat and flush with the surface of the insulating material, subsequent manufacturing processes can perform alignment by using the conductive pillars as alignment targets.

To sum up, the semiconductor packaging substrate and its manufacturing method of the present invention utilizes a stacked manufacturing method to form conductive pillars and patterned circuit layout through electroplating, thereby reducing the distance between the conductive pillars. Moreover, using the flat surface of the metal layer (conductive pillar or patterned circuit layout) as an alignment target, the patterned circuit layout can be directly formed on the end surface of the conductive pillar, and the conventional connection for bridging can be omitted. Pad, so the line pitch can also be greatly reduced (for example, reduced from the conventional 75 μm to 25 μm). Accordingly, the semiconductor packaging substrate of the present invention has the beneficial effect of increasing circuit density. In addition, in terms of the semiconductor packaging substrate and its manufacturing method, the manufacturing process can be simplified because the process steps of the connection pad are eliminated. It can effectively increase product yield and reduce costs.

The present invention meets the requirements of an invention patent, and a patent application is filed in accordance with the law. However, what is described above is only a preferred embodiment of the present invention, which cannot limit the scope of the patent application of this case. For those who are familiar with the technology of this case, the equivalent modifications or changes made according to the spirit of the invention of this case should be included in the scope of the following patent application.

20:Semiconductor package substrate

21: Conductive column layer

211a, 211b: conductive pillars

2111a, 2111b: first end face

2112a, 2112b: second end face

212: The first insulating material

2121: first surface

2122: second surface

22: Patterned circuit layer

221: Patterned circuit layout

222: second insulating material

2211,2221: surface

Claims (10)

A semiconductor packaging substrate, comprising: at least one conductive column layer, including a plurality of columnar conductive columns, and a first insulating material covering the conductive column, wherein the conductive column has a first end surface and a first The two end surfaces are used as electrical connection pads, and the first insulating material has a first surface and a second surface, and the first end surface of the conductive post is exposed on the first surface of the first insulating material and is flush with the first surface of the first insulating material. , and the second end surface of the conductive column is exposed on the second surface of the first insulating material; and at least one patterned circuit layer includes a patterned circuit layout and a second layer covering the patterned circuit layout Insulating material, wherein the patterned circuit layout is erected on the first end surface of the conductive column and the first surface of the first insulating material, and the line width of the overlapping part of the patterned circuit layout and the conductive column equal to or less than the column width of the conductive column, and part of the surface of the patterned circuit layout is exposed on a surface of the second insulating material; wherein, the patterned circuit layer is in contact with the conductive column and the first insulating material The surface system is the same plane. The semiconductor package substrate according to claim 1, wherein the minimum distance between the conductive pillars of the conductive pillar layer is between 25 microns and 50 microns. The semiconductor package substrate as claimed in claim 1, wherein the patterned circuit layout of the patterned circuit layer includes a plurality of conductive bumps for connecting electronic components, wherein the electronic components include active components or passive components. The semiconductor package substrate as described in claim 1, wherein the second end surface of the conductive column of the conductive column layer can be connected with a conductive element to be combined with a circuit board, and the conductive element includes a solder ball . The semiconductor packaging substrate as described in Claim 1, wherein the first insulating material includes photosensitive dielectric material, non-photosensitive dielectric material, organic dielectric material, ABF, prepreg with or without glass fiber , molding compound, epoxy molding resin, or primer. The semiconductor packaging substrate as described in Claim 1, wherein the second insulating material includes photosensitive dielectric material, non-photosensitive dielectric material, organic dielectric material, ABF, organic Glass fiber or no glass fiber prepreg, molding compound, epoxy molding resin, primer, solder mask, or photosensitive ink. A method for manufacturing a semiconductor packaging substrate, comprising the following steps: on a temporary substrate, patterned exposure, development and electroplating are used to form a plurality of conductive pillars with a first end face and a second end face, wherein the first end face and the second end face The two end surfaces are respectively used as an electrical connection pad; a first insulating material having a first surface and a second surface is formed on the temporary substrate to cover the conductive column, wherein the first end surface of the conductive column Exposed on the first surface of the first insulating material and flush; on the first end surface of the conductive column and the first surface of the first insulating material, a patterned circuit layout is formed by patterned exposure, development and electroplating , wherein the line width of the overlap between the patterned circuit layout and the first end surface of the conductive pillar is equal to or smaller than the pillar width of the conductive pillar; a second insulating material is formed on the first surface of the first insulating material material to cover the patterned wiring layout, and part of the surface of the patterned wiring layout is exposed on a surface of the second insulating material; and removing the temporary substrate to make the second end surface of the conductive pillar exposed on the second surface of the first insulating material. The method for manufacturing a semiconductor package substrate as claimed in claim 7, wherein the minimum distance between the conductive pillars is between 25 microns and 50 microns. The method for manufacturing a semiconductor package substrate as described in claim 7, wherein the patterned circuit layout includes a plurality of conductive bumps that can be connected to electronic components, wherein the electronic components include active components or passive components, and the conductive The bumps include metal bumps or solder bumps. The method for manufacturing a semiconductor package substrate as claimed in claim 7, wherein the second end surface of the conductive column can be connected with a conductive element to be combined with a circuit board, and the conductive element includes a solder ball.

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