TWI795819B - semiconductor memory, non-volatile memory - Google Patents

Abstract

An embodiment of the present invention can provide a semiconductor memory and a nonvolatile memory capable of suppressing an increase in chip area. According to an embodiment, the semiconductor memory (100) includes: Memory group MG, which is a plurality of memory cells MC containing data that can hold multiple bits in more than three multiple states; a word line WL connected to a plurality of cells; and The first circuit (121) converts one external address received from the external controller (200) into plural internal addresses. The first page size of the page data that the memory group can hold is smaller than the second page size of the input data corresponding to the external address.

Description

semiconductor memory, non-volatile memory

Embodiments of the present invention relate to semiconductor memory and non-volatile memory.

[Related application]

This case enjoys the priority of Japanese Patent Application No. 2020-192523 (filing date: November 19, 2020) and Japanese Patent Application No. 2020-214800 (filing date: December 24, 2020) as the basic applications. This application includes the entire contents of the basic application by referring to this basic application.

As a memory chip mounted in a memory system, there is a semiconductor memory using a NAND flash memory, and a non-volatile memory is known.

One embodiment of the present invention is to provide a semiconductor memory and a non-volatile memory which can suppress the increase of the chip area.

A semiconductor memory of an embodiment comprises: a memory bank comprising a plurality of cells capable of holding data of a plurality of bits in more than three states; a word line connected to the plurality of cells; and a first circuit which will One external address received from the external controller is converted into plural internal addresses.

The first page size of the page data that the memory group can hold is smaller than the second page size of the input data corresponding to the external address.

1: Memory system

2: Main device

30: Semiconductor substrate

32,33,41,53,55: wiring layer

34: block insulating film

35: charge storage layer

36: Tunnel insulating film

37: Semiconductor layer

38: core layer

39: cover layer

40,51,54,56,57: contact plug

52: Gate electrode

100: NAND flash memory

110: I/O circuit

120: control department

121: command user interface circuit

122: Oscillator

123: Sequencer

124: Voltage generating circuit

125: column counter

126: Serial access controller

130: memory cell array

131: row decoder

132: Sense amplifier

133: page buffer

200: memory controller

210: main interface circuit

220: RAM

230: Processor

240: buffer memory

250: memory interface circuit

260: ECC circuit

[ Fig. 1 ] is a block diagram of a memory system including a semiconductor memory according to a first embodiment.

[ Fig. 2 ] is a block diagram of the semiconductor memory of the first embodiment.

[ Fig. 3 ] is a circuit diagram of a cell array included in the semiconductor memory according to the first embodiment.

[ Fig. 4 ] is a cross-sectional view of a cell array included in the semiconductor memory according to the first embodiment.

[ Fig. 5 ] is a block diagram of a sense amplifier and a page buffer included in the semiconductor memory according to the first embodiment.

[FIG. 6] It is a perspective view of the semiconductor memory of 1st Embodiment.

[ Fig. 7] Fig. 7 is a diagram showing the relationship between threshold voltage distribution of cell transistors of the semiconductor memory and distribution of data in the first embodiment.

[ Fig. 8] Fig. 8 is a diagram illustrating a flow of conversion operation between a logical page address and a physical page address in the semiconductor memory according to the first embodiment.

[ Fig. 9 ] is a diagram showing allocation of logical page data to physical pages of the semiconductor memory according to the first embodiment.

[ Fig. 10 ] is a flowchart of the read operation of the semiconductor memory according to the first embodiment.

[ Fig. 11 ] is a flow chart of the read operation of the semiconductor memory according to the first embodiment.

[ Fig. 12] Fig. 12 is a timing chart showing the voltage of the selected word line in the read operation of the logical first page in the semiconductor memory device according to the first embodiment.

[ Fig. 13] Fig. 13 is a time chart showing the voltage of the selected word line in the read operation of the logic page 2 in the semiconductor memory device according to the first embodiment.

[ Fig. 14 ] shows the command sequence of the reading operation of the logical first page of the semiconductor memory according to the first embodiment.

[ Fig. 15 ] is an instruction sequence of a read operation of the logic page 2 of the semiconductor memory according to the first embodiment.

[ Fig. 16 ] is a flow chart of the writing operation of the semiconductor memory according to the first embodiment.

[ Fig. 17 ] is a flow chart of the writing operation of the semiconductor memory according to the first embodiment.

[ Fig. 18 ] shows the command sequence of the full sequential write operation of the semiconductor memory according to the first embodiment.

[ Fig. 19 ] is a table showing allocation of data to each state of the semiconductor memory in the first example of the second embodiment.

[ Fig. 20 ] is a table showing allocation of data to each state of the semiconductor memory in the second example of the second embodiment.

[ Fig. 21 ] is a table showing allocation of data to each state of the semiconductor memory in the third example of the second embodiment.

[ Fig. 22 ] is a table showing allocation of data to each state of the semiconductor memory in the fourth example of the second embodiment.

[ Fig. 23 ] is a table showing allocation of data to each state of the semiconductor memory in the fifth example of the second embodiment.

[ Fig. 24 ] is a table showing allocation of data to each state of the semiconductor memory in the sixth example of the second embodiment.

[ Fig. 25] Fig. 25 is a table showing allocation of data to each state of the semiconductor memory in the seventh example of the second embodiment.

[ Fig. 26] Fig. 26 is an instruction sequence of a read operation of the logical first page of the semiconductor memory according to the first example of the third embodiment.

[ Fig. 27] Fig. 27 is an instruction sequence of a read operation of the logic page 2 of the semiconductor memory according to the first example of the third embodiment.

[ Fig. 28 ] shows the command sequence of the sequential read operation of the semiconductor memory in the second example of the third embodiment.

[FIG. 29] It is a figure which shows the relationship between the threshold voltage distribution of the memory cell transistor of the semiconductor memory of 4th Embodiment, and the distribution of data.

[FIG. 30] It is a figure explaining the flow of the conversion operation of the logical page address and the physical page address of the semiconductor memory of 4th Embodiment.

[ Fig. 31 ] is a diagram showing allocation of logical page data to physical pages of the semiconductor memory according to the fourth embodiment.

[ Fig. 32 ] is a flowchart of the read operation of the semiconductor memory according to the fourth embodiment.

[ Fig. 33 ] is an instruction sequence of a read operation of the logical first page of the semiconductor memory according to the fourth embodiment.

[ Fig. 34 ] is a flowchart of the writing operation of the semiconductor memory according to the fourth embodiment.

[ Fig. 35 ] is a flowchart of the writing operation of the semiconductor memory according to the fourth embodiment.

[ Fig. 36 ] shows the command sequence of the full sequential write operation of the semiconductor memory according to the fourth embodiment.

[ Fig. 37 ] is a block diagram of a sense amplifier and a page buffer included in the semiconductor memory according to the fifth embodiment.

[ Fig. 38] Fig. 38 is a diagram showing the relationship between the threshold voltage distribution of the cell transistor of the semiconductor memory according to the fifth embodiment and the distribution of data.

[FIG. 39] It is a figure explaining the flow of the conversion operation of a logical page address and a physical page address in the semiconductor memory of 5th Embodiment.

[ Fig. 40 ] is a diagram showing allocation of logical page data to physical pages of the semiconductor memory according to the fifth embodiment.

[ Fig. 41 ] is a flowchart of the read operation of the semiconductor memory according to the fifth embodiment.

[ Fig. 42 ] is a flowchart of the read operation of the semiconductor memory according to the fifth embodiment.

[ Fig. 43 ] is a flow chart of the read operation of the semiconductor memory according to the fifth embodiment.

[ Fig. 44 ] shows the command sequence of the reading operation of the logical first page of the semiconductor memory according to the fifth embodiment.

[ Fig. 45 ] shows the command sequence of the reading operation of the logic page 2 of the semiconductor memory according to the fifth embodiment.

[ Fig. 46 ] shows the command sequence of the reading operation of the logic page 3 of the semiconductor memory according to the fifth embodiment.

[ Fig. 47 ] is a flowchart of the writing operation of the semiconductor memory according to the fifth embodiment.

[ Fig. 48 ] is a flowchart of the writing operation of the semiconductor memory according to the fifth embodiment.

[ Fig. 49 ] is a flow chart of the writing operation of the semiconductor memory according to the fifth embodiment.

[ Fig. 50 ] is a command sequence showing the full sequential write operation of the semiconductor memory according to the fifth embodiment.

[ Fig. 51 ] is a table showing allocation of data to each state of the semiconductor memory in the first example of the sixth embodiment.

[ Fig. 52 ] is a table showing allocation of data to each state of the semiconductor memory in the second example of the sixth embodiment.

[ Fig. 53 ] is a table showing allocation of data to each state of the semiconductor memory in the third example of the sixth embodiment.

[ Fig. 54 ] is a table showing allocation of data to each state of the semiconductor memory in the fourth example of the sixth embodiment.

[ Fig. 55 ] is a table showing allocation of data to each state of the semiconductor memory in the fifth example of the sixth embodiment.

[ Fig. 56 ] is a table showing allocation of data to each state of the semiconductor memory in the sixth example of the sixth embodiment.

[ Fig. 57 ] is a table showing allocation of data to each state of the semiconductor memory in the seventh example of the sixth embodiment.

[ Fig. 58 ] is a table showing allocation of data to each state of the semiconductor memory in the eighth example of the sixth embodiment.

[ Fig. 59 ] is a table showing allocation of data to each state of the semiconductor memory in the ninth example of the sixth embodiment.

[ Fig. 60 ] is a table showing allocation of data to each state of the semiconductor memory in the tenth example of the sixth embodiment.

[ Fig. 61 ] is a table showing allocation of data to each state of the semiconductor memory in the eleventh example of the sixth embodiment.

[ Fig. 62 ] is a table showing allocation of data to each state of the semiconductor memory in the twelfth example of the sixth embodiment.

[ Fig. 63 ] is an instruction sequence of a read operation of the logical first page of the semiconductor memory according to the first example of the seventh embodiment.

[ Fig. 64 ] is an instruction sequence of a read operation of the logic page 2 of the semiconductor memory according to the first example of the seventh embodiment.

[ Fig. 65] Fig. 65 is an instruction sequence of a reading operation of the logic page 3 of the semiconductor memory according to the first example of the seventh embodiment.

[ Fig. 66 ] shows the command sequence of the sequential read operation of the semiconductor memory in the second example of the seventh embodiment.

[ Fig. 67] Fig. 67 is a diagram illustrating the flow of conversion operation between logical page addresses and physical page addresses in the semiconductor memory according to the eighth embodiment.

[ Fig. 68 ] is a diagram showing allocation of logical page data to physical pages of the semiconductor memory according to the eighth embodiment.

[ Fig. 69 ] is a block diagram of a sense amplifier and a page buffer included in the semiconductor memory of the first example of the ninth embodiment.

[ Fig. 70 ] is a block diagram of a sense amplifier and a page buffer included in the semiconductor memory according to the second example of the ninth embodiment.

[ Fig. 71] Fig. 71 is a block diagram of a sense amplifier and a page buffer included in a semiconductor memory according to a third example of the ninth embodiment.

[ Fig. 72 ] is a diagram showing allocation of logical page data to physical pages of the semiconductor memory according to the tenth embodiment.

[FIG. 73] It is a table which assigns the data of each state to the semiconductor memory of 10th Embodiment.

[ Fig. 74 ] is a diagram showing allocation of logical page data to physical pages of the semiconductor memory of the first example of the eleventh embodiment.

[ Fig. 75] Fig. 75 is a diagram showing the relationship between the threshold voltage distribution of the cell transistor of the semiconductor memory according to the second example of the eleventh embodiment and the distribution of data.

[ Fig. 76 ] is a diagram showing allocation of logical page data to physical pages of the semiconductor memory of the second example of the eleventh embodiment.

[ Fig. 77] Fig. 77 is a diagram showing the relationship between the threshold voltage distribution of the cell transistor of the semiconductor memory and the distribution of data in the third example of the eleventh embodiment.

[ Fig. 78 ] is a diagram showing allocation of logical page data to physical pages of the semiconductor memory in the third example of the eleventh embodiment.

[ Fig. 79 ] is a diagram showing allocation of logical page data to physical pages of the semiconductor memory according to the twelfth embodiment.

[ Fig. 80 ] is a table showing allocation of data to each state of the semiconductor memory according to the twelfth embodiment.

[ Fig. 81] Fig. 81 is a distribution diagram of the threshold voltage of the cell transistor of the semiconductor memory according to the thirteenth embodiment.

[ Fig. 82 ] is a table showing distribution of data by two memory cell transistors in the semiconductor memory according to the thirteenth embodiment.

[ Fig. 83] Fig. 83 is a diagram showing the relationship between allocation of data to A and B cells and bit values of sectors in the semiconductor memory according to the thirteenth embodiment.

[FIG. 84] It is a figure explaining the flow of the conversion operation of the logical page address and the physical page address of the semiconductor memory of a thirteenth embodiment.

[ Fig. 85 ] is a diagram showing allocation of logical page data to physical pages of the semiconductor memory according to the thirteenth embodiment.

[ Fig. 86 ] is a flowchart of the read operation of the semiconductor memory according to the thirteenth embodiment.

[ Fig. 87 ] is a flowchart of the read operation of the semiconductor memory according to the thirteenth embodiment.

[ Fig. 88 ] is an instruction sequence of a read operation of the logical first page of the semiconductor memory according to the thirteenth embodiment.

[ Fig. 89 ] is a flowchart of the write operation of the semiconductor memory according to the thirteenth embodiment.

[ Fig. 90 ] is a flowchart of the writing operation of the semiconductor memory according to the thirteenth embodiment.

[ Fig. 91 ] shows the command sequence of the full sequential write operation of the semiconductor memory according to the thirteenth embodiment.

[ Fig. 92] Fig. 92 is a graph showing the relationship between the write operation of the semiconductor memory and the threshold voltage distribution of the memory cell transistor in the modified example.

Hereinafter, related embodiments will be described with reference to the drawings. In this description, the same symbols are attached to the constituent elements having the same function and configuration. In addition, each of the embodiments shown below is an example of an apparatus or method for realizing the technical idea of the embodiment, and the technical idea of the embodiment does not limit the material, shape, structure, arrangement, etc. of the constituent parts to those described below. By. The technical idea of the embodiment is to add various changes in the scope of the patent application.

1. The first embodiment

The memory system of the first embodiment will be described. In the following, a NAND type flash memory will be described as an example of a semiconductor memory included in a memory system.

1.1 Composition 1.1.1 The overall composition of the memory system

First, the overall configuration of a memory system including the semiconductor memory of the present embodiment will be described with reference to FIG. 1 . FIG. 1 is a block diagram showing an example of the overall configuration of a memory system. In addition, the configuration of the memory controller shown in FIG. 1 is an example, and the internal bus bar is formed to form a split structure or a hierarchical structure, or to connect additional functional blocks, etc., and other generated Shape. The memory system 1 communicates with the host device 2 , keeps data from the host device 2 according to instructions (commands) from the host device 2 , and outputs the data to the host device 2 . The main device 2 is, for example, a server computer or a personal computer, etc., and performs information processing, and uses the memory system 1 to store data. The memory system 1 is a storage function of a host device 2 that can function as an information processing device. The memory system 1 can be embedded in the main device 2, or can also be connected to the main device 2 via a cable or network. In addition, an information processing system including the memory system 1 and the host device 2 can also be configured.

As shown in Figure 1, the memory system 1 is equipped with: a NAND flash memory 100 (hereinafter also referred to as "memory 100") used as a semiconductor memory, and a memory controller (also known as "external controller") 」) 200. The memory controller 200 and the memory 100 are, for example, a semiconductor memory device that can be constituted by a combination thereof, and examples thereof include a memory card such as an SD ^TM card or an SSD (solid state drive).

The memory 100 is a non-volatile memory having a plurality of memory cell transistors (hereinafter referred to as "memory cells" or simply "cells"), and constituted as non-volatile memory data. In addition, the memory 100 may also be composed of a plurality of NAND flash memories. In this case, the plurality of NAND-type flash memories in the memory 100 and the memory controller 200 may also be connected through a through hole (TSV: Through Silicon Via). In addition, the NAND flash memory can also be a three-dimensional stacked NAND flash memory in which the memory cell transistors are three-dimensionally stacked above the semiconductor substrate, or can also be a memory cell transistor that is planarly arranged on the semiconductor substrate. planar NAND flash memory.

The memory 100 is connected to the memory controller 200 through a memory bus, and operates according to commands from the memory controller 200 . More specifically, the memory 100 communicates with the memory controller 200 such as an 8-bit signal DQ[7:0] and clock signals DQS and DQSn. Signals DQ[7:0] are, for example, data, address and command. The clock signals DQS and DQSn are clock signals used for input and output of the signal DQ, and the clock signal DQSn is an inverted signal of the clock signal DQS.

Moreover, the memory 100 receives from the memory controller 200, for example, a chip enable signal CEn, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, and a read enable signal REn. . Moreover, the memory 100 sends the ready/busy signal RBn to the memory controller 200 .

The chip enable signal CEn is a signal for enabling the memory 100 , for example, is asserted at a Low (“L”) level. The command latch enable signal CLE is a signal indicating that the signal DQ is a command, for example, asserted at a High (“H”) level.

The address latch enable signal ALE is a signal indicating that the signal DQ is an address, for example, it is asserted at the “H” level.

The write enable signal WEn is a signal used to take the received signal into the memory 100, and each time the memory controller 200 receives instructions, addresses, and data, for example, it is asserted at the "L" bit allow. Therefore, the signal DQ is loaded into the memory 100 every time WEn is toggled.

The read enable signal REn is a signal for the memory controller 200 to read data from the memory 100 . The read enable signal REn is, for example, As claimed in the "L" level.

The ready/busy signal RBn is a signal indicating that the memory 100 cannot receive the signal DQ from the memory controller 200 or can receive the signal DQ. For example, when the memory 100 is in a busy state, it is “L”. level.

The memory controller 200 responds to requests (commands) from the host device 2 and instructs the memory 100 to read, write, and erase data. Also, the memory controller 200 manages the memory space (memory area) of the memory 100 .

The memory controller 200 includes: a main interface circuit 210 , a built-in memory (RAM; Random Access Memory) 220 , a processor 230 , a buffer memory 240 , a memory interface circuit 250 and an ECC circuit 260 . In addition, each function of the memory controller 200 can be implemented by a dedicated circuit, or can also be implemented by a processor executing firmware.

The main interface circuit 210 is connected to the main device 2 through the main bus, and is in charge of the communication with the main device 2 . The main interface circuit 210 transfers the request and data received from the main device 2 to the processor 230 and the buffer memory 240 . In the following, the data received from the host device 2 will be described as "user data". The main interface circuit 210 responds to the command of the processor 230 and forwards the user data in the buffer memory 240 to the main device 2 .

RAM 220 is a volatile memory such as DRAM, and is used as a working area of processor 230 . The RAM 220 is firmware for managing the memory 100, or holding various management tables. Moreover, RAM220 temporarily memorizes the look-up table mentioned later.

The processor 230 controls the overall operation of the memory controller 200 . For example, the processor is a CPU (Central Processing Unit) or an MPU (Micro Processing Unit). When the processor 230 receives a request from the host device 2, it performs control according to the request. For example, when the processor 230 receives a write request (including instructions, logical addresses, and user data) from the host device 2 , the processor 230 executes the write operation on the memory 100 through the memory interface circuit 250 . Moreover, when the processor 230 receives a read request (including a command and a logical address) from the host device 2 , it executes a read operation on the memory 100 through the memory interface circuit 250 .

The processor 230 implements wear leveling technology (Wear leveling) etc. to manage various processes of the memory 100 . Furthermore, the processor 230 performs various calculations. For example, the processor 230 performs data encryption or randomization.

Furthermore, the processor 230 determines the storage area (memory area) of the memory 100 for the logical address and user data received from the host device 2 .

More specifically, for example, when the processor 230 receives a write request from the host device 2, it reads out data (hereinafter referred to as an external address) that associates the logical address with the logical page address (also described as an external address) from the memory 100. called "Lookup table"). The logical address is attached to the access request from the host device 2 . A logical page is a unit of data attached to one address of the memory 100 (input data to the memory 100) when the processor 230 controls the write operation and read operation of the memory 100, etc. . The page size of the logical page (also described as "data length", "data volume") is corresponding to the page size attached to 1 The size of the user data in logical addresses. Hereinafter, an address with a logical page is described as a "logical page address" (or an address input from the outside in the memory 100, so it is also described as an "external address"). In the present embodiment, a logical page is different from a page (hereinafter referred to as a "physical page") that is written collectively in the memory 100 in units. The relationship between logical pages and physical pages will be described later. The logical page address corresponds to one logical page and designates a certain part of the memory area of the memory 100 . Therefore, the size of the logical memory area formed by the plurality of logical pages is the same as the size of the memory area of the memory 100 formed by the physical pages.

When the processor 230 receives a write request from the host device 2, it updates the look-up table in the memory controller 200, and assigns one logical page address to one logical address. After re-allocating the logical page address, the processor 230 performs a write operation on the memory 100 . Also, the processor 230 updates the look-up table in the memory 100 at any timing.

Also, for example, upon receiving a read request from the host device 2, the processor 230 converts the logical address into a logical page address using a lookup table, and then executes a read operation on the memory 100.

The buffer memory 240 temporarily stores user data received from the host device 2 and read data received by the memory controller 200 from the memory 100 .

The memory interface circuit 250 is connected to the memory 100 through a memory bus, and is in charge of communication with the memory 100 . The memory interface circuit 250 controls the writing operation, reading operation and erasing operation of the memory 100 according to the control of the processor 230 .

The ECC circuit 260 encodes the user data to generate codewords. The user data is stored in the memory 100 as encoded codewords. Also, the ECC circuit 260 decrypts the code word read from the memory 100 .

In addition, the memory controller 200 may or may not encode the user data. When the memory controller 200 is not encoding, the data written into the memory 100 is consistent with the user data. Also, the ECC circuit 260 can generate one codeword from user data corresponding to one logical page, or can generate one codeword from divided data into which the user data is divided. Furthermore, the ECC circuit 260 can also generate one codeword using user data corresponding to a plurality of logical pages.

Further, the ECC circuit 260 may also be embedded in the memory interface circuit 250 or in the memory 100 .

1.1.2 Composition of NAND flash memory

Next, the configuration of the memory 100 will be described using FIG. 2 . FIG. 2 is a block diagram showing an example of the internal configuration of the memory 100 according to this embodiment. In addition, in FIG. 2, a part of the connection between each block is shown by the arrow line, but the connection between each block is not limited to this.

As shown in FIG. 2 , the memory 100 includes an I/O circuit 110 , a control unit 120 , a grid array 130 , a row decoder 131 , a sense amplifier 132 and a page buffer 133 . The memory 100 is, for example, formed on a semiconductor substrate (silicon substrate) and chipped.

The I/O circuit 110 is controlled by the memory controller 200 Signal input and output. More specifically, the I/O circuit 110 is for example receiving the signal DQ (data DAT, logical page address, command CMD) and various control signals (signals CEn, CLE, ALE, WEn and REn) received from the memory controller 200. sent to the control unit 120. Furthermore, the I/O circuit 110 sends the data DAT received from the control unit 120 to the memory controller 200 .

The control unit 120 controls the operation of the memory 100 according to the command CMD received from the memory controller 200 via the I/O circuit 110 . Specifically, when receiving the write command, the control unit 120 controls to write the received write data DAT into the physical page of the memory grid array 130 . Moreover, when the control unit 120 receives the read command, it controls to read the data DAT from the memory grid array 130 and output it to the memory controller 200 through the I/O circuit 110 .

The control unit 120 includes: a command user interface circuit 121 , an oscillator 122 , a sequencer 123 , a voltage generating circuit 124 , a column counter 125 and a serial access controller 126 .

The command user interface circuit 121 receives the command CMD and the logical page address from the I/O circuit 110 . The command user interface circuit 121 sends the received command CMD to the sequencer 123 . In addition, the instruction user interface circuit 121 converts the received logical page address into an address ADD corresponding to the physical page (hereinafter also referred to as "physical page address" or "internal address"), and sends it to the sequencer 123. In this embodiment, since the page size of the logical page is larger than the page size of the physical page, a plurality of physical pages are allocated to the data of one logical page. Therefore, the command user interface circuit 121 converts one logical page address into a corresponding plurality of physical page addresses ADD, sent to the sequencer 123. In addition, the sequencer 123 can also convert the logical page address into the physical page address ADD.

The oscillator 122 is a circuit that generates a clock signal. The clock signal generated by the oscillator 122 is supplied to each component including the sequencer 123 . The sequencer 123 is a state machine driven by a clock signal supplied from the oscillator 122 .

The sequencer 123 controls the overall operation of the memory 100 . For example, the sequencer 123 controls the instruction user interface circuit 121, the oscillator 122, the voltage generating circuit 124, the column counter 125, and the serial access controller 126, as well as the row decoder 131, the sense amplifier 132, and the page Buffer 133. The sequencer 123 controls access to the memory cell array 130 (writing operation, reading operation, erasing operation, etc.). The sequencer 123 sends, for example, a control signal for controlling operation timing and the like to the voltage generating circuit 124 and the column counter 125 according to the command CMD received from the command user interface circuit 121 . Furthermore, the sequencer 123 supplies the row address RA included in the physical page address ADD received from the instruction user interface circuit 121 to the row decoder 131 . The row address RA is an address for selecting a wiring (word line, etc.) arranged in a row direction in the cell array 130 . Further, the sequencer 123 supplies the column address CA included in the physical page address ADD received from the instruction user interface circuit 121 to the column counter 125 . The column address CA is an address for selecting wirings (bit lines, etc.) arranged in the column direction in the cell array 130 .

The voltage generation circuit 124 generates a voltage according to the control of the sequencer 123 and supplies it to the row decoder 131 and the sense amplifier 132 and the like.

The column counter 125 sends the column address CA to the page buffer 133 during a write operation or a read operation. The column counter 125 starts with the column address CA supplied from the sequencer 123 and sequentially advances (counts up) the column address CA according to the control signal supplied from the serial access controller 126 .

The serial access controller 126 controls the transmission and reception of the data DAT with the page buffer 133 . More specifically, the serial access controller 126 is connected to the page buffer 133 via a data bus. The serial access controller 126 sends the data DAT received from the I/O circuit 110 (for example, 8-bit serial data corresponding to the 8-bit signal DQ) to the page buffer 133 during the write operation. In addition, the serial access controller 126 sends the data DAT (serial data) received from the page buffer 133 to the I/O circuit 110 during the read operation.

The memory cell array 130 includes a plurality of blocks BLK (BLK0, BLK1, . . . ) including nonvolatile memory cell transistors (hereinafter also referred to as “cells”) corresponding to rows and columns. Each block BLK includes a plurality of string units SU. In the example of FIG. 2 , the block BLK includes four string units SU0 , SU1 , SU2 and SU3 . Furthermore, each string unit SU includes a plurality of NAND strings NS. In addition, the number of blocks BLK in the memory cell array 130 and the number of string units SU in the block BLK can be designed arbitrarily. Details about the grid array 130 will be described later.

The row decoder 131 is connected to wirings (for example, word lines and select gate lines) arranged along the row direction in each block BLK. The row decoder 131 converts the row bits during the write operation, read operation and erase operation. The address RA is decoded, and a voltage is applied to the wiring of the selected block BLK.

The sense amplifier 132 transfers the data stored in the page buffer 133 to the memory cell transistor during the writing operation. In addition, the sense amplifier 132 determines whether the data read from the memory grid array 130 is "0" or "1" during the read operation. The sense amplifier 132 transfers the acquired data to the page buffer 133 . The data stored in the page buffer 133 is output to the memory controller 200 through the serial access controller 126 and the I/O circuit 110 .

The page buffer 133 is a buffer for temporarily storing data DAT received from the memory controller 200 or temporarily storing data read from the memory grid array 130 . Page buffer 133 includes a plurality of latch circuits. The page buffer 133 sequentially stores the data DAT received from the serial access controller 126 in the latch circuit corresponding to the column address CA received from the column counter 125 during the writing operation. In addition, the page buffer 133 sequentially sends the data stored in the latch circuit corresponding to the column address CA received from the column counter 125 to the serial access controller 126 during the read operation.

Hereinafter, circuits other than the grid array 130 (the control unit 120 , the row decoder 131 , the sense amplifier 132 , and the page buffer 133 , etc.) are collectively described as “peripheral circuits”.

1.1.3 The circuit configuration of memory grid array

Next, an example of the circuit configuration of the memory grid array 130 will be described using FIG. 3 . The example in FIG. 3 is shown by extracting one block BLK among the plurality of blocks BLK included in the grid array 130 .

As shown in FIG. 3 , the block BLK includes, for example, four string units SU0 - SU3 . Each string unit SU includes a plurality of NAND strings NS.

The plurality of NAND strings NS are respectively associated with the bit lines BL0 ˜BL(k−1) (k is an integer greater than or equal to 2). Each NAND string NS includes, for example, memory cell transistors MC0 - MC7 and select transistors ST1 and ST2 . Hereinafter, when the bit lines BL0 to BL(k−1) are not limited, the bit line BL is simply referred to as the bit line. When the memory cell transistors MC0-MC7 are not limited, they are referred to as the memory cell transistor MC for short.

The memory grid transistor MC includes a control gate and a charge storage layer, and stores data in a non-volatile manner. Each of the selection transistors ST1 and ST2 is used to select the string unit SU in various operations.

In addition, the memory cell transistor MC can be a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) type in which an insulating layer is used in the charge storage layer, or an FG (Floating Gate) type in which a conductive layer is used in the charge storage layer. . Hereinafter, in this embodiment, the MONOS type will be described as an example.

In each NAND string NS, the drain of the selection transistor ST1 is connected to the associated bit line BL, and the source of the selection transistor ST1 is connected to one end of the series memory cell transistors MC0-MC7. In the same block BLK, the gates of the selection transistors ST1 in the string units SU0 - SU3 are commonly connected to the respective selection gate lines SGD0 - SGD3 . The select gate lines SGD0 ˜ SGD3 are connected to the row decoder 131 .

In each NAND string NS, the drain of the select transistor ST2 is connected to the other end of the series memory cell transistors MC0 - MC7 . exist In the same block BLK, the source of the selection transistor ST2 is commonly connected to the source line SL, and the gate of the selection transistor ST2 is commonly connected to the selection gate line SGS. The select gate line SGS is connected to the row decoder 131 .

The bit lines BL are commonly connected to one NAND string NS included in each of the string units SU0 to SU3 located in each block BLK. The source lines SL are, for example, connected in common between a plurality of blocks BLK.

Hereinafter, a set of a plurality of memory cell transistors MC connected to a common word line WL in one string unit SU is described as a "memory group MG". The memory cell transistors MC included in one memory group MG are respectively associated with the bit lines BL0˜BL(k−1). Therefore, the number of memory cell transistors MC included in one memory group MG is k. For example, the memory capacity of the memory group MG including k memory cell transistors MC each storing 1-bit data is defined as 1 page of data (page size) of a physical page. The memory group MG can have a memory capacity of more than 2 pages of data in a physical page according to the number of bits of data stored in the memory cell transistor MC. Hereinafter, in this embodiment, the case where 3-bit data can be stored in the memory cell transistor MC, that is, the case where the memory group MG has the memory capacity of 3 pages of data in a physical page will be described.

In addition, the circuit configuration of the memory grid array 130 is not limited to the configuration described above. For example, the numbers of memory cell transistors MC and selection transistors ST1 and ST2 contained in each NAND string NS can be designed to be arbitrary numbers respectively. The number of string units SU included in each block BLK can be designed to be arbitrary.

1.1.4 Sectional structure of memory grid array

Next, the cross-sectional configuration of the cell array 130 will be described using FIG. 4 . The example in FIG. 4 shows a cross section of one NAND string NS. In addition, in the example of FIG. 4 , in order to simplify the description, one transistor used for the sense amplifier 132 is shown on the semiconductor substrate 30 . Also, in the example of FIG. 4, a part of the interlayer insulating film is omitted.

As shown in FIG. 4, on the semiconductor substrate 30, a transistor used for the sense amplifier 132 is provided. That is, a sense amplifier 132 is disposed between the semiconductor substrate 30 and the memory cell array 130 . In addition, other peripheral circuits such as a row decoder 131 or a page buffer 133 may also be provided between the semiconductor substrate 30 and the memory grid array 130 . The structure in which peripheral circuits are provided under the cell array 130 is also described as a CUA (CMOS Under Allay) structure. In this embodiment, the case where the sense amplifier 132 and the page buffer 133 are provided between the semiconductor substrate 30 and the memory cell array 130 in the CUA structure will be described. In addition, the memory 100 may also have a structure in which an array chip provided with the memory cell array 130 and a circuit chip provided with peripheral circuits are bonded together.

First, the structure of the grid array 130 will be described. Wiring layers 32 that function as source lines SL are formed extending in the X direction substantially parallel to the semiconductor substrate 30 and in the Y direction intersecting the X direction. The wiring layer 32 is made of conductive materials, such as semiconductor materials added with impurities, or metal materials.

On the top of the wiring layer 32, as the selection gate line SGS, the word lines WL0~WL7 and the selection gate line SGD function, extending in the X direction For example, 10 wiring layers 33 are separated and sequentially arranged in the Z direction substantially perpendicular to the semiconductor substrate 30 via an interlayer insulating film not shown.

The wiring layer 33 is made of a conductive material, for example, a semiconductor material or a metal material to which impurities are added. For example, a laminated structure of titanium nitride (TiN)/tungsten (W) can be used as the wiring layer 33 . TiN has, for example, a barrier layer for preventing the reaction between W and SiO ₂ when W is formed into a film by CVD (chemical vapor deposition), or an adhesion layer for improving the adhesion of W. function.

Furthermore, a memory pillar MP whose bottom surface reaches the wiring layer 32 is formed penetrating through the wiring layer 33 of 10 layers. 1 memory pillar MP will correspond to 1 NAND string NS. The memory pillar MP includes a block insulating film 34 , a charge storage layer 35 , a tunnel insulating film 36 , a semiconductor layer 37 , a core layer 38 and a capping layer 39 .

More specifically, a hole corresponding to the memory pillar MP is formed so that the bottom surface reaches the wiring layer 32 through the wiring layer 33 . On the side of the hole, a block insulating film 34 , a charge storage layer 35 , and a tunnel insulating film 36 are stacked in this order. Furthermore, the semiconductor layer 37 is formed so that the side surface is in contact with the tunnel insulating film 36 and the bottom surface is in contact with the wiring layer 32 . The semiconductor layer 37 is a region where channels of the memory cell transistor MC and the select transistors ST1 and ST2 are formed. Therefore, the semiconductor layer 37 functions as a signal line connecting the current path of the selection transistor ST2, the memory cell transistors MC0-MC7, and the selection transistor ST1. Inside the semiconductor layer 37 is a core layer 38 . Furthermore, a cap layer 39 is formed on the semiconductor layer 37 and the core layer 38 so that its side surface is in contact with the tunnel insulating film 36 .

For the block insulating film 34 , the tunnel insulating film 36 and the core layer 38 , for example, SiO ₂ can be used. For the charge storage layer 35, for example, a silicon nitride film (SiN) can be used. For example, polysilicon can be used for the semiconductor layer 37 and the cap layer 39 .

Contact plugs 40 are formed on the cap layer 39 . A wiring layer 41 extending in the Y direction is formed on the contact plug 40 and functions as a bit line BL. The contact plug 40 and the wiring layer 41 are made of a conductive material, for example, a stacked structure of titanium (Ti)/TiN/W, or copper (Cu).

In addition, in the example of FIG. 4, the wiring layer 33 which functions as the selection gate line SGD and SGS is each provided in one layer, but a plurality of layers may be provided.

The memory cell transistors MC0-MC7 are respectively formed by the memory pillar MP and the 8-layer wiring layer 33 which functions as the word lines WL0-WL7 respectively. Similarly, the selection transistors ST1 and ST2 are formed by the memory pillar MP and the two-layer wiring layer 33 functioning as the selection gate lines SGD and SGS respectively.

Next, briefly describe the transistors included in the sense amplifier 132 .

On the semiconductor substrate 30, for example, a transistor included in the sense amplifier 132 is provided. For example, two wiring layers 53 and 55 are connected to the source and drain of the transistor through contact plugs 51 and 54 . The gate electrode 52 of the transistor is connected to the wiring layer 53 via a contact plug 51 .

On the wiring layer 55 corresponding to the source or the drain of the transistor, there is formed a contact plug 56 whose upper surface is positioned above the uppermost wiring layer 33 . The contact plug 56 is not electrically connected to the wiring Layers 32 and 33. A contact plug 57 is formed on the contact plug 56 . The contact plug 56 is connected to the wiring layer 41 via a contact plug 57 . The contact plugs 51, 54, 56 and 57, the gate electrode 52 and the wiring layers 53 and 55 are made of conductive material.

1.1.5 Configuration of Sense Amplifier and Page Buffer

Next, an example of the configuration of the sense amplifier 132 and the page buffer 133 will be described with reference to FIGS. 5 and 6 . FIG. 5 is a block diagram of the sense amplifier 132 and the page buffer 133 . Fig. 6 is a perspective view showing the structure of the CUA.

As shown in FIG. 5, in the present embodiment, the sequencer 123 divides the plurality of memory grid transistors MC in one memory group MG into two of the first grid area and the second grid area. control. Similarly, the sequencer 123 is controlled by dividing the sense amplifier 132 and the page buffer 133 into two corresponding to the first grid area and the second grid area. For example, memory cell transistor MC included in the first cell area is associated with bit lines BL0 ˜BL(i−1) (i is an integer greater than 1 and less than k). The memory cell transistor MC contained in the second cell area is associated with the bit lines BL(i)~BL(k-1). In addition, it is desirable that the number of memory cell transistors MC included in the first cell area is the same as the number of memory cell transistors MC included in the second cell area. For example, when the number of memory cell transistors MC contained in the first cell area is the same as the number of memory cell transistors MC contained in the second cell area, i and k are in the relationship of i=k/2 .

The sense amplifier 132 includes a plurality of sense circuits SA provided for each bit line BL. The sensing circuit SA reads data from the memory grid transistor MC connected to the corresponding bit line BL during the read operation, and judges Set data as "0" or "1". In addition, the sensing circuit SA applies a voltage to the bit line BL according to the writing data during the writing operation. The sensing circuit SA may also include a latch circuit for temporarily memorizing read data or write data. Hereinafter, the sensing circuit connected to the bit line BL corresponding to the memory cell transistor MC contained in the first cell area is described as "sensing circuit SA1". Also, the sensing circuit connected to the bit line BL corresponding to the memory cell transistor MC included in the second cell area is described as "sensing circuit SA2".

The page buffer 133 corresponds to one sensing circuit SA, and includes latch circuits ADL, BDL, and XDL. The sensing circuit SA and the latch circuits ADL, BDL and XDL are connected to each other. In other words, the sensing circuit SA and the latch circuits ADL, BDL, and XDL are connected to transmit and receive data. The latch circuits ADL, BDL and XDL temporarily store the data DAT. For example, during the read operation, the read data determined by the sense circuit SA is transferred from the sense circuit SA to any one of the latch circuits ADL, BDL, and XDL.

The latch circuit XDL is connected to the serial access controller 126 via a data bus, and is used for data transmission and reception between the serial access controller 126 and the sense amplifier 132 .

In addition, the configuration of the page buffer 133 is not limited thereto, and various changes can be made. For example, the number of latch circuits included in the page buffer 133 can be designed according to the number of bits of data held by one memory cell transistor MC.

In the following, the latch circuit corresponding to the sensing circuit SA1 ADL, BDL, and XDL are described as "latch circuit ADL1", "latch circuit BDL1", and "latch circuit XDL1". Also, the latch circuits ADL, BDL, and XDL corresponding to the sensing circuit SA2 are described as "latch circuit ADL2", "latch circuit BDL2", and "latch circuit XDL2". Also, a combination of the sense circuit SA, latch circuits ADL, BDL, and XDL corresponding to one bit line BL is described as a "sense amplifier unit SAU". Furthermore, the combination of the sensing circuit SA1, the latch circuits ADL1, BDL1, and XDL1 is described as "sense amplifier unit SAU1", and the combination of the sensing circuit SA2, latch circuits ADL2, BDL2, and XDL2 is described as "sense amplifier unit SAU1". Unit SAU2".

In this embodiment, a plurality of sense amplifier units SAU1 corresponding to the first grid area are arranged in one area, and a plurality of sense amplifier units SAU2 corresponding to the second grid area are aggregated in another area. configured for the region.

Next, the relationship between the configuration of the memory group MG and the configuration of the sense amplifier unit SAU will be described.

As shown in FIG. 6 , in the case of the CUA structure, the memory grid array 130 is disposed above the sense amplifier 132 and the page buffer 133 in the Z direction. For example, in the memory cell array 130, a plurality of memory cell transistors MC included in the memory group MG are arranged in an X direction. Also, a plurality of blocks BLK are arranged in a row in the Y direction. In the sense amplifier 132 and the page buffer 133, in the sense amplifier unit SAU corresponding to one memory cell transistor MC, the sense circuit SA, the latch circuits ADL, BDL, and XDL are arranged in the Y direction and configuration. In addition, it is difficult to integrate the sensing circuit SA, The latch circuits ADL, BDL, and XDL are arranged in one stage, or may be arranged in plural stages.

1.2 Threshold voltage distribution of memory cell transistors

Next, the obtained threshold voltage distribution related to the memory cell transistor MC will be described using FIG. 7 . FIG. 7 is a graph showing the relationship between the threshold voltage distribution of memory cell transistor MC and the distribution of data. Hereinafter, in this embodiment, the case of a TLC (Triple Level Cell) (or also referred to as "3bit/Cell") which can hold 8-value (3-bit) data in the memory cell transistor MC will be described. However, the data that the memory cell transistor MC can hold is not limited to 8 values.

As shown in FIG. 7, the threshold voltage of each memory cell transistor MC takes a value included in any one of discrete, for example, eight distributions. Hereinafter, the eight distributions are described as "S0" state (or also described as critical value area), "S1" state, "S2" state, "S3" state, and "S4" in order of lower threshold voltage state, "S5" state, "S6" state and "S7" state.

The "S0" state is, for example, a state corresponding to data erasure. Moreover, the states "S1"-"S7" correspond to the states in which charges are injected into the charge storage layer and data is written. In the write operation, verify voltages corresponding to the respective threshold voltage distributions are V1 to V7. Therefore, the voltage values are in the relationship of V1<V2<V3<V4<V5<V6<V7<Vread. The voltages V1~V7 are applied to the word line WL (hereinafter also referred to as "selected word") connected to the memory cell transistor MC to be read during the read operation. Line WL") voltage. The voltage Vread is a voltage applied to a word line WL (hereinafter also referred to as “non-selected word line WL”) connected to a memory cell transistor MC not to be read during a read operation. When the voltage Vread is applied to the gate of the memory cell transistor MC, it is set to an ON state regardless of the data held.

More specifically, the threshold voltage included in the "S0" state is the sub-full voltage V1. The threshold voltage included in the "S1" state is equal to or greater than the voltage V1 and less than the full voltage V2. The threshold voltage included in the "S2" state is above the voltage V2 and below the voltage V3. The threshold voltage included in the "S3" state is equal to or greater than the voltage V3 and less than the full voltage V4. The threshold voltage included in the "S4" state is equal to or greater than the voltage V4 and less than the full voltage V5. The threshold voltage included in the "S5" state is equal to or greater than the voltage V5 and less than the full voltage V6. The threshold voltage included in the "S6" state is equal to or greater than the voltage V6 and less than the full voltage V7. Furthermore, the threshold voltage included in the "S7" state is equal to or greater than the voltage V7 and less than the full voltage Vread.

In addition, the set value of the verification voltage and the set value of the read voltage corresponding to each state may be the same or different. In the following, for simplification of the description, the case where the verify voltage and the read voltage have the same set value will be described.

Hereinafter, the read operations corresponding to the states "S1"-"S7" are described as read operations R1, R2, R3, R4, R5, R6, and R7, respectively. The readout operation R1 is to determine whether the threshold voltage of the memory cell transistor MC is less than the full voltage V1. The readout operation R2 is to determine whether the threshold voltage of the memory cell transistor MC is less than the full voltage V2. Following, similarly, the read operation R3-R7 respectively determine whether the threshold voltage of the memory cell transistor MC is less than the full voltage V3-V7.

Each memory cell transistor MC can take 8 kinds of states by having any one of 8 threshold voltage distributions. By distributing these states as "000"~"111" in binary system, each memory cell transistor MC can hold 3-bit data. Hereinafter, the data of 3 bits are respectively described as Lower bit, Middle bit and Upper bit. A set of Lower bits to be written (read) together into the memory group MG is described as a Lower page, a set of Middle bits is described as a Middle page, and a set of Upper bits is described as an Upper page.

In the example of FIG. 7 , for memory cell transistors MC included in each threshold voltage distribution, data is allocated as "Upper bit/Middle bit/Lower bit" as follows. For each state, data is allocated in such a manner that 1-bit data is changed between two adjacent states (states) in Gray code.

"S0" status: "111" data

"S1" status: "101" data

"S2" status: "001" data

"S3" status: "011" data

"S4" status: "010" data

"S5" status: "110" information

"S6" status: "100" data

"S7" status: "000" data

When reading the data allocated in this way, the Lower page is Determined by the readout action R4. The Middle page is determined by the read operations R1, R3 and R6. The upper page is determined by the read operations R2, R5 and R7. That is, the values of the Lower bit, the Middle bit, and the Upper bit are determined by 1, 3, and 3 read operations, respectively. In other words, the number of voltages that will be used to determine the boundary of the bit value (hereinafter referred to as "the number of boundaries") is 1, 3, and 3 for the Lower bit, Middle bit, and Upper bit . Hereinafter, the allocation of this data is described as "1-3-3 code" by using the boundary number.

In this embodiment, in the allocation of data to Upper bits, Middle bits, and Lower bits, one bit has a boundary number of one. Furthermore, the level number of bits whose level number is not 1 is coded in such a manner that the maximum value of the level number becomes the minimum. For example, in the case of TLC, that is, in the case of 3bit/Cell, the total number of boundaries is 7, so when the remaining 2 bits are used to share the remaining 6 boundaries, the maximum value of the number of boundaries is formed to be the smallest. The case where the level number of meta is set to 3.

In addition, the allocation of data in the states "S0"~"S7" is not limited to 1-3-3 encoding.

1.3 Conversion action of logical page address and physical page address

Next, an example of conversion operations between logical page addresses and physical page addresses will be described with reference to FIGS. 8 and 9 . FIG. 8 is a diagram illustrating a flow of conversion operations between logical page addresses and physical page addresses. FIG. 9 is a diagram showing allocation of logical page data to physical pages.

In this embodiment, the logical page of 2 pages will be described The case where the input data is allocated to 3 physical pages (that is, one memory group MG capable of storing 3 pages of data).

As shown in FIG. 8, for example, if the memory controller 200 receives a write request from the host device 2, it allocates two logical page bits corresponding to the received two logical addresses "00001" and "00002". address "90001" and "90002". Hereinafter, the allocated two logical pages are described as "1st logical page" and "2nd logical page". In the example of FIG. 8 , the logical page 1 corresponds to the logical page address “90001”, and the logical page 2 corresponds to the logical page address “90002”.

If the instruction user interface circuit 121 receives a write command including a logical page address of two pages and a logical page from the memory controller 200, the logical pages of two pages are divided into two pages according to a preset matching (mapping). The address is converted into a physical page address divided into three pages. In this embodiment, the instruction user interface circuit 121 converts the logical page address of the first logical page into the first cell area of the Lower page and the physical page address of the Middle page. In addition, the instruction user interface circuit 121 converts the logical page address of the second logical page into the second cell area of the Lower page and the physical page address of the Upper page.

The page size of a logical page of 1 page is larger than the page size of a physical page of 1 page. However, the data volume (data length) of a logical page divided into 2 pages is the same as the data volume (data length) of a physical page divided into 3 pages.

In this embodiment, the page size of a logical page of one page is set to m (m is an integer greater than or equal to 1), and the number of logical pages to be written (that is, the number of logical page addresses included in the command) is set to is a (a is an integer of 1 or greater). Also, assuming that the page size of a physical page of one page is n (n is an integer smaller than m), the written The number of physical pages (that is, the number of bits of data that can be stored by the memory cell transistor MC) is set to b (b is an integer greater than a). Therefore, the physical page of one page, that is, the page size n of one memory group MG is represented by n=m×a/b. Also, the page sizes of the first grid area and the second grid area are represented by n/2, respectively. In this embodiment, since a=2 and b=3, the page size of a physical page is n=m×2/3. For example, when the page size of the logical page is 16 [kB], the page size of the physical page is n=16×2/3=10.67 [kB]. In this case, the number of memory cell transistors MC that can realize the page size n=10.67[kB] of one physical page is an integer equal to or greater than the integer value rounded up from the decimal point of 10.67×1024 value. That is, the number of memory cell transistors MC is an integer value equal to or greater than an integer value obtained by rounding up the decimal point of the page size of one physical page.

In this embodiment, the page size of the physical page is smaller than the page size of the logical page. In such a case, if the number of string units SU in the logical block BLK constituted by logical pages is the same as the number of string units SU in the physical block BLK constituted by physical pages (that is, the block BLK of the memory grid array 130) If the number of string units SU is the same, the block size (memory capacity) of the physical block BLK is smaller than the block size (memory capacity) of the logical block BLK. Therefore, the number of string units SU in the physical block BLK can be increased from 4 to 6, for example, in a manner that the memory capacity of the logical block BLK is the same as that of the physical block BLK. Alternatively, the number of physical blocks BLK is set to be greater than the number of logical blocks BLK.

For example, the sequencer 123 writes the data of the logical first page according to the physical page address converted in the instruction user interface circuit 121 To the first grid area of the Lower page and the first and second grid areas of the Middle page of one memory group MG, write the data of the second logical page to the second grid area of the Lower page and the upper page Areas 1 and 2.

Next, the arrangement of the logical page data of one memory group MG will be described in detail.

As shown in FIG. 9 , the data on the first logical page and the second logical page are divided into three, and the first data is set as the first cluster to the third cluster. For example, the sequencer 123 writes the first cluster of the first logical page into the first grid area of the Lower page, writes the second cluster of the first logical page into the second grid area of the Middle page, and writes the second cluster of the logical first page into the second grid area of the Middle page. The 3rd cluster of 1 page is written to the 1st cell area of the Middle page. Also, the sequencer 123 writes the first cluster of the second logical page into the second grid area of the Lower page, writes the second cluster of the second logical page into the first grid area of the Upper page, and writes the second cluster of the logical second page into the first grid area of the Upper page, and writes the second cluster of the logical second page into the first grid area of the Upper page. The 3rd cluster of the 2nd page is written to the 2nd cell area of the Upper page.

1.4 Read Action

Next, the reading operation will be described. In the read operation of this embodiment, when the memory 100 receives a read command based on a logical page from the memory controller 200, data is read from the corresponding plurality of physical pages, and the read data are synthesized. Data output as logical pages.

In this embodiment, the read operation is different when the logical page to be read is the first logical page and when it is the second logical page. When the logical page is the first logical page, the physical pages to be read are the Lower page (1st cell area) and Middle page (1st cell area and 2nd cell area) area). In this case, the memory 100 sends (outputs) the data of the first grid area of the Lower page and the data of the first grid area and the second grid area of the Middle page to the memory controller 200 . On the other hand, when the logical page is the second logical page, the physical pages to be read are the Lower page (the second grid area) and the Upper page (the first grid area and the second grid area). In this case, the memory 100 sends (outputs) the data of the second grid area of the Lower page and the data of the first grid area and the second grid area of the Upper page to the memory controller 200 .

1.4.1 Flow of read operation

First, the flow of the read operation of the memory 100 will be described with reference to FIGS. 10 and 11 . 10 and 11 are flowcharts of the read operation.

As shown in FIG. 10 and FIG. 11 , the memory 100 receives a read command of the logical 1st page or the logical 2nd page from the memory controller 200 (step S1 ). After the command user interface circuit 121 converts the logical page address into a physical page address, it sends the received command and the converted physical page address to the sequencer 123 .

When the logical page address is the logical page address of the first logical page (step S2_Yes), the sequencer 123 first executes the read operation of the lower page (step S3). More specifically, the sequencer 123 performs a readout operation R4 corresponding to the readout voltage V4.

The sequencer 123 determines the data of the Lower page according to the result of the read operation R4 (step S4).

The sequencer 123 reads out the sense circuits SA1 and SA2 The data of the lower page are transferred to the latch circuits ADL1 and ADL2 respectively (step S5).

The sequencer 123 transfers the data of the latch circuit ADL1 (the data of the first cluster of the first logical page) to the latch circuit XDL1 (step S6).

The sequencer 123 sets the head address of the latch circuit XDL1 in the column counter 125, and sets the head address of the latch circuit XDL1 as the column address CA (step S7). The serial access controller 126 sequentially receives data from the head address of the latch circuit XDL1 according to the column address CA counted by the column counter 125 , and transfers the data to the I/O circuit 110 . The I/O circuit 110 starts to send (output) the data of the latch circuit XDL1 to the memory controller 200 .

The sequencer 123 executes the read operation of the Middle page in parallel with the output of the data from the latch circuit XDL1 (step S8). More specifically, the sequencer 123 executes the readout operation R1 corresponding to the readout voltage V1 , the readout operation R3 corresponding to the readout voltage V3 , and the readout operation R6 corresponding to the readout voltage V6 . In addition, the order of the readout operations R1, R3, and R6 can be set arbitrarily.

The sequencer 123 determines the data of the Middle page according to the results of the read operations R1, R3, and R6 (step S9).

The sequencer 123 transfers the data of the Middle page read by the sensing circuits SA1 and SA2 to the latch circuits ADL1 and ADL2 respectively (step S10 ).

The sequencer 123 transfers the data of the latch circuit ADL2 (the data of the second cluster of the first logical page) to the latch circuit XDL2 (step S11 ).

The sequencer 123 repeats the confirmation operation of the data output until the output of the data of the latch circuit XDL1 (the data of the first cluster of the first logical page) is not completed (step S12_No).

If the output of the data of the latch circuit XDL1 is completed (step S12_Yes), the sequencer 123 transfers the data of the latch circuit ADL1 (the data of the third cluster of the logic page 1) to the latch circuit XDL1 (step S13). The sequencer 123 ends the logic when the output of the data of the latch circuit XDL2 (the data of the second cluster on the first page of logic) and the data of the latch circuit XDL1 (the data of the third cluster of the first page of logic) is completed. Readout action for page 1.

When the logical page address is not the logical page address of the first logical page (step S2_No), that is, when the logical page address is the logical page address of the second logical page, the sequencer 123 is the same as step S3, at first Then, the reading operation of the Lower page is executed (step S14).

The sequencer 123 determines the data of the Lower page according to the result of the read operation R4 (step S15).

The sequencer 123 transfers the data of the lower page read by the sensing circuits SA1 and SA2 to the latch circuits ADL1 and ADL2 respectively (step S16 ).

The sequencer 123 transfers the data of the latch circuit ADL2 (the data of the first cluster of the logic page 2) to the latch circuit XDL2 (step S17).

The sequencer 123 sets the head address of the latch circuit XDL2 in the column counter 125 as the column address CA (step S18). The serial access controller 126 receives data sequentially from the head address of the latch circuit XDL2 according to the column address CA counted by the column counter 125, and transfers the data to the I/O circuit Road 110. The I/O circuit 110 starts to send (output) the data of the latch circuit XDL2 to the memory controller 200 .

The sequencer 123 executes the read operation of the upper page in parallel with the output of the data from the latch circuit XDL2 (step S19). More specifically, the sequencer 123 executes the readout operation R2 corresponding to the readout voltage V2, the readout operation R5 corresponding to the readout voltage V5, and the readout operation R7 corresponding to the readout voltage V7. In addition, the order of the readout operations R2, R5, and R7 can be set arbitrarily.

The sequencer 123 determines the data of the Upper page according to the results of the read operations R2, R5, and R7 (step S20).

The sequencer 123 transfers the data of the upper page read by the sensing circuits SA1 and SA2 to the latch circuits ADL1 and ADL2 respectively (step S21 ).

The sequencer 123 transfers the data of the latch circuit ADL1 (the data of the second cluster on the second logical page) to the latch circuit XDL1 (step S22 ).

The sequencer 123 repeats the confirmation operation of the data output until the output of the data of the latch circuit XDL2 (the data of the first cluster of the second logical page) is not completed (step S23_No).

If the output of the data of the latch circuit XDL2 is completed (step S23_Yes), the sequencer 123 transfers the data of the latch circuit ADL2 (the data of the third cluster on the second logical page) to the latch circuit XDL2 (step S24 ). Also, the sequencer 123 sets the head address of the latch circuit XDL1 in the column counter 125 as the column address CA. The serial access controller 126 is based on the column address CA counted by the column counter 125, from the front of the latch circuit XDL1 The header addresses receive the data in sequence, and transfer them to the I/O circuit 110 . The I/O circuit 110 starts to send (output) the data of the latch circuit XDL1 to the memory controller 200 . The sequencer 123 is to end the logic when the output of the data of the latch circuit XDL1 (the data of the second cluster on the second page of logic) and the data of the latch circuit XDL2 (the data of the third cluster of the second page of logic) is completed. Page 2 readout action.

1.4.2 Select word line voltage during read operation

Next, the voltage of the selected word line during the read operation will be described using FIG. 12 and FIG. 13 . FIG. 12 is a timing chart showing the voltage of the selected word line WL in the read operation of the first logical page. FIG. 13 is a timing chart showing the voltage of the selected word line WL in the read operation of the second logical page.

As shown in FIG. 12 , in order to read the data of the first logical page, the sequencer 123 reads the data of the Lower page and the data of the Middle page. That is, the sequencer 123 sequentially executes the read operation R4 corresponding to the Lower page and the read operations R1 , R3 and R6 corresponding to the Middle page.

More specifically, at time t0, the row decoder 131 applies the read voltage V4 corresponding to the read operation R4 to the selected word line WL.

At time t1, the row decoder 131 applies the read voltage V1 corresponding to the read operation R1 to the selected word line WL.

At time t2, the row decoder 131 applies the read voltage V3 corresponding to the read operation R3 to the selected word line WL.

At time t3, the row decoder 131 applies the read voltage V6 corresponding to the read operation R6 to the selected word line WL.

At time t4, row decoder 131 applies ground voltage VSS to selected word line WL, and ends application of the read voltage.

In addition, the order in which the row decoder 131 applies the voltages V1 , V3 , V4 , and V6 to the selected word line WL can be changed. For example, the row decoder 131 may sequentially apply the voltages V4, V6, V3 and V1 to the selected word line WL, or may also sequentially apply the voltages V1, V3, V4 and V6. In addition, the row decoder 131 can also apply the voltages V6, V4, V3 and V1 in sequence.

As shown in FIG. 13 , in order to read the data of the second logical page, the sequencer 123 reads the data of the Lower page and the data of the Upper page. That is, the sequencer 123 sequentially executes the read operation R4 corresponding to the Lower page, and the read operations R2 , R5 and R7 corresponding to the Upper page.

More specifically, at time t0, the row decoder 131 applies the read voltage V4 corresponding to the read operation R4 to the selected word line WL.

At time t1, the row decoder 131 applies the read voltage V2 corresponding to the read operation R2 to the selected word line WL.

At time t2, the row decoder 131 applies the read voltage V5 corresponding to the read operation R5 to the selected word line WL.

At time t3, the row decoder 131 applies the read voltage V7 corresponding to the read operation R7 to the selected word line WL.

At time t4, row decoder 131 applies ground voltage VSS to selected word line WL, and ends application of the read voltage.

In addition, the order in which the row decoder 131 applies the voltages V2, V4, V5, and V7 to the selected word line WL can be changed. For example, the row decoder 131 can also sequentially apply the voltages V4, V7, V5 and V2 to the selected word line WL, Alternatively, the voltages V2, V4, V5 and V7 may be applied in sequence. Moreover, the row decoder 131 can also apply the voltages V7, V5, V4 and V2 in sequence.

1.4.3 Read the command sequence of the action (command sequence)

Next, an example of the command sequence related to the read operation will be described with reference to FIGS. 14 and 15 . FIG. 14 shows the command sequence of the read operation of the first logical page. FIG. 15 shows the command sequence of the read operation of the second logical page. In the examples of FIG. 14 and FIG. 15 , the signals CEn, CLE, ALE, WEn, and REn are omitted for simplicity of description. In the following description, the ready/busy signal RBn sent from the memory 100 to the memory controller 200 is described as "external RBn signal". In addition, the internal signal indicating whether the memory 100 is in the busy state in the memory 100 is described as "internal RBn signal". In the signal DQ, the command is recorded in the circular frame, the address is recorded in the square frame, and the data is recorded in the hexagonal frame. Also, when valid data is stored in any latch circuit of the page buffer 133, the latch circuit is indicated by a square frame with rounded corners. Furthermore, in the examples of FIG. 14 and FIG. 15 , the voltage of the selected word line WL when the internal RBn signal is in the busy state is also displayed.

First, the command sequence of the read operation of the first logical page will be described.

As shown in FIG. 14 , for example, when the read object is the first logical page, the memory controller 200 sends to the memory 100 a command “00h” notifying execution of the read operation. Secondly, the memory controller 200 sends the logical page address “AD-P1” of the logical page 1. In memory 100, refers to The user interface circuit 121 converts the received logical page address "AD-P1" into a physical page address. Next, the memory controller 200 sends the command “30h” to the memory 100 to execute the reading operation. The command user interface circuit 121 sequentially sends the received command and the converted physical page address to the sequencer 123 .

The sequencer 123 responds to the command "30h" and starts the read operation. Firstly, the sequencer 123 sets the internal RBn signal and the external RBn signal to the "L" level indicating a busy state. Next, the sequencer 123 executes the read operation of the lower page (read operation R4). That is, read voltage V4 is applied to selected word line WL. The reading result of the lower page is stored in the latch circuits ADL1 and ADL2. Then, the data of the latch circuit ADL1 is transferred to the latch circuit XDL1. The sequencer 123 sets the external RBn signal to "H" level indicating a ready state when the read operation of the lower page is completed. Moreover, the sequencer 123 starts the reading operation of the next Middle page (reading operations R1, R3, and R6) after the reading operation of the Lower page is completed. That is, read voltages V1, V3, and V6 are sequentially applied to the selected word line WL.

The memory controller 200 sends a signal REn (not shown) to the memory 100 if it receives the external RBn signal of the H" level. The I/O circuit 110 starts outputting data according to the signal REn. First, the I/O The circuit 110 is to output the data of the latch circuit XDL1. During the period when the data of the latch circuit XDL1 is output, if the readout operation of the Middle page ends, the sequencer 123 sets the internal RBn signal to the "H" level. Middle The read results of the page are stored in the latch circuits ADL1 and ADL2. In addition, the data output of the latch circuit XDL1 is more complex than the read operation of the Middle page. When the beam update ends first, the sequencer 123 may also once set the external RBn signal to "L" level (busy state), so that the output of data to the memory controller 200 is interrupted. Thereby, after outputting the data of the 1st grid area of the Lower page, the data of the 2nd grid area of the Middle page can be continuously output.

Secondly, the data of the latch circuit ADL2 will be transferred to the latch circuit XDL2. The input/output circuit 110 starts outputting data from the subsequent latch circuit XDL2 when the data output from the latch circuit XDL1 is completed. While the data of the latch circuit XDL2 is being output, the data of the latch circuit ADL1 is transferred to the latch circuit XDL1. The input/output circuit 110 then executes the output of the data from the latch circuit XDL1 after the output of the data from the latch circuit XDL2 is completed. When the output of data from the latch circuit XDL1 is completed, the read operation of the first logical page is completed. In addition, the memory 100 can also set the external RBn signal to be the same as the internal RBn signal, and after reading all the data on the first logical page, set the external RBn signal (internal RBn signal) to "H" level, output data.

Next, the command sequence of the read operation of the logical page 2 will be described.

As shown in FIG. 15 , for example, when the read object is the second logical page, the memory controller 200 sends to the memory 100 a command “00h” notifying execution of the read operation. Second, the memory controller 200 sends the logical page address “AD-P2” of the logical page 2. In the memory 100, the instruction user interface circuit 121 converts the received logical page address “AD-P2” into a physical page address. Next, the memory controller 200 sends the command “30h” to the memory 100 to execute the reading operation. Command UI The circuit 121 sequentially sends the received command and the converted physical page address to the sequencer 123 .

The sequencer 123 responds to the command "30h" and starts the read operation. Firstly, the sequencer 123 sets the internal RBn signal and the external RBn signal to the "L" level indicating a busy state. Next, the sequencer 123 executes the read operation of the lower page (read operation R4). That is, read voltage V4 is applied to selected word line WL. The reading result of the lower page is stored in the latch circuits ADL1 and ADL2. Then, the data of the latch circuit ADL2 is transferred to the latch circuit XDL2. The sequencer 123 sets the external RBn signal to "H" level indicating a ready state when the read operation of the lower page is completed. Moreover, the sequencer 123 starts the next reading operation of the Upper page (reading operations R2, R5, and R7) after the reading operation of the Lower page is completed. That is, read voltages V2, V5, and V7 are sequentially applied to the selected word line WL.

The memory controller 200 sends a signal REn (not shown) to the memory 100 when receiving the external RBn signal of “H” level. The I/O circuit 110 starts data output according to the signal REn. First, the I/O circuit 110 is a material of the output latch circuit XDL2. During the period when the data of the latch circuit XDL2 is output, if the reading operation of the upper page is completed, the sequencer 123 sets the internal RBn signal to "H" level. The reading result of the upper page is stored in the latch circuits ADL1 and ADL2. In addition, when the data output of the latch circuit XDL2 is completed before the read operation of the Upper page is completed, the sequencer 123 may once set the external RBn signal to "L" level (busy state), so that the pair The data output of the memory controller 200 is interrupted. In this way, after outputting the data in the 2nd frame area of the Lower page, you can connect Continue to output the data of the first grid area on the Upper page.

Secondly, the data of the latch circuit ADL1 will be transferred to the latch circuit XDL1. The input/output circuit 110 starts to output the data from the latch circuit XDL1 after the output of the data from the latch circuit XDL2 is completed. While the data of the latch circuit XDL1 is being output, the data of the latch circuit ADL2 is transferred to the latch circuit XDL2. The input/output circuit 110 executes the output of the data from the next latch circuit XDL2 after the output of the data from the latch circuit XDL1 is completed. When the output of data from the latch circuit XDL2 is completed, the read operation of the second logical page is completed. In addition, the memory 100 can also set the external RBn signal to be the same as the internal RBn signal, and after reading all the data on the second logical page, set the external RBn signal (internal RBn signal) to "H" level, output data.

1.5 Write action

Next, the writing operation will be described. The write operation generally includes a program operation and a program verification (verify) operation. The programming operation is an operation of increasing the threshold voltage by injecting electrons into the charge storage layer (or maintaining the threshold voltage by injecting almost no electrons into the charge storage layer). The program verification operation is an operation of reading data after the program operation, and determining whether the threshold voltage of the memory cell transistor MC has reached the target target level. Hereinafter, the case where the threshold voltage of the memory cell transistor MC reaches the target level is described as "passed verification", and the case where the threshold voltage does not reach the target level is described as "verified failure". More specifically, for example, in the program verification operation, the number of failed bits of the read data is a preset standard If the value exceeds the value, it is judged as "authentication failed". Then, by repeating the combination of the program operation and the program verification operation (hereinafter referred to as "program loop"), the threshold voltage of the memory cell transistor MC is raised to the target level.

In this embodiment, the data of the first logical page and the second logical page will be written into the memory group MG having the Lower page, the Middle page and the Upper page. That is, 3-bit data will be written into one memory cell transistor MC at the same time. Hereinafter, the operation of collectively writing data on a plurality of physical pages is described as "full sequential writing operation". In the full sequential writing operation of this embodiment, writing in the "S1" state to the "S7" state is performed. For example, in a full sequential write operation, threshold voltages are written sequentially from a low state. For example, when the page size of the logical page is the same as the page size of the physical page, if the states of "S1"~"S3" are written into the memory cell array 130, the latch circuit XDL is in the state of "S1"~"S3" The write action is becoming unnecessary. Therefore, the latch circuit XDL is used as a cache memory for writing data next. However, in the case of this embodiment, since the number of physical latch circuits XDL is 2/3 (for example, 10.67kB) of the page size of a logical page (for example, 16kB), it is impossible to store all data of one page of a logical page in Latch circuit XDL. Therefore, after first inputting the page data of 2/3 of the logical page to the empty latch circuit XDL, once the signal RBn is set to a busy state. Then, it is written into the memory grid array 130 until the state of S1"~"S5". When the latch circuit ADL or the latch circuit BDL becomes unnecessary in the write operation, the signal RBn can also be set as a standby state, and input The remaining page data of the logical page to the latch circuit XDL. Or, it can also be used in each sense Add a latch circuit to the amplifier unit SAU.

In this embodiment, the memory 100 alternately transfers the input data to the latch circuits XDL1 and XDL2 , so that the data input of the logical pages can be continuously performed.

1.5.1 Flow of write operation

Next, the flow of the writing operation of the memory 100 will be described using FIGS. 16 and 17 . 16 and 17 are flowcharts of the writing operation.

As shown in FIGS. 16 and 17 , the memory 100 receives the logical page address of the logical first page from the memory controller 200 during the acceptance of the write command (step S201 ). The instruction user interface circuit 121 converts the logical page address of the logical first page into a physical page address.

The sequencer 123 sets the head address of the latch circuit XDL1 in the column counter 125 as the column address CA (step S202 ).

In the page buffer 133, data input to the first cluster of the logical first page of the latch circuit XDL1 is started based on the column address CA received from the column counter 125 (step S203).

The sequencer 123 repeats the confirmation operation of the data input until the input of the first cluster of the logic page 1 of the latch circuit XDL1 is not completed (step S204_No).

If the data input to the latch circuit XDL1 is completed (step S204_Yes), the sequencer 123 transfers the data of the latch circuit XDL1 to the latch circuit ADL1 (step S205 ). Also, if the data of the latch circuit XDL1 After the data input is completed, the data input to the second cluster of the logic page 1 of the latch circuit XDL2 is then started. In addition, step S205 may also be executed during data input to the second cluster of the first logic page of the latch circuit XDL2.

The sequencer 123 repeats the confirmation operation of the data input until the data input to the second cluster of the logic page 1 of the latch circuit XDL2 is not completed (step S206_No).

If the data input to the latch circuit XDL2 is completed (step S206_Yes), the sequencer 123 sets the head address of the latch circuit XDL1 in the column counter 125 as the column address CA (step S207).

In the page buffer 133 , based on the column address CA received from the column counter 125 , data input to the third cluster of the logical first page of the latch circuit XDL1 starts.

The sequencer 123 repeats the confirmation operation of the data input until the data input to the third cluster of the logic page 1 of the latch circuit XDL1 is not completed (step S208_No).

When the data input to the latch circuit XDL1 is completed (step S208_Yes), the data input to the logical first page of the latch circuits XDL1 and XDL2 is completed.

The sequencer 123 transfers the data of the latch circuits XDL1 and XDL2 to the latch circuits BDL1 and BDL2 respectively (step S209 ).

Next, the memory 100 receives the logical page address of the second logical page from the memory controller 200 (step S210 ). The command user interface circuit 121 converts the logical page address of the second logical page into a physical page address. In addition, in the data input of the 3rd cluster of logic page 1 of the latch circuit XDL1 In addition, the sequencer 123 can also transfer the data of the latch circuit XDL2 to the latch circuit BDL2.

The sequencer 123 sets the head address of the latch circuit XDL2 in the column counter 125 as the column address CA (step S211 ).

In the page buffer 133, data input to the first cluster of the logical second page of the latch circuit XDL2 is started based on the column address CA received from the column counter 125 (step S212). In addition, the sequencer 123 may also transfer the data of the latch circuit XDL1 to the latch circuit BDL1 during the data input to the first cluster of the logic page 2 of the latch circuit XDL2.

The sequencer 123 repeats the confirmation operation of the data input until the data input to the first cluster of the logic page 2 of the latch circuit XDL2 is not completed (step S213_No).

If the data input to the latch circuit XDL2 is completed (step S213_Yes), the sequencer 123 transfers the data of the latch circuit XDL2 to the latch circuit ADL2 (step S214 ). Also, the sequencer 123 sets the head address of the latch circuit XDL1 in the column counter 125 as the column address CA (step S215). In the page buffer 133, according to the column address CA received from the column counter 125, the data input to the second cluster of the logic page 2 of the latch circuit XDL1 and the data input to the logic second cluster of the latch circuit XDL2 are sequentially performed. Page 3 of cluster data entry. In addition, in the case of step S213_Yes, the data input to the second cluster of the logic page 2 of the latch circuit XDL1 may be started next, and the sequencer 123 executes step S214 during this period.

When the sequencer 123 is to the data input of the third cluster of the logic page 2 of the latch circuit XDL2 is not completed (step S216_No), to the input node Until the end, repeat the confirmation action of data input.

When the data input to the latch circuit XDL2 is completed (step S216_Yes), the data input to the second logic page of the latch circuits XDL1 and XDL2 is terminated. The sequencer 123 sets the external RBn signal and the internal RBn signal to "L" level. Moreover, the sequencer 123 determines the state of each memory cell transistor MC according to the combination of the data of the first logical page and the second logical page, that is, the data of the Lower page, Middle page, and Upper page.

The sequencer 123 executes the program action according to the determined state (step S217).

After the program operation is completed, the sequencer 123 performs a program verification operation (step S218).

If the verification is not passed (step S219_No), the sequencer 123 checks whether the number of program loops reaches the preset upper limit (step S220).

When the number of program loops does not reach the upper limit (step S220_No), the sequencer 123 executes the program (step S217). That is, the sequencer 123 is an iterative program loop.

When the number of program loops reaches the upper limit (step S220_Yes), the sequencer 123 ends the writing operation and reports to the memory controller 200 that the writing operation has not been completed normally.

When the verification is passed (step S219_Yes), that is, if the writing of the “S1” state to the “S7” state is completed, the sequencer 123 sets the external RBn signal to the “H” level to end the full sequential writing operation.

1.5.2 Command sequence of write operation

Next, an example of the command sequence related to the write operation will be described using FIG. 18 . FIG. 18 shows the command sequence of the full sequential write operation. In the example of FIG. 18 , the signals CEn, CLE, ALE, WEn and REn are omitted for simplicity of description.

As shown in FIG. 18 , first, the memory controller 200 sends a command “80h” to notify the write operation to the memory 100 . Secondly, the memory controller 200 sends the logical page address “AD-P1” of the logical page 1. In the memory 100, the instruction user interface circuit 121 converts the received logical page address “AD-P1” into a physical page address. Secondly, the memory controller 200 sends the data of the logical page 1 to the memory 100 . The first cluster of the logical page 1 is stored in the latch circuit XDL1 and then transferred to the latch circuit ADL1. The second cluster of the logical page 1 is stored in the latch circuit XDL2 and then transferred to the latch circuit BDL2. The third cluster of the logical page 1 is stored in the latch circuit XDL1 and then transferred to the latch circuit BDL1.

Next, the memory controller 200 sends the command “1Ah” to the memory 100 to notify the data input of the next logical page. Next, the memory controller 200 sends the command “80h” and the logical page address “AD-P2” of the second logical page to the memory 100 . In the memory 100, the instruction user interface circuit 121 converts the received logical page address “AD-P2” into a physical page address. Secondly, the memory controller 200 sends the data of the second logical page to the memory 100 . The first cluster of the second logical page is stored in the latch circuit XDL2 and then transferred to the latch circuit ADL2. The 2nd cluster of logic page 2 is stored in the latch circuit XDL1. Logical page 2 of the 3rd cluster is the Stored in the latch circuit XDL2. Next, the memory controller 200 sends the command “10h” to the memory 100 indicating the execution of the writing operation.

The sequencer 123 sets the internal RBn signal and the external RBn signal to the "L" level when receiving the command "10h". Moreover, the sequencer 123 determines the state of each memory cell transistor MC according to the data stored in the latch circuits ADL1, ADL2, BDL1, BDL2, XDL1, and XDL2, and performs a write operation. The sequencer 123 sets the internal RBn signal and the external RBn signal to "H" level after the writing operation is completed. In addition, after the first cluster of the first logical page is stored in the latch circuit XDL1, the data of the second cluster of the first logical page is stored in the latch circuit XDL2, and then transferred to the latch circuit ADL1. After the second cluster of the first logical page is stored in the latch circuit XDL2, the data of the third cluster of the first logical page is stored in the latch circuit XDL1, and then transferred to the latch circuit BDL2. After the third cluster of the logical page 1 is stored in the latch circuit XDL1, the data of the first cluster of the logical page 2 is stored in the latch circuit XDL2, and then transferred to the latch circuit BDL1. After the first cluster of the second logical page is stored in the latch circuit XDL2, the data of the second cluster of the second logical page is stored in the latch circuit XDL1, and then transferred to the latch circuit ADL2. The 2nd cluster of logic page 2 is stored in the latch circuit XDL1. Cluster 3 of logic page 2 is stored in latch circuit XDL2. By doing the above, it is possible to make it invisible from the outside (memory controller 200) to transfer data from the latch circuit XDL1 or the latch circuit XDL2 to the latch circuit ADL1 or the latch circuit ADL2, or the latch circuit BDL1 or the latch circuit Time for BDL2. Also, when there is data input from the address of the 2nd cluster or the 3rd cluster in the logical page 1, it is the input data to the latch circuits XDL2 and XDL1 or the latch circuit XDL1, and then transferred to the latch circuits BDL2 and BDL1 or the latch circuit BDL1. Also, when data is input from the address of the second cluster or the third cluster in the second logical page, the data is input to the latch circuits XDL1 and XDL2 or the latch circuit XDL2, and then the writing operation starts. In this case, the latch circuit XDL without data input is set to "1" (data not written).

1.6 Effects of this embodiment

According to the structure of this embodiment, the increase in the wafer area of a semiconductor memory can be suppressed. Details about this effect.

In order to increase the memory capacity of the flash memory, the miniaturization of memory lattice transistors is progressing day by day. If the peripheral circuits such as sense amplifiers and page buffers are also miniaturized together with the miniaturization of memory grid transistors, the chip area will be reduced, and the capacity density of each chip area can be increased. However, the speed of miniaturization of peripheral circuits is slower than the speed of miniaturization of memory cell transistors. This is because the operating voltage does not drop, and if the size of the transistor in the peripheral circuit is reduced, the leakage current will increase or the lifetime of the memory will decrease.

In order to increase the capacity density per chip area, it is proposed to arrange peripheral circuits under the memory grid array, that is, between the memory grid array and the semiconductor substrate, or form the peripheral circuit on another semiconductor substrate, and paste it with the memory grid array. Combined composition, etc. In the case of such a configuration, if the memory grid array is miniaturized. With the development of high integration (high stacking), the area of the memory grid array becomes smaller, but the area of the peripheral circuit is not too small. The area of the side circuit is larger than the area of the memory cell array. As a result, the chip size is determined by the size of the peripheral circuit, resulting in miniaturization of the cell array. Higher lamination is difficult to be reflected in the reduction of wafer area.

On the other hand, according to the structure of this embodiment, the page size of a physical page can be reduced further than that of a logical page. More specifically, the writing data constituted by the page size of the logical page can be divided and written to a plurality of physical pages. Also, data read from a plurality of physical pages can be combined and output as logical page data. Since the page size of the physical page can be reduced, the number of sense amplifier units SAU corresponding to the physical page can be reduced. That is, the number of sensing circuits in the sense amplifier 132 and the number of latch circuits in the page buffer 133 can be reduced. Therefore, an increase in the wafer area of the semiconductor memory can be suppressed.

Furthermore, according to the configuration of this embodiment, the area of the sense amplifier 132 and the page buffer 133 (the number of sense circuits and latch circuits) can be reduced by reducing the page size of the physical page compared to the logical page. Therefore, by miniaturization of memory cell array 130. Higher stacking reduces the area of the memory grid array 130 and also reduces the area of peripheral circuits. That is, the mismatch between the area of the memory grid array 130 and the area of peripheral circuits disposed below the memory grid array 130 can be reduced. Therefore, the miniaturization of memory grid array 130. Higher lamination will be easily reflected in the reduction of wafer area.

Furthermore, according to the configuration of this embodiment, the data read from a plurality of physical pages can be synthesized and output as data of a logical page. Therefore, the semiconductor memory of this embodiment can be applied without changing the specifications of the memory controller 200 . That is, since the data management method of the memory system equipped with the semiconductor memory of this embodiment is used as it is, the system design can be facilitated.

Furthermore, according to the configuration of this embodiment, the page size of the physical page can be reduced. That is, the number of memory cell transistors MC included in one memory group MG commonly connected to the word line WL can be reduced. Thereby, the wiring length of the word line WL can be shortened. Therefore, the wiring resistance and wiring capacity of the word line WL can be reduced. Therefore, in the read operation and the write operation, the charging and discharging time of the voltage applied to the word line WL can be shortened. Therefore, an increase in the processing time of the read operation and the write operation can be suppressed.

Furthermore, according to the configuration of the present embodiment, in the data encoding applied to the physical page, the number of boundaries is 1 including 1 bit. Furthermore, the level number of bits whose level number is not 1 is coded in such a manner that the maximum value of the level number becomes the minimum. This makes it possible to suppress an increase in read time due to an increase in the number of boundaries (the number of read operations) when reading a plurality of physical pages corresponding to one logical page.

2. The second embodiment

Next, the second embodiment will be described. In the second embodiment, seven examples of TLC encoding different from those in the first embodiment are shown. Hereinafter, the description will focus on points different from the first embodiment.

2.1 The first case

First, the coding of the first example will be described using FIG.19. Fig. 19 is a table showing allocation of data to each status.

As shown in FIG. 19, in this example, similarly to the first embodiment, for each state, between two adjacent states (states), 1-bit data can be changed into a Gray coding method, Assign data.

"S0" status: "111" data

"S1" status: "011" data

"S2" status: "001" data

"S3" status: "101" data

"S4" status: "100" data

"S5" status: "110" information

"S6" status: "010" data

"S7" status: "000" data

In the case of reading the data allocated in this way, the lower page is determined by the read operation R4. The Middle page is determined by the read operations R2, R5 and R7. The upper page is determined by the read operations R1, R3 and R6. Therefore, the distribution of the data in this example is 1-3-3 coding as in the first embodiment.

In this example, as in the first embodiment, in the allocation of data to Upper bits, Middle bits, and Lower bits, one bit with a boundary number of one is included. Furthermore, the level number of bits whose level number is not 1 is coded in such a manner that the maximum value of the level number becomes the minimum.

2.2 Case 2

Next, encoding in the second example will be described using FIG. 20 . Fig. 20 is a table showing allocation of data to each status.

As shown in FIG. 20, in this example, similarly to the first embodiment, for each state, between two adjacent states (states), 1-bit data can be changed into a gray coding method, Assign data.

"S0" status: "110" data

"S1" status: "100" data

"S2" status: "000" data

"S3" status: "010" data

"S4" status: "011" data

"S5" status: "111" information

"S6" status: "101" information

"S7" status: "001" data

In the case of reading the data allocated in this way, the lower page is determined by the read operation R4. The Middle page is determined by the read operations R1, R3 and R6. The upper page is determined by the read operations R2, R5 and R7. Therefore, the distribution of the data in this example is 1-3-3 coding as in the first embodiment.

In this example, as in the first embodiment, in the allocation of data to Upper bits, Middle bits, and Lower bits, one bit with a boundary number of one is included. Furthermore, the level number of bits whose level number is not 1 is coded in such a manner that the maximum value of the level number becomes the minimum.

2.3 The third case

Next, encoding in the third example will be described using FIG.21. Fig. 21 is a table showing allocation of data to each status.

As shown in FIG. 21, in this example, similarly to the first embodiment, for each state, between two adjacent states (states), 1-bit data can be changed into a Gray coding method, Assign data.

"S0" status: "110" information

"S1" status: "010" data

"S2" status: "000" data

"S3" status: "100" data

"S4" status: "101" data

"S5" status: "111" information

"S6" status: "011" data

"S7" status: "001" data

In the case of reading the data allocated in this way, the lower page is determined by the read operation R4. The Middle page is determined by the read operations R2, R5 and R7. The upper page is determined by the read operations R1, R3 and R6. Therefore, the distribution of the data in this example is 1-3-3 coding as in the first embodiment.

In this example, as in the first embodiment, in the allocation of data to Upper bits, Middle bits, and Lower bits, one bit with a boundary number of one is included. Furthermore, the level number of bits whose level number is not 1 is coded in such a manner that the maximum value of the level number becomes the minimum.

2.4 Case 4

Next, the encoding of the fourth example will be described using FIG.22. Fig. 22 is a table showing allocation of data to each status.

As shown in FIG. 22, in this example, similarly to the first embodiment, for each state, between two adjacent states (states), 1-bit data can be changed into a gray coding method, Assign data.

"S0" status: "111" information

"S1" status: "101" data

"S2" status: "001" data

"S3" status: "011" data

"S4" status: "010" data

"S5" status: "000" data

"S6" status: "100" information

"S7" status: "110" information

In the case of reading the data allocated in this way, the lower page is determined by the read operation R4. The Middle page is determined by the read operations R1, R3, R5 and R7. The upper page is determined by the read operations R2 and R6. Therefore, the distribution of the data in this example is 1-4-2 encoding.

In this example, as in the first embodiment, in the allocation of data to Upper bits, Middle bits, and Lower bits, one bit with a boundary number of one is included. However, in this example, the level number of the bit whose level number is not 1 is not coded so that the maximum value of the level number becomes the minimum.

2.5 Case 5

Next, the encoding of the fifth example will be described using FIG.23. Fig. 23 is a table showing allocation of data to each status.

As shown in FIG. 23, in this example, similarly to the first embodiment, for each state, between two adjacent states (states), 1-bit data can be changed into a gray coding method, Assign data.

"S0" status: "111" information

"S1" status: "011" data

"S2" status: "001" data

"S3" status: "101" data

"S4" status: "100" data

"S5" status: "000" data

"S6" status: "010" data

"S7" status: "110" information

In the case of reading the data allocated in this way, the lower page is determined by the read operation R4. The Middle page is determined by the read operations R2 and R6. The upper page is determined by the read operations R1, R3, R5 and R7. Therefore, the distribution of the data in this example is 1-2-4 coding.

In this example, as in the first embodiment, in the allocation of data to Upper bits, Middle bits, and Lower bits, one bit with a boundary number of one is included. However, in this example, the level number of the bit whose level number is not 1 is not coded so that the maximum value of the level number becomes the minimum.

2.6 Case 6

Next, encoding in the sixth example will be described using FIG.24. Fig. 24 is a table showing allocation of data to each status.

As shown in FIG. 24, in this example, similarly to the first embodiment, for each state, between two adjacent states (states), 1-bit data can be changed into a gray coding method, Assign data.

"S0" status: "110" data

"S1" status: "100" data

"S2" status: "000" data

"S3" status: "010" data

"S4" status: "011" data

"S5" status: "001" data

"S6" status: "101" information

"S7" status: "111" information

In the case of reading the data allocated in this way, the lower page is determined by the read operation R4. The Middle page is determined by the read operations R1, R3, R5 and R7. The upper page is determined by the read operations R2 and R6. Therefore, the distribution of the data in this example is 1-4-2 coding.

In this example, as in the first embodiment, in the allocation of data to Upper bits, Middle bits, and Lower bits, one bit with a boundary number of one is included. However, in this example, the level number of the bit whose level number is not 1 is not coded so that the maximum value of the level number becomes the minimum.

2.7 Case 7

Next, encoding in the seventh example will be described using FIG.25. Fig. 25 is a table showing allocation of data to each status.

As shown in FIG. 25, in this example, similarly to the first embodiment, for each state, between two adjacent states (states), 1-bit data can be changed into a Gray coding method, Assign data.

"S0" status: "110" information

"S1" status: "010" data

"S2" status: "000" data

"S3" status: "100" data

"S4" status: "101" data

"S5" status: "001" data

"S6" status: "011" data

"S7" status: "111" information

In the case of reading the data allocated in this way, the lower page is determined by the read operation R4. The Middle page is determined by the read operations R2 and R6. The upper page is determined by the read operations R1, R3, R5 and R7. Therefore, the distribution of the data in this example is 1-2-4 coding.

In this example, as in the first embodiment, in the allocation of data to Upper bits, Middle bits, and Lower bits, one bit with a boundary number of one is included. However, in this example, the level number of the bit whose level number is not 1 is not coded so that the maximum value of the level number becomes the minimum.

2.8 Effects of this embodiment

The coding of this embodiment can be applied to the first embodiment.

According to the structure of this embodiment, the same effect as that of the first embodiment can be obtained.

3. The third embodiment

Next, the third embodiment will be described. In the third embodiment, two examples of the reading operation different from those in the first embodiment will be described. Hereinafter, the description will focus on points different from the first embodiment.

3.1 The first case

First, the read operation of the first example will be described. In the first example, the order of the read voltages applied to the selected word line WL in the read operation of the first logical page and the second logical page is different from that of the first embodiment, using FIGS. 26 and 27. Case. FIG. 26 shows the command sequence of the read operation of the first logical page. Fig. 27 shows the command sequence of the read operation of the second logical page. In the examples of FIG. 26 and FIG. 27 , the signals CEn, CLE, ALE, WEn, and REn are omitted for simplicity of description. In addition, in the example of FIG. 26 and FIG. 27 , the voltage of the selected word line WL when the internal RBn signal is in the busy state is also displayed.

First, the command sequence of the read operation of the first logical page will be described.

As shown in Figure 26, in the Lower corresponding to the logical page 1 In the page read operation (read operation R4) and the middle page read operation (read operations R1, R3, and R6), the sequencer 123 executes the read operations in the order of R6, R4, R3, and R1. That is, read voltages V6, V4, V3, and V1 are sequentially applied to the selected word line WL. In this case, as in the first embodiment, after the read operation R4 corresponding to the lower page is completed, the external RBn signal is set to "H" level. Then, the reading result of the lower page is stored in the latch circuits ADL1 and ADL2. In addition, the memory 100 can also set the external RBn signal to be the same as the internal RBn signal, and after reading all the data on the first logical page, set the external RBn signal (internal RBn signal) to "H" level, output data.

In addition, the sequencer 123 can also execute the read operation in the order of R1, R3, R4 and R6. That is, read voltages V1, V3, V4, and V6 may be sequentially applied to the selected word line WL.

Next, the command sequence of the read operation of the logical page 2 will be described.

As shown in FIG. 27, in the read operation of the Lower page (read operation R4) and the read operation of the Upper page (read operations R2, R5, and R7) corresponding to the second logical page, the sequencer 123 The read operation is performed in the order of R7, R5, R4 and R2. That is, read voltages V7 , V5 , V4 , and V2 are sequentially applied to the selected word line WL. In this case, as in the first embodiment, after the read operation R4 corresponding to the lower page is completed, the external RBn signal is set to "H" level. Then, the reading result of the lower page is stored in the latch circuits ADL1 and ADL2. In addition, the memory 100 can also set the external RBn signal to be the same as the internal RBn signal, and read all the data on the second page of the logic. After the material, set the external RBn signal (internal RBn signal) to "H" level to output the data.

In addition, the sequencer 123 can also execute the read operation in the order of R2, R4, R5 and R7. That is, read voltages V2, V4, V5, and V7 may also be applied to the selected word line WL.

3.2 Case 2

Next, the read operation of the second example will be described. In this example, a case in which data on the Lower page, Middle page, and Upper page are collectively read will be described using FIG. 28 . Hereinafter, such a read operation will be described as "sequential read operation". In the sequential read operation of this example, the "S0" state ~ "S7" state will be read out together. Fig. 28 shows the order of commands in the sequential read operation. In the example of FIG. 28, the signals CEn, CLE, ALE, WEn, and REn are omitted for simplicity of description. In addition, in the example of FIG. 28, a part of the command and the address are also omitted. Furthermore, in the example of FIG. 28 , the voltage of the selected word line WL when the internal RBn signal is in the busy state is also displayed.

As shown in FIG. 28, when the sequencer 123 receives the command "30h", it responds to this and starts the read operation. Firstly, the sequencer 123 sets the internal RBn signal and the external RBn signal to the "L" level indicating a busy state. Next, the sequencer 123 executes a sequential read operation. More specifically, the sequencer 123 executes the read operations R1 - R7 sequentially. At this time, the read voltages V1 - V7 are sequentially applied to the selected word line WL. Sequencer 123 is to determine the data of the Lower page if the read operation R4 ends, and the external RBn The signal is set to "H" level. The data of the Lower page is stored in the latch circuits ADL1 and ADL2. Then, the data of the latch circuit ADL1 (the data of the first cluster of the logic page 1) is transferred to the latch circuit XDL1. The memory controller 200 sends a signal REn (not shown) to the memory 100 when receiving the external RBn signal of “H” level. The I/O circuit 110 starts data output according to the signal REn. First, the I/O circuit 110 is the data of the output latch circuit XDL1 (the data of the first cluster on the logic page 1).

The sequencer 123 next determines the data of the Middle page after the read operation R6 is completed. The data of the Middle page is stored in the latch circuits BDL1 and BDL2. The data of the latch circuit BDL2 (the data of the 2nd cluster of the logic page 1) is transferred to the latch circuit XDL2. The data of the latch circuit BDL1 (the data of the third cluster of the first logical page) is transferred after the output of the data of the lower page (the data of the first cluster of the logical first page) stored in the latch circuit XDL1 is completed To latch circuit XDL1.

During the period when the data of the latch circuit XDL1 or XDL2 is output, if the sequential read operation ends, the sequencer 123 sets the internal RBn signal to "H" level.

When the output of the data stored in the middle page of the latch circuit XDL2 (the data of the second cluster of the first logical page) is completed, the data of the latch circuit ADL2 (the data of the first cluster of the second logical page) is transferred To latch circuit XDL2.

When the data output of the Middle page stored in the latch circuit XDL1 (the data of the third cluster of the first logical page) is completed, the output of the data of the first logical page is completed, and then the data output of the second logical page starts. head First, the data stored in the Lower page of the latch circuit XDL2 (the data of the first cluster on the second logical page) is output. In addition, when the output of the data of the Middle page (the data of the third cluster of the first logical page) stored in the latch circuit XDL1 is completed, the data of the Upper page (the second cluster of the logical second page) are transferred from the sensing circuit SA1. data) to the latch circuit XDL1.

When the output of the data stored in the Upper page of the latch circuit XDL2 (the data of the first cluster of the second logical page) is completed, the data of the sensing circuit SA2 (the data of the third cluster of the second logical page) will be transferred To latch circuit XDL2. When the output of the data of the latch circuit XDL2 (the data of the third cluster on the second logical page) is completed, the sequential read operation is completed.

In addition, the sequencer 123 can also execute the read operation in the order of R7-R1. That is, the read voltage can also be applied to the selected word line WL in the order of the voltages V7˜V1. In addition, the memory 100 can also set the external RBn signal and the internal RBn signal to be the same, and after reading all the data, set the external RBn signal (internal RBn signal) to "H" level to output the data.

3.3 Effects of this embodiment

The coding of this embodiment can be applied to the first embodiment.

According to the structure of this embodiment, the same effect as that of the first embodiment can be obtained.

Furthermore, according to the configuration of this embodiment, in the read operation, the read voltage can be applied in ascending or descending order. In this way, it is possible to suppress the The amplitude of the change in the voltage applied to the selected word line WL increases. Therefore, the time taken for transition of the voltage applied to the selected word line WL can be shortened, and the processing time of the read operation can be reduced.

4. Fourth Embodiment

Next, the fourth embodiment will be described. In the fourth embodiment, the case where the data of one logical page is allocated to two physical pages (that is, one memory group MG capable of storing two pages of data) will be described. Hereinafter, the description will focus on points different from those of the first to third embodiments.

4.1 Threshold voltage distribution of memory cell transistors

First, the threshold voltage distribution related to the acquisition of the memory cell transistor MC will be described using FIG. 29 . FIG. 29 is a diagram showing the relationship between the threshold voltage distribution of memory cell transistor MC and the allocation of data. Hereinafter, in this embodiment, the case of an MLC (Multi Level Cell) (or also referred to as "2bit/Cell") which can hold 4-value (2-bit) data in the memory cell transistor MC will be described.

As shown in FIG. 29, the threshold voltage of each memory cell transistor MC takes a value included in any one of discrete, for example, four distributions. Hereinafter, the four distributions are respectively described as "S0" state, "S1" state, "S2" state, and "S3" state in order of lower threshold voltage.

The "S0" state is, for example, a state corresponding to data erasure. Moreover, the states "S1"-"S3" correspond to states in which charges are injected into the charge storage layer and data is written. In the write operation, the corresponding threshold value will be The verification voltage of the voltage distribution is set to V1~V3. Therefore, the voltage values are in the relationship of V1<V2<V3<Vread.

In addition, the set value of the verification voltage and the set value of the read voltage corresponding to each state may be the same or different. In the following, for simplification of the description, the case where the verify voltage and the read voltage have the same set value will be described.

Hereinafter, the readout operations corresponding to the states "S1" to "S3" are described as readout operations R1, R2, and R3, respectively. The readout operation R1 is to determine whether the threshold voltage of the memory cell transistor MC is less than the full voltage V1. The readout operation R2 is to determine whether the threshold voltage of the memory cell transistor MC is less than the full voltage V2. The readout operation R3 is to determine whether the threshold voltage of the memory cell transistor MC is less than the full voltage V3.

As above, each memory cell transistor MC can take four types of states by having any one of four threshold voltage distributions. By distributing the states as "00"~"11" in binary system, each memory cell transistor MC can hold 2-bit data. Hereinafter, 2-bit data are described as Lower bit and Upper bit, respectively. In addition, a set of Lower bits that are written (read) together in the memory group MG is described as a Lower page, and a set of Upper bits is described as an Upper page.

In the example of FIG. 29, for the memory cell transistor MC included in each threshold voltage distribution, data is allocated as "Upper bit/Lower bit" as shown below. For each state, data is allocated in such a manner that 1-bit data is changed between two adjacent states (states) in Gray code.

"S0" status: "11" data

"S1" status: "01" data

"S2" status: "00" data

"S3" status: "10" data

In the case of reading the data allocated in this way, the lower page is determined by the read operation R2. The upper page is determined by the read operations R1 and R3. That is, the values of the Lower bit and the Upper bit are respectively determined by one and two read operations. Therefore, the distribution of the data in this example is 1-2 coding.

In addition, the distribution of data in the "S0"~"S3" state is not limited to 1-2 coding.

4.2 Conversion action of logical page address and physical page address

Next, an example of conversion operations between logical page addresses and physical page addresses will be described with reference to FIGS. 30 and 31 . FIG. 30 is a diagram illustrating the flow of conversion operations between logical page addresses and physical page addresses. Fig. 31 is a diagram showing allocation of logical page data to physical pages.

As shown in FIG. 30, for example, when the memory controller 200 receives a write request from the host device 2, it allocates one logical page address "90001" corresponding to the received one logical address "00001". ". Hereinafter, the allocated logical page is described as "the first logical page". In the example of FIG. 30, logical page 1 would correspond to logical page address "90001".

If the instruction user interface circuit 121 receives a write command including a logical page address and a logical page of one page from the memory controller 200, Then, the logical page address of 1 page is converted into the physical page address of 2 pages. In this embodiment, the instruction user interface circuit 121 converts the logical page address of the first logical page into the physical page addresses of the Lower page and the Upper page.

At this time, the data length of a logical page divided into one page is the same as the data length of a physical page divided into two pages. In this embodiment, the number of logical pages to be written is a="1", and the number of physical pages to be written is b="2". Therefore, one physical page, that is, one memory group MG The page size n is represented by n=m/2. For example, when the page size of the logical page is 16 [kB], the page size of the physical page is n=16/2=8 [kB].

For example, the sequencer 123 writes the data of the first logical page into the Lower page and the Upper page of one memory group MG according to the physical page address converted in the instruction user interface circuit 121 .

Next, the arrangement of the logical page data of one memory group MG will be described in detail.

As shown in FIG. 31, in this embodiment, the data on the first logical page is divided into two, and the first data is set as the first cluster and the second cluster. For example, in the memory 100, the data of the first half of the first cluster of the logical page 1 is written in the first grid area of the Lower page, and the data of the second half of the first cluster of the logical page 1 is written in the second grid area . Also, in the memory 100, the data of the first half of the second cluster of the logical first page is written in the first grid area of the Upper page, and the data of the second half of the second cluster of the logical first page are written in the second grid area. .

4.3 Read Action

Next, the reading operation will be described. In the present embodiment, the physical pages to be read from the logical first page are the Lower page (the first frame area and the second frame area) and the Upper page (the first frame area and the second frame area). In this case, the memory 100 sends (outputs) the data of the Lower page (the first grid area and the second grid area) and the data of the Upper page (the first grid area and the second grid area) to the memory controller 200 .

4.3.1 Flow of read operation

First, the flow of the read operation of the memory 100 will be described using FIG. 32 . Fig. 32 is a flowchart of the read operation.

As shown in FIG. 32, the memory 100 receives a read command from the memory controller 200 (step S1). After the command user interface circuit 121 converts the logical page address into a physical page address, it sends the received command and the converted physical page address to the sequencer 123 .

The sequencer 123 first executes the reading operation of the Lower page (step S30). More specifically, the sequencer 123 executes the read operation R2 corresponding to the read voltage V2.

The sequencer 123 determines the data of the Lower page (the data of the first cluster of the logical first page) based on the result of the read operation R2 (step S31).

The sequencer 123 transfers the data of the lower page read by the sensing circuits SA1 and SA2 to the latch circuits ADL1 and ADL2 respectively (step S32 ).

The sequencer 123 transfers the data of the latch circuits ADL1 and ADL2 (the data of the first cluster of the logic page 1) to the latch circuit XDL1 respectively and XDL2 (step S33). In addition, the sequencer 123 can also directly transfer the data of the lower page read by the sensing circuits SA1 and SA2 to the latch circuits XDL1 and XDL2 respectively.

The sequencer 123 sets the head address of the latch circuit XDL1 in the column counter 125 as the column address CA (step S34). The serial access controller 126 sequentially receives data from the head address of the latch circuit XDL1 according to the column address CA counted by the column counter 125 , and transfers the data to the I/O circuit 110 . The I/O circuit 110 starts sending (outputting) data to the latch circuits XDL1 and XDL2 of the memory controller 200 .

The sequencer 123 executes the read operation of the upper page in parallel with the output of the data from the latch circuits XDL1 and XDL2 (step S35). More specifically, the sequencer 123 executes the read operation R1 corresponding to the read voltage V1 and the read operation R3 corresponding to the read voltage V3. In addition, the order of the readout operations R1 and R3 can be set arbitrarily.

The sequencer 123 determines the data of the Upper page (the data of the second cluster of the first logical page) based on the results of the read operations R1 and R3 (step S36).

The sequencer 123 transfers the data of the upper page read by the sensing circuits SA1 and SA2 to the latch circuits ADL1 and ADL2 respectively (step S37 ).

When the output of data by the latch circuit XDL1 is not completed (step S38_No), the sequencer 123 repeats the confirmation operation of data output until the output is completed.

If the output of the data of the latch circuit XDL1 ends (step S38_Yes), then the sequencer 123 transfers the data of the latch circuit ADL1 to the latch circuit XDL1 (step S39 ). In addition, in the case of step S38_Yes, the data output of the latch circuit XDL2 may be started next, and the sequencer 123 executes step S39 during the data output period of the latch circuit XDL2.

The sequencer 123 repeats the confirmation operation of the data output until the output of the data from the latch circuit XDL2 is not completed (step S40_No).

If the output of the data of the latch circuit XDL2 is completed (step S40_Yes), the sequencer 123 transfers the data of the latch circuit ADL2 to the latch circuit XDL2 (step S41 ). The sequencer 123 ends the read operation of the first logical page when the output of the data (data of the second cluster of the first logical page) of the latch circuits XDL1 and XDL2 is completed. In addition, in the case of step S40_Yes, the data output of the latch circuit XDL1 may be started next, and the sequencer 123 executes step S41 during the data output period of the latch circuit XDL1.

4.3.2 Command sequence of read operation

Next, an example of the command sequence related to the read operation will be described using FIG. 33 . Fig. 33 shows the command sequence of the read operation of the first logical page. In the example of FIG. 33 , the signals CEn, CLE, ALE, WEn, and REn are omitted for simplicity of description. Furthermore, in the example of FIG. 33, the voltage of the selected word line WL when the internal RBn signal is busy is also displayed.

As shown in FIG. 33 , the memory controller 200 first sends the command “00h”. Second, the memory controller 200 is to send the logic page 1 The logical page address "AD-P1". In the memory 100, the instruction user interface circuit 121 converts the received logical page address “AD-P1” into a physical page address. Secondly, the memory controller 200 sends the command “30h” to the memory 100 . The command user interface circuit 121 sequentially sends the received command and the converted physical page address to the sequencer 123 .

The sequencer 123 responds to the command "30h" and starts the read operation. Firstly, the sequencer 123 sets the internal RBn signal and the external RBn signal to the "L" level indicating a busy state. Next, the sequencer 123 executes the read operation of the lower page (read operation R2). That is, read voltage V2 is applied to selected word line WL. The reading result of the lower page is stored in the latch circuits ADL1 and ADL2. The data of the latch circuit ADL1 is transferred to the latch circuit XDL1. The data of the latch circuit ADL2 is transferred to the latch circuit XDL2. The sequencer 123 sets the external RBn signal to "H" level when the reading operation of the lower page is completed. Moreover, the sequencer 123 starts the next reading operation of the Upper page (reading operations R1 and R3 ) after the reading operation of the Lower page is completed. That is, read voltages V1 and V3 are sequentially applied to the selected word line WL.

The memory controller 200 sends a signal REn (not shown) to the memory 100 when receiving the external RBn signal of “H” level. The I/O circuit 110 starts data output according to the signal REn. First, the I/O circuit 110 is a material of the output latch circuit XDL1. During the period when the data of the latch circuit XDL1 is being output, if the reading operation of the upper page ends, the sequencer 123 sets the internal RBn signal to "H" level. The reading result of the upper page is stored in the latch circuits ADL1 and ADL2. Additionally, the latch When the data output of the circuits XDL1 and XDL2 is completed earlier than the reading operation of the Upper page, the sequencer 123 can also set the external RBn signal to "L" level (busy state) to control the memory The output of data from the device 200 is interrupted. Thereby, after outputting the data of the Lower page, the data of the Upper page can be output continuously.

The I/O circuit 110 starts to output data from the latch circuit XDL2 after the data output from the latch circuit XDL1 is completed. During the data output period of the latch circuit XDL2, the data of the latch circuit ADL1 will be transferred to the latch circuit XDL1. The input/output circuit 110 executes the output of the data from the latch circuit XDL1 following the completion of the data output from the latch circuit XDL2. While the data of the latch circuit XDL1 is being output, the data of the latch circuit ADL2 is transferred to the latch circuit XDL2. When the output of data from the latch circuit XDL2 is completed, the read operation of the first logical page is completed. In addition, the memory 100 can also set the external RBn signal to be the same as the internal RBn signal, and after reading all the data, set the external RBn signal (internal RBn signal) to "H" level to output the data.

4.4 Write action

Next, the writing operation will be described. In this embodiment, the data of the first logical page is written into the memory group MG having the lower page and the upper page at the same time, and the full sequential writing operation is performed. That is, 2-bit data will be written into one memory cell transistor MC at the same time. In the full sequential writing operation of this embodiment, writing in the "S1" state to the "S3" state is performed.

4.4.1 Flow of write operation

Next, the flow of the write operation in the memory 100 will be described with reference to FIGS. 34 and 35 . 34 and 35 are flowcharts of the write operation.

As shown in FIGS. 34 and 35 , the memory 100 receives a write command of the first logical page from the memory controller 200 during the reception of the write command (step S230 ). At this time, the command user interface circuit 121 converts the logical page address of the logical first page into a physical page address.

The sequencer 123 sets the head address of the latch circuit XDL1 in the column counter 125 as the column address CA (step S231 ).

In the page buffer 133, data input to the first half of the first cluster of the logical first page of the latch circuit XDL1 starts based on the column address CA received from the column counter 125 (step S232).

The sequencer 123 repeats the confirmation operation of the data input until the data input to the first half of the first cluster of the logic page 1 of the latch circuit XDL1 is not completed (step S233_No).

If the data input to the first half of the first cluster of the logic page 1 of the latch circuit XDL1 is completed (step S233_Yes), the sequencer 123 transfers the data of the latch circuit XDL1 to the latch circuit ADL1 (step S234 ). Also, when the data input to the first half of the first cluster of the first logical page of the latch circuit XDL1 is completed, the data input to the second half of the first cluster of the first logical page of the latch circuit XDL2 starts next. In addition, in the case of step S233_Yes, the logic of the latch circuit XDL2 can also be started The sequencer 123 executes step S234 while the data input of the second half of the first cluster of the first page is input to the latch circuit XDL2.

The sequencer 123 repeats the confirmation operation of the data input until the data input to the second half of the first cluster of the logic page 1 of the latch circuit XDL2 is not completed (step S235_No).

If the data input to the second half of the first cluster of the logic page 1 of the latch circuit XDL2 is completed (step S235_Yes), the sequencer 123 sets the head address of the latch circuit XDL1 in the column counter 125 as the row bit address CA (step S236). In the page buffer 133, according to the column address CA received from the column counter 125, data input to the first half of the second cluster of the logical first page of the latch circuit XDL1 starts.

The sequencer 123 transfers the data of the second half of the first cluster of the logic page 1 of the latch circuit XDL2 to the latch while the data of the first half of the second cluster of the logic page 1 of the latch circuit XDL1 is input. Circuit ADL2 (step S237).

After the data input to the first half of the second cluster of the first logical page of the latch circuit XDL1 is completed, the data input to the second half of the second cluster of the first logical page of the latch circuit XDL2 is started. Then, the sequencer 123 repeats the confirmation operation of the data input until the data input to the second half of the second cluster of the logic page 1 of the latch circuit XDL2 is not completed (step S238_No).

When the data input to the second half of the second cluster of the first logical page of the latch circuit XDL2 is completed (step S238_Yes), the data input to the first logical page of the latch circuits XDL1 and XDL2 is completed. Sequencer 123 is Set the external RBn signal and the internal RBn signal to "L" level. The sequencer 123 determines the state of each memory cell transistor MC according to the combination of the data of the Lower page and the Upper page.

The sequencer 123 executes the program action according to the determined state (step S239).

After the program operation is completed, the sequencer 123 executes the program verification operation (step S240).

If the verification is not passed (step S241_No), the sequencer 123 checks whether the number of program loops reaches the preset upper limit (step S242).

When the number of program loops does not reach the upper limit (step S242_No), the sequencer 123 executes the program (step S239). That is, the sequencer 123 is an iterative program loop.

When the number of program loops reaches the upper limit (step S242_Yes), the sequencer 123 ends the writing operation and reports to the memory controller 200 that the writing operation has not been completed normally.

When the verification is passed (step S241_Yes), that is, if the writing of the “S1” state to the “S3” state is completed, the sequencer 123 sets the external RBn signal to the “H” level to end the full sequential writing operation.

4.4.2 Command sequence of write operation

Next, an example of the command sequence related to the write operation will be described using FIG. 36 . Fig. 36 shows the command sequence of the full sequential write operation. In the example of FIG. 36, in order to simplify the description, the signals CEn, CLE, ALE, WEn and REn are omitted.

As shown in FIG. 36 , first, the memory controller 200 sends the command “80h” to the memory 100 . Secondly, the memory controller 200 sends the logical page address “AD-P1” of the logical page 1. In the memory 100, the instruction user interface circuit 121 converts the received logical page address “AD-P1” into a physical page address. Secondly, the memory controller 200 sends the data of the logical page 1 to the memory 100 . When the input of the data in the first half of the first cluster of the first logical page of the latch circuit XDL1 is completed, the input of the data in the second half of the first cluster of the first logical page of the latch circuit XDL2 starts next. The data stored in the latch circuit XDL1 is transferred to the latch circuit ADL1 while the data of the second half of the first cluster of the first logical page of the latch circuit XDL2 is input. When the input of the data of the second half of the first cluster of the first logical page of the latch circuit XDL2 is completed, the input of the data of the first half of the second cluster of the first logical page of the latch circuit XDL1 starts next. The data stored in the latch circuit XDL2 is transferred to the latch circuit ADL2 while the data of the first half of the second cluster of the first logical page of the latch circuit XDL1 is input. When the input of data in the first half of the second cluster of the first logical page of the latch circuit XDL1 is completed, the input of data in the second half of the second cluster of the first logical page of the latch circuit XDL2 starts. Cluster 2 of logical page 1 is stored in latch circuits XDL1 and XDL2.

Next, the memory controller 200 sends the command “10h” to the memory 100 indicating the execution of the writing operation.

If the sequencer 123 accepts the command "10h", it will internally The RBn signal and the external RBn signal are set to "L" level. Moreover, the sequencer 123 determines the state of each memory cell transistor MC according to the data stored in the latch circuits ADL1, ADL2, XDL1, and XDL2, and performs a write operation. The sequencer 123 sets the internal RBn signal and the external RBn signal to "H" level after the writing operation is completed.

4.5 Effects of this embodiment

According to the structure of this embodiment, the same effect as that of the first embodiment can be obtained.

5. Fifth Embodiment

Next, the fifth embodiment will be described. In the fifth embodiment, the case where three logical pages of data are allocated to four physical pages (that is, one memory group MG capable of storing four pages of data) will be described. Hereinafter, the description will focus on points different from those of the first to fourth embodiments.

5.1 Configuration of Sense Amplifier and Page Buffer

First, an example of the configuration of the sense amplifier 132 and the page buffer 133 will be described using FIG. 37 . FIG. 37 is a block diagram of the sense amplifier 132 and the page buffer 133 .

As shown in FIG. 37, in the present embodiment, the sequencer 123 divides the plurality of memory grid transistors MC of one memory group MG into a first grid area, a second grid area, and a third grid area. 3 and control. Similarly, the sequencer 123 is corresponding to the 1st to 3rd grid area, and the sense amplifier 132 and page buffer 133 are divided into three and controlled. For example, the memory cell transistor MC included in the first cell area is associated with the bit lines BL0˜BL(i−1). The memory cell transistor MC included in the second cell area is associated with bit lines BL(i)~BL(j-1) (j is an integer larger than i and smaller than k). The memory cell transistor MC contained in the third cell area is associated with the bit lines BL(j)~BL(k-1). In addition, the number of memory grid transistors MC included in the first grid area, the number of memory grid transistors MC included in the second grid area, and the number of memory grid transistors MC included in the third grid area is the same as ideal. For example, the number of memory grid transistors MC included in the first grid area, the number of memory grid transistors MC included in the second grid area, and the number of memory grid transistors MC included in the third grid area are the same In this case, i, j and k are in the relationship of i=j/2=k/3.

The page buffer 133 of this embodiment corresponds to one sensing circuit SA, and includes latch circuits ADL, BDL, CDL, and XDL. The sensing circuit SA and the latch circuits ADL, BDL, CDL and XDL are connected to each other. In other words, the sensing circuit SA and the latch circuits ADL, BDL, CDL, and XDL are connected in such a way that they can send and receive data. The latch circuits ADL, BDL, CDL and XDL temporarily store data DAT. For example, during the read operation, the sensing circuit SA transfers the determined read data from the sensing circuit SA to any one of the latch circuits ADL, BDL, CDL and XDL. Hereinafter, the sensing circuit connected to the bit line BL corresponding to the memory cell transistor MC included in the third cell area is described as "sensing circuit SA3". The latch circuit CDL corresponding to the sensing circuit SA1 is described as "latch circuit CDL1". The latch circuit CDL corresponding to the sensing circuit SA2 is described as "latch circuit CDL2". will correspond to the latch circuit of the sense circuit SA3 ADL, BDL, CDL, and XDL are described as "latch circuit ADL3", "latch circuit BDL3", "latch circuit CDL3", and "latch circuit XDL3". In addition, in this embodiment, the combination of the sense circuit SA1, the latch circuits ADL1, BDL1, CDL1, and XDL1 is described as "sense amplifier unit SAU1". The combination of the sense circuit SA2, the latch circuits ADL2, BDL2, CDL2, and XDL2 is described as "sense amplifier unit SAU2". The combination of the sense circuit SA3, the latch circuits ADL3, BDL3, CDL3, and XDL3 is described as "sense amplifier unit SAU3".

In the present embodiment, like the plurality of sense amplifier units SAU1 and the plurality of sense amplifier units SAU2 , the plurality of sense amplifier units SAU3 are arranged in a single region.

5.2 Threshold voltage distribution of memory cell transistors

Next, using FIG. 38, the threshold voltage distribution related to the acquisition of the memory cell transistor MC will be described. FIG. 38 is a diagram showing the relationship between the threshold voltage distribution of memory cell transistor MC and the allocation of data. Hereinafter, in this embodiment, the case where the memory cell transistor MC is a QLC (Quad Level Cell) (or "also described as 4bit/Cell") capable of holding 16-value (4-bit) data will be described.

As shown in FIG. 38, the threshold voltage of each memory cell transistor MC takes a value included in any one of discrete, for example, 16 distributions. Below, the 16 distributions are described as "S0" state, "S1" state, "S2" state, "S3" state, "S4" state, "S5" state, "S6" state in order of lower threshold voltage. " state, "S7" state, "S8" state, "S9" state, "S10" state, "S11" state, "S12" state, "S13" state, "S14" state, and "S15" state.

The "S0" state is, for example, a state corresponding to data erasure. Moreover, the states "S1"-"S15" correspond to states in which charges are injected into the charge storage layer and data is written. In the write operation, verify voltages corresponding to the respective threshold voltage distributions are V1 to V15. Therefore, the voltage values are in the relationship of V1<V2<V3<V4<V5<V6<V7<V8<V9<V10<V11<V12<V13<V14<V15<Vread. Voltages V1 to V15 are voltages applied to selected word line WL during a read operation.

More specifically, the threshold voltage included in the "S0" state is the sub-full voltage V1. The threshold voltage included in the "S1" state is equal to or greater than the voltage V1 and less than the full voltage V2. The threshold voltage included in the "S2" state is equal to or greater than the voltage V2 and less than the full voltage V3. The threshold voltage included in the "S3" state is equal to or greater than the voltage V3 and less than the full voltage V4. The threshold voltage included in the "S4" state is equal to or greater than the voltage V4 and less than the full voltage V5. The threshold voltage included in the "S5" state is equal to or greater than the voltage V5 and less than the full voltage V6. The threshold voltage included in the "S6" state is equal to or greater than the voltage V6 and less than the full voltage V7. The threshold voltage included in the "S7" state is equal to or greater than the voltage V7 and less than the full voltage V8. The threshold voltage included in the "S8" state is equal to or greater than the voltage V8 and less than the full voltage V9. The threshold voltage included in the "S9" state is equal to or greater than the voltage V9 and less than the full voltage V10. The threshold voltage included in the "S10" state is equal to or greater than the voltage V10 and less than the full voltage V11. The threshold voltage included in the "S11" state is equal to or greater than the voltage V11 and less than the full voltage V12. The threshold voltage included in the "S12" state is equal to or greater than the voltage V12 and less than the full voltage V13. In "S13" The threshold voltage included in the state is equal to or greater than voltage V13 and less than V14. The threshold voltage included in the "S14" state is equal to or greater than voltage V14 and less than V15. The threshold voltage included in the "S15" state is equal to or greater than the voltage V15 and less than the full voltage Vread.

In addition, the set value of the verification voltage and the set value of the read voltage corresponding to each state may be the same or different. In the following, for simplification of the description, the case where the verify voltage and the read voltage have the same set value will be described.

Hereinafter, the readout operations corresponding to the states "S1" to "S15" are described as readout operations R1 to R15, respectively. The readout operation R1 is to determine whether the threshold voltage of the memory cell transistor MC is less than the full voltage V1. The readout operation R2 is to determine whether the threshold voltage of the memory cell transistor MC is less than the full voltage V2. Hereinafter, similarly, the read operations R3-R15 are to determine whether the threshold voltage of the memory cell transistor MC is lower than the full voltage V3-V15, respectively.

As above, each memory cell transistor MC can take 16 kinds of states by having any one of 16 threshold voltage distributions. By distributing the states of these as "0000"~"1111" in binary system, the data of each memory cell transistor MC can be kept as 4 bits. Hereinafter, the 4-bit data are respectively described as Lower bit, Middle bit, Upper bit and Top bit. Also, a set of Lower bits to be written (read) into the memory group MG together is described as a Lower page, a set of Middle bits is described as a Middle page, and a set of Upper bits is described as an Upper page. page, and record the set of Top bits as a Top page.

In the example of Figure 38, for each threshold voltage divided For the memory cell transistor MC, as follows, the data is allocated into "Top bit/Upper bit/Middle bit/Lower bit". For each state, data is allocated in such a manner that 1-bit data is changed between two adjacent states (states) in Gray code.

"S0" status: "1111" information

"S1" status: "0111" data

"S2" status: "0011" data

"S3" status: "0001" data

"S4" status: "0101" data

"S5" status: "1101" data

"S6" status: "1001" data

"S7" status: "1011" information

"S8" status: "1010" information

"S9" status: "1110" information

"S10" status: "0110" data

"S11" status: "0100" data

"S12" status: "1100" information

"S13" status: "1000" data

"S14" status: "0000" data

"S15" status: "0010" data

In the case of reading the data allocated in this way, the lower page is determined by the read operation R8. The Middle page is determined by the read operations R3, R7, R11 and R15. The upper page is determined by the read operations R2, R4, R6, R9 and R13. The Top page is read by the read actions R1, R5, R10, R12 and R14 to determine. That is, the values of the Lower bit, Middle bit, Upper bit, and Top bit are respectively determined by 1, 4, 5, and 5 read operations. That is, the number of boundaries is 1, 4, 5, and 5 for Lower bits, Middle bits, Upper bits, and Top bits. Therefore, the allocation of data in this embodiment is 1-4-5-5 coding.

In this embodiment, in the assignment of data to Top bits, Upper bits, Middle bits, and Lower bits, one bit has a boundary number of one. Furthermore, the level number of bits whose level number is not 1 is coded in such a manner that the maximum value of the level number becomes the minimum. For example, in QLC, that is, in the case of 4bit/Cell, the total number of boundaries is 15, so when the remaining 3 bits are used to share the remaining 14 boundaries, the maximum value of the number of boundaries is formed to be the smallest. The number of boundaries is set to 4, 5, and 5 cases.

In addition, the allocation of data in the states "S0"~"S15" is not limited to 1-4-5-5 encoding.

5.3 Conversion action of logical page address and physical page address

Next, an example of conversion operations between logical page addresses and physical page addresses will be described with reference to FIGS. 39 and 40 . FIG. 39 is a diagram illustrating the flow of conversion operations between logical page addresses and physical page addresses. Fig. 40 is a diagram showing allocation of logical page data to physical pages.

As shown in FIG. 39 , for example, if the memory controller 200 accepts a write request from the host device 2, the logic corresponding to the received three Addresses "00001", "00002" and "00003" are assigned three logical page addresses "90001", "90002" and "90003". Hereinafter, the allocated three logical pages are described as "1st logical page", "2nd logical page", and "3rd logical page". In the example of FIG. 39, logical page 1 would correspond to logical page address "90001", logical page 2 would correspond to logical page address "90002", and logical page 3 would correspond to logical page address "90003". ".

The instruction user interface circuit 121 converts the logical page address of 3 pages into physical page bits of 4 pages when receiving the logical page address of 3 pages and the write command of the logical page from the memory controller 200 site. In this embodiment, the instruction user interface circuit 121 converts the logical page address of the first logical page into the first cell area of the Lower page and the physical page address of the Middle page. The instruction user interface circuit 121 converts the logical page address of the second logical page into the second grid area of the Lower page and the physical page address of the Upper page. Further, the instruction user interface circuit 121 converts the logical page address of the third logical page into the third grid area of the Lower page and the physical page address of the Top page.

At this time, the data length of the three-page logical page is the same as the data length of the four-page physical page. In this embodiment, the number of logical pages to be written is a="3", and the number of physical pages to be written is b="4". Therefore, one physical page, that is, one memory group MG The page size n is represented by n=m×3/4. Also, the page sizes of the 1st to 3rd grid areas are represented by n/3, respectively. For example, when the page size of the logical page is 16[kB], the page size of the physical page is n=16×3/4=12[kB].

For example, the sequencer 123 writes the data of the logical first page according to the physical page address converted in the instruction user interface circuit 121 To the 1st grid area of the Lower page and the 1st to 3rd grid area of the Middle page of one memory group MG. The sequencer 123 writes the data of the second logical page into the second grid area of the Lower page and the first to third grid areas of the Upper page. The sequencer 123 writes the data of the third logical page into the third grid area of the Lower page and the first to third grid areas of the Top page.

Next, the arrangement of the logical page data of one memory group MG will be described in detail.

As shown in FIG. 40, in this embodiment, the data of the logical 1st page, the 2nd logical page, and the 3rd logical page are divided into four, and the data from the top are set as the first cluster to the fourth cluster. For example, memory 100 writes the 1st cluster of logical page 1 in the 1st grid area of the Lower page, writes the 2nd cluster of the logical page 1 in the 2nd grid area of the Middle page, and writes the 2nd cluster of the logical page 1 in the 2nd grid area of the Middle page. The grid area is written to the third cluster of the logical page 1, and the fourth cluster of the logical page 1 is written to the first grid area of the Middle page. Memory 100 writes the 1st cluster of the logical page 2 in the 2nd grid area of the Lower page, writes the 2nd cluster of the logical page 2 in the 3rd grid area of the Upper page, and writes the 2nd cluster of the logical page 2 in the 1st grid area of the Upper page Write to the 3rd cluster of the logical page 2, write the 4th cluster of the logical page 2 in the 2nd cell area of the upper page. Memory 100 writes the 1st cluster of the logical page 3 in the 3rd grid area of the Lower page, writes the 2nd cluster of the logical page 3 in the 1st grid area of the Top page, and writes the 2nd cluster of the logical page 3 in the 2nd grid area of the Top page Write the 3rd cluster of the logical page 3, and write the 4th cluster of the logical page 3 in the 3rd cell area of the Top page.

5.4 Read Action

Next, the read operation will be described. In this embodiment, in The read operation differs when the logical page to be read is the first logical page, when it is the second logical page, and when it is the third logical page. When the logical page is the logical first page, the physical pages to be read are the Lower page (the first grid area) and the Middle page (the first grid area to the third grid area). In this case, the memory 100 sends (outputs) the data of the first grid area of the Lower page and the data of the first to third grid areas of the Middle page to the memory controller 200 . When the logical page is the logical second page, the physical pages to be read are the Lower page (the second grid area) and the Upper page (the first grid area to the third grid area). In this case, the memory 100 sends (outputs) the data of the second grid area of the Lower page and the data of the first to third grid areas of the Upper page to the memory controller 200 . Also, when the logical page is the third logical page, the physical pages to be read are the Lower page (third grid area) and the Top page (first to third grid areas). In this case, the memory 100 sends (outputs) the data of the third grid area of the Lower page and the data of the first to third grid areas of the Top page to the memory controller 200 .

5.4.1 Flow of read operation

First, the flow of the read operation of the memory 100 will be described with reference to FIGS. 41 to 43 . 41 to 43 are flowcharts of the read operation.

As shown in FIGS. 41 to 43 , the memory 100 receives a read command of the first logical page, the second logical page, or the third logical page from the memory controller 200 (step S1 ). After the command user interface circuit 121 converts the logical page address into a physical page address, it sends the received command and the converted physical page address to the sequencer 123 .

When the logical page address is the logical page address of the first logical page (step S50_Yes), the sequencer 123 first executes the read operation of the lower page (step S51). More specifically, the sequencer 123 performs a read operation R8 corresponding to the read voltage V8.

The sequencer 123 determines the data of the Lower page according to the result of the read operation R8 (step S52).

The sequencer 123 transfers the data of the lower page read by the sensing circuits SA1 - SA3 to the latch circuits ADL1 - ADL3 respectively (step S53 ).

The sequencer 123 transfers the data of the latch circuit ADL1 (the data of the first cluster of the first logical page) to the latch circuit XDL1 (step S54 ).

The sequencer 123 sets the head address of the latch circuit XDL1 in the column counter 125 as the column address CA (step S55). The serial access controller 126 sequentially receives data from the head address of the latch circuit XDL1 according to the column address CA counted by the column counter 125 , and transfers the data to the I/O circuit 110 . The I/O circuit 110 starts sending (outputting) data to the latch circuit XDL1 of the memory controller 200 . In addition, the sequencer 123 transfers the data of the Lower page read by the sensing circuits SA1~SA3 to the latch circuits ADL1~ADL3, and then transfers the data of the latch circuit ADL1 to the latch circuit XDL1. The data of the sensing circuit SA1 is directly transferred to the latch circuit XDL1.

The sequencer 123 executes the read operation of the Middle page in parallel with the output of the data from the latch circuit XDL1 (step S56). More specifically, the sequencer 123 executes the read operation R3 corresponding to the read voltage V3, The read operation R7 corresponds to the read voltage V7, the read operation R11 corresponds to the read voltage V11, and the read operation R15 corresponds to the read voltage V15. In addition, the order of the read operations R3, R7, R11, and R15 can be set arbitrarily.

The sequencer 123 determines the data of the Middle page according to the results of the read operations R3, R7, R11 and R15 (step S57).

The sequencer 123 transfers the data of the Middle page read by the sensing circuits SA1 - SA3 to the latch circuits ADL1 - ADL3 respectively (step S58 ).

The sequencer 123 transfers the data of the latch circuits ADL2 and ADL3 (the data of the second and third clusters of the first logical page) to the latch circuits XDL2 and XDL3 respectively (step S59 ).

The sequencer 123 repeats the confirmation operation of the data output until the output of the data of the latch circuit XDL1 (the data of the first cluster of the first logical page 1) is not completed (step S60_No).

If the output of the data of the latch circuit XDL1 is completed (step S60_Yes), the sequencer 123 transfers the data of the latch circuit ADL1 (the data of the fourth cluster of the logical page 1) to the latch circuit XDL1 (step S61). The sequencer 123 sets the head address of the latch circuit XDL1 in the column counter 125 as the column address CA when the output of data from the latch circuits XDL2 and XDL3 is completed. Then, the sequencer 123 ends the read operation of the logical first page when the output of the data from the latch circuit XDL1 is completed.

When the logical page address is the logical page address of the second logical page (step S50_No and step S62_Yes), the sequencer 123 is the same as step S51, The reading operation of the Lower page is executed (step S63).

The sequencer 123 determines the data of the Lower page according to the result of the read operation R8 (step S64).

The sequencer 123 transfers the data of the lower page read by the sensing circuits SA1 - SA3 to the latch circuits ADL1 - ADL3 respectively (step S65 ).

The sequencer 123 transfers the data of the latch circuit ADL2 (the data of the first cluster of the logic page 2) to the latch circuit XDL2 (step S66). In addition, the sequencer 123 transfers the data of the Lower page read by the sensing circuits SA1~SA3 to the latch circuits ADL1~ADL3, and then transfers the data of the latch circuit ADL2 to the latch circuit XDL2. The data of the sensing circuit SA2 is directly transferred to the latch circuit XDL2.

The sequencer 123 sets the head address of the latch circuit XDL2 in the column counter 125 as the column address CA (step S67). The serial access controller 126 sequentially receives data from the head address of the latch circuit XDL2 according to the column address CA counted by the column counter 125 , and transfers the data to the I/O circuit 110 . The I/O circuit 110 starts sending (outputting) data to the latch circuit XDL2 of the memory controller 200 .

The sequencer 123 executes the read operation of the upper page in parallel with the output of the data from the latch circuit XDL2 (step S68). More specifically, the sequencer 123 executes the readout operation R2 corresponding to the readout voltage V2, the readout operation R4 corresponding to the readout voltage V4, the readout operation R6 corresponding to the readout voltage V6, and the readout operation corresponding to the readout voltage V6. The read operation R9 corresponding to the read voltage V9 and the read operation R13 corresponding to the read voltage V13. In addition, read operations R2, R4, R6, The order of R9 and R13 can be set arbitrarily.

The sequencer 123 determines the data of the Upper page according to the results of the read operations R2, R4, R6, R9 and R13 (step S69).

The sequencer 123 transfers the data of the upper page read by the sensing circuits SA1 - SA3 to the latch circuits ADL1 - ADL3 respectively (step S70 ).

The sequencer 123 transfers the data of the latch circuits ADL1 and ADL3 (the data of the second and third clusters on the second logical page) to the latch circuits XDL1 and XDL3 respectively (step S71 ).

The sequencer 123 repeats the confirmation operation of the data output until the output of the data of the latch circuit XDL2 (the data of the first cluster of the second logical page) is not completed (step S72_No).

If the output of the data of the latch circuit XDL2 is completed (step S72_Yes), the sequencer 123 transfers the data of the latch circuit ADL2 (the data of the fourth cluster on the second logical page) to the latch circuit XDL2 (step S73). The sequencer 123 sets the head address of the latch circuit XDL1 in the column counter 125 as the column address CA when the output of the data of the latch circuit XDL3 (the data of the second cluster of the second logical page) is completed. Then, when the output of the data of the latch circuit XDL1 (the data of the third cluster on the second page of logic) and the data of the latch circuit XDL2 (the data of the fourth cluster of the second page of logic) of the sequencer 123 is completed, then The read operation of the logical page 2 ends.

When the logical page address is the logical page address of the third logical page (step S50_No and step S62_No), the sequencer 123 executes the read operation of the lower page (step S74) in the same way as step S51.

The sequencer 123 determines the data of the Lower page according to the result of the read operation R8 (step S74).

The sequencer 123 transfers the data of the lower page read by the sensing circuits SA1 - SA3 to the latch circuits ADL1 - ADL3 respectively (step S76 ).

The sequencer 123 transfers the data of the latch circuit ADL3 (the data of the first cluster of the logic page 3) to the latch circuit XDL3 (step S77). In addition, the sequencer 123 transfers the data of the Lower page read by the sensing circuits SA1~SA3 to the latch circuits ADL1~ADL3, and then transfers the data of the latch circuit ADL3 to the latch circuit XDL3. The data of the sensing circuit SA3 is directly transferred to the latch circuit XDL3.

The sequencer 123 sets the head address of the latch circuit XDL3 in the column counter 125 as the column address CA (step S78). The serial access controller 126 sequentially receives data from the head address of the latch circuit XDL3 according to the column address CA counted by the column counter 125 , and transfers the data to the I/O circuit 110 . The I/O circuit 110 starts sending (outputting) data to the latch circuit XDL3 of the memory controller 200 .

The sequencer 123 executes the read operation of the Top page in parallel with the output of the data from the latch circuit XDL3 (step S79). More specifically, the sequencer 123 executes the readout operation R1 corresponding to the readout voltage V1, the readout operation R5 corresponding to the readout voltage V5, the readout operation R10 corresponding to the readout voltage V10, and the readout operation corresponding to the readout voltage V10. A readout operation R12 for outputting the voltage V12 and a readout operation R14 corresponding to the readout voltage V14. In addition, the order of the read operations R1, R5, R10, R12, and R14 can be set arbitrarily.

The sequencer 123 determines the data of the Top page according to the results of the read operations R1, R5, R10, R12 and R14 (step S80).

The sequencer 123 transfers the data of the Top page read by the sensing circuits SA1 - SA3 to the latch circuits ADL1 - ADL3 respectively (step S81 ).

The sequencer 123 transfers the data of the latch circuits ADL1 and ADL2 (the data of the second and third clusters on the third logic page) to the latch circuits XDL1 and XDL2 respectively (step S82 ).

The sequencer 123 repeats the confirmation operation of the data output until the output of the data of the latch circuit XDL3 (the data of the first cluster of the third logic page) is not completed (step S83_No).

If the output of the data of the latch circuit XDL3 is completed (step S83_Yes), the sequencer 123 transfers the data of the latch circuit ADL3 (the data of the fourth cluster on the second logical page) to the latch circuit XDL3 (step S84). In addition, the sequencer 123 sets the head address of the latch circuit XDL1 in the column counter 125 as the column address when the output of the data of the latch circuit XDL3 (the data of the first cluster on the third page of logic) is completed. ca. Then, the sequencer 123 is if the data of the latch circuit XDL1 (the data of the 2nd cluster of the logic page 3), the data of the latch circuit XDL2 (the data of the 3rd cluster of the logic page 3) and the latch circuit XDL3 When the output of the data (the data of the fourth cluster of the logical page 3) is completed, the read operation of the logical page 3 is ended.

5.4.2 Command sequence of read operation

Next, use Figure 44 to Figure 46 to explain the readout operation An example of the command sequence. Fig. 44 shows the command sequence of the read operation of the first logical page. Fig. 45 shows the command sequence of the read operation of the second logical page. Fig. 46 shows the command sequence of the read operation of the third logical page. In the examples shown in FIGS. 44 to 46 , the signals CEn, CLE, ALE, WEn, and REn are omitted to simplify the description. In addition, in the examples of FIGS. 44 to 46 , part of the commands and addresses are also omitted. Furthermore, in the examples of FIGS. 44 to 46 , the voltage of the selected word line WL when the internal RBn signal is in a busy state is also displayed.

First, the command sequence of the read operation of the first logical page will be described.

As shown in FIG. 44, the sequencer 123 responds to the command "30h" and starts the read operation. Firstly, the sequencer 123 sets the internal RBn signal and the external RBn signal to the "L" level indicating a busy state. Next, the sequencer 123 executes the read operation of the lower page (read operation R8). That is, read voltage V8 is applied to selected word line WL. The read results of the lower page are stored in the latch circuits ADL1~ADL3. Then, the data of the latch circuit ADL1 is transferred to the latch circuit XDL1. The sequencer 123 sets the external RBn signal to "H" level indicating a ready state when the read operation of the lower page is completed. Moreover, the sequencer 123 starts the reading operation of the next Middle page (reading operations R3, R7, R11, and R15) after the reading operation of the Lower page is completed. That is, read voltages V3, V7, V11, and V15 are sequentially applied to the selected word line WL.

The memory controller 200 sends a signal REn (not shown) to the memory 100 when receiving the external RBn signal of “H” level. output The input circuit 110 starts data output according to the signal REn. First, the I/O circuit 110 is a material of the output latch circuit XDL1. The sequencer 123 sets the external RBn signal to "L" once the data output from the latch circuit XDL1 is completed during the middle page read operation until the middle page read is completed.

The read results of the Middle page are stored in the latch circuits ADL1~ADL3. Then, the data of the latch circuits ADL1~ADL3 are transferred to the latch circuits XDL1~XDL3. When the read operation of the Middle page is completed, the sequencer 123 sets the external RBn signal and the internal RBn signal to "H" level.

If the memory controller 200 receives the external RBn signal of “H” level, it will restart sending the signal REn (not shown). The I/O circuit 110 outputs data in sequence from the latch circuits XDL2 , XDL3 and XDL1 according to the signal REn. When the output of data from the latch circuit XDL1 is completed, the read operation of the first logical page is completed. In addition, the memory 100 can also set the external RBn signal to be the same as the internal RBn signal, and after reading all the data, set the external RBn signal (internal RBn signal) to "H" level to output the data.

Next, the command sequence of the read operation of the logical page 2 will be described.

As shown in FIG. 45, the sequencer 123 starts the read operation according to the command "30h". Firstly, the sequencer 123 sets the internal RBn signal and the external RBn signal to the "L" level indicating a busy state. Next, the sequencer 123 executes the read operation of the lower page (read operation R8). as well as That is, the read voltage V8 is applied to the selected word line WL. The read results of the lower page are stored in the latch circuits ADL1~ADL3. Then, the data of the latch circuit ADL2 is transferred to the latch circuit XDL2. The sequencer 123 sets the external RBn signal to "H" level indicating a ready state when the read operation of the lower page is completed. Moreover, the sequencer 123 starts the reading operation of the Upper page next after the reading operation of the Lower page (reading operations R2, R4, R6, R9, and R13). That is, read voltages V2, V4, V6, V9, and V13 are sequentially applied to the selected word line WL.

The memory controller 200 sends a signal REn (not shown) to the memory 100 when receiving the external RBn signal of “H” level. The I/O circuit 110 starts data output according to the signal REn. First, the I/O circuit 110 is a material of the output latch circuit XDL2. The sequencer 123 sets the external RBn to "L" once the data output from the latch circuit XDL2 is completed while the reading operation of the upper page is being executed until the reading of the upper page is completed.

The reading result of the upper page is stored in the latch circuits ADL1-ADL3. Moreover, the data of the latch circuits ADL1~ADL3 are transferred to the latch circuits XDL1~XDL3. When the reading operation of the upper page is completed, the sequencer 123 sets the external RBn and the internal RBn to "H" level.

If the memory controller 200 receives the external RBn signal of “H” level, it will restart sending the signal REn (not shown). The I/O circuit 110 outputs data in the order of the latch circuits XDL3, XDL1, and XDL2 according to the signal REn. When the output of data from the latch circuit XDL2 is completed, the read operation of the second logical page is completed. In addition, the memory 100 can also be external The external RBn signal is set to be the same as the internal RBn signal. After reading all the data, set the external RBn signal (internal RBn signal) to "H" level to output the data.

Next, the command sequence of the read operation of the logic page 3 will be described.

As shown in FIG. 46, the sequencer 123 responds to the command "30h" and starts the read operation. Firstly, the sequencer 123 sets the internal RBn signal and the external RBn signal to the "L" level indicating a busy state. Next, the sequencer 123 executes the read operation of the lower page (read operation R8). That is, the read voltage V8 is applied to the selected word line WL. The read results of the lower page are stored in the latch circuits ADL1~ADL3. Then, the data of the latch circuit ADL3 is transferred to the latch circuit XDL3. The sequencer 123 sets the external RBn signal to "H" level indicating a ready state when the read operation of the lower page is completed. Moreover, the sequencer 123 starts the reading operation of the Top page next after the reading operation of the Lower page (reading operations R1, R5, R10, R12, and R14). That is, read voltages V1, V5, V10, V12, and V14 are sequentially applied to the selected word line WL.

The memory controller 200 sends a signal REn (not shown) to the memory 100 when receiving the external RBn signal of “H” level. The I/O circuit 110 starts data output according to the signal REn. First, the I/O circuit 110 is a material of the output latch circuit XDL3. The sequencer 123 sets the external RBn once to "L" level until the completion of the reading of the Top page when the output of the data from the latch circuit XDL3 is completed while the reading operation of the Top page is being executed.

The read results of the Top page are stored in the latch circuits ADL1~ADL3. Then, the data of the latch circuits ADL1~ADL3 are transferred to the latch circuits XDL1~XDL3. When the read operation of the Top page is completed, the sequencer 123 sets the external RBn and the internal RBn to "H" level.

If the memory controller 200 receives the external RBn signal of “H” level, it will restart sending the signal REn (not shown). The I/O circuit 110 outputs data in the order of the latch circuits XDL1, XDL2, and XDL3 according to the signal REn. When the output of the data from the latch circuit XDL3 is completed, the read operation of the logical page 3 is completed. In addition, the memory 100 can also set the external RBn signal to be the same as the internal RBn signal, and after reading all the data, set the external RBn signal (internal RBn signal) to "H" level to output the data.

5.5 Write action

Next, the writing operation will be described. In this embodiment, the data of the logical first to third pages are written into the memory group MG having the Lower page, Middle page, Upwer page and Top page at the same time. That is, 4-bit data will be written into one memory cell transistor MC at the same time. In the full sequential writing operation of this embodiment, writing in the "S1" state to the "S15" state is performed.

5.5.1 Flow of write operation

Next, the writing operation of the memory 100 will be described with reference to FIGS. 47 to 49 . 47 to 49 are flowcharts of the writing operation.

As shown in FIGS. 47 to 49 , the memory 100 receives the logical page address of the first logical page from the memory controller 200 during the acceptance of the write command (step S251 ). The instruction user interface circuit 121 converts the logical page address of the logical first page into a physical page address.

The sequencer 123 sets the head address of the latch circuit XDL1 in the column counter 125 as the column address CA (step S252 ).

In the page buffer 133, data input to the first cluster of the logical first page of the latch circuit XDL1 is started based on the column address CA received from the column counter 125 (step S253).

The sequencer 123 repeats the confirmation operation of the data input until the input of the first cluster of the logical page 1 of the latch circuit XDL1 is not completed (step S254_No).

If the data input to the latch circuit XDL1 is completed (step S254_Yes), the sequencer 123 transfers the data of the latch circuit XDL1 to the latch circuit ADL1 (step S255 ). Also, when the data input to the latch circuit XDL1 is completed, the data input to the second cluster of the logic page 1 of the latch circuit XDL2 and the data input to the third cluster of the logic page 1 of the latch circuit XDL3 are sequentially performed. data entry.

The sequencer 123 repeats the confirmation operation of the data input until the data input to the third cluster of the logic page 1 of the latch circuit XDL3 is not completed (step S256_No).

If the data input to the latch circuit XDL3 is completed (step S256_Yes), the sequencer 123 sets the head address of the latch circuit XDL1 in the column counter 125 as the column address CA (step S257).

In the page buffer 133 , according to the column address CA received from the column counter 125 , data input to the fourth cluster of the logical first page of the latch circuit XDL1 starts.

The sequencer 123 repeats the confirmation operation of the data input until the data input to the 4th cluster of the logic page 1 of the latch circuit XDL1 is not completed (step S258_No).

When the data input to the latch circuit XDL1 is completed (step S258_Yes), the data input to the logical first page of the latch circuits XDL1 to XDL3 is completed.

The sequencer 123 transfers the data of the latch circuits XDL1-XDL3 to the latch circuits BDL1-BDL3 respectively (step S259). This completes the input of data on the first logical page. In addition, the sequencer 123 can also transfer data from the latch circuit XDL1 to the latch circuit ADL1 during the data input period to the latch circuit XDL2, or can also transfer data from the latch circuit XDL3 to the latch circuit XDL3 during the data input period. The latch circuit XDL2 transfers the data to the latch circuit BDL2, or it can also transfer the data from the latch circuit XDL3 to the latch circuit BDL3 during the data input to the latch circuit XDL1, or it can also transfer the data to the latch circuit XDL2 During data input, data is transferred from the latch circuit XDL1 to the latch circuit BDL1.

Next, the memory 100 receives the logical page address of the second logical page from the memory controller 200 (step S260). At this time, the instruction user interface circuit 121 converts the logical page address of the second logical page into a physical page address.

The sequencer 123 is in the column counter 125, setting the latch voltage The head address of the way XDL2 is used as the column address CA (step S261).

In the page buffer 133, data input to the first cluster of the logical second page of the latch circuit XDL2 is started based on the column address CA received from the column counter 125 (step S262).

The sequencer 123 repeats the confirmation operation of the data input until the data input to the first cluster of the logic page 2 of the latch circuit XDL2 is not completed (step S263_No).

If the data of the first cluster of the logic page 2 of the latch circuit XDL2 is input (step S263_Yes), the sequencer 123 transfers the data of the latch circuit XDL2 to the latch circuit ADL2 (step S264 ). Also, when the data input to the latch circuit XDL2 is completed, the data input to the second cluster of the logic page 2 of the latch circuit XDL3 is performed next.

The sequencer 123 repeats the confirmation operation of the data input until the data input to the second cluster of the logic page 2 of the latch circuit XDL3 is not completed (step S265_No).

If the data input to the second cluster of the logic page 2 of the latch circuit XDL3 ends (step S265_Yes), the sequencer 123 sets the head address of the latch circuit XDL1 in the column counter 125 as the column address CA (step S266). In the page buffer 133, according to the column address CA received from the column counter 125, the data input to the third cluster of the logic page 2 of the latch circuit XDL1 and the data input to the logic page 2 of the latch circuit XDL2 are sequentially performed. Data input for the 4th cluster.

When the sequencer 123 is to the data input of the 4th cluster of the logic page 2 of the latch circuit XDL2 is not finished (step S267_No), to the input node Until the end, repeat the confirmation action of data input.

When the fourth cluster data input to the logic page 2 of the latch circuit XDL2 is completed (step S267_Yes), the data input to the logic page 2 of the latch circuits XDL1 to XDL3 is completed.

The sequencer 123 transfers the data of the latch circuits XDL1-XDL3 to the latch circuits CDL1-CDL3 respectively (step S268). In addition, the sequencer 123 can also transfer data from the latch circuit XDL2 to the latch circuit ADL2 during the data input period to the latch circuit XDL3, or can also transfer data from the latch circuit XDL1 during the data input period to the latch circuit XDL1. The latch circuit XDL3 transfers the data to the latch circuit BDL3, or it can also transfer the data from the latch circuit XDL1 to the latch circuit BDL1 during the data input to the latch circuit XDL2, or it can also transfer the data to the latch circuit XDL3. During data input, data is transferred from the latch circuit XDL2 to the latch circuit BDL2.

Next, the memory 100 receives the logical page address of the third logical page from the memory controller 200 (step S269 ). At this time, the instruction user interface circuit 121 converts the logical page address of the third logical page into a physical page address.

The sequencer 123 sets the head address of the latch circuit XDL3 in the column counter 125 as the column address CA (step S270).

In the page buffer 133, data input to the first cluster of the logical third page of the latch circuit XDL3 is started based on the column address CA received from the column counter 125 (step S271).

When the sequencer 123 is to the data input of the first cluster of the logic page 3 of the latch circuit XDL3 not finished (step S272_No), to the input node Until the end, repeat the confirmation action of data input.

If the data input to the first cluster of the third logical page of the latch circuit XDL3 is completed (step S272_Yes), the sequencer 123 transfers the data of the latch circuit XDL3 to the latch circuit ADL3 (step S273 ).

The sequencer 123 sets the head address of the latch circuit XDL1 in the column counter 125 as the column address CA (step S274). In the page buffer 133, according to the column address CA received from the column counter 125, the data input to the second cluster of the logic page 3 of the latch circuit XDL1, and the data input to the logic page 3 of the latch circuit XDL2 are sequentially performed. The data input of the 3rd cluster, and the data input of the 4th cluster of the logic page 3 of the latch circuit XDL3.

The sequencer 123 repeats the confirmation operation of the data input until the data input to the fourth cluster of the logic page 3 of the latch circuit XDL3 is not completed (step S275_No).

When the data input to the fourth cluster of the logic page 3 of the latch circuit XDL3 is completed (step S275_Yes), the data input to the logic page 3 of the latch circuits XDL1 to XDL3 is completed. The sequencer 123 sets the external RBn signal to "L" level. Moreover, the sequencer 123 determines the state of each memory cell transistor MC according to the input data of the first to third pages of logic, that is, the combination of the data of the Lower page, Middle page, Upper page, and Top page. In addition, the sequencer 123 may also transfer data from the latch circuit XDL3 to the latch circuit ADL3 during the period of data input to the latch circuit XDL1.

The sequencer 123 executes the program according to the determined state Action (step S276).

After the program operation is completed, the sequencer 123 executes the program verification operation (step S277).

If the verification is not passed (step S278_No), the sequencer 123 checks whether the number of program loops reaches the preset upper limit (step S279).

When the number of program loops does not reach the upper limit (step S279_No), the sequencer 123 executes the program (step S276). That is, the sequencer 123 is an iterative program loop.

When the number of program loops reaches the upper limit (step S279_Yes), the sequencer 123 terminates the write operation and reports to the memory controller 200 that the write operation has not been completed normally.

When the verification is passed (step S278_Yes), that is, if the writing of the “S1” state to the “S15” state is completed, the sequencer 123 sets the external RBn signal to the “H” level to end the full sequential writing operation.

5.5.2 Command sequence of write operation

Next, an example of the command sequence related to the write operation will be described using FIG. 50 . Fig. 50 shows the command sequence of the full sequential write operation. In the example of FIG. 50, the signals CEn, CLE, ALE, WEn, and REn are omitted for simplicity of description.

As shown in FIG. 50 , first, the memory controller 200 sends the command “80h” to the memory 100 . Secondly, the memory controller 200 sends the logical page address “AD-P1” of the logical page 1. 100 in memory Among them, the instruction user interface circuit 121 converts the received logical page address "AD-P1" into a physical page address.

Secondly, the memory controller 200 sends the data of the logical page 1 to the memory 100 . The first cluster of the logical page 1 is stored in the latch circuit XDL1 and then transferred to the latch circuit ADL1. The second and third clusters of the logical page 1 are stored in the latch circuits XDL2 and XDL3 and then transferred to the latch circuits BDL2 and BDL3. The fourth cluster of the logical page 1 is stored in the latch circuit XDL1 and then transferred to the latch circuit BDL1.

Next, the memory controller 200 sends the command “1Ah” to the memory 100 to notify the data input of the next logical page. Next, the memory controller 200 sends the command “80h” and the logical page address “AD-P2” of the second logical page to the memory 100 . In the memory 100, the instruction user interface circuit 121 converts the received logical page address “AD-P2” into a physical page address.

Secondly, the memory controller 200 sends the data of the second logical page to the memory 100 . The first cluster of the second logical page is stored in the latch circuit XDL2 and then transferred to the latch circuit ADL2. The second cluster of the logical page 2 is stored in the latch circuit XDL3 and then transferred to the latch circuit CDL3. The third cluster of the logic page 2 is stored in the latch circuit XDL1 and then transferred to the latch circuit CDL1. The fourth cluster of the logical page 2 is stored in the latch circuit XDL2 and then transferred to the latch circuit CDL2.

Next, the memory controller 200 sends the command “1Ah” to the memory 100 to notify the data input of the next logical page. Secondly, remember The memory controller 200 sends the command “80h” and the logical page address “AD-P3” of the third logical page to the memory 100 . In the memory 100, the instruction user interface circuit 121 converts the received logical page address “AD-P3” into a physical page address.

Secondly, the memory controller 200 sends the data of the third logical page to the memory 100 . The first cluster of the logic page 3 is stored in the latch circuit XDL3 and then transferred to the latch circuit ADL3. Cluster 2 of logic page 3 is stored in latch circuit XDL1. The 3rd cluster of logic page 3 is stored in the latch circuit XDL2. Cluster 4 of logic page 3 is stored in latch circuit XDL3.

Next, the memory controller 200 sends the command “10h” to the memory 100 indicating the execution of the writing operation.

The sequencer 123 sets the internal RBn signal and the external RBn signal to the "L" level when receiving the command "10h". Moreover, the sequencer 123 determines the state of each memory cell transistor MC according to the data stored in the latch circuits ADL1~ADL3, BDL1~BDL3, CDL1~CDL3, and XDL1~XDL3, and performs a write operation. The sequencer 123 sets the internal RBn signal and the external RBn signal to "H" level after the writing operation is completed.

5.6 Effects of this embodiment

According to the structure of this embodiment, the same effect as that of the first embodiment can be obtained.

6. The sixth embodiment

Next, the sixth embodiment will be described. In the sixth embodiment, 12 examples of coding of QLC different from the fifth embodiment are shown. In each example, in the assignment of data to Top bits, Upper bits, Middle bits, and Lower bits, there is one bit whose boundary number is one. Furthermore, the level number of bits whose level number is not 1 is coded in such a manner that the maximum value of the level number becomes the minimum. Hereinafter, the description will focus on points different from the fifth embodiment.

6.1 The first case

First, the encoding of the first example will be described using FIG.51. Fig. 51 is a table showing the assignment of data to each status.

As shown in FIG. 51, in this example, similarly to the fifth embodiment, for each state, between two adjacent states (states), 1-bit data is allocated in a manner of changing Gray codes. material.

"S0" status: "1111" data

"S1" status: "0111" data

"S2" status: "0011" data

"S3" status: "0001" data

"S4" status: "0101" data

"S5" status: "1101" data

"S6" status: "1001" data

"S7" status: "1011" information

"S8" status: "1010" information

"S9" status: "1000" data

"S10" status: "0000" data

"S11" status: "0010" data

"S12" status: "0110" data

"S13" status: "1110" information

"S14" status: "1100" information

"S15" status: "0100" data

In the case of reading the data allocated in this way, the lower page is determined by the read operation R8. The Middle page is determined by the read operations R3, R7, R9, R11 and R14. The upper page is determined by the read operations R2, R4, R6 and R12. The Top page is determined by the read operations R1, R5, R10, R13 and R15. Therefore, the distribution of the data in this example is 1-5-4-5 coding.

6.2 Case 2

Next, the encoding of the second example will be described using FIG.52. Fig. 52 is a table showing allocation of materials to each status.

As shown in FIG. 52, in this example, similarly to the fifth embodiment, for each state, between two adjacent states (states), 1-bit data can be changed into a gray coding method, Assign data.

"S0" status: "1111" data

"S1" status: "0111" data

"S2" status: "0011" data

"S3" status: "0001" data

"S4" status: "0101" data

"S5" status: "1101" data

"S6" status: "1001" data

"S7" status: "1011" information

"S8" status: "1010" information

"S9" status: "1110" information

"S10" status: "1100" information

"S11" status: "0100" data

"S12" status: "0110" data

"S13" status: "0010" data

"S14" status: "0000" data

"S15" status: "1000" data

In the case of reading the data allocated in this way, the lower page is determined by the read operation R8. The Middle page is determined by the read operations R3, R7, R10, R12 and R14. The upper page is determined by the read operations R2, R4, R6, R9 and R13. The Top page is determined by the read operations R1, R5, R11 and R15. Therefore, the distribution of the data in this example is 1-5-5-4 coding.

6.3 Case 3

Next, encoding in the third example will be described using FIG.53. Fig. 53 is a table showing allocation of data to each status.

As shown in FIG. 53, in this example, similarly to the fifth embodiment, for each state, between two adjacent states (states), 1-bit data can be changed into a gray coding method, Assign data.

"S0" status: "1111" information

"S1" status: "0111" data

"S2" status: "0011" data

"S3" status: "0001" data

"S4" status: "0101" data

"S5" status: "1101" data

"S6" status: "1001" data

"S7" status: "1011" information

"S8" status: "1010" information

"S9" status: "0010" data

"S10" status: "0000" data

"S11" status: "0100" data

"S12" status: "0110" data

"S13" status: "1110" information

"S14" status: "1100" information

"S15" status: "1000" data

In the case of reading the data allocated in this way, the lower page is determined by the read operation R8. The Middle page is determined by the read operations R3, R7, R10, R12 and R14. The upper page is determined by the read operations R2, R4, R6, R11 and R15. The Top page is determined by the read operations R1, R5, R9 and R13. Therefore, the distribution of the data in this example is 1-5-5-4 coding.

6.4 Case 4

Next, encoding in the fourth example will be described using FIG.54. Fig. 54 is a table showing allocation of data to each status.

As shown in FIG. 54, in this example, similarly to the fifth embodiment, for each state, between two adjacent states (states), 1-bit data can be changed into a gray coding method, Assign data.

"S0" status: "1111" data

"S1" status: "0111" data

"S2" status: "0011" data

"S3" status: "1011" data

"S4" status: "1001" data

"S5" status: "1101" data

"S6" status: "0101" data

"S7" status: "0001" data

"S8" status: "0000" data

"S9" status: "0010" data

"S10" status: "0110" data

"S11" status: "0100" data

"S12" status: "1100" data

"S13" status: "1110" information

"S14" status: "1010" information

"S15" status: "1000" data

In the case of reading the data allocated in this way, the lower page is determined by the read operation R8. The Middle page is determined by the read operations R4, R9, R11, R13 and R15. The Upper page is read by the action R2, R5, R7, R10 and R14 to determine. The Top page is determined by the read operations R1, R3, R6 and R12. Therefore, the distribution of the data in this example is 1-5-5-4 coding.

6.5 Case 5

Next, encoding in the fifth example will be described using FIG.55. Fig. 55 is a table showing allocation of materials to each status.

As shown in FIG. 55, in this example, similarly to the fifth embodiment, for each state, between two adjacent states (states), 1-bit data becomes a gray coded system that changes, Assign data.

"S0" status: "1111" information

"S1" status: "0111" data

"S2" status: "0011" data

"S3" status: "1011" data

"S4" status: "1001" data

"S5" status: "1101" data

"S6" status: "0101" data

"S7" status: "0001" data

"S8" status: "0000" data

"S9" status: "0010" data

"S10" status: "1010" information

"S11" status: "1000" data

"S12" status: "1100" data

"S13" status: "1110" information

"S14" status: "0110" data

"S15" status: "0100" data

In the case of reading the data allocated in this way, the lower page is determined by the read operation R8. The Middle page is determined by the read operations R4, R9, R11, R13 and R15. The upper page is determined by the read operations R2, R5, R7 and R12. The Top page is determined by the read operations R1, R3, R6, R10 and R14. Therefore, the distribution of the data in this example is 1-5-4-5 coding.

6.6 Case 6

Next, encoding in the sixth example will be described using FIG.56. Fig. 56 is a table showing allocation of data to each status.

As shown in FIG. 56, in this example, similarly to the fifth embodiment, for each state, between two adjacent states (states), 1-bit data can be changed into a gray coding system, Assign data.

"S0" status: "1111" information

"S1" status: "0111" data

"S2" status: "0011" data

"S3" status: "1011" data

"S4" status: "1001" data

"S5" status: "0001" data

"S6" status: "0101" data

"S7" status: "1101" data

"S8" status: "1100" information

"S9" status: "1110" information

"S10" status: "1010" information

"S11" status: "1000" data

"S12" status: "0000" data

"S13" status: "0010" data

"S14" status: "0110" data

"S15" status: "0100" data

In the case of reading the data allocated in this way, the lower page is determined by the read operation R8. The Middle page is determined by the read operations R4, R9, R11, R13 and R15. The upper page is determined by the read operations R2, R6, R10 and R14. The Top page is determined by the read operations R1, R3, R5, R7 and R12. Therefore, the distribution of the data in this example is 1-5-4-5 coding.

6.7 Case 7

Next, encoding in the seventh example will be described using FIG.57. Fig. 57 is a table showing allocation of data to each status.

As shown in FIG. 57, in this example, similarly to the fifth embodiment, for each state, between two adjacent states (states), 1-bit data can be changed into a gray coding system, Assign data.

"S0" status: "1111" information

"S1" status: "0111" data

"S2" status: "0011" data

"S3" status: "1011" data

"S4" status: "1001" data

"S5" status: "0001" data

"S6" status: "0101" data

"S7" status: "1101" data

"S8" status: "1100" information

"S9" status: "1000" data

"S10" status: "1010" information

"S11" status: "1110" information

"S12" status: "0110" data

"S13" status: "0100" data

"S14" status: "0000" data

"S15" status: "0010" data

In the case of reading the data allocated in this way, the lower page is determined by the read operation R8. The Middle page is determined by the read operations R4, R10, R13 and R15. The upper page is determined by the read operations R2, R6, R9, R11 and R14. The Top page is determined by the read operations R1, R3, R5, R7 and R12. Therefore, the distribution of the data in this example is 1-4-5-5 coding.

6.8 Case 8

Next, encoding in the eighth example will be described using FIG.58. Fig. 58 is a table showing the assignment of data to each status.

As shown in FIG. 58, in this example, as in the fifth embodiment, for each state, between two adjacent states (states), one bit The data of the meta will become the gray coding method of the change, and distribute the data.

"S0" status: "1111" information

"S1" status: "0111" data

"S2" status: "0011" data

"S3" status: "0001" data

"S4" status: "0101" data

"S5" status: "1101" data

"S6" status: "1001" data

"S7" status: "1011" information

"S8" status: "1010" information

"S9" status: "1000" data

"S10" status: "0000" data

"S11" status: "0100" data

"S12" status: "1100" information

"S13" status: "1110" information

"S14" status: "0110" data

"S15" status: "0010" data

In the case of reading the data allocated in this way, the lower page is determined by the read operation R8. The Middle page is determined by the read operations R3, R7, R9 and R13. The upper page is determined by the read operations R2, R4, R6, R11 and R14. The Top page is determined by the read operations R1, R5, R10, R12 and R14. Therefore, the distribution of the data in this example is 1-4-5-5 coding.

6.9 Case 9

Next, the encoding of the ninth example will be described using FIG.59. Fig. 59 is a table showing allocation of data to each status.

As shown in FIG. 59, in this example, similarly to the fifth embodiment, for each state, between two adjacent states (states), 1-bit data can be changed into a gray coding method, Assign data.

"S0" status: "1111" information

"S1" status: "0111" data

"S2" status: "0011" data

"S3" status: "1011" data

"S4" status: "1001" data

"S5" status: "0001" data

"S6" status: "0101" data

"S7" status: "1101" data

"S8" status: "1100" information

"S9" status: "1110" information

"S10" status: "1010" information

"S11" status: "1000" data

"S12" status: "0000" data

"S13" status: "0100" data

"S14" status: "0110" data

"S15" status: "0010" data

In the case of reading the data allocated in this way, the lower page is determined by the read operation R8. The Middle page is read by the read action R4, R9, R11 and R14 to determine. The upper page is determined by the read operations R2, R6, R10, R13 and R15. The Top page is determined by the read operations R1, R3, R5, R7 and R12. Therefore, the distribution of the data in this example is 1-4-5-5 coding.

6.10 Case 10

Next, the encoding of the tenth example will be described using FIG.60. Fig. 60 is a table showing allocation of data to each state.

As shown in FIG. 60, in this example, similarly to the fifth embodiment, for each state, between two adjacent states (states), 1-bit data can be changed into a gray coding method, Assign data.

"S0" status: "1111" data

"S1" status: "0111" data

"S2" status: "0011" data

"S3" status: "0001" data

"S4" status: "0101" data

"S5" status: "1101" data

"S6" status: "1001" data

"S7" status: "1011" information

"S8" status: "1010" information

"S9" status: "0010" data

"S10" status: "0000" data

"S11" status: "1000" data

"S12" status: "1100" data

"S13" status: "1110" information

"S14" status: "0110" data

"S15" status: "0100" data

In the case of reading the data allocated in this way, the lower page is determined by the read operation R8. The Middle page is determined by the read operations R3, R7, R10, R13 and R15. The upper page is determined by the read operations R2, R4, R6 and R12. The Top page is determined by the read operations R1, R5, R9, R11 and R14. Therefore, the distribution of the data in this example is 1-5-4-5 coding.

6.11 Case 11

Next, encoding in the eleventh example will be described using FIG.61. Fig. 61 is a table showing allocation of data to each status.

As shown in FIG. 61, in this example, similarly to the fifth embodiment, for each state, between two adjacent states (states), 1-bit data can be changed into a gray coding method, Assign data.

"S0" status: "1111" data

"S1" status: "0111" data

"S2" status: "0011" data

"S3" status: "1011" data

"S4" status: "1001" data

"S5" status: "1101" data

"S6" status: "0101" data

"S7" status: "0001" data

"S8" status: "0000" data

"S9" status: "0100" data

"S10" status: "0110" data

"S11" status: "1110" information

"S12" status: "1100" data

"S13" status: "1000" data

"S14" status: "1010" information

"S15" status: "0010" data

In the case of reading the data allocated in this way, the lower page is determined by the read operation R8. The Middle page is determined by the read operations R4, R10, R12 and R14. The upper page is determined by the read operations R2, R5, R7, R9 and R13. The Top page is determined by the read operations R1, R3, R6, R11 and R15. Therefore, the distribution of the data in this example is 1-4-5-5 coding.

6.12 Case 12

Next, encoding in the twelfth example will be described using FIG.62. Fig. 62 is a table showing allocation of data to each status.

As shown in FIG. 62, in this example, similarly to the fifth embodiment, for each state, between two adjacent states (states), 1-bit data can be changed into a gray coding method, Assign data.

"S0" status: "1111" information

"S1" status: "0111" data

"S2" status: "0011" data

"S3" status: "1011" data

"S4" status: "1001" data

"S5" status: "1101" data

"S6" status: "0101" data

"S7" status: "0001" data

"S8" status: "0000" data

"S9" status: "1000" data

"S10" status: "1010" information

"S11" status: "1110" information

"S12" status: "1100" information

"S13" status: "0100" data

"S14" status: "0110" data

"S15" status: "0010" data

In the case of reading the data allocated in this way, the lower page is determined by the read operation R8. The Middle page is determined by the read operations R4, R10, R12 and R14. The upper page is determined by the read operations R2, R5, R7, R11 and R15. The Top page is determined by the read operations R1, R3, R6, R9 and R13. Therefore, the distribution of the data in this example is 1-4-5-5 coding.

6.13 Effects of this embodiment

The coding of this embodiment can be applied to the fifth embodiment.

According to the configuration of this embodiment, it is possible to obtain Shi form the same effect.

7. Seventh Embodiment

Next, the seventh embodiment will be described. In the seventh embodiment, two examples of QLC readout operations different from those in the fifth embodiment will be described. Hereinafter, the description will focus on points different from the fifth embodiment.

7.1 The first case

First, the read operation of the first example will be described. In the first example, the case where the order of the read voltages applied to the selected word line WL in the read operation of the first to third pages of logic is different from that of the fifth embodiment will be described with reference to FIGS. 63 to 65. .

Fig. 63 shows the command sequence of the read operation of the first logical page. Fig. 64 shows the command sequence of the read operation of the second logical page. Fig. 65 shows the command sequence of the reading operation of the third logical page. In the examples shown in FIGS. 63 to 65 , the signals CEn, CLE, ALE, WEn, and REn are omitted to simplify the description. In addition, in the examples in FIGS. 63 to 65 , part of the commands and addresses are also omitted. Furthermore, in the examples of FIGS. 63 to 65 , the voltage of the selected word line WL when the internal RBn signal is in the busy state is also displayed.

First, the command sequence of the read operation of the first logical page will be described.

As shown in FIG. 63, the read operation (read operation R8) of the Lower page corresponding to the logical first page and the read operation (read operation R8) of the Middle page (read operation R3, R7, R11, and R15), the sequencer 123 executes the read operation in the order of R15, R11, R8, R7, and R3. That is, read voltages V15, V11, V8, V7, and V3 are sequentially applied to the selected word line WL. The sequencer 123 sets the external RBn signal and the internal RBn signal to the "H" level after the read operation R3 is completed. Therefore, after the reading operation of the Middle page is completed, the output of the read data starts.

In addition, the sequencer 123 can also execute the read operation in the order of R3, R7, R8, R11 and R15. That is, read voltages V3, V7, V8, V11, and V15 may be sequentially applied to the selected word line WL. In addition, when the sequencer 123 executes the read operation R8, since the data of the lower page is determined, the external RBn signal can also be set to "H" level to output the data.

Next, the command sequence of the read operation of the logical page 2 will be described.

As shown in FIG. 64, in the read operation of the Lower page (read operation R8) and the read operation of the Upper page (read operations R2, R4, R6, R9, and R13) corresponding to the second logical page, The sequencer 123 executes the read operation in the order of R13, R9, R8, R6, R4 and R2. That is, read voltages V13 , V9 , V8 , V6 , V4 , and V2 are sequentially applied to the selected word line WL. The sequencer 123 sets the external RBn signal and the internal RBn signal to the "H" level after the read operation R2 is completed. Therefore, after the reading operation of the Upper page is completed, the output of the read data starts.

In addition, the sequencer 123 can also execute the read operation in the order of R2, R4, R6, R8, R9 and R13. That is, for selection character lines WL sequentially applies readout voltages V2, V4, V6, V8, V9 and V13. In addition, when the sequencer 123 executes the read operation R8, since the data of the lower page is determined, the external RBn signal can also be set to "H" level to output the data.

Next, the command sequence of the read operation of the logic page 3 will be described.

As shown in FIG. 65, in the read operation of the Lower page (read operation R8) corresponding to the third logical page and the read operation of the Top page (read operations R1, R5, R10, R12, and R14), The sequencer 123 executes the read operation in the order of R14, R12, R10, R8, R5 and R1. That is, read voltages V14, V12, V10, V8, V5, and V1 are sequentially applied to the selected word line WL. The sequencer 123 sets the external RBn signal and the internal RBn signal to the "H" level after the read operation R1 is completed. Therefore, after the reading operation of the Top page is completed, the output of the read data starts.

In addition, the sequencer 123 can also execute the read operation in the order of R1, R5, R8, R10, R12, and R14. That is, read voltages V1 , V5 , V8 , V10 , V12 , and V14 may be sequentially applied to the selected word line WL. In addition, when the sequencer 123 executes the read operation R8, since the data of the lower page is determined, the external RBn signal can also be set to "H" level to output the data.

7.2 Case 2

Next, the read operation of the second example will be described. In the second example, FIG. 66 is used to explain about the Lower page, The case where the data of the Middle page, Upper page and Top page are read out at the same time. In the sequential read operation of this example, the "S0" state ~ "S15" state will be read together. Fig. 66 shows the command sequence of the sequential read operation. In the example of FIG. 66, the signals CEn, CLE, ALE, WEn, and REn are omitted for simplification of description. In addition, in the example of FIG. 66, part of the command and the address are also omitted. In addition, in the example of FIG. 66, the voltage of the selected word line WL when the internal RBn signal is in the busy state is also displayed.

As shown in FIG. 66, when the sequencer 123 receives the command "30h", it responds to this and starts the read operation. Firstly, the sequencer 123 sets the internal RBn signal and the external RBn signal to the "L" level indicating a busy state. Next, the sequencer 123 executes a sequential read operation. More specifically, the sequencer 123 executes the read operations R1 - R15 sequentially. At this time, the read voltages V1 - V15 are sequentially applied to the selected word line WL. The sequencer 123 determines the data of the Lower page when the read operation R8 is completed, and sets the external RBn signal to "H" level. The data of the Lower page is stored in the latch circuits ADL1~ADL3. The data of the latch circuit ADL1 (the data of the first cluster of the logic page 1) is transferred to the latch circuit XDL1. The memory controller 200 sends a signal REn (not shown) to the memory 100 when receiving the external RBn signal of “H” level. The I/O circuit 110 starts outputting the data of the latch circuit XDL1 (the data of the first cluster of the first logical page) according to the signal REn.

The sequencer 123 sets the external RBn signal to "L" once the data output from the latch circuit XDL1 is completed during the sequential read operation, until the sequential read is completed.

After the sequencer 123 finishes reading R13, it determines the data of the Upper page. The data of the Upper page is stored in the latch circuits CDL1~CDL3. In addition, the sequencer 123 determines the data of the Middle page after finishing the reading operation R15. The data of the Middle page is stored in the latch circuits BDL1~BDL3. The data of the latch circuit BDL2 (the data of the 2nd cluster of the logic page 1) is transferred to the latch circuit XDL2. The data of the latch circuit BDL3 (the data of the 3rd cluster of the logic page 1) is transferred to the latch circuit XDL3. The data of the latch circuit BDL1 (the data of the 4th cluster of the logic page 1) is transferred to the latch circuit XDL1.

When the sequential read operation is completed, the sequencer 123 sets the external RBn signal and the internal RBn signal to "H" level.

If the memory controller 200 receives the external RBn signal of “H” level, it will restart sending the signal REn (not shown). The I/O circuit 110 outputs data in sequence from the latch circuits XDL2 , XDL3 and XDL1 according to the signal REn. When the output of the data of the latch circuit XDL1 (the data of the fourth cluster of the first logical page) is completed, the output of the data of the first logical page is completed.

Next, the output of the data on the second logical page is started. The data of the latch circuit ADL2 (the data of the first cluster of the logic page 2) is transferred to the latch circuit XDL2. The data of the latch circuit CDL3 (the data of the 2nd cluster of the logic page 2) is transferred to the latch circuit XDL3. The data of the latch circuit CDL1 (the data of the 3rd cluster on the logic page 2) is transferred to the latch circuit XDL1. Then, the data are output in the order of the latch circuits XDL2, XDL3 and XDL1. When the output of the data of the latch circuit XDL2 (the data of the first cluster on the second page of the logic) is completed, the data of the latch circuit CDL2 (the data of the first cluster on the second page of the logic) The data of the 4th cluster) will be transferred to the latch circuit XDL2. When the output of the data of the latch circuit XDL1 (the data of the third cluster on the second logical page) is completed, the data of the latch circuit XDL2 (the data of the fourth cluster on the second logical page) is output. When the data output of the latch circuit XDL2 is completed, the data output of the logic page 2 is completed.

Next, the output of the data on the third logical page is started. The data of the latch circuit ADL3 (the data of the 1st cluster on the logic page 3) is transferred to the latch circuit XDL3. The data of the sensing circuit SA1 (the data of the 2nd cluster of the logic page 3) is transferred to the latch circuit XDL1. The data of the sensing circuit SA2 (the data of the 3rd cluster of the logic page 3) is transferred to the latch circuit XDL2. Then, the data are output in the order of the latch circuits XDL3, XDL1 and XDL2. When the output of the data of the latch circuit XDL3 (the data of the first cluster of the logic page 3) is completed, the data of the sensing circuit SA3 will be transferred to the latch circuit XDL3. When the output of the data of the latch circuit XDL2 (the data of the third cluster on the third logic page) is completed, the data of the latch circuit XDL3 (the data of the fourth cluster on the third logic page) is output. When the data output of the latch circuit XDL3 is completed, the data output of the logic page 3 is completed. In addition, in the sequential read operation, it is also possible to read out together in the order of the "S15" state to the "S0" state.

7.3 Effects of this embodiment

According to the structure of this embodiment, the same effect as that of the first embodiment can be obtained.

8. Eighth embodiment

Next, the eighth embodiment will be described. In the eighth embodiment, a case will be described in which allocation of logical page data related to physical pages is different from that in the first embodiment. Hereinafter, the description will focus on points different from the first embodiment.

8.1 Conversion action of logical page address and physical page address

An example of conversion operations between logical page addresses and physical page addresses will be described with reference to FIGS. 67 and 68 . Fig. 67 is a diagram illustrating the flow of conversion operations between logical page addresses and physical page addresses. Fig. 68 is a diagram showing allocation of logical page data to physical pages.

In this embodiment, as in the first embodiment, the case where two logical pages of data are allocated to three physical pages (that is, one memory group MG capable of storing three pages of data) will be described. .

As shown in FIG. 67 , the instruction user interface circuit 121 converts the logical page address of two pages into The physical page address of 3 pages. In this embodiment, the instruction user interface circuit 121 converts the logical page address of the first logical page into the first grid area of the Lower page, the first grid area of the Middle page, and the first grid area of the Upper page. Physical page address. In addition, the instruction user interface circuit 121 converts the logical page address of the second logical page into the physical page address of the second grid area of the Lower page, the second grid area of the Middle page, and the second grid area of the Upper page .

For example, the sequencer 123 is based on the instruction user interface The converted physical page address in the circuit 121 writes the data of the first logical page into the first grid area of the Lower page, the first grid area of the Middle page, and the first grid area of the Upper page of the memory group MG , write the data of the second logical page into the second grid area of the Lower page, the second grid area of the Middle page, and the second grid area of the Upper page.

Next, the arrangement of the logical page data of one memory group MG will be described in detail.

As shown in FIG. 68, for example, the memory 100 writes the first cluster of the logical first page in the first grid area of the Lower page, and writes the second cluster of the logical first page in the first grid area of the Middle page. , write the third cluster of logical page 1 in the first grid area of the Upper page. Also, the memory 100 writes the first cluster of the logical page 2 in the second grid area of the Lower page, writes the second cluster of the logical page 2 in the second grid area of the Middle page, and writes the second cluster of the logical page 2 in the second grid area of the Upper page. The grid area is written to the 3rd cluster of the logical 2nd page.

8.2 Effects of this embodiment

According to the structure of this embodiment, the same effect as that of the first embodiment can be obtained.

9. Ninth Embodiment

Next, the ninth embodiment will be described. In the ninth embodiment, three examples of configurations of the sense amplifier 132 and the page buffer 133 which are different from those of the first embodiment will be described. Hereinafter, the description will focus on points different from the first embodiment.

9.1 Case 1

First, the configuration of the sense amplifier 132 and the page buffer 133 in the first example will be described using FIG. 69 . FIG. 69 is a block diagram of the sense amplifier 132 and the page buffer 133 . In addition, in the example of FIG. 69, the bit line BL is omitted for simplification of description.

As shown in FIG. 69, in this example, the first grid area and the sense amplifier unit SAU1 corresponding to the first grid area, the second grid area and the sense amplifier unit SAU2 corresponding to the second grid area are alternately ground configuration. Therefore, in the memory group MG, for example, the memory cell transistor MC connected to the even-numbered bit line BL will contain the memory connected to the odd-numbered bit line BL in the first cell area. Grid transistor MC will be included in the 2nd grid area. The latch circuits XDL ( XDL1 and XDL2 ) are connected to the serial access controller 126 through the data bus, and are used for transmitting and receiving data between the serial access controller 126 and the sense amplifier 132 .

9.2 Case 2

Next, the configuration of the sense amplifier 132 and the page buffer 133 in the second example will be described using FIG. 70 . FIG. 70 is a block diagram of the sense amplifier 132 and the page buffer 133 . In addition, in the example of FIG. 70, the bit line BL is omitted for simplification of description.

As shown in FIG. 70, in this example, the latch circuits ADL (ADL1 and ADL2) and the latch circuits XDL (XDL1 and XDL2) are connected to the serial access controller 126 through the data bus, and are used in serial memory Transmit and receive data between the controller 126 and the sense amplifier 132 .

In addition, the latch circuits BDL ( BDL1 and BDL2 ) and the latch circuits XDL ( XDL1 and XDL2 ) can also be connected to the serial access controller 126 through the data bus.

9.3 Case 3

Next, the configuration of the sense amplifier 132 and the page buffer 133 in the third example will be described using FIG. 71 . FIG. 71 is a block diagram of the sense amplifier 132 and the page buffer 133 . In addition, in the example of FIG. 71, the bit line BL is omitted for simplification of description.

As shown in FIG. 71, in this example, the latch circuits ADL (ADL1 and ADL2), the latch circuits BDL (BDL1 and BDL2), and the latch circuits XDL (XDL1 and XDL2) are connected to the serial bus through the data bus. The column access controller 126 is used for transmitting and receiving data between the serial access controller 126 and the sense amplifier 132 .

9.4 Effects of this embodiment

According to the structure of this embodiment, the same effect as that of the first embodiment can be obtained.

Furthermore, according to the configuration of the first example of this embodiment, the sense amplifier unit SAU1 and the sense amplifier unit SAU2 can be alternately arranged. Thereby, data movement between the sense amplifier unit SAU1 and the sense amplifier unit SAU2 becomes possible. Such physical division (arrangement) is based on the improvement of the response speed of the circuit and the layout of the wiring between the circuits. It is performed for various reasons such as simplification and simplification of computation between latch circuits.

Furthermore, in the configurations of the second and third examples of this embodiment, the latch circuit ADL and/or the latch circuit BDL are connected to the serial access controller 126 via a data bus. Therefore, the latch circuit ADL and/or the latch circuit BDL can transmit and receive data with the serial access controller 126 without going through the latch circuit XDL. Therefore, the movement speed can be increased. Furthermore, the frequency of data transfer can be reduced, thereby reducing power consumption. In addition, in the case of QLC, the page buffer 133 may include a latch circuit CDL in addition to the latch circuits ADL, BDL, and XDL.

In addition, you may combine the 1st example and the 2nd example or the 3rd example of this embodiment.

10. The tenth embodiment

Next, the tenth embodiment will be described. In the tenth embodiment, a case where different codes are applied to the first frame area and the second frame area will be described. Hereinafter, the description will focus on points different from the first embodiment.

10.1 Conversion between logical page address and physical page address

First, an example of conversion operations between logical page addresses and physical page addresses will be described using FIG. 72 . Fig. 72 is a diagram showing allocation of logical page data to physical pages.

In this embodiment, the description will be given on the allocation of two logical pages of data to three physical pages (that is, one record that can store three pages of data) memory group MG).

As shown in FIG. 72, the data of the first logical page and the second logical page are divided into three, and the data from the top are set as the first cluster to the third cluster. For example, memory 100 writes the first cluster of logical page 1 in the first grid area of the Lower page, writes the second cluster of logical page 1 in the second grid area of the Lower page, and writes the second cluster of the logical page 1 in the second grid area of the Middle page. The grid area is written to the 3rd cluster of logical page 1. Also, the memory 100 writes the first cluster of the logical page 2 in the second grid area of the Middle page, writes the second cluster of the logical page 2 in the first grid area of the Upper page, and writes the second cluster of the logical page 2 in the first grid area of the Upper page. The grid area is written to the 3rd cluster of the logical 2nd page.

10.2 Encoding of Memory Cell Transistor

Next, the encoding of the memory cell transistor MC will be described using FIG. 73 . Fig. 73 is a table showing allocation of data to each status.

As shown in FIG. 73, in this embodiment, different codes are applied to the first frame area and the second frame area. In this case, in the read operation of the logical page, each code is selected so that the position of the boundary defined by the data of the logical page is the same in the first frame area and the second frame area.

More specifically, in the case of the read operation of the first logical page, the position of the boundary where the data of the Lower page and the Middle page are determined in the first grid area and the boundary where the data of the Lower page is determined in the second grid area The position will become the same. Also, in the case of the read operation of the second logical page, the position of the border defined by the data of the Upper page in the first grid area and the position of the border between the data of the Middle page and the Upper page in the second grid area will be the same. for the same.

For example, in the 1st cell area, data is allocated as "Upper bit/Middle bit/Lower bit" for the memory cell transistor MC as shown below.

"S0" status: "111" data

"S1" status: "011" data

"S2" status: "001" data

"S3" status: "101" data

"S4" status: "100" data

"S5" status: "000" data

"S6" status: "010" data

"S7" status: "110" data

In the case of reading the data allocated in this way, the lower page is determined by the read operation R4. The Middle page is determined by the read operations R2 and R6. The upper page is determined by the read operations R1, R3, R5 and R7. Therefore, the allocation of data in the first frame area is 1-2-4 coding.

Also, in the second cell area, data is assigned to "Upper bit/Middle bit/Lower bit" for the memory cell transistor MC as shown below.

"S0" status: "111" data

"S1" status: "101" data

"S2" status: "100" data

"S3" status: "000" data

"S4" status: "001" data

"S5" status: "011" data

"S6" status: "010" data

"S7" status: "110" information

In the case of reading the data allocated in this way, the lower page is determined by the read operations R2, R4 and R6. The Middle page is determined by the read operations R1 and R5. The upper page is determined by the read operations R3 and R7. Therefore, the allocation of data in the second grid area is 3-2-2 coding.

When the read operation of the first logical page is performed, the targets of the read operation are the first and second grid areas of the Lower page and the first grid area of the Middle page. In the first area, the data of the lower page is determined by the read operation R4. The data of the Middle page is determined by the read operations R2 and R6. Also, in the second grid area, the data of the lower page is determined by the read operations R2, R4 and R6. Therefore, the data of the first logical page is determined by the readout operations R2, R4 and R6 in both the first grid area and the second grid area. In addition, in the read operation of the first logical page, the read voltage may be applied to the selected word line WL in the order of voltages V2, V4, and V6, or the read voltage may be applied in the order of voltages V6, V4, and V2. Voltage. In addition, when the read operation R4 is completed, since the data of the first cluster of the first logical page is determined, the memory 100 can also transfer the data to the latch circuit XDL for output to the outside.

When the read operation of the second logical page is performed, the targets of the read operation are the second grid area of the Middle page and the first and second grid areas of the Upper page. In the first grid area, the data of the Upper page is determined by the read operations R1, R3, R5 and R7. In the second grid area, the resources of the Middle page The material is determined by read operations R1 and R5. The data of the Upper page is determined by the read actions R3 and R7. Therefore, the data of the second logical page is determined by the readout operations R1, R3, R5 and R7 in both the first grid area and the second grid area. In addition, in the read operation of the second logical page, read voltages may be applied to the selected word line WL in the order of voltages V1, V3, V5, and V7, or in the order of voltages V7, V5, V3, and V1. Apply the read voltage. For example, when the read voltage is applied to the selected word line WL in the order of voltages V1, V3, V5, and V7, if the read operations R1 and R5 are completed, the data of the first cluster of the second logical page is determined, so the memory The bank 100 can also transfer the data to the latch circuit XDL and output it to the outside. For example, when the read voltage is applied to the selected word line WL in the order of voltages V7, V5, V3, and V1, if the read operations R7 and R2 are completed, the data of the third cluster on the second logical page is determined, so the memory The bank 100 can also transfer the data to the latch circuit XDL and output it to the outside. In this case, for example, in the memory 100, the allocation of the first cluster of the logical second page and the allocation of the third cluster of the logical second page described with reference to FIG. 72 may be replaced. By changing the allocation, the memory 100 can output the data of the first cluster of the logical page 2 to the outside earlier than before changing the allocation.

10.3 Effects of this embodiment

According to the structure of this embodiment, the same effect as that of the first embodiment can be obtained.

Furthermore, with the configuration of this embodiment, different codes can be applied to each grid area. Further, the read action of the logical page In this, the code can be selected so that the position of the boundary defined by the data of the logical page is made the same in each grid area. This makes it possible to minimize the number of boundaries when reading data of a plurality of physical pages in a logical page read operation. Therefore, an increase in the number of reading operations can be suppressed, so that the throughput can be improved. For example, in the case of this embodiment, data can be identified by three read operations for the first logical page, and data can be confirmed by four read operations for the second logical page.

11. Eleventh Embodiment

Next, the eleventh embodiment will be described. In the eleventh embodiment, three examples will be described for the case where the data of one logical page is allocated to a plurality of physical pages. Hereinafter, the description will focus on points different from those of the first to tenth embodiments.

11.1 Case 1

First, the conversion operation between the logical page address and the physical page address in the first example will be described using FIG. 74 . Fig. 74 is a diagram showing allocation of logical page data to physical pages.

In this example, the case of allocating one logical page of data to three physical pages (that is, one memory group MG capable of storing three pages of data) will be described.

As shown in FIG. 74 , the data on the first logical page are divided into three, and the first data is set as the first cluster to the third cluster. For example, memory 100 is cluster 1 written to logical page 1 on the Lower page, and written to logical page 1 on the Middle page Into the 2nd cluster of the logical page 1, and write the 3rd cluster of the logical page 1 on the Upper page.

11.2 Case 2

Next, the conversion operation between the logical page address and the physical page address in the second example will be described.

In this example, the case where the data of one logical page is allocated to four physical pages (that is, one memory group MG capable of storing four pages of data) will be described.

First, an example of the obtained threshold voltage distribution of the memory cell transistor MC of this example will be described using FIG. 75 . FIG. 75 is a diagram showing the relationship between the threshold voltage distribution of memory cell transistor MC and the distribution of data.

As shown in Figure 75, in this example, for the memory cell transistor MC contained in each threshold voltage distribution, as follows, the data is distributed into "Top bit/Upper bit/Middle bit/Lower bit Yuan". For each state, data is allocated in such a manner that 1-bit data is changed between two adjacent states (states) in Gray code.

"S0" status: "1111" data

"S1" status: "0111" data

"S2" status: "0101" data

"S3" status: "1101" data

"S4" status: "1100" data

"S5" status: "1000" data

"S6" status: "1001" data

"S7" status: "1011" information

"S8" status: "0011" data

"S9" status: "0001" data

"S10" status: "0000" data

"S11" status: "0100" data

"S12" status: "0110" data

"S13" status: "0010" data

"S14" status: "1010" information

"S15" status: "1110" information

In the case of reading the data allocated in this way, the lower page is determined by the read operations R4, R6 and R10. The Middle page is determined by the read operations R2, R7, R9 and R12. The upper page is determined by the read operations R5, R11, R13 and R15. The Top page is determined by the read operations R1, R3, R8 and R14. Therefore, the distribution of the data in this example is 3-4-4-4 coding.

In addition, the distribution of data in the states "S0"~"S15" is not limited to 3-4-4-4 coding. For example, any of the encodings described in the fifth and sixth embodiments can also be applied.

Next, the conversion operation between the logical page address and the physical page address will be described using FIG. 76 . Fig. 76 is a diagram showing allocation of logical page data to physical pages.

As shown in FIG. 76 , the data on the first logical page are divided into four, and the first data is set as the first cluster to the fourth cluster. For example, memory 100 is to write the 1st cluster of the logical page 1 on the Lower page, write the 2nd cluster of the logical page 1 on the Middle page, write the 3rd cluster of the logical page 1 on the Upper page, and write the logical page 1 on the Top page Cluster 4 on page 1.

11.3 Case 3

Next, the conversion operation between the logical page address and the physical page address in the third example will be described.

In this example, the case of allocating data of 2 logical pages to 4 physical pages (that is, one memory group MG capable of storing 4 pages of data) will be described.

First, an example of the obtained threshold voltage distribution of the memory cell transistor MC of this example will be described with reference to FIG. 77 . FIG. 77 is a diagram showing the relationship between the threshold voltage distribution of memory cell transistor MC and the allocation of data.

As shown in Figure 77, in this example, for the memory cell transistor MC contained in each threshold voltage distribution, as follows, the data is distributed into "Top bit/Upper bit/Middle bit/Lower bit Yuan". For each state, data is allocated in such a manner that 1-bit data is changed between two adjacent states (states) in Gray code.

"S0" status: "1111" information

"S1" status: "0111" data

"S2" status: "0011" data

"S3" status: "1011" data

"S4" status: "1001" data

"S5" status: "1101" data

"S6" status: "1100" information

"S7" status: "0100" data

"S8" status: "0101" data

"S9" status: "0001" data

"S10" status: "0000" data

"S11" status: "1000" data

"S12" status: "1010" information

"S13" status: "1110" information

"S14" status: "0110" data

"S15" status: "0010" data

In the case of reading the data allocated in this way, the lower page is determined by the read operations R6, R8, and R10. The Middle page is determined by the read operations R4 and R12. The upper page is determined by the read operations R2, R5, R9, R13 and R15. The Top page is determined by the read operations R1, R3, R7, R11 and R14. Therefore, the distribution of the data in this example is 3-2-5-5 coding.

In addition, the distribution of data in the states "S0"~"S15" is not limited to 3-2-5-5 encoding. For example, any of the encodings described in the fifth and sixth embodiments can also be applied. Alternatively, the 3-4-4-4 encoding described in the second example of the eleventh embodiment can also be applied.

Next, the conversion operation between the logical page address and the physical page address will be described using FIG. 78 . Fig. 78 is a diagram showing allocation of logical page data to physical pages.

As shown in FIG. 78, the data on the logical first and second pages are divided into two, and the first data is set as the first cluster and the second cluster. For example, memory 100 is written to the first cluster of logical page 1 on the Lower page, written to the second cluster of logical page 1 on the Middle page, written to the first cluster of logical page 2 on the Upper page, and written to the first cluster of logical page 2 on the Upper page. The page is written to cluster 2 of logical page 2.

11.4 Effects of this embodiment

According to the structure of this embodiment, the same effect as that of the first embodiment can be obtained.

12. Twelfth Embodiment

Next, the twelfth embodiment will be described. In the twelfth embodiment, a case where different codes are applied to the first to third frame regions will be described. Hereinafter, the description will focus on points different from those of the first to eleventh embodiments.

12.1 Conversion action of logical page address and physical page address

First, an example of conversion operations between logical page addresses and physical page addresses will be described using FIG. 79 . Fig. 79 is a diagram showing allocation of logical page data to physical pages.

In this embodiment, a case will be described in which three logical pages of data are allocated to four physical pages (that is, one memory group MG capable of storing four pages of data).

As shown in Figure 79, divide the data on pages 1 to 3 of the logic into Do not divide into 4, set the first cluster to the fourth cluster from the previous data. For example, memory 100 writes the 1st cluster of logical page 1 in the 1st grid area of the Lower page, writes the 2nd cluster of the logical page 1 in the 2nd grid area of the Lower page, and writes the 2nd cluster of the logical page 1 in the 2nd grid area of the Lower page. The grid area is written to the 3rd cluster of logical page 1. Memory 100 writes the 4th cluster of logical page 1 in the 1st grid area of Middle page, writes the 1st cluster of logical page 2 in the 2nd grid area of Middle page, and writes the 1st cluster of logical page 2 in the 3rd grid area of Middle page Write to cluster 2 of logical page 2. Memory 100 writes the 3rd cluster of the logical page 2 in the 1st grid area of the Upper page, writes the 4th cluster of the logical page 2 in the 2nd grid area of the Upper page, and writes the 4th cluster of the logical page 2 in the 3rd grid area of the Upper page Write to cluster 1 of logical page 3. Memory 100 writes the 2nd cluster of the logical page 3 in the 1st grid area of the Top page, writes the 3rd cluster of the logical page 3 in the 2nd grid area of the Top page, and writes the 3rd cluster of the logical page 3 in the 3rd grid area of the Top page Write to cluster 4 of logical page 3.

12.2 Encoding of Memory Cell Transistor

Next, the encoding of the memory cell transistor MC will be described using FIG. 80 . Fig. 80 is a table showing allocation of data to each status.

As shown in FIG. 80, in this embodiment, different codes are applied to the first to third grid areas. In this case, in the read operation of the logical page, the respective codes are selected so that the position of the border defined by the data of the logical page is different in the first frame area, the second frame area, and the third frame area.

More specifically, in the case of the read operation of the first logical page, the data of the Lower page and the Middle page are determined in the first cell area. The position of the border, the position of the border defined by the data on the Lower page in the second frame area, and the position of the border defined by the data on the Lower page in the third frame area will be the same. In addition, in the case of the read operation of the logical second page, the position of the boundary where the data of the Upper page is specified in the first grid area, the position of the boundary where the data of the Middle page and the Upper page are specified in the second grid area, It will be the same as the position of the border determined by the data on the Middle page in the third frame area. Furthermore, in the case of the read operation of the third logical page, the position of the boundary where the data of the Top page is determined in the first grid area, the position of the boundary where the data of the Top page is determined in the second grid area, and the position of the border defined by the data of the Top page in the second grid area In the 3-frame area, the position of the border defined by the data of the Upper page and the Top page will be the same.

For example, in the first cell area, the data is allocated as "Top bit/Upper bit/Middle bit/Lower bit" for the memory cell transistor MC as follows.

"S0" status: "1111" data

"S1" status: "1101" data

"S2" status: "0101" data

"S3" status: "0100" data

"S4" status: "0000" data

"S5" status: "1000" data

"S6" status: "1100" data

"S7" status: "1110" information

"S8" status: "1010" information

"S9" status: "0010" data

"S10" status: "0110" data

"S11" status: "0111" data

"S12" status: "0011" data

"S13" status: "1011" information

"S14" status: "1001" data

"S15" status: "0001" data

In the case of reading the data allocated in this way, the lower page is determined by the read operations R3 and R11. The Middle page is determined by the read operations R1, R7 and R14. The upper page is determined by the read operations R4, R6, R8, R10 and R12. The Top page is determined by the read operations R2, R5, R9, R13 and R15. Therefore, the allocation of the data in the first grid area is 2-3-5-5 coding.

In the second grid area, for the memory grid transistor MC, as shown below, the data is allocated as "Top bit/Upper bit/Middle bit/Lower bit".

"S0" status: "1111" data

"S1" status: "1110" data

"S2" status: "0110" data

"S3" status: "0111" data

"S4" status: "0011" data

"S5" status: "1011" information

"S6" status: "1001" data

"S7" status: "1000" data

"S8" status: "1010" information

"S9" status: "0010" data

"S10" status: "0000" data

"S11" status: "0001" data

"S12" status: "0101" data

"S13" status: "1101" information

"S14" status: "1100" information

"S15" status: "0100" data

In the case of reading the data allocated in this way, the lower page is determined by the read operations R1, R3, R7, R11 and R14. The Middle page is determined by the read operations R6, R8 and R10. The upper page is determined by the read operations R4 and R12. The Top page is determined by the read operations R2, R5, R9, R13 and R15. Therefore, the allocation of data in the second grid area is 5-3-2-5 coding.

In the third grid area, for the memory grid transistor MC, as shown below, the data is allocated into "Top bit/Upper bit/Middle bit/Lower bit".

"S0" status: "1111" data

"S1" status: "1110" data

"S2" status: "0110" data

"S3" status: "0111" data

"S4" status: "0101" data

"S5" status: "0001" data

"S6" status: "0011" data

"S7" status: "0010" data

"S8" status: "0000" data

"S9" status: "1000" data

"S10" status: "1010" information

"S11" status: "1011" information

"S12" status: "1001" data

"S13" status: "1101" data

"S14" status: "1100" information

"S15" status: "0100" data

In the case of reading the data allocated in this way, the lower page is determined by the read operations R1, R3, R7, R11 and R14. The Middle page is determined by the read operations R4, R6, R8, R10 and R12. The upper page is determined by the read operations R5 and R13. The Top page is determined by the read operations R2, R9 and R15. Therefore, the allocation of the data in the third grid area is 5-5-2-3 coding.

When the read operation of the first logical page is performed, the targets of the read operation are the first to third grid areas of the Lower page and the first grid area of the Middle page. In the first area, the data of the lower page is determined by the read operations R3 and R11. The data of the Middle page is determined by the read operations R1, R7 and R14. In the second grid area, the data of the Lower page is determined by R1, R3, R7, R11 and R14. In the third grid area, the data of the Lower page is determined by R1, R3, R7, R11 and R14. Therefore, the data of the first logical page is determined by the readout operations R1 , R3 , R7 , R11 and R14 in the first grid area, the second grid area and the third grid area. In addition, in the read operation of the first logical page, the order of the read voltages applied to the selected word line WL may be voltages V1, V3, V7, V11, and The sequence of V14, or the sequence of voltages V14, V11, V7, V3 and V1. In addition, when the read operations R11 and R3 are completed, since the data of the first cluster of the logical page 1 is determined, the memory 100 can also transfer the data to the latch circuit XDL and output it to the outside.

When the read operation of the second logical page is performed, the targets of the read operation are the second and third grid areas of the Middle page and the first and second grid areas of the Upper page. In the first cell area, the data of the Upper page is determined by the read operations R4, R6, R8, R10 and R12. In the second cell area, the data of the Middle page is determined by the read operations R6, R8 and R10. The data of the Upper page is determined by the read actions R4 and R12. In the third grid area, the data of the Middle page is determined by the read operations R4, R6, R8, R10 and R12. Therefore, the data of the second logical page is determined by the readout operations R4, R6, R8, R10 and R12 in the first grid area, the second grid area and the third grid area. In addition, in the read operation of the second logical page, the order of the read voltages applied to the selected word line WL may be the order of the voltages V4, V6, V8, V10, and V12, or the order of the voltage V12. , V10, V8, V6 and V4 in sequence. In addition, when the read operations R6, R8, and R10 are completed, since the data of the first cluster of the second logical page is determined, the memory 100 can also transfer the data to the latch circuit XDL and output it to the outside. Moreover, when the read operations R4 and R12 are completed, since the data of the fourth cluster of the second logical page is determined, the memory 100 can also transfer the data to the latch circuit XDL and output it to the outside. In this case, for example, in the memory 100, the allocation of the first cluster of the logical second page and the allocation of the fourth cluster of the logical second page described with reference to FIG. 79 may be replaced. by replacing points Allocation, the memory 100 can output the data of the first cluster on the second logical page to the outside earlier than before the allocation is changed.

When the read operation of the third logical page is performed, the targets of the read operation are the third grid area of the Upper page and the first to third grid areas of the Top page. In the first grid area, the data of the Top page is determined by the read operations R2, R5, R9, R13 and R15. In the second cell area, the data of the Top page is determined by the read operations R2, R5, R9, R13 and R15. In the third grid area, the data of the Upper page is determined by the readout operations R5 and R13. The data of the Top page is determined by the read actions R2, R9 and R15. Therefore, the data on the third logical page is all through the read operations R2, R5, R9, R13 and R15 in the first grid area, the second grid area and the third grid area. In addition, in the read operation of the logic page 3, the order of the read voltages applied to the selected word line WL may be the order of the voltages V2, V5, V9, V13, and V15, or the order of the voltage V15. , V13, V9, V5 and V2 in sequence. After the read operations R13 and R5 are completed, since the data of the first cluster of the logical page 3 is determined, the memory 100 can also transfer the data to the latch circuit XDL and output it to the outside.

12.3 Effects of this embodiment

According to the configuration of this embodiment, the same effects as those of the first and tenth embodiments can be obtained. For example, in the case of this embodiment, the logical page 1 is data that can be read out 5 times, the logical page 2 is data that can be read out 5 times, and the logical page 3 is data that can be read out 5 times. Confirm the information.

13. The thirteenth embodiment

Next, the thirteenth embodiment will be described. In the thirteenth embodiment, a case where 3-bit data is stored using two memory cell transistors MC will be described. Hereinafter, the description will focus on points different from those of the first to twelfth embodiments.

13.1 Threshold Voltage Distribution of Memory Cell Transistor

First, the obtained threshold voltage distribution related to memory cell transistor MC will be described using FIG. 81 . FIG. 81 is a distribution diagram of the threshold voltage of the memory cell transistor MC.

As shown in FIG. 81, the threshold voltage of each memory cell transistor MC takes a value included in any one of discrete, for example, three distributions. That is, the memory cell transistor MC of this embodiment is 1.5bit/Cell capable of holding 3-value data. Hereinafter, the three distributions are respectively described as "S0" state, "S1" state, and "S2" state in order of lower threshold voltage.

The "S0" state is, for example, a state corresponding to data erasure. Furthermore, the "S1" and "S2" states correspond to states in which charges are injected into the charge storage layer and data is written. In the address operation, verify voltages corresponding to the respective threshold voltage distributions are V1 and V2. Therefore, the voltage values are in the relationship of V1<V2<Vread.

In addition, the set value of the verification voltage and the set value of the read voltage corresponding to each state may be the same or different. In the following, in order to simplify the description, the verify voltage and the read voltage are set to be the same The situation of fixed value will be explained.

Hereinafter, the readout operations corresponding to the readout operations in the states of S1 and S2 are respectively described as readout operations R1 and R2. The readout operation R1 is to determine whether the threshold voltage of the memory cell transistor MC is less than the full voltage V1 The readout operation R2 is to determine whether the threshold voltage of the memory cell transistor MC is less than the full voltage V2.

Hereinafter, the data corresponding to the read operation R1 (read voltage V1) will be described as "V1 data", and the data corresponding to the read operation R2 (read voltage V2) will be described as "V2 data".

As above, each memory cell transistor MC can assume three types of states by having any one of three threshold voltage distributions.

13.2 Coding

Next, the relevant encoding will be described using FIG.82. Fig. 82 is a table showing allocation of data by two memory cell transistors MC.

In this embodiment, two memory cell transistors MC are used as a combination (hereinafter also referred to as "cell unit") to hold 8-value (3-bit) data. Therefore, the cell array 130 has a configuration of 3bit/2Cell (hereinafter also referred to as "D1.5 (3-value)"). Hereinafter, the two memory cell transistors MC constituting the cell unit are described as "cell A" and "cell B", respectively. In this embodiment, the memory cell transistor MC included in the first cell area will function as "A cell", and the memory cell transistor MC included in the second cell area will function as "B cell". In addition, the unit of data written collectively to a plurality of cell units is described as "section". For example, write When data is stored in one sector, the sector size (data length) is 1/2 of the number of memory cell transistors MC included in one memory group MG. That is, the size of a sector is 1/2 the page size of a physical page.

By assigning the 8-value state of the cell to "000"~"111" in binary, the cell can hold 3-bit data. Hereinafter, the 3-bit data of a cell is described as "the first bit of the cell", "the second bit of the cell", and "the third bit of the cell". In addition, the set of the first bits of the cells of the memory group MG that are written (read) together is described as "the first sector", and the set of the second bits of the cells is described as "Second field" describes a set of 3rd bits of a cell as "3rd field".

In the example of FIG. 82, for the combination of the state of "A grid/B grid", as shown below, the data is allocated as "the first segment (the first bit of the cell unit)/the second segment ( 2nd bit of cell)/3rd segment (3rd bit of cell)".

"S0/S0" status: "111" information

"S0/S1" status: "100" data

"S0/S2" status: "000" data

"S1/S0" status: "110" information

"S1/S1" status: "101" data

"S1/S2" status: "001" data

"S2/S0" status: "010" data

"S2/S1" status: "011" data

By the combination of the states of the grid A and the grid B, 3 digits are represented state of the element. In addition, the case where A cell/B cell = "S2/S2" is defined as not used.

The bit value of the first section (the first bit of the grid unit) is read by the readout operation R2 (read voltage V2) of grid A (the first grid area) and the read operation of grid B (the second grid area). It is determined by the action R2 (reading voltage V2). In the case that the A cell or the B cell is in the "S2" state, the bit value in the first segment is assigned "0".

The bit value of the second segment (the second bit of the grid unit) is read by the readout operation R2 (read voltage V2) of grid A (the first grid area) and the read operation of grid B (the second grid area). Output action R1 (read voltage V1) to determine. When cell A is in the state of "S0" or "S1" and cell B is in the state of "S1" or "S2", the bit value in the second segment is assigned "0".

The bit value of the third segment (the third bit of the grid unit) is read by the readout operation R1 (read voltage V1) of grid A (the first grid area) and the read operation of grid B (the second grid area). Output action R1 (read voltage V1) to determine. If cell A is in "S0" state and cell B is in "S1" or "S2" state, or cell A is in "S1" or "S2" state and cell B is in "S0" state, The bit value of the segment is assigned "0".

13.3 Calculation of the bit value of the segment

Next, the calculation of the bit value of the sector will be described using FIG. 83 . Fig. 83 is a diagram showing the relationship between allocation of data for A frame and B frame and bit values of extents. In the example of FIG. 83, "&" represents logical product operation, and "~" represents negation of data.

As shown in Figure 83, the readout action R1 in A grid or B grid In this method, when the threshold voltage is higher than the read voltage V1, a "0" data is assigned as the V1 data, and when the threshold voltage is less than the read voltage V1, a "1" data is assigned as the V1 data. Also, in the readout operation R2 of grid A or grid B, when the threshold voltage is greater than or equal to the readout voltage V2, "0" data is allocated, and as V2 data, when the threshold voltage is less than the readout voltage V2, data is allocated. "1" data, as V2 data. Therefore, the bit value of each segment is calculated by the following operations.

The bit value of the first segment is the logic of negation and exclusion by reference to the read result (V2 data) of grid A using the read voltage V2 and the read result (V2 data) of grid B using the read voltage V2 And operation (EXNOR) to calculate.

The bit value of the second segment is the negated logical product of the read result of grid A using the read voltage V2 (V2 data) and the read result of grid B using the read voltage V1 (V1 data) Operation (NAND) operation to calculate.

The bit value of the third sector is the logic of negation and exclusion by reference to the read result (V1 data) of grid A using the read voltage V1 and the read result (V1 data) of grid B using the read voltage V1 And operation (EXNOR) to calculate.

13.4 Conversion between logical page address and physical page address

Next, an example of conversion operations between logical page addresses and physical page addresses will be described with reference to FIG. 84 and FIG. 85 . Fig. 84 is a diagram illustrating the flow of conversion operation between logical page addresses and physical page addresses. Figure 85 is a representation of the logic A graph of page data versus allocation of physical pages.

In this embodiment, a case will be described in which the data of one logical page is allocated to three sectors in one memory group MG.

As shown in FIG. 84, for example, when the memory controller 200 receives a write request from the host device 2, it allocates one logical page address "90001" corresponding to the received one logical address "00001". ” (logic p. 1).

Instruction user interface circuit 121 converts the logical page address of one page into The physical page address of the 3 segments. In this case, the data length of one logical page is the same as the data length of three sectors.

The page size of a logical page of 1 page is set to m (m is an integer greater than 1), and the number of logical pages to be written (that is, the number of logical page addresses included in the command) is set to a (a is greater than 1 integer). Also, set the page size of the physical page of one memory group MG as n (n is an integer smaller than m), and set the number of sectors (that is, the bits that can be held by the group of A grid and B grid) arity) is set to c (c is an integer greater than a). Therefore, since the page size n of one physical page is twice the size of the extent (the number of cells), it is represented by n=m×2a/c. In this embodiment, since a=1 and c=3, the page size of a physical page is n=m×2/3. For example, when the page size of the logical page is 16[kB], the page size of the physical page is n=16×2/3=10.67[kB]. In this case, the number of memory cell transistors MC that can realize the page size n=10.67[kB] of one physical page is an integer equal to or greater than the integer value rounded up from the decimal point of 10.67×1024 value. That is, the number of memory cell transistors MC is an integer value equal to or greater than an integer value obtained by rounding up the decimal point of the page size of one physical page.

Next, the arrangement of the logical page data of one memory group MG will be described in detail.

As shown in Fig. 85, the data on the first logical page is divided into three, and the first data is set as the first cluster to the third cluster. For example, the memory 100 writes the data of the first cluster in the first sector, writes the data of the second cluster in the second sector, and writes the data of the third cluster in the third sector. In this embodiment, the data in the first segment is the data corresponding to the first cluster on the first logical page, the data on the second segment is the data corresponding to the second cluster on the first logical page, and the third segment The material is the material corresponding to the 3rd cluster of the logical 1st page.

13.5 Configuration of Sense Amplifier and Page Buffer

Next, the structure of the sense amplifier 132 and the page buffer 133 will be briefly described. The cell array 130 of the present embodiment has a 3bit/2Cell configuration in which cell A of the first cell area and cell B of the second cell area are combined. Therefore, the configuration of the sense amplifier 132 and the page buffer 133 is preferably a configuration in which the sense amplifier units SAU1 and SAU2 are alternately arranged as described in the first example of the ninth embodiment using FIG. 69 . This is because it is easier to design the corresponding sense circuit SA and latch circuits XDL, ADL, and BDL that are physically close to each other when computing the data of grid A and grid B.

13.6 Read Action

Next, the reading operation will be described. In the read operation of this embodiment, when the memory 100 receives a read command based on a logical page from the memory controller 200, it reads data from the corresponding plurality of physical pages, calculates the read data to calculate the area After the segments, the segments are synthesized and output as logical page data.

13.6.1 Flow of read operation

First, the flow of the read operation of the memory 100 will be described with reference to FIGS. 86 and 87 . 86 and 87 are flowcharts of the read operation.

As shown in FIG. 86 and FIG. 87, the memory 100 receives a read command of the first logical page from the memory controller 200 (step S1). After the command user interface circuit 121 converts the logical page address into a physical page address, it sends the received command and the converted physical page address to the sequencer 123 .

The sequencer 123 first executes the read operation R2 corresponding to the read voltage V2 (step S90).

The sequencer 123 transfers the data (V2 data) read by the sensing circuits SA1 and SA2 to the latch circuits BDL1 and BDL2 respectively (step S91 ).

Sequencer 123 is to use the data of latch circuit BDL1 (V2 data of A grid) and the data of latch circuit BDL2 (V2 data of B grid) to calculate the data of the first section (logic page 1 Resources for cluster 1 of material) (step S92).

The sequencer 123 transfers the calculated data of the first segment to the latch circuit XDL1 (step S93).

The sequencer 123 executes the read operation R1 corresponding to the read voltage V1 (step S94).

The sequencer 123 transfers the data (V1 data) read by the sensing circuits SA1 and SA2 to the latch circuits ADL1 and ADL2 respectively (step S95 ).

Sequencer 123 is to perform operation processing using the data of latch circuit BDL1 (V2 data of A grid) and the data of latch circuit ADL2 (V1 data of B grid), and calculates the data of the second section (logic page 1 The data of the 2nd cluster) (step S96).

The sequencer 123 transfers the calculated data of the second sector to the latch circuit XDL2 (step S97).

The sequencer 123 performs calculation processing using the data of the latch circuit ADL1 (the V1 data of the A grid) and the data of the latch circuit ADL2 (the V1 data of the B grid), and calculates the data of the third segment (logic page 1 The data of the 3rd cluster) (step S98).

The sequencer 123 transfers the calculated data of the third sector to the latch circuit BDL1 (step S99).

The sequencer 123 sets the head address of the latch circuit XDL1 in the column counter 125 as the column address CA (step S100 ). The serial access controller 126 receives data sequentially from the head address of the latch circuit XDL1 according to the column address CA counted by the column counter 125, and transfers them to the I/O circuit 110. The I/O circuit 110 starts to send (output) the data of the latch circuit XDL1 (the data of the first cluster of the logic page 1) to the memory controller 200 .

When the data output of the latch circuit XDL1 is not completed (step S101_No), the sequencer 123 repeats the confirmation operation of the data output until the output is completed.

If the data output of the latch circuit XDL1 is finished (step S101_Yes), the sequencer 123 transfers the data of the latch circuit BDL1 to the latch circuit XDL1 (step S102 ). Moreover, when the output of the data of the latch circuit XDL1 is completed, the output of the data of the latch circuit XDL2 (the data of the second cluster of the logical page 1) starts next.

When the data output of the latch circuit XDL2 is not completed (step S103_No), the sequencer 123 repeats the confirmation operation of the data output until the output is completed.

If the data output of the latch circuit XDL2 is completed (step S103_Yes), the head address of the latch circuit XDL1 is set in the column counter 125 as the column address CA (step S104). The serial access controller 126 sequentially receives data from the head address of the latch circuit XDL1 according to the column address CA counted by the column counter 125 , and transfers the data to the I/O circuit 110 . The I/O circuit 110 starts to send (output) the data of the latch circuit XDL1 (the data of the third cluster on the logic page 1) to the memory controller 200 . The sequencer 123 ends the read operation of the first logical page when the output of the data from the latch circuit XDL1 is completed. In addition, after the read operation R2 is completed, during the period of performing the read operation R1, since the data of the first sector is determined, the memory 100 is also The external RBn signal can be set to "H" level to output data.

13.6.2 Command Sequence of Read Operation

Next, an example of the command sequence related to the read operation will be described using FIG. 88 . Fig. 88 shows the command sequence of the read operation of the first logical page. In the example of FIG. 88, the signals CEn, CLE, ALE, WEn, and REn are omitted for simplicity of description. Also, in the example of FIG. 88, part of the command and the address are omitted. Further, in the example of FIG. 88, the voltage of the selected word line WL when the internal RBn signal is in the busy state is also displayed.

As shown in FIG. 88, when the sequencer 123 receives the command "30h", it responds to this and starts a read operation. Firstly, the sequencer 123 sets the internal RBn signal and the external RBn signal to the "L" level indicating a busy state. Next, the sequencer 123 executes the read operation R2. That is, the read voltage V2 is applied to the selected word line WL. The result of reading the data (V2 data) is stored in the latch circuits BDL1 (corresponding to the A grid) and BDL2 (corresponding to the B grid).

The sequencer 123 executes the read operation R1 after the read operation R2 is completed. That is, the read voltage V1 is applied to the selected word line WL. The result of reading data (V1 data) is stored in the latch circuits ADL1 (corresponding to grid A) and ADL2 (corresponding to grid B).

While the read operation R1 is being executed, the sequencer 123 performs arithmetic processing using the data of the latch circuit BDL1 and the data of the latch circuit BDL2 to calculate the data of the first sector. The calculated data is stored in the latch circuit XDL1.

The sequencer 123 sets the internal RBn signal and the external RBn signal to the "H" level indicating the ready state when the read operation R1 is completed. Moreover, the sequencer 123 performs arithmetic processing using the data of the latch circuit BDL1 and the data of the latch circuit ADL2, and calculates the data of the 2nd sector. The calculated data is stored in the latch circuit XDL2.

The memory controller 200 sends a signal REn (not shown) to the memory 100 when receiving the external RBn signal of “H” level. The I/O circuit 110 starts data output according to the signal REn. First, the I/O circuit 110 is the data of the output latch circuit XDL1 (the data of the first cluster on the logic page 1).

While the data of the latch circuit XDL1 is being output, the sequencer 123 performs arithmetic processing using the data of the latch circuit ADL1 and the data of the latch circuit ADL2 to calculate the data of the third segment. The calculated data is stored in the latch circuit BDL1.

When the data output of the latch circuit XDL1 is finished, the data of the latch circuit BDL1 will be transferred to the latch circuit XDL1. The I/O circuit 110 is connected to the latch circuit XDL1 and outputs the data of the latch circuit XDL2 (the data of the second cluster of the logic page 1). Furthermore, the I/O circuit 110 is connected to the latch circuit XDL2, and outputs the data of the latch circuit XDL1 (the data of the third cluster on the first logical page). When the data of the latch circuit XDL1 is completed, the read operation of the first logical page is completed.

In addition, the order of applying the read voltages V1 and V2 can also be changed. In addition, when the output of the data from the latch circuit XDL2 is completed before the data of the third sector is stored in the latch circuit BDL1, the sequencer 123 It is also possible to interrupt data output once the external RBn signal is set to "L" level. In addition, after the read operation R2 is completed, during the period of executing the read operation R1, since the data of the first segment is determined, the memory 100 can also set the external RBn signal to "H" level to output data.

13.7 Write action

Next, the writing operation will be described. In this embodiment, a full sequential write operation in which the data of the first to third sectors are collectively written into the memory group MG is performed. That is, in the full sequential writing operation of this embodiment, writing in the "S1" and "S2" states is performed.

13.7.1 Flow of write operation

Next, the flow of the write operation in the memory 100 will be described using FIGS. 89 and 90 . 89 and 90 are flowcharts of the writing operation.

As shown in FIGS. 89 and 90 , the memory 100 receives the logical page address of the logical first page from the memory controller 200 during the acceptance of the write command (step S280 ). The instruction user interface circuit 121 converts the logical page address of the logical first page into a physical page address.

The sequencer 123 sets the head address of the latch circuit XDL1 in the column counter 125 as the column address CA (step S281).

In the page buffer 133, data input to the first cluster of the logical first page of the latch circuit XDL1 is started based on the column address CA received from the column counter 125 (step S282).

When the data input to the latch circuit XDL1 is not completed (step S283_No), the sequencer 123 repeats the confirmation operation of the data input until the input is completed.

If the data input to the latch circuit XDL1 is completed (step S283_Yes), the sequencer 123 transfers the data of the latch circuit XDL1 to the latch circuit BDL1 (step S284 ). Also, when the data input to the latch circuit XDL1 is completed, the data input to the second cluster of the logical first page of the latch circuit XDL2 starts next. In addition, in the case of step S283_Yes, the data input to the second cluster of the logic page 1 of the latch circuit XDL2 may be started next, and the sequencer 123 executes step S284 during the data input period.

When the data input to the latch circuit XDL2 is not completed (step S285_No), the sequencer 123 repeats the confirmation operation of the data input until the input is completed.

If the data input to the latch circuit XDL2 is completed (step S285_Yes), the sequencer 123 transfers the data of the latch circuit XDL2 to the latch circuit BDL2 (step S286 ).

The sequencer 123 sets the head address of the latch circuit XDL1 in the column counter 125 as the column address CA (step S287). In the page buffer 133 , based on the column address CA received from the column counter 125 , data input to the third cluster of the logical first page of the latch circuit XDL1 starts. In addition, in the case of step S285_Yes, the data input to the third cluster of the logic page 1 of the latch circuit XDL1 may be started next, and the sequencer 123 executes step S286 during the data input period.

When the data input to the latch circuit XDL1 is not completed by the sequencer 123 (step S288_No), the confirmation operation of the data input is repeated until the input is completed.

When the data input to the latch circuit XDL1 is completed (step S288_Yes), the data input to the logical first page of the latch circuits XDL1 and XDL2 is completed. The sequencer 123 sets the external RBn signal and the internal RBn signal to "L" level.

The sequencer 123 calculates the data of the latch circuits BDL1, BDL2 and XDL1, that is, the data of the first sector, the second sector and the third sector, and calculates the V1 data of the A grid and the B grid (step S289). The calculated V1 data of grid A and grid B are respectively transferred to latch circuits ADL1 and ADL2 (step S290 ).

The sequencer 123 calculates the data of the operation latch circuits BDL1, BDL2 and XDL1, that is, the data of the 1st segment, the 2nd segment and the 3rd segment, and calculates the V2 data of the A grid and the B grid (step S291) . The calculated V2 data of the A frame and the B frame are respectively transferred to the latch circuits XDL1 and XDL2 (step S292 ). At this time, the data of the third segment is stored in the latch circuit XDL1, but the data of the V2 of the A cell can also be overwritten. The sequencer 123 determines the state of each memory cell transistor MC according to the combination of the data of the latch circuits ADL1, ADL2, XDL1 and XDL2.

The sequencer 123 executes the program operation according to the determined state (step S293).

After the program operation is completed, the sequencer 123 performs a program verification operation (step S294).

If the verification is not passed (step S295_No), the sequencer 123 checks whether the number of program loops reaches the preset upper limit (step S296).

When the number of program loops does not reach the upper limit (step S296_No), the sequencer 123 executes the program (step S293). That is, the sequencer 123 is an iterative program loop.

When the number of program loops reaches the upper limit (step S296_Yes), the sequencer 123 ends the writing operation and reports to the memory controller 200 that the writing operation has not been completed normally.

When the verification is passed (step S295_Yes), that is, if the writing of the “S1” and “S2” states ends, the sequencer 123 sets the external RBn signal to the “H” level to end the full sequential writing operation.

13.7.2 Command Sequence of Write Action

Next, an example of the command sequence related to the write operation will be described using FIG. 91 . Fig. 91 shows the command sequence of the full sequential write operation. In the example of FIG. 91 , the signals CEn, CLE, ALE, WEn, and REn are omitted for simplicity of description.

As shown in FIG. 91 , first, the memory controller 200 sends the command “80h” to the memory 100 . Secondly, the memory controller 200 sends the logical page address “AD-P1” of the logical page 1. In the memory 100, the instruction user interface circuit 121 converts the received logical page address “AD-P1” into a physical page address. Secondly, the memory controller 200 sends the data of the logical page 1 to the memory 100 . Cluster 1 of logical page 1 is the After being stored in the latch circuit XDL1, it is transferred to the latch circuit BDL1. Next, the second cluster of the logical page 1 is stored in the latch circuit XDL2 and then transferred to the latch circuit BDL2. Cluster 3 of logic page 1 is stored in latch circuit XDL1.

Secondly, the memory controller 200 sends the command “10h” to the memory 100 .

The sequencer 123 sets the internal RBn signal and the external RBn signal to the "L" level when the command "10h" is received.

The sequencer 123 performs operations on the V1 data based on the data stored in the latch circuits BDL1, BDL2, and XDL1, and stores the result in the latch circuits ADL1 and ADL2. Also, the sequencer 123 performs calculations on the V2 data based on the data stored in the latch circuits BDL1, BDL2, and XDL1, and stores the result in the latch circuits XDL1 and XDL2. The sequencer 123 determines the state of each memory cell transistor MC according to the combination of the data of the latch circuits ADL1, ADL2, XDL1 and XDL2, and executes the write operation. The sequencer 123 sets the internal RBn signal and the external RBn signal to "H" level after the writing operation is completed.

13.8 Effects of this embodiment

According to the structure of this embodiment, the same effect as that of the first embodiment can be obtained.

For example, the memory 100 may have a multi-valued (2~4bit/Cell) memory area and a memory area for high speed and high reliability. For example, the high-speed and high-reliability memory area is for accessing high It is used as binary value (1bit/Cell) memory data for speed-up or high-reliability data. Although it is also possible to set the high-speed and high-reliability memory areas of the first to twelfth embodiments as binary values (1bit/Cell), since the page size of the physical page of the multi-valued memory area is smaller than the logical page size Small, so the logical pages of the high-speed high-reliability memory area will become smaller. In this case, the first to twelfth embodiments can also be applied to a multivalued memory area, and this embodiment can be applied to a high-speed/high-reliability memory area. Thereby, the page size of the logical page of the multivalued memory area and the page size of the logical page of the high-speed/high-reliability memory area can be set to be the same.

In addition, the allocation of 3-bit data stored in 2 grids and 3 values is, for example, described in US Patent Application No. 16/123, No. 162 filed on September 6, 2018 in "Semiconductor Memory (SEMICONDUCTOR MEMORY)" . This patent application is its entirety used by reference in this case description.

In addition, in this embodiment, the case where the memory cell transistor MC holds 3-bit data by 3-value 2-cell (1.5 bit/Cell) is described, but it is not limited to this. For example, the memory grid transistor MC can also use 6-value 2 grids (2.5bit/Cell) to keep 5-bit data, or can also use 12-value 2 grids (3.5bit/Cell) to keep 7-bit data, or 23-value or 24-value 2 cells (4.5bit/Cell) can also be used to hold 9-bit data.

14. Modifications, etc.

The semiconductor memory of the above-mentioned embodiment is to comprise: memory group (MG), and it is to contain the memory group (MG) that can be more than 3 A plurality of memory cells (MC) that hold data of a plurality of bits in a plurality of states; word lines (WL), which are connected to the plurality of memory cells; 200) The received one external address (logical page address) is converted into a plurality of internal addresses (physical page address).

The size of the first page of the page data (data of the physical page) that the memory group can hold is smaller than the size of the second page of the input data (data of the logical page) corresponding to the external address.

By applying the above-described embodiments, it is possible to provide a semiconductor memory capable of suppressing an increase in chip area.

In addition, embodiment is not limited to the form demonstrated above, Various deformation|transformation is possible.

For example, in each code, "0" data and "1" data may be reversed.

For example, in the above-mentioned first to twelfth embodiments, an example in which the memory cell transistor MC is 2 to 4 bits/Cell is described, but the present invention is not limited thereto. For example, the memory cell transistor MC can also be 5bit/Cell. Also, the memory grid transistor MC can also use 6-value 2-grid (2.5bit/Cell) to keep 5-bit data, or can also use 12-value 2-grid (3.5bit/Cell) to keep 7-bit data, or 23-value or 24-value 2 cells (4.5bit/Cell) can also be used to hold 9-bit data.

For example, the memory 100 is not limited to NAND flash memory. The memory 100 is as long as only in the address space of the memory grid array It is only necessary to select the address of a part of the word line to perform the read operation or the non-volatile memory for the write operation. For example, the memory 100 may be PCM (Phase Change Memory), MRAM (Magnetoresistive Random Access Memory), or FeRAM (Ferroelectric Random Access Memory).

In addition, in the above-mentioned first to twelfth embodiments, the 8-value or 16-value state is written in one write operation, but in order to suppress the influence of adjacent cells, for example, two write steps may be used. to write. In this case, when the influence of the adjacent cells is large, after the writing operation of the first page of the first word line (WLn), the writing operation of the first page of the adjacent second word line (WLn+1) is performed, Then, the write operation of the second page on the first word line (WLn) is performed. For example, in the case of the tenth embodiment, as shown in FIG. 92 , during the writing operation of the first logical page, the memory cell transistor MC in the first cell area is transferred to the first logical page of the Lower page. Cluster 1 and data written to cluster 3 on the logical first page of the Middle page are written in state S0, S2, S4 or S6. On the other hand, the memory cell transistor MC in the second cell area is written into the state S0 or S2 by writing data to the second cluster of the logical first page of the lower page. In addition, the state of the write operation of the logical page 1 may be lower than the state of the write operation of the logical page 2. Also, the step-up voltage amount of the programming operation of the first logical page may be larger than the step-up voltage amount of the programming operation of the logical second page. Then, during the write operation of the second logical page, the data written in the write operation of the first logical page is read out through the internal read operation, and the memory cell transistor MC in the first cell area is If the writing data of the second cluster of the logical second page of the Upper page is written into the state S0, it is written into the state When S0 or S1 is written to state S2, it is written to state S2 or S3, when it is written to state S4, it is written to state S4 or S5, and when it is written to state S6, it is Write to state S6 or S7. The memory cell transistor MC in the second grid area is written into the state S0 by writing data to the first cluster of the logical second page of the Middle page and to the third cluster of the second logical page of the Upper page. In case, it is written in state S0, S1, S4, or S5, and in case of state S2, it is written in state S2, S3, S6, or S7. In addition, if the read operation is performed before the write operation of the logical page 2 and after the write operation of the logical page 1, the Vth distribution after the write operation of the logical page 2 will not be written, so it becomes Incorrect information. Therefore, it is also possible to separately set the read command at this time, or prepare a flag grid for each page, and change the read level.

For example, the above-mentioned embodiments can be combined as much as possible.

In addition, the so-called "connection" in the above-mentioned embodiments also includes a state of being indirectly connected with something else such as a transistor or a resistor.

The embodiments are illustrative, and the scope of the invention is not limited thereto.

Claims (7)

A semiconductor memory characterized by comprising: a memory group comprising a plurality of cells capable of holding data of a plurality of bits in more than three states; a word line connected to the plurality of cells memory cells; and a first circuit, which transforms one external address received from the external controller into plural internal addresses. The size of the first page of the page data that the aforementioned memory group can hold is smaller than the size of the second page of the input data corresponding to the aforementioned external address. The semiconductor memory according to claim 1, wherein the input data is written into at least 2 bits of a part of the plurality of memory cells. The semiconductor memory as described in Claim 1 or 2, wherein, if the size of the aforementioned second page is set to m, the number of pages of the aforementioned input data contained in the command received from the aforementioned external controller is set to a, and the aforementioned The number of pages of the aforementioned page data that the memory group can hold is set to b, and the size of the aforementioned first page is set to n, then n=m×a/b. The semiconductor memory as described in Claim 1 or 2, wherein, in the read operation, the plurality of aforementioned page data is read from the aforementioned memory group, at least a part of the read aforementioned plurality of page data is synthesized, and the output is outputted. synthetic data. The semiconductor memory according to claim 1 or 2, wherein at least one bit among the plurality of bits of the plurality of cells is read out by one readout operation using one readout voltage Sure. A semiconductor memory, characterized by having: a memory group comprising a plurality of first memory cells and a plurality of second memory cells; a word line connected to the plurality of first memory cells and the aforementioned A plurality of second memory cells; and a first circuit, which converts one external address received from an external controller into a plurality of internal addresses, the first page of the page data that the aforementioned memory group can hold The size is smaller than the size of the second page of the input data corresponding to the aforementioned external address, and can be kept complex by combining any one of the aforementioned plurality of first memory cells with any one of the aforementioned plurality of second memory cells digital data. The semiconductor memory as described in claim 6, wherein, if the size of the second page is set to m, the number of pages of the input data included in the command received from the external controller is set to a, and the combination of the aforementioned The number of bits that can be held is set as c, and the aforementioned first page size is set as n, then n=m×2a/c.

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