TWI778864B - Gate driving circuit and display panel - Google Patents

Abstract

A gate driving circuit and a panel are disclosed. An n-th shift register of the gate driving circuit includes an emitting signal generating circuit, an emitting signal controlling circuit, a reset signal generating circuit, and a reset signal controlling circuit. The emitting signal generating circuit has a node outputting an emitting signal to a pixel array. The emitting signal controlling circuit and the reset signal generating circuit are coupled to the node. During a first reset period, the reset signal generating circuit generates an enabled resetting signal in response to the emitting signal. During a second reset period, the emitting signal controlling circuit disables the resetting signal in response to the emitting signal.

Description

Gate drive circuit and display panel

The present invention relates to a gate driving circuit and a display panel, and more particularly, to a gate driving circuit and a display panel which can reduce the occupied space.

Generally speaking, a gate driving circuit in a display panel outputs a light-emitting signal to drive pixels. At the same time, the light-emitting signal will cooperate with the reset signal to make the pixel light up or not. However, the current circuit for generating the reset signal and the gate driving circuit are controlled by different control signals. Therefore, when multiple pixels are set to balance the variable luminous efficiency, it is also necessary to set multiple control circuits to control the reset signal and the luminous signal correspondingly, which reduces the configurable circuit space of the display panel and is not conducive to the display of the zero-frame design. panel.

Embodiments of the present invention provide a gate driving circuit, which can increase the circuit space that can be configured on a display panel.

The gate driving circuit of the embodiment of the present invention has a multi-stage shift temporary storage circuit. The shift temporary storage circuit of the nth stage includes a light-emitting signal generating circuit, a light-emitting signal control circuit circuit, a reset signal generating circuit and a reset signal control circuit. The light-emitting signal generating circuit has a first node to output the light-emitting signal to the pixel array. During the period from the first light-emitting stage to the second light-emitting stage, the light-emitting signal generating circuit enables the light-emitting signal. The lighting signal control circuit is coupled to the first node. During the period from the first reset phase to the second reset phase, the lighting signal control circuit maintains the voltage level of the lighting signal as a disabled voltage level. The reset signal generating circuit is coupled to the first node. During the first reset phase, the reset signal generating circuit generates an enabled reset signal in response to the light-emitting signal. The reset signal control circuit is coupled to the lighting signal control circuit and the reset signal generating circuit. During the second reset phase, the reset signal control circuit is responsive to the lighting signal to disable the reset signal.

Embodiments of the present invention further provide a display panel. The display panel includes a pixel array and the gate driving circuit of the above embodiment. The gate driving circuit is coupled to the pixel array.

Based on the above, the gate driving circuit and the display panel according to the embodiments of the present invention generate the reset signal according to the light-emitting signal. In this way, the circuit for generating the light-emitting signal and the circuit for generating the reset signal are integrated, and the gate driving circuit and the display panel do not need to be additionally provided with a control circuit to generate the reset signal, so as to reduce the number of gate driving circuits. The circuit space occupied by itself increases the configurable circuit space on the display panel.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.

100, 500: Display panel

110, 210: Lighting signal generating circuit

120, 220: Lighting signal control circuit

130, 230: reset signal generating circuit

140, 240: reset signal control circuit

C1, C2: capacitors

CK: clock signal

EM(n+1): Post-stage lighting signal

EM(n-1): Pre-stage luminous signal

EM(1), EM(2), EM(n): luminescence signal

GC: gate drive circuit

GC_1, GC_2, GC_n: Shift temporary storage circuit

ND1, ND2, ND3, ND4: Nodes

P(n): first control signal

P(n+1): The first control signal of the latter stage

P(n-1): The first control signal of the previous stage

PEM1, PEM2, PRT1, PRT2: Period

PXL: pixel array

PXL_1, PXL_2: Subpixel array

Q(n): the second control signal

R: Resistor

RST(1), RST(2), RST(n): reset signal

T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13: Transistor

VGH1, VPH: disable voltage level

VGL, VGH: voltage signal

VGL1, VGL2, VPL: enable voltage level

FIG. 1A is a block diagram of a display panel according to an embodiment of the present invention.

FIG. 1B is a block diagram of the n-th stage of the shift register circuit according to the embodiment of FIG. 1A of the present invention.

FIG. 2 is a circuit diagram of the n-th stage shift register circuit according to the embodiment of FIG. 1B of the present invention.

3 is a schematic diagram of the operation of the n-th stage of the shift register circuit shown in the embodiment of FIG. 2 according to the present invention.

4A to 4D are schematic diagrams illustrating operations of the n-th stage of the shift register circuit according to the embodiment of FIG. 3 of the present invention.

FIG. 5 is a block diagram of a display panel according to another embodiment of the present invention.

Some embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Element symbols quoted in the following description will be regarded as the same or similar elements when the same element symbols appear in different drawings. These examples are only a part of the invention and do not disclose all possible embodiments of the invention. Rather, these embodiments are only examples within the scope of the patent application of the present invention.

Please refer to FIG. 1A . FIG. 1A is a block diagram of a display panel according to an embodiment of the present invention. In this embodiment, the display panel 100 includes a pixel array PXL and a gate driving circuit GC. The gate drive circuit GC has a multi-level shift temporary storage circuit GC_1, GC_2, ..., GC_n. The multi-stage shift register circuits GC_1 ˜GC_n are sequentially coupled together. The shift register circuits GC_1 ˜GC_n of each stage are coupled to the pixel array PXL. Specifically, the first-stage shift register circuit GC_1 outputs the first-stage light-emitting signal EM( 1 ) and the reset signal RST( 1 ) to the first pixel row in the pixel array PXL. The second-stage shift register circuit GC_2 outputs the second-stage light-emitting signal EM( 2 ) and the reset signal RST( 2 ) to the second pixel row in the pixel array PXL, and so on. The shift register circuit GC_n of the n-th stage outputs the light-emitting signal EM(n) of the n-th stage and the reset signal RST(n) to the corresponding pixel row in the pixel array PXL.

In this embodiment, the shift register circuits GC_1 ˜GC_n of each stage may have the same circuit structure.

Please refer to FIG. 1B together. FIG. 1B is a block diagram of the n-th stage of the shift register circuit according to the embodiment of FIG. 1A of the present invention. In this embodiment, the n-th stage of the shift buffer circuit GC_n includes a lighting signal generating circuit 110 , a lighting signal controlling circuit 120 , a reset signal generating circuit 130 and a reset signal controlling circuit 140 . The lighting signal generating circuit 110 has a node ND1. The node ND1 of the lighting signal generating circuit 110 outputs the lighting signal EM(n) to the pixel array PXL. In this embodiment, the light-emitting signal generating circuit 110 is used for enabling the light-emitting signal EM(n) to drive the pixel array PXL during the corresponding light-emitting phase.

The lighting signal control circuit 120 is coupled to the node ND1. In this embodiment, during the reset phase, the light-emitting signal control circuit 120 maintains the light-emitting signal EM(n) at a disabled voltage level.

The reset signal generating circuit 130 is coupled to the node ND1. reset signal generation The circuit 130 has an output terminal for outputting the reset signal RST(n) to the pixel array PXL. In the present embodiment, in the early stage of the reset phase, the reset signal generating circuit 130 generates the enabled reset signal RST(n) in response to the light-emitting signal EM(n) to reset the pixel array PXL.

The reset signal control circuit 140 is coupled to the lighting signal control circuit 120 . The reset signal control circuit 140 is coupled to the output end of the reset signal generation circuit 130 . The reset signal control circuit 140 has an input terminal to receive the lighting signal EM(n). In the present embodiment, in the later period of the reset phase, the reset signal control circuit 140 is responsive to the light emission signal EM(n) to disable the reset signal RST(n) to stop resetting the pixel array PXL.

In this embodiment, the lighting phase occurs before the reset phase.

It is worth mentioning here that the reset signal generating circuit 130 and the reset signal control circuit 140 enable or disable the reset signal RST(n) according to the light-emitting signal EM(n). In this way, the shift register circuit GC_n of the n-th stage does not need to set an additional circuit to generate the reset signal RST(n). Therefore, the circuit for generating the light-emitting signal EM(n) and the circuit for generating the reset signal RST(n) are integrated in the same shift register circuit GC_n of the n-th stage to reduce the shift of the n-th stage. The circuit space occupied by the bit buffer circuit GC_n increases the configurable circuit space on the display panel 100 to facilitate the design of the display panel 100 with a zero border.

Please refer to FIG. 2 . FIG. 2 is a circuit diagram of the n-th stage of the shift register circuit according to the embodiment of FIG. 1B of the present invention. In this embodiment, the shift temporary storage circuit GC_n of the nth stage includes a light-emitting signal generating circuit 210, a light-emitting signal control circuit 220, The reset signal generation circuit 230 and the reset signal control circuit 240 are provided.

In this embodiment, the reset signal generating circuit 230 includes transistors T1, T2 and a capacitor C1. The control terminal of the transistor T1 is coupled to the node ND1. The transistor T1 is controlled by the signal on the node ND1 (ie, the light-emitting signal EM(n)) to perform switching operations. The first end of the transistor T1 receives the first control signal P(n-1) of the previous stage. The second end of the transistor T1 and the reset signal control circuit 240 are coupled to the node ND2. The control terminal of the transistor T2 is coupled to the node ND2. The transistor T2 is controlled by the signal on the node ND2 to perform switching operations. The first end of the transistor T2 receives the clock signal CK. The second end of the transistor T2 outputs the reset signal RST(n). The first end of the capacitor C1 is coupled to the node ND2. The second end of the capacitor C1 is coupled to the second end of the transistor T2. In this embodiment, the second terminal of the capacitor C1 and the second terminal of the transistor T2 are used as the output terminals of the reset signal generating circuit 230 to output the reset signal RST(n).

In this embodiment, the reset signal control circuit 240 includes transistors T3, T4 and T5. The control terminal of the transistor T3 receives the first control signal P(n+1) of the subsequent stage. The first end of the transistor T3 is coupled to the node ND2. The second terminal of the transistor T3 receives the voltage signal VGH. In this embodiment, the voltage signal VGH may be referred to as the first voltage signal VGH. The control terminal of the transistor T4 is coupled to the control terminal of the transistor T3. The transistors T3 and T4 are controlled together by the first control signal P(n+1) of the subsequent stage to perform switching operations. The first terminal of the transistor T4 is coupled to the second terminal of the transistor T2 and the second terminal of the capacitor C1 (ie, the output terminal of the reset signal generating circuit 230 ). The second terminal of the transistor T4 receives the voltage signal VGH. The control terminal of the transistor T5 receives the light-emitting signal EM(n). The transistor T5 is controlled by the light-emitting signal EM(n) to perform switching operations. in this In the embodiment, the control terminal of the transistor T5 is used as the input terminal of the reset signal control circuit 240 . The first end of the transistor T5 is coupled to the second end of the transistor T2 and the second end of the capacitor C1. The second terminal of the transistor T5 receives the voltage signal VGH.

In this embodiment, the light-emitting signal generating circuit 210 includes transistors T6, T7 and a capacitor C2. The control terminal of the transistor T6 receives the clock signal CK. The transistor T6 is controlled by the clock signal CK to perform switching operations. The first end of the transistor T6 receives the pre-stage light-emitting signal EM(n-1). The second end of the transistor T6 is coupled to the node ND3. The first end of the capacitor C2 receives the post-stage lighting signal EM(n+1). The second end of the capacitor C2 is coupled to the node ND3. The control terminal of the transistor T7 is coupled to the node ND3. The transistor T7 is controlled by the signal on the node ND3 (ie, the second control signal Q(n)) to perform switching operations. The first terminal of the transistor T7 receives the voltage signal VGL. In this embodiment, the voltage signal VGL may be referred to as the second voltage signal VGL. The second end of the transistor T7 is coupled to the node ND1. In this embodiment, the second terminal of the transistor T7 is used as the output terminal of the light-emitting signal generating circuit 210 to output the light-emitting signal EM(n).

In this embodiment, the lighting signal control circuit 220 includes transistors T8 , T9 , T10 , T11 , T12 , T13 and a resistor R. The control terminal of the transistor T8 is coupled to the first terminal of the transistor T8. The control terminal and the first terminal of the transistor T8 receive the clock signal CK. The transistor T8 is coupled in a diode configuration and receives the clock signal CK. The control end of the transistor T9 receives the preceding stage lighting signal EM(n-1). The transistor T9 is controlled by the previous-stage light-emitting signal EM(n-1) to perform switching operations. The first end of the transistor T9 is coupled to the second end of the transistor T8. The second terminal of the transistor T9 receives the voltage signal VGH. The control terminal of the transistor T10 is coupled to the second terminal of the transistor T8 and the transistor The first end of body T9. The first terminal of the transistor T10 is coupled to the control terminal and the first terminal of the transistor T8. The second end of the transistor T10 is coupled to the first end of the resistor R. The second end of the resistor R is coupled to the node ND4. The control terminal of the transistor T11 receives the second control signal Q(n). The transistor T11 is controlled by the second control signal Q(n) to perform switching operations. The first end of the transistor T11 is coupled to the node ND4. The second terminal of the transistor T11 receives the voltage signal VGH. The control terminal of the transistor T12 is coupled to the node ND4. The first end of the transistor T12 is coupled to the node ND3. The second terminal of the transistor T12 receives the voltage signal VGH. The control terminal of the transistor T13 is coupled to the control terminal of the transistor T12 (ie, the node ND4). The transistors T12 and T13 are jointly controlled by the signal on the node ND4 (ie, the first control signal P(n)) to perform switching operations. The first end of the transistor T13 is coupled to the node ND1. The second terminal of the transistor T13 receives the voltage signal VGH.

In this embodiment, the voltage signals VGH and VGL are different constant voltage signals. In this embodiment, the voltage signal VGH has a disabled voltage level to disable any one of the transistors T1 ˜ T13 . The voltage signal VGL has an enabled voltage level to enable any one of the transistors T1 ˜ T13 . The voltage signal VGH may have a relatively high voltage level, and the voltage signal VGL may have a relatively low voltage level.

Please refer to FIG. 3 and FIGS. 4A to 4D . FIG. 3 is a schematic diagram illustrating the operation of the n-th stage of the shift register circuit according to the embodiment of FIG. 2 of the present invention. 4A to 4D are schematic diagrams illustrating operations of the n-th stage of the shift register circuit according to the embodiment of FIG. 3 of the present invention. In FIG. 3 , the horizontal axis is the operation time of the n-th stage shift buffer circuit GC_n, and the vertical axis is the voltage value.

Regarding the period of the shift register circuit GC_n of the nth stage in the first light-emitting stage For details of operations in the PEM1, please refer to FIG. 3 and FIG. 4A at the same time. During the first light-emitting phase period PEM1, the light-emitting signal EM(n) has an enable voltage level VGL2. In this embodiment, the enabling voltage level VGL2 is shown in the following formula (1): VGL2=VGL1+2×|VTH|...Formula (1)

In formula (1), VGL1 is expressed as the voltage level of the voltage signal VGL (ie, the enable voltage level VGL1 ). VTH represents the threshold voltage level of any one of the transistors T1 to T13. In this embodiment, the voltage signal VGH has a disable voltage level VGH1.

The enabled light-emitting signal EM(n) turns on the transistors T1 and T5. The turned-on transistor T1 outputs the first control signal P(n-1) of the previous stage to the control terminal of the transistor T2. The first control signal P(n-1) of the previous stage has a disable voltage level VPH. The disabled first control signal P(n-1) of the preceding stage turns off the transistor T2. The post-stage first control signal P(n+1) has an enable voltage level VPL. The enabled first control signal P(n+1) of the subsequent stage turns on the transistors T3 and T4. The turned-on transistors T3 and T4 respectively pull the signals across the capacitor C1 to the voltage signal VGH (ie, the disable voltage level VGH1 ) to disable the reset signal RST(n).

On the other hand, in the period PEM1 of the first light-emitting stage, the previous-stage light-emitting signal EM(n-1) has an enable voltage level VGL1. The enabled front-stage light-emitting signal EM(n-1) turns on the transistor T9. The turned-on transistor T9 pulls the signal on the control terminal of the transistor T10 to the voltage signal VGH (ie, the disable voltage level VGH1) to turn off the transistor T10. The clock signal CK has an enable voltage level VGL1. The clock signal CK enables the transistors T6 and T8 to be turned on. Transistor T6 being turned on will node The second control signal Q(n) on the ND3 is pulled to the enabled pre-emission signal EM(n-1) (ie, the enable voltage level VGL1) to turn on the transistor T7. The enabled second control signal Q(n) turns on the transistor T11. The turned-on transistor T11 pulls the first control signal P(n) on the node ND4 to the voltage signal VGH (ie, the disable voltage level VGH1) to turn off the transistors T12, T13. The turned-on transistor T7 pulls the light-emitting signal EM(n) to the voltage signal VGL (ie, the enable voltage level VGL1 ) to output the enabled light-emitting signal EM(n).

Please refer to FIG. 3 and FIG. 4B for details of the operation of the n-th stage of the shift buffer circuit GC_n in the period PEM2 of the second light-emitting stage. During the second light-emitting phase PEM2, the subsequent first control signal P(n+1) has a disable voltage level VPH. The disabled first control signal P(n+1) of the subsequent stage turns off the transistors T3 and T4. The light-emitting signal EM(n) has an enable voltage level VGL1. The enabled light-emitting signal EM(n) turns on the transistors T1 and T5. The turned-on transistor T1 outputs the first control signal P(n-1) of the previous stage to the node ND2. The first control signal P(n-1) of the previous stage has an enabling voltage level VPL. The enabled first control signal P(n-1) of the previous stage turns on the transistor T2. The clock signal CK has a disable voltage level VGH1 so that the turned-on transistor T2 outputs the disabled reset signal RST(n).

On the other hand, in the period PEM2 of the second light-emitting stage, the previous-stage light-emitting signal EM(n-1) has a disable voltage level VGH1. The disabled pre-stage light-emitting signal EM(n-1) turns off the transistor T9. The transistor T10 remains turned off. The clock signal CK has a disable voltage level VGH1. The clock signal CK can turn off the transistors T6 and T8. Transistor T6, which is turned off, floats node ND3. Thus, electricity The container C2 can couple the change of the subsequent stage lighting signal EM(n+1) to the node ND3 to change the signal on the node ND3. At this time, the subsequent-stage light-emitting signal EM(n+1) has an enable voltage level VGL2. Through the capacitor C2, the enabled post-stage lighting signal EM(n+1) can pull down the second control signal Q(n) on the node ND3 to turn on the transistor T7. The enabled second control signal Q(n) turns on the transistor T11. The turned-on transistor T11 pulls the first control signal P(n) on the node ND4 to the voltage signal VGH (ie, the disable voltage level VGH1) to turn off the transistors T12, T13. The turned-on transistor T7 pulls the light-emitting signal EM(n) to the voltage signal VGL (ie, the enable voltage level VGL1 ) to output the enabled light-emitting signal EM(n).

Please refer to FIG. 3 and FIG. 4C for details of the operation of the n-th stage shift register circuit GC_n in the period PRT1 of the first reset phase. During the period PRT1 of the first reset phase, the light-emitting signal EM(n) has a disable voltage level VGH1. The disabled light-emitting signal EM(n) turns off the transistors T1, T5. The post-stage first control signal P(n+1) has a disable voltage level VPH. The disabled first control signal P(n+1) of the subsequent stage turns off the transistors T3 and T4. The turned-off transistors T1, T3 float node ND2. As such, capacitor C1 may couple changes in reset signal RST(n) to node ND2 to change the signal on node ND2. At this time, the reset signal RST(n) may have the enable voltage level VGL1. The enabled reset signal RST(n) can turn on the transistor T2. At this time, when the clock signal CK has the enable voltage level VGL1, the turned-on transistor T2 can output the enabled reset signal RST(n).

On the other hand, during the period PRT1 of the first reset phase, the previous The level emitting signal EM(n-1) has a disable voltage level VGH1. The disabled pre-stage light-emitting signal EM(n-1) can turn off the transistor T9. At this time, the clock signal CK has the enable voltage level VGL1. The clock signal CK enables the transistors T6 and T8 to be turned on. The turned-on transistor T6 pulls the second control signal Q(n) on the node ND3 to the previous-stage light-emitting signal EM(n-1) (ie, the disable voltage level VGH1), thereby turning off the transistors T7 and T11 . The turned-on transistor T8 pulls the signal on the control terminal of the transistor T10 to the clock signal CK (ie, the enable voltage level VGL1 ) to turn on the transistor T10 . The turned-on transistor T10 pulls the first control signal P(n) on the node ND4 to the clock signal CK to turn on the transistors T12 and T13. The turned-on transistor T12 pulls the second control signal Q(n) on the node ND3 to the voltage signal VGH (ie, the disable voltage level VGH1) to maintain the second control signal Q(n) on the node ND3 at Disable voltage level VGH1. The turned-on transistor T13 pulls the emission signal EM(n) on the node ND1 to the voltage signal VGH (ie, the disable voltage level VGH1) to disable the emission signal EM(n).

Please refer to FIG. 3 and FIG. 4D for details of the operation of the n-th stage shift register circuit GC_n in the period PRT2 of the second reset phase. During the period PRT2 of the second reset phase, the light-emitting signal EM(n) has a disable voltage level VGH1. The disabled light-emitting signal EM(n) turns off the transistors T1, T5. The post-stage first control signal P(n+1) has an enable voltage level VPL. The enabled first control signal P(n+1) of the subsequent stage turns on the transistors T3 and T4. The turned-on transistors T3, T4 respectively pull the signal on both ends of the capacitor C1 to the voltage signal VGH (ie, the disable voltage level VGH1) to turn off the transistor T2 and disable the reset signal RST(n) .

On the other hand, in the period PRT2 of the second reset phase, the previous-stage light-emitting signal EM(n-1) has a disable voltage level VGH1. The disabled pre-stage light-emitting signal EM(n-1) turns off the transistor T9. The clock signal CK has a disable voltage level VGH1. At this time, the clock signal CK can turn off the transistors T6 and T8. The transistor T10 remains turned off. The first control signal P(n) on the node ND4 maintains the signal of the previous period PRT1 (ie, the clock signal CK with the enabling voltage level VGL1 ), and keeps the transistors T12 and T13 turned on. The turned-on transistor T12 pulls the second control signal Q(n) on the node ND3 to the voltage signal VGH (ie, the disable voltage level VGH1) to maintain the signal on the node ND3 at the disable voltage level VGH1 and above Turn off the transistors T7 and T11. The turned-on transistor T13 pulls the emission signal EM(n) on the node ND1 to the voltage signal VGH (ie, the disable voltage level VGH1) to disable the emission signal EM(n).

In this embodiment, the transistors T1 ˜ T13 are implemented by p-type Metal-Oxide-Semiconductor Field-Effect Transistor (PMOSFET). In other embodiments, the transistors T1 - T13 are implemented as N-type metal-oxide-semi-field-effect transistors (NMOSFETs). In other embodiments the signals are reversed to the corresponding signals in this embodiment.

Please refer to FIG. 5 , which is a block diagram of a display panel according to another embodiment of the present invention. In this embodiment, the display panel 500 includes a pixel array PXL and a gate driving circuit GC. The pixel array PXL includes sub-pixel arrays PXL_1 and PXL_2. In a plan view, the gate driving circuit GC is disposed between the sub-pixel arrays PXL_1 and PXL_2. Regarding the implementation details of the gate drive circuit GC, in the aforementioned implementation The example has been described in detail and will not be repeated here.

To sum up, the gate driving circuit and the circuit for generating the light-emitting signal and the circuit for generating the reset signal of the display panel according to the embodiments of the present invention are integrated in the same shift register circuit. In addition, the gate driving circuit and the display panel can generate the reset signal according to the light-emitting signal. In this way, the gate driving circuit and the display panel can save additional circuits for controlling the reset signal. Therefore, the shift register circuit of each stage has an integrated circuit structure, so as to increase the configurable circuit space on the display panel and help to design a zero-frame display panel. In some embodiments, the gate driving circuit is disposed between adjacent sub-pixel arrays.

Although the present invention has been disclosed above by the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the scope of the appended patent application.

110: Lighting signal generation circuit

120: Lighting signal control circuit

130: Reset signal generation circuit

140: reset signal control circuit

EM(n): luminescence signal

GC_n: Shift temporary storage circuit

ND1: Node

RST(n): reset signal

Claims (15)

A gate drive circuit has a multi-stage shift temporary storage circuit, wherein the n-th stage of the shift temporary storage circuit comprises: a light-emitting signal generating circuit having a first node to output a light-emitting signal to a pixel array, wherein in the During a period from a first light-emitting stage to a second light-emitting stage, the light-emitting signal generating circuit enables the light-emitting signal; a light-emitting signal control circuit is coupled to the first node, wherein a first reset stage to a During the second reset phase, the light-emitting signal control circuit maintains the voltage level of the light-emitting signal as a disabled voltage level; a reset signal generating circuit is coupled to the first node, wherein the first During the reset phase, the reset signal generating circuit generates an enabled reset signal in response to the light-emitting signal; and a reset signal control circuit is coupled to the light-emitting signal control circuit and the reset signal generating circuit The circuit, wherein during the second reset phase, the reset signal control circuit is responsive to the lighting signal to disable the reset signal. The gate driving circuit of claim 1, wherein the reset signal generating circuit comprises: a first transistor having a control end coupled to the first node, and a first end of the first transistor receives a pre- A first control signal, the second end of the first transistor and the reset signal control circuit are coupled to a second node; a second transistor has a control end coupled to the second node, the second The first end of the transistor receives a clock signal, and the second end of the second transistor outputs the reset signal; and a first capacitor having a first end coupled to the second node, and a second end of the first capacitor coupled to the second end of the second transistor. The gate driving circuit of claim 2, wherein the reset signal control circuit comprises: a third transistor having a control terminal to receive a first control signal of a subsequent stage, and the first terminal of the third transistor is coupled to At the second node, the second terminal of the third transistor receives a first voltage signal; a fourth transistor has a control terminal coupled to the control terminal of the third transistor, and the third transistor of the fourth transistor has a control terminal. One end is coupled to the second end of the second transistor, the second end of the fourth transistor receives the first voltage signal; and a fifth transistor has a control end to receive the light-emitting signal, the fifth transistor The first end of the crystal is coupled to the second end of the second transistor, and the second end of the fifth transistor receives the first voltage signal. The gate driving circuit of claim 3, wherein during the first reset stage, the light-emitting signal is disabled to turn off the first transistor and the fifth transistor, and the subsequent stage first The control signal is disabled to turn off the third transistor and the fourth transistor to make the second node floating, the first capacitor changes the signal on the second node to turn on the second transistor, when The pulse signal is enabled so that the second transistor outputs the enabled reset signal. The gate drive circuit of claim 3, wherein during the second reset phase, the light-emitting signal is disabled to turn off the first transistor and the fifth a transistor, the post-stage first control signal is enabled to turn on the third transistor and the fourth transistor to pull the signal on both ends of the first capacitor to the first voltage signal to make the reset signal Disabled. The gate driving circuit of claim 3, wherein during the first light-emitting stage, the light-emitting signal is enabled to turn on the first transistor and the fifth transistor, and the pre-stage first control signal is disabled to turn off the second transistor, and the post-stage first control signal is enabled to turn on the third transistor and the fourth transistor to pull the signal across the first capacitor to the first A voltage signal to disable the reset signal. The gate driving circuit of claim 3, wherein during the second light-emitting stage, the first control signal of the latter stage is disabled to turn off the third transistor and the fourth transistor, and the light-emitting The signal is enabled to turn on the first transistor and the fifth transistor, the pre-stage first control signal is enabled to turn on the second transistor, the clock signal is disabled so that the output of the second transistor is disabled This reset signal is disabled. The gate driving circuit of claim 1, wherein the light-emitting signal generating circuit comprises: a sixth transistor having a control terminal to receive a clock signal, and a first terminal of the sixth transistor to receive a previous-stage light-emitting signal, The second end of the sixth transistor is coupled to a third node; a second capacitor has a first end that receives a post-stage lighting signal, and the second end of the second capacitor is coupled to the third node; and a seventh transistor having a control terminal coupled to the third node, the seventh transistor The first end of the body receives a second voltage signal, and the second end of the seventh transistor is coupled to the first node. The gate driving circuit of claim 8, wherein the light-emitting signal control circuit comprises: an eighth transistor having a control terminal and a first terminal to receive the clock signal; a ninth transistor having a control terminal to receive the clock signal a pre-stage light-emitting signal, the first end of the ninth transistor is coupled to the second end of the eighth transistor, and the second end of the ninth transistor receives the first voltage signal; a tenth transistor has The control end is coupled to the second end of the eighth transistor, the first end of the tenth transistor is coupled to the control end and the first end of the eighth transistor; a resistor has a first end coupled to At the second end of the tenth transistor, the second end of the resistor is coupled to a fourth node; an eleventh transistor has a control end to receive a second control signal, and the eleventh transistor has a second end. The first end is coupled to the fourth node, the second end of the eleventh transistor receives the first voltage signal; a twelfth transistor has a control end coupled to the fourth node, the twelfth transistor The first end of the transistor is coupled to the third node, the second end of the twelfth transistor receives the first voltage signal; and a thirteenth transistor has a control end coupled to the fourth node, The first end of the thirteenth transistor is coupled to the first node, and the second end of the thirteenth transistor receives the first voltage signal. The gate driving circuit of claim 9, wherein during the first reset phase, the pre-stage light-emitting signal is disabled to turn off the ninth transistor, and the clock signal is enabled to turn on The sixth transistor and the eighth transistor turn off the seventh transistor and the eleventh transistor and turn on the tenth transistor, and the signal on the fourth node is enabled to turn on the twelfth transistor The transistor and the thirteenth transistor pull the light-emitting signal to the first voltage signal to disable the light-emitting signal. The gate driving circuit of claim 9, wherein during the second reset phase, the pre-stage light-emitting signal is disabled to turn off the ninth transistor, and the clock signal is disabled to turn off the The sixth transistor and the eighth transistor are turned off, the tenth transistor, the seventh transistor and the eleventh transistor are turned off, the twelfth transistor and the thirteenth transistor are turned on to pull the light-emitting signal to the first voltage signal to disable the light-emitting signal. The gate driving circuit of claim 9, wherein during the first light-emitting stage, the pre-stage light-emitting signal is enabled to turn on the ninth transistor to turn off the tenth transistor, and the clock The signal is enabled to turn on the sixth transistor and the eighth transistor, the second control signal is enabled to turn on the eleventh transistor to pull the signal on the fourth node to the first voltage signal To turn off the twelfth transistor and the thirteenth transistor, the seventh transistor is turned on to pull the light-emitting signal to the second voltage signal to output the enabled light-emitting signal. The gate driving circuit of claim 9, wherein during the second light-emitting stage, the previous-stage light-emitting signal is disabled to turn off the ninth transistor, the tenth transistor is turned off, and the The clock signal is disabled to turn off the sixth transistor and the The eighth transistor makes the third node floating, the second capacitor changes the signal on the third node to turn on the seventh transistor and enable the second control signal, the eleventh transistor is turned on to The signal on the fourth node is pulled to the first voltage signal to turn off the twelfth transistor and the thirteenth transistor, and the seventh transistor pulls the light-emitting signal to the second voltage signal to The enabled light-emitting signal is output. A display panel, comprising: a pixel array; and the gate driving circuit according to claim 1, coupled to the pixel array. The display panel of claim 14, wherein the pixel array comprises a first sub-pixel array and a second sub-pixel array, and the gate driving circuit is disposed in the first sub-pixel array and the second sub-pixel array between subpixel arrays.

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