TWI766211B - Configuration load and unload of a reconfigurable data processor - Google Patents

Abstract

A reconfigurable data processor comprises a bus system, and an array of configurable units connected to the bus system, configurable units in the array including configuration data stores to store unit files comprising a plurality of sub-files of configuration data particular to the corresponding configurable units. Configurable units in the plurality of configurable units each include logic to execute a unit configuration load process, including receiving via the bus system, sub-files of a unit file particular to the configurable unit, and loading the received sub-files into the configuration store of the configurable unit. A configuration load controller connected to the bus system, including logic to execute an array configuration load process, including distributing a configuration file comprising unit files for a plurality of the configurable units in the array.

Description

Configuration Loading and Unloading for Reconfigurable Data Processors

The present technology relates to the configuration of reconfigurable architectures, and in particular, can be applied to the configuration of coarse-grain reconfigurable architectures.

Reconfigurable processors, including Field Programmable Gate Arrays (FPGAs), can be configured to implement a wide variety of functions more efficiently or possibly faster than is possible using general purpose processors to execute computer programs. So-called coarse-grained reconfigurable architectures (such as CGRAs) are being developed in which the configurable elements in an array are more complex than those used in typical, finer-grained FPGAs, and may enable faster or more Execution of various categories of efficiency. For example, CGRA has been proposed for its implementation of accelerators that could enable energy efficiency for machine learning and artificial intelligence workloads. See Prabhakar et al., “Plasticine: A Reconfigurable Architecture for Parallel Patterns,” ISCA ’17, June 24-28, 2017, Toronto, ON, Canada.

Configuration of reconfigurable processors involves the compilation of configuration descriptions to generate configuration files (sometimes referred to as bitstreams or bit files), and distribution of configuration files to configurable units on the processor. To start a process, the configuration file must be loaded for the process. To change a process, the configuration file must be replaced by a new configuration file.

The procedures and support structures for distributing and loading configuration files can be complex, and the execution of the procedures can be time-consuming.

In order to maximize operational efficiency and enable program swapping on reconfigurable processors, a means of efficiently loading configuration states and storing configuration and program states is required.

Describes a technique that enables processing of coarse-grained reconfigurable array processors containing programmable elements arranged in grids, tiles, and other types of reconfigurable processors. Efficient loading and unloading of configuration and control states.

The techniques described herein provide the ability to load configuration data from a formatted configuration file stored in memory and transfer it to a reconfigurable processor via a combination of parallel and serial techniques. Likewise, the techniques described herein provide an efficient means of uninstalling program control and data status into similarly formatted uninstall configuration files. In summary, loading and unloading techniques can support protocols to rapidly swap programs in and out of reconfigurable processors to enable time-sharing and other virtualization techniques.

The configuration and reconfiguration procedures and structures described herein may be used for a reconfigurable processor, which includes a busbar system, and configurable units connected to one or more arrays of the busbar system. Configurable cells in one or more arrays include configuration data storage (implemented using serial chains such as latches) to store configuration data (referred to herein as cell files). A unit file specific to a configurable unit may contain multiple subfiles of configuration data. In the example described here, subfiles consist of "chunks" with data suitable for efficient distribution using the bus system.

Configurable units in the plurality of configurable units may each include logic to perform a unit configuration loading process including receiving via the bus system specific to the configurable unit A sub-file of a unit file, and loading the received sub-file into the configuration memory of the configurable unit. In some embodiments, configurable cells of the plurality of configurable cells are used for routing in the bus system during execution after configuration is also used in the configuration loading process.

A configuration load controller is described to include logic to perform the array configuration load process. The array configuration loading process includes allocating a configuration file including cell files to a plurality of configurable cells in the array to implement a machine.

In one aspect of the technique, a unit file may be organized to contain a plurality of ordered sub-files. In some embodiments, unit files specific to different configurable units may have different numbers of ordered sub-files. The configuration file for the configurable cells of an array is set so that subfiles of the cell file are interleaved with other subfiles in the same order as for other cell files, and are set so that the position of the subfile in the configuration file is implied by the subfile Configurable cells in the file's array and their order in the configurable cell-specific cell file.

The example of the array configuration loading process described here is by sending subfiles to a plurality of configurable cells in the array in an allocation sequence of N rounds (rounds R(i), i from 0 to N-1). And execute. In each round R(i), the process transfers, via the bus system, a subfile of order (i) to a configurable cell with a cell file that includes at most (i+1) subfiles.

The configuration data stores in the configurable units of the plurality of configurable units include sequence chains, and the unit configuration load process can be loaded from the unit in a round of allocation sequences in a bus cycle. The bus system receives all or part of a first subfile of the cell file specific to the configurable cell, and during a subsequent bus cycle before receiving a second subfile in the allocation sequence of the next round Begin pushing the received first subfile into the sequence chain, and receive the second subfile from the bus system in the next round of the allocation sequence in a later bus cycle, and in the Pushing the second received subfile into the sequence chain begins after the earlier received subfile is pushed into the sequence chain.

In some rounds of allocation sequences, before the second sub-file of the plurality of sorted sub-files is received by the configurable unit, the first sub-file is grouped by the unit in the configurable unit state loading processing consumption.

The array may include more than one type of configurable cell, and the cell files for different types of configurable cells include different numbers of subfiles of configuration data. For example, the cell files for a first type of configurable cells include Z1 clusters, and the cell files for a second type of configurable cells include Z2 clusters, where Z1 is less than Z2. The array configuration loading process may include retrieving the subfile (i) that includes the cell files for all configurable cells of the first type and second type to be allocated in round R(i). A segment of the configuration file, where (i) goes from 0 to Z1-1, and then retrieves the cell file that includes the cell files for all configurable cells of the second type to be allocated in round R(i) Fragment of the configuration file of subfile (i), where (i) is from Z1 to Z2-1. This protocol can be extended to any number of configurable units of type that have different numbers of subfiles in their unit files.

In one technique for initiating the array configuration load process, a configuration load command identifying the location of the configuration file in memory may be received from a host process, and in response to the command, the process generates one or more memory access request. When the requested portion of the configuration file is returned, the allocation sequence can be executed.

The files of the plurality of unit files may be arranged in the configuration file in an interleaved manner according to the allocation sequence. This setting of the configuration file enables the configuration load process to imply the configurable unit, and position within the plurality of ordered subfiles of each subfile (by the position of the subfile in the configuration file). The array configuration loading process may include routing the subfiles to configurable cells based on their location in the configuration file.

The plurality of configurable cells that receive configuration data through the array configuration loading process may include all of the configurable cells in the configurable cells of the array. In instances where the machine implemented by the configuration file does not utilize all configurable units, the unit file for one or more unused configurable units may enable a no-op configuration. Likewise, the array configuration load process can be configured such that the plurality of configurable cells that receive configuration data by the array configuration load process includes less than all of the configurable cells of the array. unit.

In one example described herein, the configurable cells in the configurable cells of the array include individual load completion status logic that is daisy-chained starting and ending at the array configuration load logic. In the process of confirming the successful loading of configuration files using a daisy chain, the array configuration load logic forwards a configuration load complete signal on the daisy chain after the configuration file is allocated, and each In a configurable unit, when the configuration load complete signal is received from a previous member of the chain and the loading of its own unit file is complete, the configuration load complete state logic forwards the configuration load complete state logic on the daisy chain. Configuration loading complete signal.

The bus system described herein supports a plurality of arrays of configurable cells, where each array may be referred to as a tile. The bus system includes a top layer network and an array layer network, the top layer network being connected to an external data interface (such as one or more PCIE or DDR type interfaces) and to an array interface of each block, and The array layer network is connected to the array interface of the corresponding block and to the configurable units of the configurable units of the array. The array configuration load process may include receiving, from a host process, a configuration load command identifying the location of the configuration file in memory, and generating one or more memory access requests in response to the command via the top-level network to retrieve the configuration file through the external data interface. The array configuration load process may use addresses implied by the locations of the subfiles in the configuration file to route subfiles through the array layer network to the configurable units.

A configuration offload controller is described as including logic for performing an array configuration offload process, the array configuration offload process including assigning an offload command to a plurality of configurable units in the array to offload a configuration specific to a corresponding configurable unit. The unit files of the state unit, the unit files each including a plurality of ordered sub-files, the sub-files of the configurable cells received at the configuration offload controller from the array. An uninstall configuration file is assembled by setting the received subfile in memory according to the order of the configurable unit of the unit file of which the subfile is a part and the subfile in the unit file . The structure of the configuration uninstall file can be the same as that of the configuration file described above. A configurable unit in the plurality of configurable units may include logic to perform a unit configuration unloading process that includes unloading the configurable units from the configuration storage of the configurable unit Subfiles and subfiles of a cell file specific to the configurable cell are transmitted to the configuration offload controller via the bus system (eg, via an array layer network). The offloaded subfiles do not need to be received in any particular order by the configured offload controller. The configuration offload controller then transfers the cell subfile to memory through the bus system (eg, via the top-level network).

Methods for configuring reconfigurable data processors are also provided.

Additional aspects and advantages of the techniques described herein can be found in the drawings, the detailed description that follows, and the review of the patented invention.

The following description will typically refer to specific structural embodiments and methods. It is to be understood that the techniques are not intended to be limited to the specifically disclosed embodiments and methods, and instead, the techniques may be implemented using other features, elements, methods, and embodiments. The preferred embodiments are described to illustrate the technology, not to limit its scope, which is defined by the scope of the claims. Various equivalent changes will be apparent to those of ordinary skill in the art from the following description.

FIG. 1 is a system diagram showing a system including a host 120 , a memory 140 , and a reconfigurable data processor 110 . As shown in the example of FIG. 1 , the reconfigurable data processor 110 includes an array 190 of configurable cells and a configuration load/unload controller 195 . The term "configuration load/unload controller" as used herein refers to a combination of a configuration load controller and a configuration unload controller. The configuration load controller and configuration unload controller may be implemented using separate logic and data path sources, or may be implemented using a common logic and data path source as appropriate for a particular embodiment. In some embodiments, the system may include only configuration load controllers of the type described herein. In some embodiments, the system may only include configuration offload controllers of the type described herein.

The processor 110 includes an external I/O interface 130 connected to the host 120 and an external I/O interface 150 connected to the memory 140 . The I/O interfaces 130 , 150 are connected to the array 190 of configurable cells and the configuration load/unload controller 195 via the bus system 115 . The bus system 115 can have a bus width that carries a cluster of data, which in this example can be 128 bits (roughly, the 128 bits referenced in this description can be considered as an example cluster size) . In general, a clustered configuration file can have a number of N bits of data, and a bus system can be configured to transmit N bits of data in one bus cycle, where N is any practical bus width . The sub-files allocated in the allocation sequence may consist of a cluster, or other amount of data (as appropriate for the particular embodiment). Programs are described using subfiles consisting of one cluster of data each. Of course, techniques can be configured to allocate subfiles of different sizes, including subfiles that can be composed of two clusters that are allocated, for example, in two bus cycles.

To configure the configurable cells and configuration files in the array 190 of configurable cells, the host 120 may configure the configuration through the interface 130 , the bus system 115 , and the interface 150 in the reconfigurable data processor 110 The file is sent to memory 140 . Configuration files can be loaded in a number of ways, including data paths external to configurable processor 110 (as appropriate for a particular architecture). The configuration file can be retrieved from memory 140 via memory interface 150 . The configuration file for the cluster may then be sent to the configurable cells in the array 190 of configurable cells in the reconfigurable data processor 110 according to the allocation sequence described herein.

An external clock generator 170 or other clock signal source may provide a clock signal 175 or a plurality of clock signals to elements in the reconfigurable data processor 110, including the array 190 of configurable cells, and busses The row system 115, and the external data I/O interface.

Figure 2 is a simplified block diagram of components of a Coarse Grain Reconfigurable Architecture (CGRA) processor. In this example, the CGRA processor has two tiles (Tile1, Tile2). A block contains an array of configurable cells connected to a bus system, including in this example an array-level network. The bus system includes a top-level network that connects the blocks to the external I/O interface 205 (or any number of interfaces). In other embodiments, different busbar system configurations may be utilized. The configurable units in each block are, in this example, nodes on the array layer network.

Each of the two blocks has four Address Generation and Coalescing Units (AGCU) (eg MAGCU1, AGCU12, AGCU13, AGCU14). The AGCU is a node on the top-level network and a node on the array-level network, and includes resources used to route data in each block between nodes on the top-level network and nodes on the array-level network.

In this example, nodes on the top-level network include one or more external I/Os, including interface 205 . The interface to the external device includes resources used to route data between nodes on the top-level network and the external device, such as high-capacity memory, host processors, other CGRA processors, FPGA devices, etc. connected to the interface.

One of the AGCUs in the block is configured as the main AGCU in this example, which includes the array configuration load/unload controller for that block. In other embodiments, more than one array configuration load/unload controller may be implemented and one array configuration load/unload controller may be implemented with logic distributed among more than one AGCU.

MAGCU1 includes a configuration load/unload controller for Tile1 and MAGCU2 includes a configuration load/unload controller for Tile2. In other embodiments, the configuration load/unload controller may be designed to load and unload configurations of more than one block. In other embodiments, more than one configuration controller may be designed for the configuration of a single block. Likewise, configuration load/unload controllers can be implemented in other parts of the system, including top-level and array-level networks or separate nodes on multiple networks.

The top-level network is constructed using top-level switches (211-216) connected to each other and to other nodes on the top-level network, including the AGCU, and the I/O interface 205. Top-level networks include links to top-level switches (eg, L11, L12, L21, L22). Data moves in packets between top-level switches on a link, and from switches to nodes on the network connected to the switch. For example, top switches 211 and 212 are connected by link L11, top switches 214 and 215 are connected by link L12, top switches 211 and 214 are connected by link L13, and Top switches 212 and 213 are connected by link L21. A link may include one or more buses and supporting control lines, including, for example, a chunk-wide bus (vector bus). For example, the top-level network may include data, request and response channels operable to coordinate the transfer of data in a manner similar to an AXI compliant protocol. See AMBA® AXI and ACE Protocol Specification, ARM, 2017.

The top switcher can be connected to the AGCU. For example, top-level switches 211, 212, 214, and 215 are connected to MAGCU1, AGCU12, AGCU13, and AGCU14 in block Tile1, respectively. Top switches 212, 213, 215 and 216 are connected to MAGCU2, AGCU22, AGCU23 and AGCU24 in block Tile2, respectively.

The top-level switch can be connected to one or more external I/O interfaces (eg, interface 205).

Figure 3 is a simplified diagram of a block and an array layer network that can be used in the configuration of Figure 2, where the configurable cells in the array are nodes on the array layer network.

In this example, the array 300 of configurable cells includes a plurality of types of configurable cells. These types of configurable units in this example include Pattern Compute Unit (PCU), Pattern Memory Unit (PMU), Switch Unit (S), and Address Generation and Merging Units (each including two address generators AG and a shared CU). An example of the functionality of these types of configurable cells can be found in "Plasticine: A Reconfigurable Architecture For Parallel Patterns" by Prabhakar et al., ISCA '17, June 24-28, 2017, Toronto, ON, Canada, which is incorporated in its entirety Here as a reference. Each of these configurable units contains configuration storage containing a set of registers or flip-flops representing the settings or sequences of the program to be run, and may include the number of nested loops, the limit of each loop iterator , the instructions to be executed at each stage, the source of the operands, and the network parameters for the input and output interfaces.

In addition, each of these configurable units contains configuration storage that includes a set of registers or flip-flops that can be used to track progress in nested loops or otherwise. A configuration file contains a stream of bits representing the initial configuration or starting state of the components of the executing program. This bitstream is referred to as a bitfile. Program loading is based on the contents of a bit file to set configuration memory in the configurable cells of the array to allow all components to execute programs (ie, machines). Program loading may also require loading of all PMU memory.

Array layer nets include links that interconnect configurable cells in the array. Links in an array-level network include one or more (and in this case, three) types of physical busses: chunk-level vector busses (eg, 128-bit data), Word-level scalar buses (eg, 32-bit data), and multiple bit-level control buses. For example, interconnect 321 between switching cells 311 and 312 includes a vector bus interconnect with a vector bus width of 128 bits, a scalar bus interconnect with a scalar bus width of 32 bits , and control bus interconnection.

The three types of physical busses differ in the granularity with which the data is conveyed. In one embodiment, a vector bus can carry a cluster that includes 16 bytes (=128 bytes) of data as its payload. A scalar bus can have a 32-bit payload and carry scalar operands or control information. The control bus can carry control handshakes such as tokens and other signals. Vectors and scalar buses can be packet-switched, including headers indicating the destination of each packet and other information, such as sequence numbers, which can be used to reassemble files when packets are received out of order. Each packet header may contain a destination identifier, which identifies the geographic coordinates of the destination switch unit (eg, column and row in the array), and an interface identifier, which identifies the destination switch used to reach the destination unit interface (eg north, south, east, west, etc.). The control network may be circuit switched based on, for example, sequential circuits in the device. The configuration load/unload controller can generate headers for configuration data for each cluster of 128 bits. The header is transmitted to each of the configurable cells of the array on the header bus.

In one example, data for clusters of 128 bits are transmitted on the vector bus, which provides the clusters as vector inputs to configurable cells. A vector bus may include 128 payload lines, and a set of header lines. The header may include the sequence ID for each cluster, which may include: • A bit used to indicate whether the cluster is scratchpad memory or configuration storage data. • The bits that form the cluster number. • A bit representing the row identifier. • A bit representing the column identifier. • A bit representing the component identifier.

For a load operation, the configuration load controller may send a number N of clusters to the configurable units in order from N-1 to 0. In this example, 6 clusters are sent in most significant bit first order as Cluster 5 -> Cluster 4 -> Cluster 3 -> Cluster 2 -> Cluster 1 -> Cluster 0. (It should be noted that this most significant bit first order causes cluster 5 to be allocated from the array configuration load controller in the round 0 allocation sequence.) For unload operations, the configuration unload controller may Write sequentially to memory. For both load and unload operations, the transition in the configuration sequence chain in the configuration data store in the configurable unit is from the least-significant-bit (LSB) to the most significant-bit ( most-significant-bit; MSB), or MSB first.

Figure 3A shows an example of a switching unit connected to elements in an array layer network. As in the example of FIG. 3A, the switching unit may have 8 interfaces. The north, south, east, and west interfaces of the switching units are used for the connection between the switching units. The northeast, southeast, northwest, and southwest interfaces of the switching unit are each used to form a connection to the PCU or PMU instance. A set of 2 switching units in each block quadrant has connections to an address generation and merging unit (AGCU) comprising a plurality of address generation (AG) units and a coalescing unit connected to the plurality of address generation units ; CU). The Merge Unit (CU) arbitrates between AGs and handles memory requests. Each of the eight interfaces of the switching unit may include a vector interface, a scalar interface, and a control interface to communicate with the vector network, the scalar network, and the control network.

During execution after machine configuration, data may be sent via one or more cell switches and one or more links between cell switches to vectors using one or more switching cells on the array layer network Configurable unit for bus and vector interface.

In the embodiments described herein, prior to the configuration of the blocks, data may be transferred from groups using the same vector bus via one or more cell switches and one or more links between cell switches. The state loading controller sends to the configurable units using the vector bus and vector interface of one or more switching units on the array layer network. For example, configuration data specific to configurable unit PMU 341 for a cluster in the unit file may be via a link between configuration load/unload controller 301 and the West (W) vector interface of switch unit 311 320. The switch unit 311, the link 331 between the Southeast (SE) vector interface of the switch unit 311 and the PMU 341 is sent from the configuration load/unload controller 301 to the PMU 341.

In this example, one of the AGCUs is configured as the main AGCU, which includes a configuration load/unload controller (eg, 301). The master AGCU implements the scratchpad, and through the scratchpad, the host (120, FIG. 1 ) can send commands to the master AGCU via the bus system. The main AGCU controls operations on the array of configurable cells in the block and implements a program-controlled state machine to track the state of the block by writing to registers based on commands it receives from the host. For each state transition, the master AGCU issues commands to all components on the block via the daisy-chain command bus (Figure 4). Commands include a program reset command to reset the configurable cells in the array of configurable cells in the block, and a program load command to load a configuration file into the configurable cells.

The configuration loading controller in the main AGCU is responsible for reading configuration files from memory and sending configuration data to each configurable unit of the block. The main AGCU can read the configuration file from memory at preferably the maximum throughput of the top-level network. Data read from memory is transmitted by the main AGCU to the corresponding configurable unit through the vector interface on the array layer network according to the allocation sequence described herein.

In one embodiment, there is a way to reduce wiring requirements within configurable cells, maintaining the configuration in a component of cell files to be loaded in a configuration load process or unloaded in a configuration unload process The state register is linked by a sequence chain and can be loaded by a program that transfers bits through the sequence chain. In some embodiments, more than one sequence chain may be arranged in parallel or in series. When a configurable unit receives, for example, 128 bits of configuration data from the main AGCU in one bus cycle, the configurable unit transfers this data through its serial chain at a rate of 1 bit per cycle, transferring The cycle can be run at the same rate as the bus cycle. The configurable unit would require 128 transfer cycles to load the 128 configuration bits along with the 128 bits of data received through the vector interface. The 128-bit configuration data is referenced as a cluster. A configurable unit can request data from multiple clusters to load all of its configuration bits. An example shift register structure is shown in Figure 6.

The configurable unit interfaces with memory through a plurality of memory interfaces (150, FIG. 1). Each of the memory interfaces can be accessed using several AGCUs. Each AGCU contains a reconfigurable scalar data path to generate requests for off-chip memory. Each AGCU contains first-in-first-out buffers (FIFO) for organizing data to buffer out commands, data, and incoming responses from off-chip memory.

The address generator AG in the AGCU can generate sparse or dense memory commands. Intensive requests can be used to bulk transfer adjacent off-chip memory regions, and can be used to read data from or write data to a cluster from configurable cells in an array of configurable cells. Configurable cells in an array of configuration cells. Intensive requests can be converted to multiple off-chip memory burst requests by a merge unit (CU) in the AGCU. Sparse requests can cause a stream of addresses to be enqueued into a merge unit. The merge unit uses merge caching to maintain metadata on issued off-chip memory requests and to combine sparse addresses belonging to the same off-chip memory request to minimize the number of issued off-chip memory requests .

FIG. 4 is a block diagram showing an example configurable unit 400, such as a pattern computing unit (PCU). Configurable cells in an array of configurable cells include configuration data storage 420 (eg, serial chain) to store cell files, including clusters (or other sized subfiles) specific to corresponding configurable cells ) configuration data. The configurable cells in the array of configurable cells each include cell configuration load logic 440 connected to configuration data store 420 via line 422 to perform cell configuration load processing. The cell configuration loading process includes receiving a cell file specific to a cluster of configurable cells via a bus system (eg, vector input), and loading the received cluster into the configuration data store 420 of the configurable cell. The unit configuration loading process will be further explained with reference to FIG. 5 .

Configuration data storage in a configurable unit of the plurality of configurable units in this example includes a sequence chain of latches that store bits that control the configuration of resources in the configurable unit . The sequence chain in the configuration data store may include a shift register chain for configuration data and a second shift register chain for status information and serially connected counter values. The configuration memory will be further described with reference to FIG. 6 .

Configurable units can interface scalar, vector, and control busses using three corresponding sets of inputs and outputs (IOs): scalar input/output, vector input/output, and control input/output. Scalar IO can be used to communicate with a single word of data (eg, 32 bits). Vector IO can be used to communicate with clustered data (eg, 128 bits), receive configuration data, such as in the unit configuration load process, and after configuration during operation from one side of a long pipeline to the other. In the case of transmitting and receiving data between PCUs. Control IO can be used to communicate with control signals, such as the start or end of the execution of a configurable unit. Control inputs are received by control block 470 and control outputs are provided by control block 470 .

Each vector input is buffered using a vector FIFO in vector FIFO block 460, which may include one or more vector FIFOs. Each scalar input is buffered using scalar FIFO 450 . Using input FIFOs decouples timing between data producers and consumers, and simplifies control logic between configurable units, by making them robust to input delay mismatches.

Input configuration data 410 may be provided to the vector FIFO as vector input and then transferred to configuration data store 420 . Output configuration data 430 may be unloaded from configuration data store 420 using vector output.

CGRA uses a daisy-chain completion bus to indicate when a load/unload command has been completed. The master AGCU transmits program load and unload commands to the configurable cells in the array of configurable cells through the daisy-chained command bus (to transition from S0 to S1, Figure 5). As shown in the example of FIG. 4 , daisy chain completion bus 491 and daisy chain command bus 492 are connected to daisy chain logic 493 , which communicates with unit configuration load logic 440 . Daisy chain logic 493 may include load complete status logic, as described below. The daisy-chained completion bus is further explained below. Other topologies for the command and completion bus are obviously possible, but not described here.

The configurable unit includes a plurality of reconfigurable data paths in block 480 . The data path in the configurable unit can be organized as a multi-stage (Stage 1 . . . Stage N), reconfigurable single instruction, multiple data (SIMD) pipeline. The data pushed to the clusters in the configuration sequence chain in the configurable unit includes configuration data for each stage of each data path in the configurable unit. The configuration sequence chain in configuration data store 420 is connected via line 421 to a plurality of data paths in block 480 .

Along with the bus interface used in the PCU, a patterned memory unit (eg, PMU) may contain scratchpad memory coupled with reconfigurable scalar data paths for address computation. PMUs can be used to distribute on-chip memory throughout an array of reconfigurable units. In one embodiment, in-memory address computations in the PMU are performed on the PMU datapath, while core computations are performed in the PCU.

Figure 5 shows an example of a state machine that can be used to control the cell configuration loading process in a configurable cell. Typically, the unit configuration load process receives a first cluster (or sub-file) of configurable unit-specific unit files from the bus system during one bus cycle, begins loading the first received first during a subsequent transfer cycle Clusters are pushed into the sequence chain, which occurs at the same rate as the bus cycle before the cell file for the second cluster is received. Once a cell file specific to a second cluster of configurable cells is received from the bus system at a later bus cycle, the program begins to push the received second cluster after pushing the earlier received cluster into the sequence chain Clusters are pushed into sequence chains. During some or all rounds of the configuration load process, the first cluster may be received by the configurable unit before the second of the plurality of ordered clusters (next in the order of the cluster's unit files) is received by the configurable unit. Configuration load processing is consumed in configurable units.

The state machine of FIG. 5 includes six states S0 to S5. In state S0 (idle), the unit configuration load process waits for a configuration load/unload command from the configuration load/unload controller in the main AGCU. The configuration load/unload controller is responsible for configuration data from/to off-chip memory (140, Fig. 1) and to/from the array of configurable cells (190, Fig. 1) ) loading and unloading. When a load command is received at the configuration load/unload controller, the unit configuration load process enters state S1.

In state S1 (waiting for quiescence), functional wobbles in multiple data paths are disabled so that functional wobbles do not cycle, while scalar outputs, vector outputs and control outputs are turned off so that the outputs do not drive any loads. If the load command has been received, the unit configuration load process proceeds to state S2. When the unload command is received, the unit configuration loading process goes to state S4.

In state S2 (waiting for input valid), the unit configuration load process waits for the input FIFO (610, Figure 6) to become valid. When the input FIFO becomes active, the input FIFO has received configuration data for the cluster of configuration files from the bus system. For example, the configuration data for a cluster may include 128 bits of load data received on the vector network of the bus system and the vector network has a vector bus width of 128 bits. When the input FIFO becomes active, the unit configuration loading process enters state S3.

In state S3 (load transfer), the configuration data of the 128-bit cluster is first de-queued from the input FIFO in one clock cycle, and then the configuration data of the 128-bit cluster is 128 clock cycles are transferred to the input shift register (620, Figure 6). The input shift register may have the same length (eg 128 bits) as the clustered configuration data, and it takes the same number of shifter clock cycles (eg 128) to transfer the clustered configuration data The length of the configuration data into the input shift register as a cluster. As mentioned above, in some embodiments, the shifter clock and the bus clock (or bus period) may operate at the same ratio.

The configuration data storage in the configurable unit includes a chain of configuration sequences (630, 640, Fig. 6), which can be configured as a FIFO chain to store data containing a plurality of clusters specific to the configurable unit. The unit file of configuration data. The configuration data of the plurality of clusters includes the configuration data of the first cluster and the configuration data of the last cluster. The configuration data of the clusters in the input shift register are further sequentially transferred into the configuration data store in subsequent clock cycles. The configuration data storage will be further described with reference to FIG. 6 .

After the cell file specific to the first cluster of configurable cells is transferred into the input shift register in state S3, the cell configuration load process determines whether the configuration data of the first cluster is specific to the configurable cell The configuration data of the last cluster. If so, the loading of the unit file for the configurable unit is complete, and the unit configuration loading process enters state S0. If not, the unit configuration load process enters state S2 and waits for the input FIFO to become available for configuration data specific to the second cluster of configurable units.

When an unload command is received in state S1, the unit configuration loading process proceeds to state S4.

In state S4 (unload transfer), the configuration data from the cluster of configuration data stores is transferred into the output shift register (650, FIG. 6). The configuration data for the cluster can include 128 bits of offload data. The output shift register can have the same length as the clustered configuration data (eg 128), and it takes the same number of shifter clock cycles (eg 128) to transfer the clustered configuration data from the configuration data The memory is transferred into the output FIFO as the length of the cluster's configuration data. When the configuration data of the cluster is transferred into the output shift register, the unit configuration loading process enters state S5 (waiting for output to be valid).

In state S5 (waiting for output to be active), the unit configuration load process waits for the output FIFO (660, Figure 6) to become active. When the output FIFO becomes active, the configuration data from the output shift register with clusters of 128 bits is inserted into the output FIFO in one clock cycle. The clustered configuration data in the output FIFO can then be sent to the bus system (Figure 3).

After the configuration data of the first cluster is transferred into the output FIFO in state S5, the unit configuration loading process determines whether the configuration data of the first cluster is the configuration data of the last cluster in the configuration data store. If so, the unloading of the configuration data for the configurable unit is complete, and the unit configuration loading process enters state S0. If not, the cell configuration loading process enters state S4 and the configuration data from the second cluster of configuration data stores are sequentially transferred into the output shift register.

Figure 6 is a logical representation of configuration memory in a configurable unit. In this embodiment, the configuration data storage (420, FIG. 4) in the configurable unit includes a configuration sequence chain, including a first shift register chain 630 and a second shift register chain 640. The first shift register chain 630 includes a set of registers or latches. The second shift register chain 640 includes another set of registers or latches (flip-flops). In this embodiment, the first shift register chain and the second shift register chain are connected in series to form a single chain.

The configuration file includes configuration data for clusters of each of the configurable cells in the array of configurable cells. The configuration data of the cluster represents the initial configuration, or starting state, of the individual configurable units. The configuration load operation in this system is the process of setting the unit file of configuration data in the array of configurable units to allow all configurable units to execute the program.

The set of registers in the first shift register chain 630 may represent the settings or sequences of running programs, including definitions of the operation of the configurable units containing the registers. These registers can register the number of nested loops, the limits of each loop iterator, the instructions executed for each stage, the source of operands, and network parameters for input and output interfaces. The set of registers in the second shift register chain may contain data about the running state of programs that are periodically loaded into the configurable unit.

As shown in the example of FIG. 6, the first shift register chain 630 and the second shift register chain 640 are connected in series such that the most significant bit (MSB) of the first shift register chain ) is connected to the least significant bit (LSB) of the second shift register chain. The load signal or the unload signal can be used as a transfer enable signal coupled to the LSB of the first shift register chain and the LSB of the second shift register chain to control the first shift register chain and the LSB of the second shift register chain. Load/unload operations on the second shift register chain. Input FIFO 610 is coupled to input shift register 620 via selector 670 . When the load signal is active, selector 670 connects input shift register 620 to the input of the configuration data store (LSB of first shift register chain 630).

When the load signal is active, the configuration data in the input shift register 620 can be transferred to the first shift register chain 630 and the second shift register chain 640 in the configuration sequence chain Inside. Here, the load signal can function as an enable signal for the input shift register, the first shift register chain, and the second shift register chain. The load operation can be repeated until the configuration data for all clusters of the configurable unit is loaded into the configuration data store in the configurable unit. When the length of a sequence chain differs from the length of a cluster (or sub-file) of integers, the first cluster in the sequence can pad the difference, and when the last cluster is shifted in, the padding bits are shifted to the end of the chain. For example, a configuration data store in a configurable cell can store a cell file with a size of 760 bits. The unit configuration load process can load clusters of integer N. In this example, N=6, and the number N of clusters includes cluster 5, cluster 4, cluster 3, cluster 2, cluster 1, and cluster 0. The vector bus has a vector width of 128 bits, the configuration data of the cluster has 128 bits, and the cluster can be sent to the configurable unit in one bus clock cycle. The N clusters have a size of N x 128 = 6 * 128 = 768 bits, which includes 8 padding bits to match the unit file size of 760 bits.

To recover from errors, the unload operation may checkpoint the status of each configurable unit. The uninstall operation stores the execution state of each configurable unit needed to restart, and enables the application to be restarted if an error occurs. It also allows the state of the configurable unit to be stored or transmitted for debugging purposes. The state to be stored includes at least part of the contents of the first or second shift register, and optionally the contents of the PMU memory. Program unloading would also require unloading the state of all the first and second shift registers.

Output FIFO 660 is coupled to output shift register 650, which is then coupled to the output of the configuration data store (MSB of second shift register chain 640). For the unload operation, the configuration data in the second shift register chain 640 and the first shift register chain 630 can be transferred to the output shift register 650 when the unload signal is active. When the output FIFO 660 is active, the configuration data (eg, 128 bits) in the output shift register 650 can be inserted into the output FIFO 660 in one clock cycle. The unload operation can be repeated until the configuration data of all clusters in the configuration data store in the configurable unit are unloaded into the output FIFO.

In order to synchronize and communicate the completion of configuration load commands issued by the configuration load controller in the MAGCU, a single-line daisy-chain scheme is implemented in one example due to the daisy-chain logic in the components of the chain (eg Supported by logic included in daisy chain logic 493) in Figure 4. This solution requires each component to have the following 2 ports:

1. Input port, called PROGRAM_LOAD_DONE_IN

2. Output port, called PROGRAM_LOAD_DONE_OUT

A component will drive its PROGRAM_LOAD_DONE_OUT signal when it has finished executing the command issued by the MAGCU and its PROGRAM_LOAD_DONE_IN input is driven high. When it has completed all the steps required to execute the command, the MAGCU will start the daisy chain by driving its PROGRAM_LOAD_DONE_OUT. The last component in the chain will drive its PROGRAM_LOAD_DONE_OUT, which will be connected to the MAGCU's PROGRAM_LOAD_DONE_IN. PROGRAM_LOAD_DONE_IN of MAGCU goes high to indicate the completion of the command. After passing data corresponding to all components of all clusters, MAGCU drives its PROGRAM_LOAD_DONE_OUT port high. When all components have finished loading all their configuration bits, all components will drive their individual PROGRAM_LOAD_DONE_OUT ports high.

When the MAGCU input port PROGRAM_LOAD_DONE_IN is determined, the configuration file loading is completed.

FIG. 7 is a flow chart showing the operation of a host coupled to a reconfigurable data processor. At step 711, the host (120, Fig. 1) sends the configuration file for the array of configurable cells off-chip via the PCIE interface (130, Fig. 1) and the top-level network (115, Fig. 1) The memory (140, FIG. 1), or otherwise stores the configuration file in memory accessible to the configurable processor.

At step 712, when the loading of the configuration file to the memory is completed, the host 120 sends a configuration load command to the configuration load controller in the processor (in this example, part of the main AGCU). The main AGCU can implement a scratchpad, and through the scratchpad, the host can send configuration load commands to the configuration load controller. The configuration load command can identify a location in memory that is accessible through the memory interface on the configurable processor. The configuration load controller may then generate one or more memory access requests via the top-level network in response to the command to retrieve the configuration file. The host may then monitor the configurable processor for a signal that the configuration file has been fully loaded (714). When the file loading is complete, the host can then initiate the function to be performed by the machine (716).

Figure 8 is a flow diagram showing the operation of a configuration load controller, which may be a MAGCU or otherwise part of the communication with the configurable units of the array in the block. The configuration load controller is responsible for reading the configuration file from the off-chip memory (140, FIG. 1) and sending the configuration data to each configurable cell in the array of configurable cells. The flow diagram begins with the configuration load controller waiting for a configuration load command (810). As mentioned above, the configuration load command identifies the configuration file and its location in processor-accessible memory.

Once the load command is received, at step 811, the configuration load controller issues a load request to the memory (140, Figure 1) connected to the reconfigurable data processor (110, Figure 1). In step 812, the configuration load controller retrieves the configuration file of the cluster on the top-level network via the memory interface. At step 813, the configuration load controller distributes the cluster's configuration files to the configurable units in the array on the array layer network in the sequenced rounds. At step 814, when the configuration files of all clusters have been received and allocated, the configuration load controller generates an allocation complete signal (eg, its PROGRAM_LOAD_DONE_OUT). At step 815, the configuration load controller then waits for confirmation from the configurable unit that its individual unit file has been loaded, for example, by its It is indicated by the judgment of PROGRAM_LOAD_DONE_IN. Once a successful configuration load is confirmed, the configuration load controller may notify the host (816).

Figure 9 shows an example organization of a configuration file. Other organizations may also be used and configured to conform to specific protocols for loading and unloading configuration files. In the example described with reference to FIG. 9, the configurable cells in the array of configurable cells include switches, PCUs, PMUs, and AGCUs. Each of these configurable units contains a set of registers representing the settings or sequence of programs to be run. These registers include data that defines the operation of the configurable unit containing it, such as the number of nested loops, the limits of each loop iterator, the instructions to execute for each stage, the source of operands, and the input used for input Network parameters for the output interface. In addition, each configuration file may include data used to set the context of a set of counters that track their progress in each nested loop.

A program (executable) contains a bitstream representing the initial configuration or start state of each configurable element of the executing program. This bitstream is referenced as a bit file, or here as a configuration file. Program loading is based on the content of the configuration file to set the configuration memory in the configurable unit to allow all configurable units to execute the program. Program unloading is the process of unloading the configuration storage from the configurable unit and combining the bitstream (referred to herein as unloading the configuration file). In the example described here, the uninstall configuration file has the same settings cluster or subfile and configuration file that is used for the program load.

The configuration file includes configuration data for a plurality of clusters of configurable cells in the array of configurable cells, the clusters are arranged in the configuration file in a manner consistent with their assigned sequence. This organization of the configuration file enables the array configuration load process to route clusters to configurable units based on the location of the clusters in the configuration file.

As shown in Figure 9, the configuration file (and the uninstall configuration file set in the same way) includes the unit file for the plurality of clusters of each configurable unit of the plurality of configurable units, the unit file has the most M (in this example, Z4 = 6) subfiles with order (i) in the unit file. In Figure 9, M is six, and the clusters are ordered from first to sixth (ie, in this index, the first to sixth clusters correspond to clusters (0) to (5)). The cluster is set up so that for all unit files in the load or unload configuration file, all sub-files in order (i), (i) from 0 to M-1, are stored in the corresponding block (i) in memory In the address space of (i) from 0 to M-1. Clusters of order (0) are stored in block (0) comprising addresses A0 to A1-1. In this example, for a switch unit, the cluster of order (0) is in a group of adjacent addresses within block (0). For PCUs, clusters of order (0) are in groups of adjacent addresses within block (0). For the PMU, clusters of order (0) are in groups of adjacent addresses within block (0). For an AGCU, clusters of order (0) are located in groups of adjacent addresses. Clusters of order (1) are stored in block (1) comprising addresses A1 to A2-1. In this example, for switching units, the clusters of order (1) are stored in groups of adjacent addresses within block (1). For PCUs, clusters of order (1) are in groups of adjacent addresses within block (1). For the PMU, the clusters of order (1) are in groups of adjacent addresses within block (1). For an AGCU, clusters of order (1) are in groups of adjacent addresses within block (1). The clusters in order 3 to 5 are arranged as shown in Figure 9, following the pattern in blocks (2) to (5).

As can be seen from the figure, in this example, a linear address space is allocated on line boundaries within the blocks used for configuration files. In other embodiments, linear address spaces may be configured on word boundaries or cluster boundaries. The boundaries can be chosen to match the efficiency characteristics of the memory being used. Therefore, the configuration file in this example contains memory lines with sequential line addresses.

Likewise, the array includes more than one type of configurable cell, and the cell files for different types of configurable cells include different numbers of sub-files of configuration data, and wherein the sub-files of a block (i) Within the address space, for each type of configurable unit, the sub-files are stored in corresponding groups of adjacent addresses within the address space of block (i).

The array may include more than one type of configurable cell, and the cell files for different types of configurable cells include configuration data for different numbers of clusters. For example, as shown in FIG. 3, the types of configurable cells in the array may include switching cells, PCU (pattern computing unit), PMU (pattern memory unit), and AGCU (address generation and merging unit) .

Example configuration file organizations include: W (for example, in Figure 3, 28) switching units, each unit needs the configuration bits of the Z1 cluster; X (for example, 9) PCU units, each unit requires configuration bits of the Z2 cluster; Y (for example, 9) PMU units, each unit needs the configuration bits of the Z3 cluster; Z (eg, 4) AGCU units, each requiring Z4 clusters of configuration bits.

Thus, the cell file for a first type of configurable cell may include Z1 clusters, and the cell file for a second type of configurable cells includes Z2 clusters, where Z1 is less than Z2. The array configuration load process may include retrieving a segment of the configuration file including the cluster (i) of cell files for all configurable cells of the first type and second type in round Z1, where (i) from 0 to Z1-1, and then fetch a segment of the configuration file including the cluster (i) of cell files for all configurable cells of the second type in round Z2, where (i) from Z1 to Z2 -1. The cell files for the third type of configurable cells may include Z3 clusters, and the cell files for the fourth type of configurable cells include Z4 clusters, where Z1 is less than Z2, Z2 is less than Z3, and Z3 is less than Z4. The allocation sequence can continue in this pattern for one round, which requires more than (i+1) clusters for each cluster (i) for all different types of configurable units.

As shown in the example configuration file organization, the configuration data for the clusters in the configuration file are set up in an interleaved fashion: • For round R (i = 0), the first of the configuration bits of the 2 clusters for each of the switching cells; • For round R (i = 0), the first of the configuration bits of the 3 clusters for each of the PCU units; • For round R (i = 0), the first of the configuration bits of the 5 clusters for each of the PMU units; • For round R (i = 0), the first of the configuration bits of the 6 clusters for each of the AGCU units; • For round R (i = 1), the second of the configuration bits of the 2 clusters for each of the switching cells; • For round R (i = 1), the second of the configuration bits of the 3 clusters for each of the PCU units; • For round R (i = 1), the second of the configuration bits of the 5 clusters for each of the PMU units; • For round R (i = 1), the second of the configuration bits of the 6 clusters for each of the AGCU units; • For round R (i = 2), the third of the configuration bits of the 3 clusters for each of the PCU units; • For round R (i = 2), the third of the configuration bits of the 5 clusters for each of the PMU units; • For round R (i = 2), the third of the configuration bits of the 6 clusters for each of the AGCU units; • For round R (i = 3), the fourth of the configuration bits of the 5 clusters for each of the PMU units; • For round R (i = 3), the fourth of the configuration bits of the 6 clusters for each of the AGCU units; • For round R (i = 3), the fifth of the configuration bits of the 5 clusters for each of the PMU units; • For round R (i = 4), the fifth of the configuration bits of the 6 clusters for each of the AGCU units; • For round R (i = 5), the sixth of the configuration bits of the 6 clusters for each of the AGCU units.

Unit archives can be organized to contain a plurality of ordered clusters (or other sized sub-archives). In some embodiments, unit files specific to different configurable units may have different numbers of ordered clusters. The configuration file for the array of configurable cells is set so that the cell files of the cluster are grouped in clusters in the same order as the other cell files. Likewise, the configuration file is set such that the location of the clusters in the configuration file implies the configurable cells in the array of clusters and their specific ordering of the configurable cells in the cell file.

The array configuration loading process can retrieve fragments of configuration files, including all possible types of the first type (switch type), the second type (PCU type), the third type (PMU type) and the fourth type (AGCU type). The unit file of cluster (i) of configuration units, where (i) is from 0 to Z1-1 (=1). The cell files of the cluster (0) of all configurable cells of the four types are retrieved in the first round, and the cell files of the cluster (1) of all the configurable cells of the four types are retrieved in the second round captured in. After the first and second rounds, the unit files of all (2) clusters of all configurable units of the first type (switch type) have been retrieved. The unit files of all configurable units of the first, second, third and fourth types have 0, 1, 3 and 4 clusters respectively remaining to be retrieved.

The array configuration load process may then retrieve segments of the configuration file in the third pass, including the cell files of all clusters (i) of configurable cells of the second, third, and fourth types. After the third round, the unit files of all (3) clusters of all configurable units of the second type (PCU type) have been retrieved. The cell files of all configurable cells of the first, second, third and fourth types have 0, 0, 2 and 3 clusters respectively remaining to be retrieved.

The array configuration loading process may then retrieve segments of the configuration file in the fourth pass, including the cell files of all clusters (i) of configurable cells of the third and fourth types. After the fourth round, the unit files of all (4) clusters of all configurable units of the third type (PMU type) have been retrieved. The cell files of all configurable cells of the first, second, third and fourth types have 0, 0, 1 and 2 clusters respectively remaining to be retrieved.

The array configuration load process may then retrieve segments of the configuration file in the fifth and sixth rounds, including the cell files of all clusters of configurable cells of the third and fourth types (i), (i) from Z3 (=4) to Z4-1(5). After the sixth round, the unit files of all (6) clusters of all configurable units of the fourth type (AGCU type) have been retrieved. The cell files of all configurable cells of the first, second, third and fourth types have clusters of 0, 0, 0 and 0 respectively remaining to be retrieved.

In the manner described above, the array configuration loading process may continue until the cell files for all configurable cells of the first, second, third and fourth types have no clusters remaining to be retrieved.

The array configuration load process routes clusters of configuration data to configurable units through the array layer network using the addresses implied by the location of the clusters in the configuration file. For example, the first of the configuration bits for 2 clusters of each of 198 switching units has a linear memory address of 0-12288, while the first of 2 clusters for each of 198 switching units has a linear memory address of 0-12288 The second of the configuration bits has linear memory addresses 33792-46080.

In some embodiments, the clustered configuration files may be returned to the configuration load controller out of sequence from memory. The location of the cluster in the configuration file can be used to route the cluster to the correct configurable unit. Because of the organization of rounds in the allocation sequence, configurable cells are guaranteed to receive clusters of their cell files in order.

FIG. 10 is a state machine diagram showing an example of the logic used to execute the array configuration loading process for systems like those of FIGS. 2 and 3, including allocating the containing cell file for a plurality of configurable cells in the array. In the configuration file, the unit files each contain a plurality of sorted clusters (or sub-files), which are sorted by the bus system in a sequence of N rounds (R(i), i from 0 to N-1). (i) A unit cluster is sent to all configurable units including at most N sub-files in the plurality of configurable units until the unit file in the configuration file is allocated to the configurable units in the plurality of configurable units configuration unit.

In this example, the state machine includes six states S1 to S6. In state S1 (idle), the configuration loading controller waits for a configuration loading command from the host. When a configuration load command is received, the load process enters state S2 to begin executing the allocation sequence of the first round R(0). Each round traverses states S2 to S6. In the example described here, there are six rounds because the maximum number of clusters assigned to configurable cells in the array is six.

In state S2 (switch request), the configuration load controller generates a memory access request to retrieve the cluster in state S2 via the top-level network for the configuration unit file of the round R(i) of the individual switch unit, and The captured clusters are assigned to individual switching units. For i=0, in round R(0), the configuration load controller generates a memory access request for cluster (0) of the plurality of clusters for the individual switch unit, and sends cluster (0) to the individual switch unit Switch unit. For i=1, in round R(1), the configuration load controller generates a memory access request for cluster (1) of the plurality of clusters for the individual switch unit, and sends the cluster to the individual switch unit. In round R(i), the load process enters the state when the configuration load controller has generated a memory access request for cluster (i) of multiple clusters for an individual switch unit and assigned the cluster to all switch units S3.

In state S3 (PCU request), the configuration load controller generates a memory access request to retrieve the cluster of configuration unit files for round R(i) of the individual PCU unit (pattern computing unit) via the top-level network, and assigning the captured clusters to individual PCU units. In state S3 of round R(i), the configuration load controller generates a memory access request for cluster (i) of the plurality of clusters for the individual PCU unit, and sends the cluster (i) to the individual PCU unit . In round R(i), when the configuration load controller has generated memory access requests and allocated clusters for individual PCU units for cluster (i) of the plurality of clusters, the loading process enters state S4.

In state S4 (PMU request), the configuration load controller generates a memory access request for configuration cell file retrieval via the top-level network for individual PMU cells (pattern memory cells) in the array of configurable cells The clusters are fetched, and the fetched clusters are sent to individual PMU units. In state S4 of round R(i), the configuration load controller generates a memory access request for cluster (i) of the plurality of clusters for the individual PMU unit and sends the cluster (i) to the individual PMU unit . For example, for i=0, in round R(0), the configuration load controller generates a memory access request for cluster(0) of multiple clusters for individual PMU units, and sends cluster(0) to individual PMU units. For i=1, in round R(1), the configuration load controller generates a memory access request for cluster(1) of multiple clusters for the individual PMU unit, and sends cluster(1) to the individual PMU unit PMU unit. In round R(i), when the configuration load controller has generated memory access requests and allocated clusters for individual PMU units for cluster (i) of the plurality of clusters, the loading process proceeds to state S5.

In state S5 (AGCU request), the configuration load controller generates a memory access request for configuration cell file retrieval via the top-level network for individual AGCUs (address generation and merging units) in the array of configurable cells Clusters are fetched, and the fetched clusters are sent to individual AGCU units. In state S5 of round R(i), the configuration load controller generates a memory access request for cluster (i) of the plurality of clusters for the individual AGCU unit, and sends the cluster (i) to the individual AGCU unit . In state S5 of round R(i), when the configuration load controller has generated memory access requests and allocated clusters for individual AGCU units for cluster (i) of the plurality of clusters, the load process enters round R( i) state S6.

In state S6 (response wait), the configuration load controller waits to ensure that the configurable units (switches, PCUs, PMUs, AGCU units) in the array are read to receive configurations for more clusters in the next round material. If all clusters of switching units have not been sent, the load process is incremented by (i) and proceeds to state S2 to start the next round R(i+1). If all clusters of switching units are sent but all clusters of PCU clusters are not sent, the load process increments (i) and proceeds to state S3 to start the next round R(i+1). If all clusters of switching units and PCU units are sent but not all clusters of PMU clusters, the load process increments (i) and proceeds to state S4 to start the next round R(i+1). If all clusters of switching units, PCU units, and PMU units are sent but not all clusters of AGCU clusters, the load process increments (i) and proceeds to state S5 to start the next round R(i+1). If all clusters of all configurable units (switches, PCUs, PMUs, AGCU units) are sent (ie, all rounds complete), the loading process proceeds to state S1.

FIG. 11 is a timing diagram showing the timing of the allocation sequence of an earlier round similar to that of FIG. 10. FIG. In this example, the configurated unit file of the cluster has data of a number B of bits (eg B=128), a round in the allocation sequence may include a number X of configurable cells, and an array of configurable cells may include a number of Configurable unit of Y (eg Y=148). For round R(0), X may be equal to Y. In subsequent rounds, X may be less than or equal to Y.

In this example, round R(0) includes Y=148 configurable cells. For rounds R(0) and R(1), X=Y. After the first two rounds R(0) and R(1), the switching unit has received all (2) of its clusters, so the third round R(2) includes less than 128 configurable units.

As shown in the example of FIG. 11, round R(0), the configuration unit file of the first cluster P11 is received at the configurable unit via the bus system in the first bus cycle C0. The first cluster is then loaded into the configuration memory of the first configurable unit "unit 1" by loading the The B bits of data in the first cluster P11 are transferred sequentially in parallel tasks in B clock cycles (which can run at the same rate as the bus clock). The configuration file of the second cluster P21 is received via the bus system in the second bus cycle C1. By transferring the B bits of data in the second cluster P21 during the B clock cycle, the second cluster is then loaded into the configuration memory of the second configurable unit "Cell 2" in parallel tasks. The configuration file of the third cluster P31 is received via the bus system in the third bus cycle C2. The third cluster P31 is then loaded into the configuration memory of the third configurable unit "Cell 3" by transferring the B bits of data in the third cluster P31 during the B clock cycle. This round proceeds until all configurable cells receive cell files specific to their first cluster.

Round R(0) involves assigning the configuration files of the first set of Y clusters (P11, P21, P31 . . . PY1 ) to Y individual configurable cells (Cell 1 . . . Cell Y) in the array. The configuration file of the cluster has data of B number of bits, and the array of configurable cells has Y number of configurable cells. When round R(0) is complete, the configuration files for the Y clusters in the first group (P11, P21, P31...PY1) have been received at Y in the array in the Y bus cycle (C0 to CY-1) configurable unit, and the first cluster P11 has been loaded or serially transferred into the configuration memory of the first configurable unit "unit 1" in the B clock cycle. The B clock period follows the first clock period C0 in which the first cluster P11 is received.

The next round R(1) consists of receiving the configuration files of the second set of Y clusters (P12, P22, P32...Py2) in Y individual configurable cells in the array (Cell 1... Cell Y). When round R(1) is complete, the configuration files for the Y clusters in the second group (P12, P22, P32...Py2) have been received at Y in the array in the Y bus cycle (Cy to C2y-1) Individual configurable units. When round R(1) is completed, the second cluster P12 for the first configurable cell "cell 1" has been loaded in the B clock cycle following the first clock cycle (Cy) in round R(1) Or sequentially transferred to the configuration memory of the first configurable unit "Unit 1". Likewise, when the second round is completed, the last cluster PY1 in the configuration file of the first group of Y clusters received in round R(0) has been loaded or serially transferred to the last configurable unit "Unit Y" ” in the configuration memory.

As long as the number of bits B (128) in the cluster is less than the number X of configurable cells in the round, the configurable cells will receive the cell configuration file of the next cluster after the previous cluster has been loaded, making the configurable cells Should be ready without the need for a sequence to procrastinate. In this example, the number B of bits in the cluster is 128, and the number X of configurable cells in round R(0) is X=Y=148. Since 128 clock cycles are required to serially transfer the 128 bits in the cluster into the configuration data store of the configurable unit, there are 20 (Y-B=148-128) buffers available after the transfer is complete cycle to ensure that the first configurable unit "unit 1" is ready to receive the next cluster in the next round R(1) (P12). When the number B of bits in a cluster is greater than the number X of configurable units in a round, the previous cluster is consumed while the next cluster can be received. Here, "consumed" refers to the serial transfer of bits in the cluster into the configuration data store of the configurable unit.

Typically, the cell configuration load process receives the first cluster (or subfile) of cell files specific to configurable cells from the bus system in one bus cycle, before the second cluster of cell files is received in the next round Begin pushing the first cluster received into the sequence chain during a subsequent bus cycle, receive a configurable unit-specific cell file from the bus system in a later bus cycle for the next round of the sequence and the second cluster received into the sequence chain starts to be pushed into the sequence chain during the period of the sequence after the cluster received earlier is pushed into the sequence chain. In some rounds, all receive clusters may be consumed before the next cluster is received.

Since different types of configurable units can have different numbers of configuration bits, configurable units may require different numbers of clusters. Once a configurable unit that requires a smaller number of clusters has loaded all of its configuration bits, the configuration load controller stops sending data to it. This results in fewer configurable units (number X) being staggered and can cause configurable units to receive new clusters before they have finished processing previous clusters. This can cause back-pressure on the array layer network.

Back pressure can be handled on the array layer network via a credit mechanism. For example, each input FIFO may have hop-to-hop credit, so if a PCU's input FIFO fills up, switches in the array layer network trying to send configuration data to that PCU's input FIFO cannot Data is sent until the input FIFO empties an entry and credit is sent back to the sending switch. Finally, because the link is busy, backpressure can delay the AGCU sending data. However, once the configurable unit consumes all 128-bit clusters, it empties an input FIFO entry, the credit is released, and the sender can send new clusters (if any).

FIG. 12 is a flowchart showing the unit configuration loading process in the configurable unit. At step 1221, the unit configuration load process waits for the input FIFO (610, Figure 6) to become active. When active, the input FIFO has received configuration data for the cluster of configuration files from the bus system to configure the configurable units. When the input FIFO is valid, the flow proceeds to step 1222.

At step 1222, the input FIFO is dequeued. At step 1223, the configuration data from the clusters of the input FIFOs are loaded in parallel into the input shift register (620, FIG. 6). At step 1224, the configuration data of the cluster in the input shift register is transferred into the configuration sequence chain in the configuration data store of the configurable unit.

At step 1225, the unit configuration loading process determines whether the configuration data of the loaded cluster is the configuration data of the last cluster of configurable units. If so, the loading of the configuration data of the configurable unit is completed. If not, flow proceeds to step 1221 and the cell configuration load process waits for the input FIFO to become available for the configuration data of the next cluster. The cell configuration loading process in the configurable cell will be further explained with reference to FIGS. 5 and 6 .

FIG. 13 is a state machine diagram of an example of the logic used to execute the array configuration offload processing for systems like those of FIGS. 2 and 3. FIG.

In this example, the state machine includes three states S1 to S3. In state S1 (idle), the configuration offload controller waits for a configuration offload command from the host. The configuration unload controller implements two counts "next_unld_req_count" and "next_unld_resp_count" for array configuration unload processing. The count "next_unld_req_count" records the next unload request count. The count "next_unld_resp_count" records the next unload response count. In state S1, both counts are reset to an initial value, eg, zero. When the configuration uninstall command is received, the uninstall process goes to state S2.

In state S2 (generating request), the configuration offload controller generates offload requests for each of the configurable cells in the array of configurable cells, including the switch unit, PCU, PMU, and AGCU in the array. For each unload request generated, the count "next_unld_req_count" is incremented. The count "next_unld_req_count" is compared to a predetermined number PROGRAM_UNLOAD_REQ_COUNT, which represents the total number of configurable cells in the array of configurable cells. As long as the count "next_unld_req_count" is less than PROGRAM_UNLOAD_REQ_COUNT, the unload processing remains in state S2. When the count "next_unld_req_count" equals PROGRAM_UNLOAD_REQ_COUNT, an unload request has been generated for each of the configurable cells in the array, and the unload process enters state S3.

In state S3 (response wait), the configuration offload controller increments the count "next_unld_resp_count" for each response received from a configurable unit in the array. The response includes clusters (subfiles) in the unit file of configuration data for the configurable unit. In some examples, the response may also include PMU cache fill data. During the unload process, the response is provided to the vector output of the configurable unit and sent on the vector bus to the configuration load controller. The unload processing remains in state S3 as long as the count "next_unld_resp_count" is less than PROGRAM_UNLOAD_REQ_COUNT.

In state S3, the offload process generates a memory address for each response received, and inserts each response received along with the memory address generated on the top-level network. Each response includes the offload cluster and sequence ID. The memory address is generated from the header, which accompanies the packet transporting the cluster in the array layer network, including the cluster number, row identifier, column identifier, and component identifier represented by the sequence ID. The component identifier may indicate whether the configurable unit is a switching unit, a PCU unit, a PMU unit, or an AGCU unit. The sequence ID will be further explained with reference to FIG. 3 .

When the count "next_unld_resp_count" equals At PROGRAM_UNLOAD_REQ_COUNT, a response has been received from each of the configurable units in the array and inserted on the top-level net, and the unload process transitions back to state S1.

In one embodiment, the order of linear memory addresses for configuration data in switch cells is the first cluster of each column of switch cells in the first row, followed by each of the switch cells in the second row. The first cluster of columns, followed by the first cluster of columns in the switching unit of the third row, ... up to the first cluster of columns in the last row. It groups the first clusters of all switching units in a linear address space. The first clusters of other types of configurable units are loaded in groups in adjacent address spaces. Then, the order is followed by the second cluster of columns in the switching cells in the first row, followed by the second cluster in the columns in the switching cells in the second row, followed by the switching cells in the third row The second cluster of each column, ... up to the last cluster of the last column in the last row of switching units, in this way for the second cluster of all types of configurable units.

As described above, the following pseudo code shows how to generate a linear memory address for a switch unit (comp_switch) using the order of memory addresses for the configuration data of the switch unit. The pseudocode uses 4 inputs: comp_id: component identifier (component identifier); comp_col: column identifier (row identifier); comp_row: row identifier (column identifier); comp_chunk: chunk number (cluster number); and produces the output: linear_address: linear memory address for an unload chunk (the linear memory address of the unload cluster);

其中 • comp_switch表示切換單元； • NUM_ROW_SW為所有切換單元之列的數量； • COMP_COUNT_ALL為所有可組態單元的總和。Pseudocode for generating linear memory addresses for a particular offload cluster of switching units is as follows:

Where • comp_switch represents the switching unit; • NUM_ROW_SW is the number of all switching units; • COMP_COUNT_ALL is the sum of all configurable units.

To generate linear memory addresses for a specific offload cluster of PCU, PMU, or AGCU units, a similar code can be used. One difference is that the number of ranks of all switching units is different from the number of ranks of all PCUs, the number of ranks of all PMUs, and the number of ranks of all AGCUs. Another difference is that the linear memory addresses for the switch unit can start at the base address (eg 0), while the linear memory addresses for the PCU, PMU and AGCU are at the end of the switch unit, PCU, and PMU respectively. The address after the cluster starts.

FIG. 14 is a flowchart showing the unit configuration unloading process in the configurable unit. At step 1431, configuration data from clusters of configuration sequence chains in the configuration data store are sequentially transferred into the output shift register (650, FIG. 6). The flow proceeds to step 1432 .

At step 1432, the cell configuration offload process waits for an output FIFO (660, Figure 6) or other type of output buffer circuit to become active. At step 1433, when the output FIFO becomes active, the configuration data from the cluster of output shift registers is inserted into the output FIFO. At step 1434, the configuration data of the cluster in the output FIFO is written to the bus system (FIG. 3).

At step 1435, the unit configuration offload process determines whether the configuration data of the first cluster is the configuration data of the last cluster in the configuration data store. If so, the unloading of the configuration data of the configurable unit is completed. If not, the flow transitions back to step 1431 and the configuration data from the second cluster of the configuration data store is sequentially transferred into the output shift register.

While the present invention has been disclosed with reference to the preferred embodiments and the above-detailed examples, it should be understood that these examples are for illustration only and not for limitation. It should be considered that modifications and combinations will easily occur to those with ordinary knowledge in the art, and the modifications and combinations will fall within the spirit of the present invention and the scope of the following claims.

110: Reconfigurable Data Processor 115: Busbar system 120: host 130: External I/O interface 140: memory 150: External I/O interface 170: External clock generator 175: clock signal 190: Array of Configurable Units 195: Configuration Load/Unload Controller 205: External I/O interface 211: Top Switcher 212: Top Switcher 213: Top Switcher 214: Top Switcher 215: Top Switcher 216: Top Switcher 300: Array of Configurable Units 301: Configuration load/unload controller 311: Switch unit 312: Switch unit 320: Link 321: Interconnect 331: Link 341: Pattern Memory Cell 400: Configurable unit 410: Input configuration data 420: Configuration data storage 421: Line 422: Line 430: Output configuration data 440: Unit Configuration Loading Logic 450: Scalar FIFO 460: FIFO block 470: Control Block 480: block 491: Daisy Chain Completion Bus 492: Daisy Chain Command Bus 493: Daisy Chain Logic 610: Input FIFO 620: Input shift register 630: Configure Sequence Chain 640: Configure Sequence Chain 650: Output shift register 660: Output FIFO 670: selector 711: Steps 712: Steps 714: Steps 716: Steps 810: Steps 811: Steps 812: Steps 813: Steps 814: Steps 815: Steps 816: Steps 1221: Steps 1222: Steps 1223: Steps 1224: Steps 1225: Steps 1431: Steps 1432: Steps 1433: Steps 1434: Steps 1435: Steps A0: address A1: address A2: address A3: address A4: address A5: address AG: address generator AGCU12: Address Generation and Merging Unit AGCU13: Address Generation and Merging Unit AGCU14: Address Generation and Merge Unit AGCU22: Address Generation and Merging Unit AGCU23: Address Generation and Merging Unit AGCU24: Address Generation and Merge Unit C0: bus cycle C1: bus cycle C2: Bus cycle C2y-1: bus cycle CU: Merge Unit Cy: bus cycle Cy+1: bus cycle Cy+2: bus cycle Cy-1: Bus cycle L11: Link L12: Link L21: Link L22: Link LSB: Least Significant Bit MAGCU1: Address Generation and Merging Unit MAGCU2: Address Generation and Merging Unit MSB: Most Significant Bit P11: Cluster configuration file P12: Cluster configuration file P21: Cluster configuration file P22: Cluster configuration file P31: Cluster configuration file P32: Cluster configuration file PCU: Pattern Calculation Unit PMU: Pattern-like memory unit PY1: Cluster configuration file PY2: Cluster configuration file S: switch unit Stage 1: Stage Stage N: Stage Tile1: block Tile2: Square

[FIG. 1] is a system diagram showing a system including a host, a memory, and a reconfigurable data processor.

[Fig. 2] is a simplified block diagram of the top-level network and components of the Coarse Grain Reconfigurable Architecture (CGRA).

[FIG. 3] is a simplified diagram of a block and an array-level network that can be used in the configuration of FIG. 2, where the configurable units in the array are nodes on the array-level network.

[FIG. 3A] shows an example of a switching unit connected to elements in an array layer network.

[FIG. 4] is a block diagram showing an example configurable unit.

[FIG. 5] shows an example of a state machine diagram that may be used to control the cell configuration loading process in a configurable cell.

[FIG. 6] is a logical representation of the structure supporting the loading of configuration memory in a configurable unit.

[FIG. 7] is a flow chart showing the operation of a host coupled to a reconfigurable data processor.

[FIG. 8] is a flowchart showing the operation of a configuration load controller, which may be the main AGCU or otherwise part of the communication with the configurable units of the array in the block.

[Figure 9] shows an example organization of configuration files.

[FIG. 10] is a state machine diagram showing an example of the logic used to execute the array configuration loading process for systems like those of FIGS. 2 and 3. FIG.

[FIG. 11] is a timing diagram showing the timing of the allocation sequence of an earlier round similar to FIG. 10. FIG.

[Fig. 12] is a flowchart showing the unit configuration loading process in the configurable unit.

[FIG. 13] is a state machine diagram showing an example of logic to execute the array configuration offload processing for systems like those of FIGS. 2 and 3. FIG.

[FIG. 14] is a flowchart showing the unit configuration unloading process in the configurable unit.

110: Reconfigurable Data Processor

115: Busbar system

120: host

130: External I/O interface

140: memory

150: External I/O interface

170: External clock generator

175: clock signal

190: Array of Configurable Units

195: Configuration Load/Unload Controller

Claims (60)

A reconfigurable data processor comprising: a busbar system; Configurable cells connected to an array of the bus system, the configurable cells in the array including configuration data storage to store a plurality of subfiles containing configuration data specific to the corresponding configurable cells unit file; wherein each of the configurable units in the plurality of configurable units includes logic for performing a unit configuration loading process that includes receiving, via the bus system, a process specific to the configurable unit a subfile of a unit file, and loading the received subfile into the configuration memory of the configurable unit; and A configuration load controller connected to the bus system includes logic for executing an array configuration load process, the array configuration load process including assigning a cell file to a plurality of configurable cells in the array A configuration file, each of the unit files containing a plurality of ordered subfiles, by the bus system in a sequence of N rounds (R(i), i from 0 to N-1) A unit subfile of (i) is sent to all configurable units including at most (i+1) subfiles among the plurality of configurable units. The processor of claim 1, wherein the plurality of configurable cells comprise all of the configurable cells in the array and are used for the processing of one or more of the configurable cells The unit file implements a no-op configuration. The processor of claim 1, wherein the configuration data stores in the configurable cells of the plurality of configurable cells comprise serial chains, and the cell configuration load processing from The bus system receives a first sub-file of the cell file specific to the configurable cell, begins to process the received first sub-file during a subsequent bus cycle before a second sub-file of the cell file is received subfiles are pushed into the sequence chain, the second subfile of the cell file specific to the configurable cell is received from the bus system for the next turn of the sequence in a later bus cycle, and Pushing the second subfile received into the sequence chain begins during the cycle of the sequence after the earlier received subfile is pushed into the sequence chain. The processor of claim 3, wherein the first subfile is grouped by the unit in the configurable unit before the second subfile of the plurality of sorted subfiles is received by the configurable unit state loading processing consumption. The processor of claim 1, wherein the array configuration load process includes receiving a configuration load command from a host process identifying the location of the configuration file in memory, and generating one or more memories in response to the command Access request to retrieve the configuration file. The processor of claim 1, wherein for each configurable unit in the plurality of configurable units, the configuration file includes a plurality of sub-files of the unit file, the sub-files being arranged in an interleaved manner consistent with the sequence in the configuration file, and wherein the array configuration loading process includes routing the subfiles to configurable units based on their location in the configuration file. The processor of claim 1, wherein the subfile has an amount of N bits of data, and the bus system is configured to transfer the N bits of data in one bus cycle. The processor of claim 7, wherein the configuration data stores in the configurable cells of the plurality of configurable cells comprise serial chains, and the cell configuration load processing is performed in one bus cycle from The bus system receives a first subfile of the cell file specific to the configurable cell, pushes the received first subfile into the sequence chain during N subsequent bus cycles, and at a A second subfile of the cell file specific to the configurable cell is received from the bus system in a later bus cycle, and at N after pushing the earlier received subfile into the sequence chain The received second subfile is pushed into the sequence chain during a subsequent bus cycle. The processor of claim 8, wherein the array includes more than N configurable cells. The processor of claim 1, wherein the array includes more than one type of configurable cell, and the cell files for different types of configurable cells include different numbers of subfiles of configuration data. The processor of claim 1, wherein the unit files for a configurable unit of a first type include Z1 sub-files, and the unit files for a second type of configurable unit include Z2 sub-files file, where Z1 is less than Z2, and the array configuration load process includes: Retrieve a segment of the configuration file that includes sub-file (i) of the unit files for all configurable units of the first type and second type, where (i) goes from 0 to Z1-1, and then A segment of the configuration file including sub-file (i) of the unit files for all configurable units of the second type is retrieved, where (i) is from Z1 to Z2-1. The processor of claim 1, wherein the configurable cells in the array of configurable cells include individual load completion status logic connected in a daisy chain starting and ending at the array configuration load logic. The processor of claim 12, wherein the array configuration load logic forwards a load complete signal on the daisy chain after the configuration file is allocated, and in each configurable unit in the array, when the When the load complete signal is received for a previous member of the chain and the loading of its cell file is complete, the load complete state logic forwards the load complete signal on the daisy chain. The processor of claim 1, wherein the bus system includes a top layer network and an array layer network, the top layer network includes an external data interface and an array interface, and the array layer network is connected to the array interface and to the configurable units of the array's configurable units. The processor of claim 14, wherein the array configuration load process includes receiving a configuration load command from a host process identifying the location of the configuration file in memory, and generating a configuration load command via the top-level network in response to the command or more memory access requests to retrieve the configuration file through the external data interface. The processor of claim 15, wherein the array configuration load process routes the subfiles of configuration data to the array layer network using addresses implied by the locations of the subfiles in the configuration file and other configurable units. The processor of claim 1, wherein the configurable elements of the plurality of configurable elements are used for routing in the bus system during execution after configuration is also used in the configuration loading process. A method for operating a reconfigurable data processor comprising a bus system and configurable units connected to an array of the bus system, the configurable units in the array The state unit includes a configuration data store to store a unit file including a plurality of sub-files of configuration data specific to the corresponding configurable unit, the method comprising: For a plurality of configurable cells in the array, a configuration file is allocated that includes a cell file, each of which includes a plurality of ordered sub-files, by which in N rounds (R(i), i from 0 to N-1) in the sequence via the bus system sends a unit subfile of order (i) to all configurables including at most (i+1) subfiles in the plurality of configurable units unit; and The subfiles specific to a unit file of the configurable unit are received, and the received subfiles are loaded into the configuration memory of the configurable unit. The method of claim 18, wherein the plurality of configurable cells comprise all of the configurable cells of the array and are used for the configurable cell of one or more of the configurable cells The unit file implements a no-op configuration. The method of claim 18, wherein the configuration data stores in configurable units of the plurality of configurable units comprise serial chains, the method comprising receiving at a particular configurable unit in a bus cycle A first subfile of the unit file in the configuration unit begins to push the received first subfile into the sequence chain during a subsequent bus cycle before a second subfile of the unit file is received , and the second subfile of the cell file received in the particular configurable cell for the next round of the sequence in a later bus cycle, and the subfile to be received earlier upon completion Pushing into the sequence chain begins to push the received second subfile into the sequence chain during the cycle of the sequence. The method of claim 20, wherein before the second subfile of the plurality of ordered subfiles is received by a configurable unit, the first subfile is configured by the unit in the configurable unit Load processing consumption. The method of claim 18, comprising receiving from a host process a configuration load command identifying the location of the configuration file in memory prior to said assigning, and generating one or more memory accesses in response to the command Request to retrieve this configuration file. The method of claim 18, wherein for each configurable unit in the plurality of configurable units, the configuration file includes a plurality of sub-files of the unit file, the sub-files being disposed in the configuration file in an interleaved manner and the method includes routing the subfiles to configurable units based on their location in the configuration file. The method of claim 23, wherein the subfile has an amount of N bits of data, and the bus system is configured to transmit the N bits of data in one bus cycle. The method of claim 24, wherein the configuration data stores in the configurable cells of the plurality of configurable cells comprise serial chains, the method comprising in a bus cycle in a configurable cell Receives a first subfile of the cell file specific to the configurable cell at and pushes the received first subfile into the sequence chain during N subsequent bus cycles, and at a later Receives a second subfile of the cell file specific to the configurable cell in the bus cycle of , and during N subsequent bus cycles after pushing the earlier received subfile into the sequence chain Push the received second subfile into the sequence chain. The method of claim 25, wherein the array includes more than N configurable cells. The method of claim 18, wherein the array includes more than one type of configurable cell, and the cell files for different types of configurable cells include different numbers of subfiles of configuration data. The method of claim 18, wherein the unit files for a configurable unit of a first type include Z1 subfiles, and the unit files for a second type of configurable unit include Z2 subfiles , where Z1 is less than Z2, the method includes: Retrieve a segment of the configuration file that includes sub-file (i) of the unit files for all configurable units of the first type and second type, where (i) goes from 0 to Z1-1, and then A segment of the configuration file including sub-file (i) of the unit files for all configurable units of the second type is retrieved, where (i) is from Z1 to Z2-1. The method of claim 18, comprising loading a completion state in a daisy chain of configurable units. The method of claim 29, comprising forwarding a load complete signal from a first node on the daisy chain after the configuration file is allocated, and in each configurable unit in the array, when the When the load complete signal of a previous node is received and the loading of its cell file is completed, the load complete signal is forwarded on the daisy chain. The method of claim 18, comprising receiving from a host process a configuration load command identifying the location of the configuration file in memory, and generating one or more memory access requests in response to the command via a top-level network to retrieve the configuration file. The method of claim 31, wherein the array configuration load process routes the subfiles of configuration data to the subfiles over the array layer network using addresses implied by the locations of the subfiles in the configuration file Configurable unit. The method of claim 18, during execution, after configuration is also used for routing in the bus system after said allocation process. A reconfigurable data processor comprising: busbar system; Configurable cells connected to an array of the busbar system, the configurable cells in the array including configuration data storage arranged in a serial chain to store groups comprising configurable cells specific to the corresponding A unit file of a plurality of sub-files of state data; and A configuration load controller connected to the bus system includes logic for assigning a configuration file containing cell files to the plurality of the configurable cells in the array of parallel subfiles. A method for operating a reconfigurable data processor comprising a bus system and configurable units connected to an array of the bus system, the configurable units in the array The state unit includes a configuration data store disposed in the serial chain to store a unit file including a plurality of sub-files of configuration data specific to the corresponding configurable unit, and the method includes: A configuration file containing cell files is allocated to a plurality of configurable cells in the array of parallel subfiles. A reconfigurable data processor comprising: a busbar system; Configurable cells connected to an array of the bus system, the configurable cells in the array including configuration data storage to store a plurality of subfiles containing configuration data specific to the corresponding configurable cells unit file; and A configuration offload controller connected to the bus system includes logic for executing an array configuration offload process, the array configuration offload process including assigning a command to a plurality of configurable units in the array to unloading the cell files specific to the corresponding configurable cell, the cell files each containing a plurality of ordered subfiles, receiving the subfiles from the configurable cells of the array via the bus system, and according to the subfiles the configurable unit of the unit file of which the file is a part and the order of the subfile in the unit file to combine an unload configuration file by setting the received subfile in memory; wherein each of the configurable units in the plurality of configurable units includes logic for executing a unit configuration unloading process, the unit configuration unloading process includes unloading the configurable unit from the configuration storage of the configurable unit Equal sub-files and transfer the sub-files of a unit file specific to the configurable unit to the configuration offload controller via the bus system. The processor of claim 36, wherein the configuration data store in a configurable unit of the plurality of configurable units includes a sequence chain and an output buffer coupled to the sequence chain, and the The cell configuration offload process transfers the subfiles of the cell file from the sequence chain to the output buffer, and transfers the subfiles from the output buffer on the bus system. The processor of claim 36, wherein the array configuration offload process comprises receiving a configuration offload command from a host process, the configuration offload command identifying an address location in memory where to store an offload configuration file, And the combining step includes calculating an address offset from the address location for the sub-files. The processor of claim 36, wherein for each configurable unit in the plurality of configurable units, the configuration file includes a plurality of sub-files of a unit file having up to M files with data in the unit The child files of order (i) in the file, and are set in the unload configuration file such that for all unit files in the unload configuration file, all child files of order (i) are stored in the corresponding memory The address space of block (i) of , where (i) is from 0 to M-1. The processor of claim 39, wherein the array includes more than one type of configurable cell, and the cell files for different types of configurable cells include different numbers of subfiles of configuration data, and wherein the Within the address space of a block (i), for each type of configurable unit, the subfiles are stored in groups of adjacent addresses within the block (i). The processor of claim 36, wherein the subfile has an amount of N bits of data, and the bus system is configured to transfer the N bits of data in one bus cycle. The processor of claim 36, wherein the cell files of the configurable cells in the array of configurable cells have at most M subfiles, and the subfiles received by the setting are in memory Steps include: Store the offload configuration file in memory at addresses in blocks (i), where (i) ranges from 0 to at most M-1, and for blocks (i) at addresses in the plurality of configurable all configurable cells in a cell store subfiles (i) of those cell files; and The transmitting subfile step includes sending a packet on the bus system having a header and a payload, the payload including the subfiles, and the header identifying the configurable from the subfile being sent The unit and the order in which the subfile is identified. The processor of claim 36, wherein the bus system includes a top layer network and an array layer network, the top layer network includes an external data interface and an array interface, and the array layer network is connected to the array interface and to the configurable units of the array's configurable units. The processor of claim 43, wherein the array configuration offload process uses addresses implied by the order of the subfiles in the cell files of the configurable cells via the top-level network to Subfiles of uninstalled configuration files are routed to memory. The processor of claim 43, wherein the cell configuration offload process uses addresses implied by the order of the subfiles in the cell files of the configurable cells via the top-level network to Subfiles of uninstalled configuration files are routed to memory. The processor of claim 36, wherein a configurable unit of the plurality of configurable units is used in the bus system during execution before the configuration file is unloaded and also used in the configuration unloading process route. The processor of claim 36, wherein the cell files include a plurality of ordered subfiles, and the offload configuration file for an array of configurable cells is combined such that for all configurable cells of the same type , subfiles of the same order are stored in the address space of a block such that the position of a subfile in the offload configuration file corresponds to the configurable unit in the subfile of the array and is specific to the The order of configurable cells in this cell file. A method for operating a reconfigurable data processor comprising a bus system and configurable units connected to an array of the bus system, the configurable units in the array The state unit includes a configuration data store to store a unit file including a plurality of sub-files of configuration data specific to the corresponding configurable unit, the method comprising: assigning a command to a plurality of configurable cells in the array to unload the cell files specific to the corresponding configurable cell, each of the cell files containing a plurality of ordered subfiles; A subfile is received from the bus system from a configurable cell of the array, and the configurable cell of the cell file of which the subfile is a part and the subfile in the cell file are ordered by Set the received subfile in memory to assemble an uninstall configuration file. The method of claim 48, comprising unloading the subfiles from the configuration store of the configurable unit and transferring the subfiles of a unit file specific to the configurable unit to the configuration via the bus system Uninstall the controller. The method of claim 48, wherein the configuration data store in a configurable unit of the plurality of configurable units includes a serial chain and an output buffer coupled to the serial chain, and the The unloading step includes transferring the sub-files of the unit file out of the sequence chain to the output buffer, and transferring the sub-files from the output buffer on the bus system. The method of claim 48, comprising receiving a configuration unload command from a host process, the configuration unload command identifying an address location in memory where to store an unload configuration file, and the combining step includes for the The subfile calculates the address offset from this address location. The method of claim 48, wherein for each configurable unit in the plurality of configurable units, the configuration file includes a plurality of sub-files of a unit file, the unit files having up to M files with data in the unit file subfiles in order (i), and are set in the uninstall configuration file such that for all unit files in the uninstall configuration file, all subfiles in order (i) are stored in the corresponding memory The address space of block (i), where (i) is from 0 to M-1. The method of claim 52, wherein the array includes more than one type of configurable cell, and the cell files for different types of configurable cells include different numbers of subfiles of configuration data, and one of them Within the address space of block (i), for each type of configurable unit, the subfiles are stored in groups of adjacent addresses within the address space of block (i). The method of claim 48, wherein the subfile has an amount of N bits of data, and the bus system is configured to transmit the N bits of data in one bus cycle. The method of claim 48, wherein the cell files of the configurable cells in the array of configurable cells have at most M subfiles, and the step of setting the received subfiles in memory include: Store the offload configuration file in memory in the address space of a plurality of blocks (i), where (i) is from 0 to at most M-1, and for blocks in the address space of block (i) in the address space all configurable units of the plurality of configurable units store sub-files (i) of the unit files; and Subfiles are transmitted from the configurable units in the array by sending packets with a header and a payload on the bus system, the payload includes a subfile, and the header is sent from The subfile in the payload identifies the configurable unit and identifies the order of the subfile. The method of claim 48, wherein the bus system includes a top layer network and an array layer network, the top layer network includes an external data interface and an array interface, and the array layer network is connected to the array interface and to the configurable units of the configurable units of the array. The method of claim 56, wherein the array configuration offload process uses an address implied by the order of the subfiles in the unit files of the configurable units via the top-level network to offload the offload Subfiles of configuration files are routed to memory. The method of claim 56, wherein the cell configuration offload process uses an address implied by the order of the subfiles in the cell files of the configurable cells via the top-level network to offload the cell configuration Subfiles of configuration files are routed to memory. The method of claim 48, including using routing in the bus system before unloading the configuration file is also used to receive the subfiles during execution. The method of claim 48, wherein the cell files include a plurality of ordered subfiles, and the offload configuration file for an array of configurable cells is combined such that for all configurable cells of the same type, Subfiles in the same order are stored in a linear address space such that the location of a subfile in the offload configuration file corresponds to the configurable unit in the subfile of the array and specific to the configurable its order in the unit file of the state unit.

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