TWI762993B - Ultra-high voltage device - Google Patents

Abstract

An ultra-high voltage device includes a substrate, an interdigitated source electrode, an interdigitated drain electrode, and a gate electrode. The interdigitated source electrode is disposed on a surface of the substrate, and the interdigitated source electrode includes a plurality of first interdigitated portions and a peripheral portion surrounding the first interdigitated portions. The interdigitated drain electrode is disposed on the surface of the substrate, and the interdigitated drain electrode is a mirror-symmetrical pattern complementary to the interdigitated source electrode. The gate electrode is disposed on the substrate between the interdigitated source electrode and the interdigitated drain electrode. The layout of the interdigitated source electrode and the interdigitated drain electrode can uniform E-field distribution and prevent the occurrence of local current crowding effect.

Description

Ultra-high voltage components

The present invention relates to an ultra-high voltage device technology, and in particular, to an ultra-high voltage device (UHV device) for improving the uneven distribution of electric field.

In recent years, ultra-high voltage components such as laterally diffused metal oxide semiconductor power transistors (LDMOS) have been widely developed and integrated for solar energy, light emitting diode drivers (LED drivers) and motor drivers, etc. Therefore, the development of electrostatic discharge protection (ESD protection) It plays an important role in ultra-high voltage components.

Electrostatic discharge (Electrostatic Discharge, ESD) test simulates the possible damage caused by external static electricity to the IC, and discharges static electricity between the pin (PIN) and PIN of the IC. At present, the ultra-high voltage laterally diffused NMOS (UHV LDNMOS) architecture is connected to the PIN in the IC application, including the drain (Drain), the source (Source) and the base (Bulk), and the other terminals such as the gate (Gate) are connected to The internal circuit controls the UHV LDNMOS channel on or off by the internal circuit.

However, through ESD testing, it is found that the layout with interdigitated electrodes generally has a non-uniform E-field distribution and a local current crowding effect, resulting in safe turn-on. The operating area (SOA) is not enough and the ESD cannot reach the Human Body Model (HBM) minimum specification of 2kV.

The above problem is caused by the uneven electric field and uneven current generated at the large curvature of the fork-shaped Drain end corner, which is the damage point of the device under the ESD and SOA tests. Therefore, in terms of ESD protection of ultra-high voltage components, external high-voltage ESD protection components are usually used, but this will occupy an excessively large area and be difficult to manufacture.

The present invention provides an ultra-high voltage element, which can improve the problem of uneven distribution of electric field, and does not require an external high-voltage ESD protection element.

The ultra-high voltage device of the present invention includes a substrate, an interdigitated source electrode, an interdigitated drain electrode and a gate electrode. The interdigitated source electrode is disposed on the surface of the substrate, and the interdigitated source electrode includes a plurality of first interdigitated portions and a peripheral portion surrounding the first interdigitated portions. The interdigitated drain electrodes are disposed on the surface of the substrate, and the interdigitated drain electrodes are mirror-symmetrical and complementary to the interdigitated source electrodes. The gate electrode is disposed on the substrate between the interdigitated source electrode and the interdigitated drain electrode.

In an embodiment of the present invention, the pattern of the interdigitated drain electrodes includes a central portion and a plurality of second interdigitated portions extending from the central portion to both sides.

In an embodiment of the present invention, the above-mentioned ultra-high voltage component further includes a lead connected to the central portion.

In an embodiment of the present invention, the peripheral portion of the interdigitated source electrode is a closed ring.

In an embodiment of the present invention, the number of the first interdigitating portions is M, and the number of the second interdigitating portions is (M+2), where M is an even number.

In an embodiment of the present invention, the gate electrode and the interdigitated source electrode are partially overlapped.

In an embodiment of the present invention, the gate electrode and the interdigitated drain electrode are separated by a predetermined distance.

In an embodiment of the present invention, the above-mentioned ultra-high voltage element is a laterally diffused N-type metal-oxide-semiconductor power transistor.

Based on the above, the ultra-high voltage device of the present invention can improve the uneven electric field distribution, reduce the high curvature region in the device, and reduce the corner current crowding effect in the corner region through the interdigitated source electrode and the interdigitated drain electrode of the specific layout. , thus enhancing ESD capability and improving SOA without affecting the performance of ultra-high voltage components. In addition, because the present invention can achieve the above-mentioned effects by changing the layout design, not only does it not require external high-voltage ESD protection components, but also can be integrated into existing manufacturing without increasing the number of masks.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.

The following examples are described in detail with the accompanying drawings, but the provided examples are not intended to limit the scope of the present invention. In addition, the drawings are for illustrative purposes only and are not drawn in full scale. In order to facilitate understanding, the same elements in the following description will be denoted by the same symbols.

FIG. 1A is a schematic top view of an ultra-high voltage device according to an embodiment of the present invention. Fig. 1B is a schematic cross-sectional view of the line segment I-I' of Fig. 1A.

Referring to FIG. 1A and FIG. 1B , the ultra-high voltage device includes a substrate 100 , an interdigitated source electrode 102 , an interdigitated drain electrode 104 and a gate electrode 106 . The interdigitated source electrode 102 is disposed on the surface 100a of the substrate 100. The interdigitated source electrode 102 includes a plurality of first interdigitated portions 102a and a peripheral portion 102b surrounding the first interdigitated portions 102a, wherein the The peripheral portion 102b is, for example, a closed ring. In FIG. 1A, two first interdigitated portions 102a are shown, but the present invention is not limited thereto. The interdigitated drain electrodes 104 are also disposed on the surface 100 a of the substrate 100 , and the interdigitated drain electrodes 104 are mirror-symmetrical and complementary to the interdigitated source electrodes 102 ; for example, the interdigitated drain electrodes 104 are The pattern may include a central portion 104a and a plurality of second interdigitated portions 104b extending from the central portion 104a to both sides. Therefore, if the number of the first interdigitated portions 102a is M, then the number of the second interdigitated portions 104b The number is (M+2), where M is an even number. As shown in FIG. 2 , when the number of the first interdigitating portions 102a is 4, the number of the second interdigitating portions 104b is 6, and so on. In this embodiment, the ultra-high voltage element further includes a pin (not shown) that is connected to the connecting portion 108 of the central portion 104a. Since the junction 108 of the interdigitated drain 104 is located away from the corner of the peripheral portion 102b of the interdigitated source 102, the electric field can be uniformized and the current crowding effect can be reduced, so that the current of the ultra-high voltage device is mainly in the horizontal direction of the flat side. Mainly to reduce high curvature areas and avoid damage to corner areas to improve ESD and SOA capabilities.

Please continue to refer to FIG. 1B , the gate electrode 106 is disposed on the substrate 100 between the interdigitated source electrode 102 and the interdigitated drain electrode 104 . In this embodiment, the gate electrode 106 and the interdigitated source electrode (the outer portion 102b) partially overlap, and the gate electrode 106 and the interdigitated drain electrode (the second interdigitated portion 104b) are separated by a predetermined distance. In the present embodiment, the ultra-high voltage element is an N-type metal-oxide-semiconductor power transistor, such as a laterally diffused N-type metal-oxide-semiconductor power transistor (LDNMOS), which may also be formed in the substrate 100 and connected to the substrate 100 through the contact window 110a. The source region 112 of the peripheral portion 102b, the drain region 114 formed in the substrate 100 and connected to the second interdigitated portion 104b through the contact window 110b, the insulating structure 116 located under part of the gate electrode 106 and extending to the drain region 114 , the gate insulating layer 118 , the base (bulk) region not shown next to the source region 112 and other components. Therefore, by arranging the junction 108 of the interdigitated drain 104 at the central portion 104a, when ESD occurs, the LDNMOS and the parasitic BJT element can be turned on to discharge the ESD current evenly, and the current crowding effect can be reduced at the same time. At the same time, the SOA capability of the components is improved. Moreover, it can be seen from FIG. 1B that the device itself does not need to add a structure of a mask manufacturing process, so the sequence of the existing device manufacturing process can be used, and no external high-voltage ESD protection device is required.

In order to verify the efficacy of the present invention, please refer to the following experiments, but the scope of the present invention is not limited to the following contents.

<Comparative example>

An ultra-high voltage device as shown in FIG. 3A is fabricated, and its overall width and length are generally designed with interdigitated electrodes. The drain terminal pin is connected to the bonding portion 300, which has high curvature regions 310a and 310b.

Then, the test was accumulated at intervals of 0.5KV to obtain Fig. 3B.

<Experimental example>

To manufacture an ultra-high voltage device as shown in FIG. 1A , its overall width is increased by about 15% compared with the layout generally designed with interdigitated electrodes, and the overall length is the same as the layout generally designed with interdigitated electrodes.

Then, the test is accumulated at intervals of 0.5KV, and Figure 4 is obtained.

Through the results of Figure 3B and Figure 4, it is determined whether it fails, and the failure standard is that the leakage current increases or the BV exceeds the 550V specification. The results are therefore shown in Table 1 below.

Table 1 Control example Experimental example leakage current 1KV ＞2.5KV breakdown voltage 1.5KV ＞2.5KV

From Table 1, it is apparent that the present invention can withstand higher operating voltages.

To sum up, the present invention moves the Drain Pad away from the corner of the Source (and the Bulk) by changing the layout, so as to make the electric field uniform and reduce the current crowding effect, so that the current of the element is mainly in the horizontal direction, and this The invention does not have the high-curvature regions of the conventional ultra-high voltage devices (such as the high-curvature regions 310a and 310b in FIG. 3A ), therefore, the damage of the corner regions can be avoided, the ESD and SOA capabilities can be improved, and the performance of the ultra-high voltage device is not affected, such as Maintain ultra-high voltage device characteristics and breakdown voltage. In addition, the above structural changes will not increase the number of masks, and only the order of the existing component manufacturing process can be used. Compared with the traditional method that requires external high-voltage ESD protection components, not only the process cost is low, but additional area is not required to add The above high voltage ESD protection components.

Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the appended patent application.

100: Substrate 100a: Surface 102: Interdigitated source 102a: first interdigital 102b: Peripheral 104: Forked Drain 104a: Central Section 104b: second interdigital 106: Gate 108, 300: Joint 110a, 110b: Contact windows 112: source region 114: Drain region 116: Insulation structure 118: gate insulating layer 310a, 310b: high curvature area

FIG. 1A is a schematic top view of an ultra-high voltage device according to an embodiment of the present invention. Fig. 1B is a schematic cross-sectional view of the line segment I-I' of Fig. 1A. FIG. 2 is a schematic top view of another ultra-high voltage element according to an embodiment of the present invention. FIG. 3A is a schematic top view of the ultra-high voltage element of the comparative example. Figure 3B is a graph of the I-V curves of the control at different KVs. Fig. 4 is the I-V curve diagram of the experimental example at different KV.

100: Substrate 102: Interdigitated source 102a: first interdigital 102b: Peripheral 104: Forked Drain 104a: Central Section 104b: second interdigital 108: Joints

Claims (8)

An ultra-high voltage element, comprising: a substrate; an interdigitated source electrode disposed on a surface of the substrate, the interdigitated source electrode comprising a plurality of first interdigitated portions and surrounding the plurality of first fingers a peripheral portion of the fork portion; a finger-shaped drain electrode disposed on the surface of the substrate, and the finger-shaped drain electrode is a mirror-symmetrical pattern complementary to the finger-shaped source electrode; and a gate The electrode is disposed on the substrate between the interdigitated source electrode and the interdigitated drain electrode. The ultra-high voltage device of claim 1, wherein the pattern of the interdigitated drain electrodes comprises a central portion and a plurality of second interdigitated portions extending from the central portion to both sides. The ultra-high voltage component according to claim 2, further comprising a lead connected to the central portion. The ultra-high voltage element according to claim 1, wherein the peripheral portion of the interdigitated source electrode is a closed ring. The ultra-high voltage element according to claim 2, wherein the number of the plurality of first fingers is M, the number of the plurality of second fingers is (M+2), and M is an even number . The ultra-high voltage element of claim 1, wherein the gate and the interdigitated source partially overlap. The ultra-high voltage device of claim 1, wherein the gate electrode and the interdigitated drain electrode are separated by a predetermined distance. The ultra-high voltage element according to claim 1, wherein the ultra-high voltage element is a laterally diffused N-type metal-oxide-semiconductor power transistor.

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