TWI762239B - Direct current offset protection circuit and method - Google Patents

Abstract

A direct current (DC) offset protection circuit includes: a DC offset detection circuit and a control circuit. The DC offset detection circuit is arranged to detect whether a DC component exists in pulse-width-modulation (PWM) signals and accordingly generate a DC offset detection result. The control circuit is arranged to control an audio system according to the DC offset detection result. The DC offset detection circuit comprises a PWM polarity judgment circuit, a cascaded integrator-comb (CIC) filter and a DC offset judgment circuit. The PWM polarity judgment circuit is arranged to judge a polarity of complementary PWM signals and accordingly generate a polarity indication value. The CIC filter is arranged to generate a filter output signal by averaging a plurality of polarity indication values. The DC offset judgment circuit is arranged to generate the DC offset detection result by comparing the filter output signal with a predetermined DC threshold.

Description

DC offset protection circuit and method

The present invention relates to an audio system, in particular to a DC offset protection circuit and method for detecting DC components in the audio system and performing protection control.

In audio systems, protection of circuits and components is a necessary design consideration, one of which is output DC offset protection. Generally speaking, the DC offset voltage is defined as the DC voltage level at the input or output of a circuit when no voltage is applied to the input of the circuit. DC offset voltage at the output can be caused by component/component mismatch, component degradation over time, electrical overstress, or other factors. The DC offset voltage will cause a large amount of DC current to flow through the speakers of the audio system, possibly causing irreversible damage to the speakers. Also, there is a risk of burning due to the large amount of DC current drain on the speaker. In view of this, the DC offset voltage may have a negative impact on the audio system, so it needs to be appropriately reduced.

Based on the above reasons, one of the objectives of the present invention is to provide a DC offset protection circuit and method for an audio system. In various embodiments of the present invention, a DC offset detection mechanism is provided to detect DC components in pulse width modulated signals, which are commonly used in audio systems based on class D amplifiers . The DC offset detection mechanism of the present invention mainly relies on cascaded integrator-comb (CIC) filters to average the samples of the PWM signal Calculated to detect the DC component in the PWM signal.

An embodiment of the present invention provides a DC offset protection circuit for an audio system. The DC offset protection circuit includes a DC offset detection circuit and a control circuit. The DC offset detection circuit is used for detecting whether a DC component exists in a plurality of pulse width modulation signals, and generates a DC offset detection result accordingly. The control circuit is used for controlling at least a part of the audio system according to the DC offset detection result. The DC offset detection circuit includes: a pulse width modulation polarity judgment circuit, a cascaded integrator-comb filter and a DC offset judgment circuit. The pulse width modulation polarity judgment circuit is used for judging the polarity of the complementary pulse width modulation signal pair, and generates a polarity indication value accordingly. The cascaded integrator-comb filters are used to generate a filter output signal by averaging a plurality of polarity indicating values. The DC offset determination circuit is used for comparing the output signal of the filter with at least a DC offset threshold value to generate the DC offset detection result accordingly.

An embodiment of the present invention provides a DC offset protection method for an audio system. The method includes: judging the polarity of the complementary pulse width modulation signal pair, and generating a polarity indication value accordingly; using a cascaded integrator-comb filter to average a plurality of polarity indication values to generate a filter output signal; The filter output signal is compared with at least a DC offset threshold to generate a DC offset detection result; and according to the DC offset detection result, at least a part of the audio system is controlled.

10: Audio system

15: Audio signal processing circuit

20: Power stage

30: DC offset protection circuit

100: DC offset detection circuit

110: PWM polarity judgment circuit

120:CIC filter

122, 123, 126: Scratchpad circuit

130: DC offset judgment circuit

200: Control circuit

FIG. 1 is a schematic structural diagram of a DC offset protection circuit used in an audio system according to an embodiment of the present invention.

FIG. 2 illustrates the structure of the DC offset detection circuit in the DC offset protection circuit according to the embodiment of the present invention Schematic.

FIG. 3 is a schematic structural diagram of a cascaded integrator-comb filter used in a DC offset detection circuit according to an embodiment of the present invention.

4A and 4B are waveform diagrams showing the DC offset detection result, the filter output signal, the combination of the positive DC offset threshold and the negative DC offset threshold.

FIG. 5 is a flowchart illustrating a DC offset protection method according to an embodiment of the present invention.

In the following text, numerous specific details are described in order to provide the reader with a thorough understanding of the embodiments of the present invention. However, one skilled in the art will understand how to practice the invention in the absence of one or more of the specific details, or with other methods or elements or materials, and the like. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring the core concepts of the invention.

Reference in the specification to "an embodiment" means that a particular feature, structure, or characteristic described in the embodiment may be included in at least one embodiment of the present invention. Thus, the appearances of "in an embodiment" in various places in this specification do not necessarily mean the same embodiment. Furthermore, the particular features, structures or characteristics described above may be combined in any suitable form in one or more embodiments.

Please refer to FIG. 1 , which shows a DC offset protection circuit for an audio system according to an embodiment of the present invention. As shown in the figure, the audio system 10 includes (but is not limited to): an audio signal processing circuit 15 , a power stage 20 , a plurality of speakers 25 , and a DC offset protection circuit 30 . The DC offset protection circuit 30 includes a DC offset detection circuit 100 and a control circuit 200 . The DC offset detection circuit 100 is configured to detect whether there is a DC component in the audio system 10 . The control circuit 200 is configured to detect the circuit based on the DC offset The detection result of 100 controls at least a part of the audio system 10 .

In one embodiment, the audio signal processing circuit 15 may include (not shown) a sampling rate conversion unit, an equalizer, a volume control unit, a dynamic range control unit, a limiter unit, a PWM pulse generator, etc. The digital audio signal performs a series of audio signal processing and accordingly drives the speaker 25 in an on-off manner (ie, through a pulse-width modulation (PWM) signal). Audio system 10 may contain N audio channels. The audio signal processing circuit 15 outputs 2N PWM signals corresponding to the N audio channels, thereby driving the N speakers. In general, a pair of stereo speakers 25 will be driven by four PWM signals PWML+, PWML-, PWMR+ and PWMR-. Among them, the four PWM signals include two pairs of complementary signals, one pair of complementary PWM signals PWML+ and PWML- are used to drive the speaker 25 on the left channel, and another pair of complementary PWM signals PWMR+ and PWMR- are used to drive the speaker 25 on the right channel. The speaker 25 is driven on the road. The power stage 20 further outputs a PWM signal. The power stage 20 may include a plurality of power gates controlled by PWM signals, and accordingly provide PWM to drive the speaker 25 . Please note that the number of channels, speakers and PWM signals in the audio system 10 referred to herein is not a substantial limitation of the scope of the invention.

The DC offset detection circuit 100 is coupled to the power stage 20 and detects whether there is a DC component in any PWM signal output by the power stage 20 . Based on the detection of the DC component, the DC offset detection circuit 100 will generate a detection signal DC_DET to notify the control circuit 200 . According to the detection signal DC_DET, the control circuit 200 can control the power stage 25 to stop providing the PMW signal to the speaker 25 (once the DC component is detected). According to various embodiments of the present invention, the power stage 25 will stop providing PWM signals to all the speakers 25 in the audio system 10 even if only one channel contains a DC component. In another embodiment, the power stage 25 will stop providing the PWM signal to the specific speaker 25 associated with the channel containing the DC component. In addition, according to various embodiments of the present invention, when the DC component is detected, the control circuit 200 may further The rest of the audio system 10 is turned off.

FIG. 2 illustrates the DC offset detection circuit 100 in the embodiment of the present invention. As shown in the figure, the DC offset detection circuit 100 includes a PWM polarity determination circuit 110 , a cascaded integrator-comb (CIC) filter 120 and a DC offset determination circuit 130 . The PWM polarity determination circuit 110 is used for detecting the polarity of the PWM signal output by the power stage 20, thereby generating a plurality of polarity indication values PI, wherein the polarity indication value PI is used to indicate a pair of complementary PWM signals PWMR+ and PWMR- in the PWM signal (or, PWML+ and PWML-) polarity. In one embodiment, the PWM polarity determination circuit 110 generates the polarity indication value PI according to the relationship between the sampling samples of the positive PMW signal (PWMR+) and the sampling samples of the negative PWM signal (PWMR-). For example, the positive PWM signal PWMR+ and the negative PWM signal PWMR- will be sampled at specific clock edges of a reference clock (not shown). Therefore, the PWM polarity determination circuit 110 generates the polarity indication value PI according to the real-time sampling samples of the positive PMW signal PWMR+ and the negative PWM signal PWMR-. Depending on the relationship between them (ie, the samples of the positive PMW signal PWMR+ are larger, equal to or smaller than the samples of the negative PWM signal PWMR-), the polarity indicator value PI will be different.

In one embodiment, the polarity indication value may be represented by a signed floating point number. In addition, the number of bits of the sampling samples of the complementary PWM signals PWMR+ and PWMR- is smaller than the number of bits of the polarity indication value. For example, the samples of the positive PWM signal PWMR+ or the negative PWM signal PWMR- may be 2-bit data, and the polarity indication value PI may be 3-bit data.

The polarity indication value PI will be output to the CIC filter 120 every time the complementary PWM signals PWMR+ and PWMR- are sampled. The CIC filter 120 is configured to average a plurality of polarity indication values PI over a period of time to generate the filter output signal F_OUT. FIG. 3 shows a schematic structural diagram of using a CIC filter in the DC offset detection circuit 100 according to an embodiment of the present invention. As shown, the CIC filter 120 pack It includes a first adding circuit 121 , a first register circuit 122 , a second register circuit 123 , a switch circuit 124 , a second adding circuit 125 and a third register circuit 126 .

The first summation circuit 121 is coupled to the PWM polarity determination circuit 110 and is configured to add the polarity indication value PI to the first register output RO1 from the first register circuit 122 to generate a first Add up the result SUM1. The first register circuit 122 is coupled to the first summation circuit 121 and is configured to store the first summation result SUM1 and accordingly provide the first register output RO1. During a certain time interval, the polarity indication value PI will be accumulated in the first register circuit 122 . The second register circuit 123 is coupled to the first register circuit 122 and is configured to store the first register output RO1 and correspondingly provide the second register output RO2. The switch circuit 124 is coupled between the first register circuit 122 and the second register circuit 123, and is configured to turn on the first register circuit 122 and the second register circuit 122 after a predetermined period of time expires. signal paths between the register circuits 123 . For example, after the first summation circuit 121 has added the polarity indication value PI to the first register output RO1 for ²²² times, the switch circuit 124 will turn on the signal path. The second summation circuit 125 is coupled to the switch circuit 124 and the second register circuit 123 and is configured to subtract the second register from the first register output RO1 when the switch circuit 124 conducts the signal path output RO2 to provide a second summation result SUM2. The third register circuit 126 is coupled to the second summation circuit 125 and the DC offset judgment circuit 130, and is configured to store the second summation result SUM2, and correspondingly provide a third register output, so as to As the filter output signal F_OUT. In short, the CIC filter 120 is configured to perform a moving average calculation of the polarity indicator value PI over a period of time, and the filter output signal F_OUT is the result of this calculation.

The DC offset determination circuit 130 is configured to compare the filter output signal F_OUT with at least one of a positive DC offset threshold PTH and a negative DC offset threshold NTH to generate a DC offset detection result DC_DET. Among them, the DC offset detection result DC_DET indicates that the power stage 20 Whether there is a positive DC component or a negative DC component in the output PWM signal. Referring to FIGS. 4A and 4B , the graphs show the detection result DC_DET, the filter output signal F_OUT, and the waveforms of the positive DC offset threshold PTH and the negative DC offset threshold NTH. As shown in the figure, when the filter output signal F_OUT exceeds the positive DC offset threshold PTH, or when the filter output signal F_OUT exceeds the negative DC offset threshold NTH, the DC offset detection result DC_DET will be pulled up. In one embodiment, the positive DC offset threshold PTH and the negative DC offset threshold NTH may be determined by the rated power of the speaker 25 .

5 is a flowchart of a DC offset protection method according to an embodiment of the present invention. The process includes the following steps: Step 410 : determine the polarity of the PWM signal, and generate a polarity indication value accordingly; Step 420 : use A CIC filter averages a plurality of polarity indication values to generate a filter output signal; Step 430: Compare the filter output signal with at least a DC offset threshold to generate a DC offset detection signal; and Step 440: At least a part of an audio system is controlled according to the DC offset detection signal.

Since the principles and specific operations of the DC offset protection circuit 30 have been explained in detail in the above context, for the sake of brevity, further explanations on the principles and specific operations of steps 410 to 440 are omitted here. It is worth noting that in addition to steps 410 to 440, the DC offset protection method of the present invention may have more additional steps to realize DC offset detection and protection.

In summary, the present invention provides a DC offset protection circuit and method. of the present invention The DC offset detection mechanism can be used to detect the DC component in the PWM signal used in the audio system with the class D amplifier as the core structure. In addition, the average calculation is performed on the sampling samples of the PWM signal through the CIC filter, thereby detecting the DC component in the PWM signal, so as to prevent the potential DC current from damaging the components in the speaker or audio system.

Embodiments of the present invention may be implemented using an apparatus, method or computer program product. Therefore, the embodiments of the present invention may take the following forms: a complete hardware architecture, a complete software architecture (including firmware, resident software, microcode, etc.), or an architecture combining both software and hardware. These architectures can be described in this Instructions are described in terms of "module" or "system". Further, the embodiments of the present invention can use software or firmware stored in a memory to implement the embodiments of the present invention through an appropriate instruction execution system, and can also apply any of the following technologies or their related It is accomplished by combining: an individual arithmetic logic with logic gates that can perform logic functions according to data signals, an application specific integrated circuit (ASIC) with a suitable combinational logic gate, a programmable gate array (programmable gate array) array, PGA) or a field programmable gate array (field programmable gate array, FPGA), etc.

The processes and blocks in the flowcharts within the specification illustrate the architecture, functionality, and operations that can be implemented by systems, methods, and computer software products based on various embodiments of the present invention. In this regard, each block in the flowchart or functional block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). In addition, each block of the functional block diagrams and/or flowchart illustrations, and combinations of blocks, can be substantially implemented by special purpose hardware systems that perform the specified functions or actions, or combinations of special purpose hardware and computer program instructions. . These computer program instructions may also be stored in a computer-readable medium that enables a computer or other programmable data The processing device operates in a manner such that the instructions stored in the computer-readable medium perform the functions/acts specified by the blocks in the flowcharts and/or functional block diagrams.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

100: DC offset detection circuit

110: PWM polarity judgment circuit

120: Cascade Integral Comb Filter Filter

130: DC offset judgment circuit

Claims (8)

A DC offset protection circuit for an audio system, comprising: a DC offset detection circuit for detecting DC components in a plurality of pulse-width modulation (PWM) signals, comprising: a a PWM polarity judging circuit for judging the polarity of the complementary PWM signal pair, and generating a polarity indication value accordingly, wherein the number of bits of the sampling sample of the complementary PWM signal pair is lower than the number of bits in the polarity indication value, and The polarity indication value is a floating-point number with a sign; a cascaded integrator-comb (CIC) filter is coupled to the PWM polarity determination circuit for averaging a plurality of polarity indication values to obtain a generating a filter output signal; and a DC offset determination circuit, coupled to the CIC filter, for comparing the filter output signal with at least a DC offset threshold value, and generating a DC offset detection accordingly the result; and a control circuit, coupled to the DC offset determination circuit, for controlling at least a part of the audio system according to the DC offset detection result. The DC offset protection circuit as claimed in claim 1, wherein the PWM polarity determination circuit generates according to the relationship between a sampling sample of a positive PWM signal and a sampling sample of a negative PWM signal in the complementary PWM signal pair The polarity indicates the value. The DC offset protection circuit of claim 1, wherein the CIC filter comprises: a first summing circuit, coupled to the PWM polarity determination circuit, for combining the polarity indication value with a first register The outputs are added to generate a first summation result; A first register circuit, coupled to the first summation circuit, for storing the first summation result and providing the first register output accordingly; a second register circuit, coupled to to the first register circuit for storing the output of the first register and providing a second register output accordingly; a switch circuit coupled to the first register circuit and the second register between the register circuits for turning on a signal path between the first register circuit and the second register circuit after a predetermined time expires; a second summing circuit coupled to the a switch circuit and the second register circuit for subtracting the second register output from the first register output to provide a second summation result when the switch circuit turns on the signal path and a third register circuit, coupled to the second summation circuit and the DC offset judgment circuit, for storing the second summation result, thereby providing a third register output as the filter output signal. The DC offset protection circuit of claim 1, wherein the DC offset determination circuit is configured to perform the filter output signal with at least one of a positive DC offset threshold value and a negative DC offset threshold value and comparing to generate the DC offset detection result, wherein the DC offset detection result indicates whether there is a positive DC component or a negative DC component in the PWM signal. A DC offset protection method for an audio system, comprising judging the polarity of a complementary pulse-width modulation (PWM) signal pair, and generating a polarity indication value accordingly, wherein the complementary PWM signal pair is sampled The number of bits of the sample is lower than the number of bits in the polarity indication value, and the polarity indication value is a signed floating point number; A cascaded integrator-comb (CIC) filter is used to average a plurality of polarity indications to generate a filter output signal; the filter output signal is compared with at least a DC offset threshold to generate a constant a flow offset detection result; and controlling at least a part of the audio system according to the DC offset detection result. The DC offset protection method of claim 5, wherein the step of generating the polarity indication value comprises: according to a difference between a sampling sample of a positive PWM signal and a sampling sample of a negative PWM signal in the pair of complementary PWM signals relationship to generate the polarity indication value. The DC offset protection method of claim 5, wherein the step of using the CIC filter to average the plurality of polarity indication values to generate the filter output signal comprises: using a first summing circuit to add the polarity indication value to the A first register output is added to generate a first summation result; a first register circuit is used to store the first summation result, and the first register output is provided accordingly; a second register circuit is used to store the first summation result. summing circuit that subtracts a second register output from the first register output after a predetermined period of time expires to provide a second summing result; and utilizing a second register circuit, a storing the first register output after a predetermined time period expires, and providing the second register output accordingly; and utilizing a third register circuit to store the second summation result and providing a third register circuit accordingly The register output is used as the filter output signal. The DC offset protection method of claim 5, wherein the step of comparing the filter output signal with the at least DC offset threshold to generate the DC offset detection result comprises: outputting the filter The signal is compared with at least one of a positive DC offset threshold and a negative DC offset threshold to generate the DC offset detection result, wherein the DC offset detection result indicates whether there is a presence in the PWM signal A positive DC component or a negative DC component.

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