TWI750049B - Pixel driving circuit - Google Patents

Abstract

A pixel driving circuit includes a light emitting unit, seven or eight switches and one capacitor. One of the switches and the capacitor are connected in series between a control terminal and a terminal of the driving switch to compensate a threshold voltage and IR drop by the coupling of the capacitor. Accordingly, the light emitting unit can provide consistent brightness.

Description

Pixel drive circuit

This disclosure relates to a pixel driving circuit for light-emitting diodes.

At present, light-emitting diodes have been widely used in various types of displays. The brightness of the light-emitting diode when it emits light is related to the size of its driving current, and the size of its driving current is controlled by the driving transistor. However, because of the variation of the manufacturing process, the threshold voltage (Vth) of the driving transistor of each pixel in the display will be different, which will cause the light-emitting diodes in different pixels to have different values. The driving current causes the brightness of each light-emitting diode to be different, which in turn causes the problem of uneven brightness when the display displays pictures. In addition, the driving current is provided by the operating voltage, and the operating voltage is prone to IR drop due to the line resistance in the transmission path, which makes the operating voltage of each pixel different, causing errors in the driving current.

Therefore, how to compensate for the critical voltage of the driving transistor of the display pixel and also compensate for the operating voltage is the goal of the research by those skilled in the art.

The embodiment of the disclosure provides a pixel driving circuit, which includes the following components. The light-emitting unit has a first end and a second end, and the first end of the light-emitting unit is connected to the first operating voltage. The first switch has a first terminal, a second terminal and a control terminal. The first terminal of the first switch is connected to the second terminal of the light-emitting unit, and the control terminal of the first switch is connected to the first control signal. The second switch has a first terminal, a second terminal and a control terminal. The first terminal of the second switch is connected to the second terminal of the first switch, and the second terminal of the second switch is connected to the second operating voltage. The third switch has a first terminal, a second terminal and a control terminal. The first terminal of the third switch is connected to the control terminal of the second switch, the second terminal of the third switch is connected to the first operating voltage, and the second terminal of the third switch is connected to the first operating voltage. The control terminal is connected to the second control signal. The fourth switch has a first end, a second end and a control end. The first end of the fourth switch is connected to the second end of the first switch and the first end of the second switch, and the second end of the fourth switch is connected to The first operating voltage, the control terminal of the fourth switch is connected to the second control signal. The capacitor has a first end and a second end, and the first end of the capacitor is connected to the second end of the first switch, the first end of the second switch, and the first end of the fourth switch. The fifth switch has a first terminal, a second terminal, and a control terminal. The first terminal of the fifth switch is connected to the second terminal of the capacitor, and the second terminal of the fifth switch is connected to the control terminal of the second switch and the third switch The first end of the fifth switch is connected to the first control signal. The sixth switch has a first terminal, a second terminal and a control terminal. The first terminal of the sixth switch is connected to the second terminal of the capacitor and the first terminal of the fifth switch, and the second terminal of the sixth switch is connected to the first terminal. For the diode signal, the control terminal of the sixth switch is connected to the third control signal. The seventh switch has a first terminal, a second terminal, and a control terminal. The first terminal of the seventh switch is connected to the control terminal of the second switch, the first terminal of the third switch, and the second terminal of the fifth switch. The second end of the switch is connected to the second diode signal, and the control end of the seventh switch is connected to the third control signal. The eighth switch has a first end, a second end, and a control end. The first end of the eighth switch is connected to the second end of the capacitor, the first end of the fifth switch, and the first end of the sixth switch. The eighth switch The second terminal of is connected to the second operating voltage, and the control terminal of the eighth switch is connected to the second control signal.

In some embodiments, the pixel driving circuit operates sequentially in the first period, the second period, and the third period. In the first period, the first switch, the second switch, the fifth switch, the sixth switch, and the seventh switch are in an off state, and the third switch, the fourth switch, and the eighth switch are in an on state. In the second period, the first switch, the third switch, the fourth switch, the fifth switch and the eighth switch are in the off state, and the second switch, the sixth switch and the seventh switch are in the on state. In the third period, the third switch, the fourth switch, the sixth switch, the seventh switch, and the eighth switch are in the off state, and the first switch, the second switch, and the fifth switch are in the on state.

The embodiment of the disclosure provides a pixel driving circuit, which includes the following components. The light-emitting unit has a first end and a second end, and the first end of the light-emitting unit is connected to the first operating voltage. The first switch has a first end, a second end and a control end. The first end of the first switch is connected to the second end of the light-emitting unit, and the control end of the first switch is connected to the first control signal. The second switch has a first terminal, a second terminal and a control terminal. The first terminal of the second switch is connected to the second terminal of the first switch, and the second terminal of the second switch is connected to the second operating voltage. The third switch has a first terminal, a second terminal and a control terminal. The first terminal of the third switch is connected to the control terminal of the second switch, and the second terminal of the third switch is connected to the second terminal and the second terminal of the first switch. The first end of the switch and the control end of the third switch are connected to the second control signal. The fourth switch has a first terminal, a second terminal, and a control terminal. The first terminal of the fourth switch is connected to the second terminal of the first switch, the second terminal of the second switch, and the second terminal of the third switch. The second terminal of the switch is connected to the first operating voltage, and the control terminal of the fourth switch is connected to the second control signal. The capacitor has a first end and a second end, and the first end of the capacitor is connected to the second end of the first switch, the first end of the second switch, the second end of the third switch, and the first end of the fourth switch. The fifth switch has a first terminal, a second terminal, and a control terminal. The first terminal of the fifth switch is connected to the second terminal of the capacitor, and the second terminal of the fifth switch is connected to the control terminal of the second switch and the control terminal of the third switch. At the first end, the control end of the fifth switch is connected to the first control signal. The sixth switch has a first terminal, a second terminal, and a control terminal. The first terminal of the sixth switch is connected to the second terminal of the capacitor and the first terminal of the fifth switch, and the second terminal of the sixth switch is connected to the first terminal. Polar body signal, the control terminal of the sixth switch is connected to the third control signal. The seventh switch has a first terminal, a second terminal, and a control terminal. The first terminal of the seventh switch is connected to the control terminal of the second switch, the first terminal of the third switch, and the second terminal of the fifth switch. The seventh switch The second end of is connected to the second diode signal, and the control end of the seventh switch is connected to the fourth control signal.

In some embodiments, the pixel driving circuit sequentially operates in the first period, the second period, the third period, and the fourth period. In the first period, the first switch, the second switch, the fifth switch, the sixth switch, and the seventh switch are in the off state, and the third switch and the fourth switch are in the on state. In the second period, the first switch, the second switch, the fifth switch, and the seventh switch are in the off state, and the third switch, the fourth switch, and the sixth switch are in the on state. In the third period, the first switch, the third switch, the fourth switch and the fifth switch are in the off state, and the second switch, the sixth switch and the seventh switch are in the on state. In the fourth period, the third switch, the fourth switch, the sixth switch, and the seventh switch are in the off state, and the second switch and the fifth switch are in the on state.

In some embodiments, the first to seventh switches are N-type transistors, and the first operating voltage is lower than the second operating voltage. In the first period, the first control signal, the third control signal, and the fourth control signal are at a low level, and the second control signal is at a high level. In the second period, the first control signal and the fourth control signal are at a low level, and the second control signal and the third control signal are at a high level. In the third period, the first control signal and the second control signal are at a low level, and the third control signal and the fourth control signal are at a high level. In the fourth period, the first control signal is at the high level, and the second control signal, the third control signal, and the fourth control signal are at the low level.

In some embodiments, the first switch to the seventh switch are P-type transistors, and the first operating voltage is greater than the second operating voltage. In the first period, the first control signal, the third control signal, and the fourth control signal are at a high level, and the second control signal is at a low level. In the second period, the first control signal and the fourth control signal are at a high level, and the second control signal and the third control signal are at a low level. In the third period, the first control signal and the second control signal are at a high level, and the third control signal and the fourth control signal are at a low level. In the fourth period, the first control signal is at the low level, and the second control signal, the third control signal, and the fourth control signal are at the high level.

In some embodiments, the pixel driving circuit further includes an eighth switch, which has a first terminal, a second terminal, and a control terminal. The first end of the eighth switch is connected to the second end of the capacitor, the first end of the fifth switch and the first end of the sixth switch, the second end of the eighth switch is connected to the first diode signal, and the eighth switch The control terminal of is connected to the second control signal.

In some embodiments, the pixel driving circuit operates sequentially in the first period, the second period, and the third period, and the third control signal is the same as the fourth control signal. In the first period, the first switch, the second switch, the fifth switch, the sixth switch, and the seventh switch are in the off state, and the third switch, the fourth switch, and the eighth switch are in the on state. In the second period, the first switch, the third switch, the fourth switch, the fifth switch and the eighth switch are in the off state, and the second switch, the sixth switch and the seventh switch are in the on state. In the third period, the third switch, the fourth switch, the sixth switch, the seventh switch, and the eighth switch are in the off state, and the first switch, the second switch, and the fifth switch are in the on state.

In some embodiments, the first switch to the eighth switch are N-type transistors, and the first operating voltage is lower than the second operating voltage. In the first period, the first control signal and the third control signal are at a low level, and the second control signal is at a high level. In the second period, the first control signal and the second control signal are at a low level, and the third control signal is at a high level. In the third period, the first control signal is at a high level, and the second control signal and the third control signal are at a low level.

In some embodiments, the first switch to the eighth switch are P-type transistors, and the first operating voltage is higher than the second operating voltage. In the first period, the first control signal and the third control signal are at a high level, and the second control signal is at a low level. In the second period, the first control signal and the second control signal are at a high level, and the third control signal is at a low level. In the third period, the first control signal is at a low level, and the second control signal and the third control signal are at a high level.

In the above pixel driving circuit, due to the compensation of the threshold voltage and the operating voltage, the light-emitting unit will provide consistent brightness.

Regarding the “first”, “second”, etc. used in this text, it does not particularly mean the order or sequence, but only distinguishes elements or operations described in the same technical terms. The connection mentioned in this article can be a direct connection.

The pixel driving circuit proposed in the present disclosure can compensate for the threshold voltage and the operating voltage, so that the light-emitting unit can provide consistent brightness. A number of embodiments will be described below.

[First Embodiment]

FIG. 1 is a circuit structure diagram of a pixel driving circuit according to the first embodiment. The pixel driving circuit 100 can be disposed in the display panel as a pixel, and the disclosure is not limited thereto. The pixel driving circuit 100 includes a light emitting unit 110, switches T1 to T17, and a capacitor C1. The light-emitting unit 110 is, for example, a light-emitting diode, and the size of the light-emitting diode may be on the order of micrometers or other suitable sizes, and the present disclosure is not limited thereto. In the embodiment of FIG. 1, the switches T1 to T7 are, for example, thin film transistors, and are N-type transistors.

The light emitting unit 110 has a first terminal 110-1 and a second terminal 110-2, and the first terminal 110-1 of the light emitting unit 110 is connected to the operating voltage VSS. The switch T1 has a first terminal T1-1, a second terminal T1-2, and a control terminal T1-3. The first terminal T1-1 of the switch T1 is connected to the second terminal 110-2 of the light-emitting unit 110, and the control of the switch T1 The terminal T1-3 is connected to the control signal EM. The switch T2 has a first terminal T2-1, a second terminal T2-2, and a control terminal T2-3. The first terminal T2-1 of the switch T2 is connected to the second terminal T1-2 of the switch T1, and the second terminal of the switch T2 T2-2 is connected to the operating voltage VDD, where the operating voltage VDD is greater than the operating voltage VSS. The switch T3 has a first terminal T3-1, a second terminal T3-2, and a control terminal T3-3. The first terminal T3-1 of the switch T3 is connected to the control terminal T2-3 of the switch T2, and the second terminal T3 of the switch T3 -2 is connected to the second terminal T1-2 of the switch T1 and the first terminal T2-1 of the switch T2, and the control terminal T3-3 of the switch T3 is connected to the control signal Sn1. The switch T4 has a first terminal T4-1, a second terminal T4-2, and a control terminal T4-3. The first terminal T4-1 of the switch T4 is connected to the second terminal T1-2 of the switch T1 and the second terminal of the switch T2. T2-2 and the second terminal T3-2 of the switch T3, the second terminal T4-2 of the switch T4 is connected to the operating voltage VSS, and the control terminal T4-3 of the switch T4 is connected to the control signal Sn1.

The capacitor C1 has a first terminal C1-1 and a second terminal C1-2. The first terminal C1-1 of the capacitor C1 is connected to the second terminal T1-2 of the switch T1, the first terminal T2-1 of the switch T2, and the switch T3. The second terminal T3-2 of the switch and the first terminal T4-1 of the switch T4. The switch T5 has a first terminal T5-1, a second terminal T5-2, and a control terminal T5-3. The first terminal T5-1 of the switch T5 is connected to the second terminal C1-2 of the capacitor C1, and the second terminal of the switch T5 T5-2 is connected to the control terminal T2-3 of the switch T2 and the first terminal T3-1 of the switch T3, and the control terminal T5-3 of the switch T5 is connected to the control signal EM. The switch T6 has a first terminal T6-1, a second terminal T6-2, and a control terminal T6-3. The first terminal T6-1 of the switch T6 is connected to the second terminal C1-2 of the capacitor C1 and the first terminal of the switch T5 T5-1, the second terminal T6-2 of the switch T6 is connected to the diode signal SL, and the control terminal T6-3 of the switch T6 is connected to the control signal Sn2. The switch T7 has a first terminal T7-1, a second terminal T7-2, and a control terminal T7-3. The first terminal T7-1 of the switch T7 is connected to the control terminal T2-3 of the switch T2 and the first terminal T3 of the switch T3. -1 and the second terminal T5-2 of the switch T5, the second terminal T7-2 of the switch T7 is connected to the diode signal Ref, and the control terminal T7-3 of the switch T7 is connected to the control signal Sn3. For the sake of illustration, nodes A, B, and C are also shown in FIG. 1.

FIG. 2 is a timing diagram of various signals and node voltages in the pixel driving circuit according to the first embodiment. Please refer to FIG. 2, the pixel driving circuit sequentially operates in the first period 210, the second period 220, the third period 230, and the fourth period 240.

FIG. 3 is a schematic diagram showing the switching of the pixel driving circuit in the first period according to the first embodiment. 2 and 3, in the first period 210, the control signal Sn1 is at a high level, the control signal Sn2, the control signal Sn3, and the control signal EM are at a low level. Therefore, in the first period 210, the switch T1, the switch T2, the switch T5, the switch T6, and the switch T7 are in the off state, and the switch T3 and the switch T4 are in the on state. At this time, the potentials of the node A and the node C are the same as the operating voltage VSS.

4 is a schematic diagram showing the switching of the pixel driving circuit in the second period according to the first embodiment. 2 and 4, in the second period 220, the control signal Sn1 and the control signal Sn2 are at a high level, and the control signal Sn3 and the control signal EM are at a low level. Therefore, in the second period 220, the switch T1, the switch T2, the switch T5, and the switch T7 are in the off state, and the switch T3, the switch T4, and the switch T6 are in the on state. At this time, the potential of the node A is the same as the operating voltage VSS. The diode signal SL provides the data voltage V _data , and the potential of the node B is the same as the data voltage V _data . The potential of the node C is the same as the operating voltage VSS.

FIG. 5 is a schematic diagram showing the switching of the pixel driving circuit in the third period according to the first embodiment. 2 and 5, in the third period 230, the control signal Sn1 and the control signal EM are at a low level, and the control signal Sn2 and the control signal Sn3 are at a high level. Therefore, in the third period 230, the switch T1, the switch T3, the switch T4, and the switch T5 are in the off state, and the switch T2, the switch T6, and the switch T7 are in the on state. At this time, the diode signal Ref provides the reference voltage V _ref , and the potential of the node A is the same as the reference voltage V _ref . The potential of the node B is the same as the data voltage Vdata. At the beginning of the third period 230, the switch T2 is in the on state, and then the potential of the node C will continue to rise until reaching the potential V _ref -V _{th_T2} , the switch T2 is switched to the off state, where Vth_T2 is the threshold voltage of the switch T2.

6 is a schematic diagram showing the switching of the pixel driving circuit in the fourth period according to the first embodiment. 2 and 6, in the fourth period 240, the control signal Sn1, the control signal Sn2, and the control signal Sn3 are at a low level, and the control signal EM is at a high level. Therefore, in the fourth period 240, the switch T3, the switch T4, the switch T6, and the switch T7 are in the off state, and the switch T2 and the switch T5 are in the on state. At this time, the potential of the node C is the same as VSS+V _LED , where V _LED is the voltage across the two ends when the light-emitting unit 110 is turned on. Since the potential of node C _{changes from Vref-V th_T2 in the} third period 230 to VSS+V _{LED in the} fourth period 240, and the amount of change is VSS+V _LED -V _ref +V _{th_T2} , the potential of node B changes from V _data Change to V _data +VSS+V _LED -V _ref +V _{th_T2} . The potential of the node A is the same as the potential of the node B. This potential will turn on the switch T2 to generate a current I _d , and the magnitude of the current I _d is shown in the following equation 1. [Math 1]

Wherein K is a constant, V _A is the potential of the node A, V _C is the C node potential. It is worth noting that in the mathematical formula 1, the threshold voltage V _{th_T2} and the reference voltage VSS cancel each other out due to compensation, so the current I _d is no longer affected by the threshold voltage V _{th_T2} and the reference voltage VSS.

[Second Embodiment]

FIG. 7 is a circuit structure diagram of a pixel driving circuit according to a second embodiment. Please refer to Figure 7. The difference between Figure 7 and Figure 1 is the addition of a switch T8. The switch T8 has a first terminal T8-1, a second terminal T8-2, and a third terminal T8-3. The first terminal T8- of the switch T8 1 is connected to the second terminal C1-2 of the capacitor C1, the first terminal T5-1 of the switch T5, and the first terminal T6-1 of the switch T6. The second terminal T8-2 of the switch T8 is connected to the diode signal SL, The control terminal T8-3 of the switch T8 is connected to the control signal Sn1.

FIG. 8 is a timing diagram of various signals and node voltages in the pixel driving circuit according to the second embodiment. Referring to FIG. 8, in the second embodiment, the control signal Sn3 is the same as the control signal Sn2. For the sake of simplicity, the control signal Sn3 is not shown below. The pixel driving circuit sequentially operates in the first period 810, the second period 820, and the third period 830.

FIG. 9 is a schematic diagram illustrating the switching of the pixel driving circuit in the first period according to the second embodiment. 8 and 9, in the first period 810, the control signal Sn1 is at a high level, and the control signal Sn2 and the control signal EM are at a low level. Therefore, in the first period 810, the switch T1, the switch T2, the switch T5, the switch T6, and the switch T7 are in the off state, and the switch T3, the switch T4, and the switch T8 are in the on state. At this time, the potential of the node A is the same as the operating voltage VSS. The diode signal SL provides the data voltage V _data , and the potential of the node B is the same as the data voltage V _data . The potential of the node C is the same as the operating voltage VSS.

FIG. 10 is a schematic diagram showing the switching of the pixel driving circuit in the second period according to the second embodiment. 8 and 10, in the second period 820, the control signal Sn1 and the control signal EM are at a low level, and the control signal Sn2 is at a high level. Therefore, in the second period 820, the switch T1, the switch T3, the switch T4, the switch T5, and the switch T8 are in the off state, and the switch T2, the switch T6, and the switch T7 are in the on state. The diode signal Ref provides a reference voltage V _ref , and the potential of the node A is the same as the reference voltage V _ref . The potential of the node B is the same as the data voltage V _data . At the beginning of the second period 820, the switch T2 is in the on state, and then the potential of the node C will continue to rise until reaching the potential V _ref -V _{th_T2} , the switch T2 is switched to the off state, where Vth_T2 is the threshold voltage of the switch T2.

FIG. 11 is a schematic diagram showing the switching of the pixel driving circuit in the third period according to the second embodiment. 8 and 11, in the third period 830, the control signal Sn1 and the control signal Sn2 are at a low level, and the control signal EM is at a high level. Therefore, in the third period 830, the switch T3, the switch T4, the switch T6, the switch T7, and the switch T8 are in the off state, and the switch T1, the switch T2, and the switch T5 are in the on state. The potential of node C is the same as VSS+V _LED . Since the potential of node C _{changes from V ref} -V _{th_T2 in the} second period 820 to VSS+V _LED , and the amount of change is VSS+V _LED -V _ref +V _{th_T2} , the potential of node B _{changes from V data} to V _data + VSS+V _LED -V _ref +V _{th_T2} . The potential of the node A is the same as the potential of the node B, and this potential will turn on the switch T2 to generate a current I _d , and the magnitude of the current I _d is as shown in Mathematical Formula 1 above.

Therefore, in the second embodiment, the threshold voltage V _{th_T2} and the reference voltage VSS cancel each other out due to compensation, and the current I _d is no longer affected by the threshold voltage V _{th_T2} and the reference voltage VSS.

[Third Embodiment]

Compared with the first embodiment, the third embodiment changes the N-type transistor to the P-type transistor. FIG. 12 is a circuit structure diagram of a pixel driving circuit according to the third embodiment, and FIG. 13 is a timing diagram of various signals and node voltages according to the third embodiment. In the first period 210, the control signal Sn1 is at the low level, and the control signal Sn2, the control signal Sn3, and the control signal EM are at the high level. In the second period 220, the control signal Sn1 and the control signal Sn2 are at a low level, and the control signal Sn3 and the control signal EM are at a high level. In the third period 230, the control signal Sn1 and the control signal EM are at a high level, and the control signal Sn2 and the control signal Sn3 are at a low level. In the fourth period 240, the control signal Sn1, the control signal Sn2, and the control signal Sn3 are at a high level, and the control signal EM is at a low level. Those with ordinary knowledge in the art should understand the circuit and operation of the third embodiment based on the description of the first embodiment above, and the details will not be repeated here.

[Fourth Embodiment]

Compared with the second embodiment, the fourth embodiment changes the N-type transistor to the P-type transistor. 14 is a circuit structure diagram of a pixel driving circuit according to the fourth embodiment, and FIG. 15 is a timing diagram of various signals and node voltages according to the fourth embodiment. In the first period 810, the control signal Sn1 is at a low level, and the control signal Sn2 and the control signal EM are at a high level. In the second period 820, the control signal Sn1 and the control signal EM are at a high level, and the control signal Sn2 is at a low level. In the third period 830, the control signal Sn1 and the control signal Sn2 are at a high level, and the control signal EM is at a low level. Those with ordinary knowledge in the art should understand the circuit and operation of the fourth embodiment based on the description of the second embodiment above, and will not be repeated here.

[Fifth Embodiment]

FIG. 16 is a circuit structure diagram of a pixel driving circuit according to a fifth embodiment. Compared with the first embodiment, the fifth embodiment exchanges the diode signal SL and the diode signal Ref. Although this will change the potential of node A and node B, the _{formula for calculating the current I d} only changes the data. The order of the voltage V _data and the reference voltage V _ref is I _d =K(V _ref -V _data ) ² , but the magnitude of the _{current I d has not changed.} It should be noted that the diode signal SL and the diode signal Ref in the second, third, and fourth embodiments can also be exchanged with each other.

[Sixth Embodiment]

FIG. 17 is a circuit structure diagram of a pixel driving circuit according to a sixth embodiment. Referring to FIG. 17, the light-emitting unit 110 has a first terminal 110-1 and a second terminal 110-2, and the first terminal 110-1 of the light-emitting unit 110 is connected to the operating voltage VSS. The switch T1 has a first terminal T1-1, a second terminal T1-2, and a control terminal T1-3. The first terminal T1-1 of the switch T1 is connected to the second terminal 110-2 of the light-emitting unit 110, and the control of the switch T1 The terminal T1-3 is connected to the control signal EM. The switch T2 has a first terminal T2-1, a second terminal T2-2, and a control terminal T2-3. The first terminal T2-1 of the switch T2 is connected to the second terminal T1-2 of the switch T1, and the second terminal of the switch T2 T2-2 is connected to the operating voltage VDD, where the operating voltage VDD is greater than the operating voltage VSS. The switch T3 has a first terminal T3-1, a second terminal T3-2, and a control terminal T3-3. The first terminal T3-1 of the switch T3 is connected to the control terminal T2-3 of the switch T2, and the second terminal T3 of the switch T3 -2 is connected to the operating voltage VSS, and the control terminal T3-3 of the switch T3 is connected to the control signal Sn1. The switch T4 has a first terminal T4-1, a second terminal T4-2, and a control terminal T4-3. The first terminal T4-1 of the switch T4 is connected to the second terminal T1-2 of the switch T1 and the first terminal of the switch T2. T2-1, the second terminal T4-2 of the switch T4 is connected to the operating voltage VSS, and the control terminal T4-3 of the switch T4 is connected to the control signal Sn1.

The capacitor C1 has a first terminal C1-1 and a second terminal C1-2. The first terminal C1-1 of the capacitor C1 is connected to the second terminal T1-2 of the switch T1, the first terminal T2-1 of the switch T2 and the switch T4 The first end T4-1. Switch T5 It has a first terminal T5-1, a second terminal T5-2 and a control terminal T5-3, the first terminal T5-1 of the switch T5 is connected to the second terminal C1-2 of the capacitor C1, and the second terminal T5- of the switch T5 2 is connected to the control terminal T2-3 of the switch T2 and the first terminal T3-1 of the switch T3, and the control terminal T5-3 of the switch T5 is connected to the control signal EM. The switch T6 has a first terminal T6-1, a second terminal T6-2, and a control terminal T6-3. The first terminal T6-1 of the switch T6 is connected to the second terminal C1-2 of the capacitor C1 and the first terminal of the switch T5 T5-1, the second terminal T6-2 of the switch T6 is connected to the diode signal SL, and the control terminal T6-3 of the switch T6 is connected to the control signal Sn2. The switch T7 has a first terminal T7-1, a second terminal T7-2, and a control terminal T7-3. The first terminal T7-1 of the switch T7 is connected to the control terminal T2-3 of the switch T2 and the first terminal T3 of the switch T3. -1 and the second terminal T5-2 of the switch T5, the second terminal T7-2 of the switch T7 is connected to the diode signal Ref, and the control terminal T7-3 of the switch T7 is connected to the control signal Sn3. The switch T8 has a first terminal T8-1, a second terminal T8-2, and a third terminal T8-3. The first terminal T8-1 of the switch T8 is connected to the second terminal C1-2 of the capacitor C1 and the first terminal C1-2 of the switch T5. The terminal T5-1 and the first terminal T6-1 of the switch T6, the second terminal T8-2 of the switch T8 is connected to the operating voltage VDD, and the control terminal T8-3 of the switch T8 is connected to the control signal Sn1. For the sake of illustration, the nodes A, B, and C are also shown in FIG. 17.

FIG. 18 is a timing diagram of each signal in the pixel driving circuit according to the sixth embodiment. Referring to FIG. 18, in this embodiment, the diode signal SL provides the data voltage V _data , and the diode signal Ref provides the reference voltage V _ref . The pixel driving circuit sequentially operates in the first period 1610, the second period 1620, the third period 1630, and the fourth period 1640, and these four periods do not overlap with each other.

19 is a schematic diagram showing the switching of the pixel driving circuit in the first period according to the sixth embodiment. Referring to FIGS. 18 and 19, in the first period 1610, the control signal Sn1 is at a high level, and the control signal Sn2 and the control signal EM are at a low level. Therefore, in the first period 1610, the switch T1, the switch T2, the switch T5, the switch T6, and the switch T7 are in the off state, and the switch T3, the switch T4, and the switch T8 are in the on state. At this time, the potential of the node A is the same as the operating voltage VSS. The potential of the node B is the same as the operating voltage VDD. The potential of the node C is the same as the operating voltage VSS.

20 is a schematic diagram showing the switching of the pixel driving circuit in the second period according to the sixth embodiment. Referring to FIGS. 18 and 20, in the second period 1620, the control signal Sn1 and the control signal EM are at a low level, and the control signal Sn2 is at a high level. Therefore, in the second period 1620, the switch T1, the switch T3, the switch T4, the switch T5, and the switch T8 are in the off state, and the switch T2, the switch T6, and the switch T7 are in the on state. The potential of the node A is the same as the reference voltage V _ref . The potential of the node B is the same as the data voltage V _data . At the beginning of the second period 1620, the switch T2 is in the on state, and then the potential of the node C will continue to rise, until the potential V _ref -V _{th_T2} is reached, the switch T2 is switched to the off state, where V _{th_T2} is the threshold voltage of the switch T2.

21 is a schematic diagram showing the switching of the pixel driving circuit in the third period according to the sixth embodiment. Referring to FIGS. 18 and 21, in the third period 1630, the control signal Sn1 and the control signal Sn2 are at a low level, and the control signal EM is at a high level. Therefore, in the third period 1630, the switch T3, the switch T4, the switch T6, the switch T7, and the switch T8 are in the off state, and the switch T1, the switch T2, and the switch T5 are in the on state. The potential of node C is the same as VSS+V _LED . Since the potential of node C _{changes from V ref} -V _{th_T2 in the} second period 1620 to VSS+V _LED , and the amount of change is VSS+V _LED -V _ref +V _{th_T2} , the potential of node B _{changes from V data} to V _data + VSS+V _LED -V _ref +V _{th_T2} . The potential of the node A is the same as the potential of the node B. This potential will turn on the switch T2 to generate a current I _d , and the magnitude of the current I _d is as shown in the above-mentioned mathematical formula 1. Therefore, in the sixth embodiment, the threshold voltage V _{th_T2} and the reference voltage VSS cancel each other due to compensation, and the current I _d is no longer affected by the threshold voltage V _{th_T2} and the reference voltage VSS.

In the fourth period 1640, the control signal Sn1, the control signal Sn2, and the control signal EM are at a low level, so the switches T1 to T8 are in an off state to turn off the light-emitting unit 110.

[Seventh embodiment]

FIG. 22 is a circuit structure diagram of a pixel driving circuit according to a seventh embodiment. Please refer to FIG. 22. Compared with the sixth embodiment, the seventh embodiment changes the N-type transistor to the P-type transistor. Those skilled in the art should understand the circuit and operation of the seventh embodiment based on the description of the sixth embodiment, and the details are not repeated here.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be defined as the scope of the attached patent application. allow.

100: Pixel drive circuit

110: light-emitting unit

T1~T8: switch

C1: Capacitance

110-1, C1-1, T1-1, T2-1, T3-1, T4-1, T5-1, T6-1, T7-1, T8-1: first end

110-2, C1-2, T1-2, T2-2, T3-2, T4-2, T5-2, T6-2, T7-2, T8-2: second end

T1-3, T2-3, T3-3, T4-3, T5-3, T6-3, T7-3, T8-3: control terminal

VDD, VSS: operating voltage

Sn1, Sn2, Sn3, EM: control signal

SL, Ref: Diode signal

A, B, C: node

I _d : current

210, 810, 1610: the first period

220, 820, 1620: the second period

230,830,1630: the third period

240, 1640: the fourth period

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings. FIG. 1 is a circuit structure diagram of a pixel driving circuit according to the first embodiment. FIG. 2 is a timing diagram of various signals and node voltages in the pixel driving circuit according to the first embodiment. FIG. 3 is a schematic diagram showing the switching of the pixel driving circuit in the first period according to the first embodiment. 4 is a schematic diagram showing the switching of the pixel driving circuit in the second period according to the first embodiment. FIG. 5 is a schematic diagram showing the switching of the pixel driving circuit in the third period according to the first embodiment. 6 is a schematic diagram showing the switching of the pixel driving circuit in the fourth period according to the first embodiment. FIG. 7 is a circuit structure diagram of a pixel driving circuit according to a second embodiment. FIG. 8 is a timing diagram of various signals and node voltages in the pixel driving circuit according to the second embodiment. FIG. 9 is a schematic diagram illustrating the switching of the pixel driving circuit in the first period according to the second embodiment. FIG. 10 is a schematic diagram showing the switching of the pixel driving circuit in the second period according to the second embodiment. FIG. 11 is a schematic diagram showing the switching of the pixel driving circuit in the third period according to the second embodiment. FIG. 12 is a circuit structure diagram of a pixel driving circuit according to a third embodiment. FIG. 13 is a timing diagram of various signals and node voltages according to the third embodiment. FIG. 14 is a circuit structure diagram of a pixel driving circuit according to the fourth embodiment. FIG. 15 is a timing diagram of various signals and node voltages according to the fourth embodiment. FIG. 16 is a circuit structure diagram of a pixel driving circuit according to a fifth embodiment. FIG. 17 is a circuit structure diagram of a pixel driving circuit according to a sixth embodiment. FIG. 18 is a timing diagram of each signal in the pixel driving circuit according to the sixth embodiment. 19 is a schematic diagram showing the switching of the pixel driving circuit in the first period according to the sixth embodiment. 20 is a schematic diagram showing the switching of the pixel driving circuit in the second period according to the sixth embodiment. 21 is a schematic diagram showing the switching of the pixel driving circuit in the third period according to the sixth embodiment. FIG. 22 is a circuit structure diagram of a pixel driving circuit according to a seventh embodiment.

100: Pixel drive circuit

110: light-emitting unit

T1~T7: switch

C1: Capacitance

110-1, C1-1, T1-1, T2-1, T3-1, T4-1, T5-1, T6-1, T7-1: first end

110-2, C1-2, T1-2, T2-2, T3-2, T4-2, T5-2, T6-2, T7-2: second end

T1-3, T2-3, T3-3, T4-3, T5-3, T6-3, T7-3: control terminal

VDD, VSS: operating voltage

Sn1, Sn2, Sn3, EM: control signal

SL, Ref: Diode signal

A, B, C: node

Claims (10)

A pixel drive circuit, including: A light emitting unit having a first end and a second end, wherein the first end of the light emitting unit is connected to a first operating voltage; A first switch has a first terminal, a second terminal and a control terminal, wherein the first terminal of the first switch is connected to the second terminal of the light-emitting unit, and the control terminal of the first switch is connected To a first control signal; A second switch has a first terminal, a second terminal and a control terminal, wherein the first terminal of the second switch is connected to the second terminal of the first switch, and the second terminal of the second switch Terminal is connected to a second operating voltage; A third switch has a first terminal, a second terminal and a control terminal, wherein the first terminal of the third switch is connected to the control terminal of the second switch, and the second terminal of the third switch Connected to the first operating voltage, and the control terminal of the third switch is connected to a second control signal; A fourth switch has a first terminal, a second terminal and a control terminal, wherein the first terminal of the fourth switch is connected to the second terminal of the first switch and the first terminal of the second switch Terminal, the second terminal of the fourth switch is connected to the first operating voltage, and the control terminal of the fourth switch is connected to the second control signal; A capacitor having a first terminal and a second terminal, wherein the first terminal of the capacitor is connected to the second terminal of the first switch, the first terminal of the second switch, and the fourth switch First end A fifth switch has a first terminal, a second terminal and a control terminal, wherein the first terminal of the fifth switch is connected to the second terminal of the capacitor, and the second terminal of the fifth switch is connected To the control terminal of the second switch and the first terminal of the third switch, the control terminal of the fifth switch is connected to the first control signal; A sixth switch having a first terminal, a second terminal and a control terminal, wherein the first terminal of the sixth switch is connected to the second terminal of the capacitor and the first terminal of the fifth switch, The second end of the sixth switch is connected to a first diode signal, and the control end of the sixth switch is connected to a third control signal; A seventh switch having a first terminal, a second terminal and a control terminal, wherein the first terminal of the seventh switch is connected to the control terminal of the second switch and the first terminal of the third switch And the second end of the fifth switch, the second end of the seventh switch is connected to a second diode signal, and the control end of the seventh switch is connected to the third control signal; and An eighth switch has a first terminal, a second terminal and a control terminal, wherein the first terminal of the eighth switch is connected to the second terminal of the capacitor, the first terminal of the fifth switch, and The first terminal of the sixth switch, the second terminal of the eighth switch are connected to the second operating voltage, and the control terminal of the eighth switch is connected to the second control signal. The pixel driving circuit according to claim 1, wherein the pixel driving circuit sequentially operates in a first period, a second period, and a third period, In the first period, the first switch, the second switch, the fifth switch, the sixth switch, and the seventh switch are in an off state, and the third switch, the fourth switch, and the eighth switch are in an off state. The switch is in an on state, In the second period, the first switch, the third switch, the fourth switch, the fifth switch, and the eighth switch are in the off state, and the second switch, the sixth switch, and the seventh switch are in the off state. The switch is in this conducting state, In the third period, the third switch, the fourth switch, the sixth switch, the seventh switch, and the eighth switch are in the off state, and the first switch, the second switch, and the fifth switch The switch is in this conducting state. A pixel drive circuit, including: A light emitting unit having a first end and a second end, wherein the first end of the light emitting unit is connected to a first operating voltage; A first switch has a first terminal, a second terminal and a control terminal, wherein the first terminal of the first switch is connected to the second terminal of the light-emitting unit, and the control terminal of the first switch is connected To a first control signal; A second switch has a first terminal, a second terminal and a control terminal, wherein the first terminal of the second switch is connected to the second terminal of the first switch, and the second terminal of the second switch Terminal is connected to a second operating voltage; A third switch has a first terminal, a second terminal and a control terminal, wherein the first terminal of the third switch is connected to the control terminal of the second switch, and the second terminal of the third switch Connected to the second end of the first switch and the first end of the second switch, and the control end of the third switch is connected to a second control signal; A fourth switch has a first terminal, a second terminal and a control terminal, wherein the first terminal of the fourth switch is connected to the second terminal of the first switch and the second terminal of the second switch Terminal and the second terminal of the third switch, the second terminal of the fourth switch is connected to the first operating voltage, and the control terminal of the fourth switch is connected to the second control signal; A capacitor having a first terminal and a second terminal, wherein the first terminal of the capacitor is connected to the second terminal of the first switch, the first terminal of the second switch, and the third switch The second end and the first end of the fourth switch; A fifth switch has a first terminal, a second terminal and a control terminal, wherein the first terminal of the fifth switch is connected to the second terminal of the capacitor, and the second terminal of the fifth switch is connected To the control terminal of the second switch and the first terminal of the third switch, the control terminal of the fifth switch is connected to the first control signal; A sixth switch having a first terminal, a second terminal and a control terminal, wherein the first terminal of the sixth switch is connected to the second terminal of the capacitor and the first terminal of the fifth switch, The second end of the sixth switch is connected to a first diode signal, and the control end of the sixth switch is connected to a third control signal; and A seventh switch having a first terminal, a second terminal and a control terminal, wherein the first terminal of the seventh switch is connected to the control terminal of the second switch and the first terminal of the third switch And the second end of the fifth switch, the second end of the seventh switch is connected to a second diode signal, and the control end of the seventh switch is connected to a fourth control signal. The pixel driving circuit according to claim 3, wherein the pixel driving circuit sequentially operates in a first period, a second period, a third period, and a fourth period, In the first period, the first switch, the second switch, the fifth switch, the sixth switch, and the seventh switch are in an off state, and the third switch and the fourth switch are in an on state , In the second period, the first switch, the second switch, the fifth switch, and the seventh switch are in the off state, and the third switch, the fourth switch, and the sixth switch are in the on state , In the third period, the first switch, the third switch, the fourth switch, and the fifth switch are in the off state, and the second switch, the sixth switch, and the seventh switch are in the on state , In the fourth period, the third switch, the fourth switch, the sixth switch, and the seventh switch are in the off state, and the second switch and the fifth switch are in the on state. The pixel driving circuit according to claim 4, wherein the first switch to the seventh switch are N-type transistors, and the first operating voltage is lower than the second operating voltage, In the first period, the first control signal, the third control signal, and the fourth control signal are at a low level, and the second control signal is at a high level, In the second period, the first control signal and the fourth control signal are at the low level, and the second control signal and the third control signal are at the high level, In the third period, the first control signal and the second control signal are at the low level, and the third control signal and the fourth control signal are at the high level, In the fourth period, the first control signal is at the high level, and the second control signal, the third control signal, and the fourth control signal are at the low level. The pixel driving circuit according to claim 4, wherein the first switch to the seventh switch are P-type transistors, the first operating voltage is greater than the second operating voltage, In the first period, the first control signal, the third control signal, and the fourth control signal are at a high level, and the second control signal is at a low level, In the second period, the first control signal and the fourth control signal are at the high level, and the second control signal and the third control signal are at the low level, In the third period, the first control signal and the second control signal are at the high level, and the third control signal and the fourth control signal are at the low level, In the fourth period, the first control signal is at the low level, and the second control signal, the third control signal, and the fourth control signal are at the high level. The pixel driving circuit described in claim 3 further includes: An eighth switch has a first terminal, a second terminal and a control terminal, wherein the first terminal of the eighth switch is connected to the second terminal of the capacitor, the first terminal of the fifth switch, and The first end of the sixth switch, the second end of the eighth switch are connected to the first diode signal, and the control end of the eighth switch is connected to the second control signal. The pixel driving circuit according to claim 7, wherein the pixel driving circuit sequentially operates in a first period, a second period, and a third period, and the third control signal is the same as the fourth control signal, In the first period, the first switch, the second switch, the fifth switch, the sixth switch, and the seventh switch are in an off state, and the third switch, the fourth switch, and the eighth switch are in an off state. The switch is in an on state, In the second period, the first switch, the third switch, the fourth switch, the fifth switch, and the eighth switch are in the off state, and the second switch, the sixth switch, and the seventh switch are in the off state. The switch is in this conducting state, In the third period, the third switch, the fourth switch, the sixth switch, the seventh switch, and the eighth switch are in the off state, and the first switch, the second switch, and the fifth switch The switch is in this conducting state. The pixel driving circuit according to claim 8, wherein the first switch to the eighth switch are N-type transistors, and the first operating voltage is lower than the second operating voltage, In the first period, the first control signal and the third control signal are at a low level, and the second control signal is at a high level, In the second period, the first control signal and the second control signal are at the low level, and the third control signal is at the high level, In the third period, the first control signal is at the high level, and the second control signal and the third control signal are at the low level. The pixel driving circuit according to claim 8, wherein the first switch to the eighth switch are P-type transistors, and the first operating voltage is higher than the second operating voltage, In the first period, the first control signal and the third control signal are at a high level, and the second control signal is at a low level, In the second period, the first control signal and the second control signal are at the high level, and the third control signal is at the low level, In the third period, the first control signal is at the low level, and the second control signal and the third control signal are at the high level.

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