TWI748494B - System for detecting address decoding error of semiconductor device and memory system - Google Patents

Abstract

A system for detecting an address decoding error of a semiconductor device and a memory system are disclosed. The system for detecting the address decoding error of the semiconductor device includes: a decoder of the semiconductor device configured to decode an original address to form a corresponding decoded address, the decoded address having a greater number of bits than the original address; an encoder of the semiconductor device configured to form a recoded address based on the decoded address; and comparison circuitry of the semiconductor device configured to: compare the recoded address and the original address; and detect an address decoding error based on the comparison.

Description

System and memory system for detecting address decoding error of semiconductor device

The present invention relates to a method and system for detecting a semiconductor device and a memory system, and more particularly to a method and system for detecting address decoding errors of a semiconductor device, and a memory system.

An integrated circuit (IC) includes one or more semiconductor devices.

The recent trend of miniaturization of ICs has led to smaller devices (consisting of smaller components), such as memory ICs, which operate at lower voltages and consume less power, and provide the same or at higher speeds. Increased functionality. Under such miniaturization, memory ICs have become more susceptible to errors caused by heat, errors caused by radiation, or the like. The types of damage to semiconductor devices caused by radiation include continuous lattice displacement (usually permanent) and/or ionization effects (usually transient). The types of errors (operational errors) in the operation of semiconductor devices include hard/permanent errors and soft/one-time errors. Lattice displacement tends to cause hard/permanent operating errors. Ionization effects tend to produce soft/one-time operation errors. Operational errors caused by heat are often soft/one-time operational errors.

The present invention provides a method for detecting an address decoding error of a semiconductor device, including: using an address decoder of the semiconductor device to decode an original address to form a corresponding decoded address; using the encoder of the semiconductor device to re-encode The decoded address is used to form a re-encoded address; the comparator of the semiconductor device is used to compare the re-encoded address with the original address; and an address decoding error is detected based on the comparison.

The present invention provides a system for detecting address decoding errors of a semiconductor device, including: a decoder of the semiconductor device configured to decode an original address to form a corresponding decoded address; and an encoder of the semiconductor device , Configured to use a look-up table to generate a re-encoded address based on the decoded address; and the comparison circuit of the semiconductor device is configured to: compare the re-encoded address with the original address by bit; and An address decoding error is detected based on the comparison.

The present invention provides a memory system of a semiconductor device, comprising: a decoder of the semiconductor device configured to decode an original address to form a corresponding decoded address; a memory cell in a non-volatile memory of the semiconductor device The array is configured to receive the decoded address; the read/write circuit is configured to read data from the memory cell array or write data to the memory cell array; the encoder of the semiconductor device , Configured to form a re-encoded address based on the decoded address; and the comparison circuit of the semiconductor device, configured to: compare the re-encoded address with the original address; and detect based on the comparison Address decoding error.

The following disclosure provides many different embodiments or examples for implementing the subject matter provided herein. Specific examples of components, values, operations, materials, configurations, etc. are described below to simplify the present invention. Of course, these components, values, operations, materials, and configurations are only examples and are not intended to be limiting. Expect other components, values, operations, materials, configurations, etc. For example, in the following description, the formation of the first feature on or on the second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include additional features that may be formed between the first feature and the second feature. An embodiment is formed between the second features such that the first feature and the second feature may not directly contact each other. In addition, the present invention may repeat reference numerals and/or letters in various examples. This repetition is for the sake of simplicity and clarity, and does not in itself indicate the relationship between the various embodiments and/or configurations discussed.

In addition, spatial relative terms such as "below", "below", "below", "above", "upper" and the like can be used in this article for descriptive purposes Purpose is used to describe the relationship between one element or feature and another element or feature described in the drawing. In addition to the orientations depicted in the figures, spatial relative terms are also intended to cover different orientations of the device in use or operation. The device can be oriented in other ways (rotated by 90 degrees or in other orientations), and the spatial relative descriptors used in this article can be interpreted accordingly.

According to at least one embodiment of the present invention, in the context of decoding the original address, an error in the address decoding is detected by comparing the original address with a reconstructed version of the original address. In some embodiments, the encoder re-encodes the original address to form a reconstructed version of the original address. The re-encoded address is compared with the original address and an error flag is set if the re-encoded address is different from the original address. According to another method, an error in address decoding is detected by the following: use first and second redundant address decoders to generate corresponding first and second redundant decoded addresses; decode the first redundant bit Comparing the address with the second redundant decoding address; and setting an error flag when the first and second redundant decoding addresses are not the same. Compared with using the first and second redundant decoding addresses, the benefit of using the encoder to re-encode and decode the addresses (according to at least one embodiment of the present invention) is that the footprint of the encoder is smaller than that of the redundant second address decoder This makes the address decoding error detection system have a smaller coverage area than the address decoding error detection system of another method. For example, by using an encoder instead of a redundant second decoder to reduce the size of the components that make up a semiconductor device, one or more of the following benefits are provided: faster operation; reduced overall IC size; reduced material cost ; Or similar.

FIG. 1 is a block diagram of a semiconductor device 100 according to at least one embodiment of the present invention.

In FIG. 1, the semiconductor device 100 particularly includes a circuit macro/module 102 and a circuit macro/module 103. In some embodiments, the semiconductor device 100 is included in an integrated circuit. In some embodiments, the circuit macro/module 102 and the circuit macro/module 103 are understood in a context analogous to the architectural hierarchy of modular programming, where subroutines/procedures are defined by the main program (Or by other subroutines) call to execute the given calculation function. Here, the semiconductor device 100 uses the circuit macro/module 102 and the circuit macro/module 103 to perform corresponding one or more given functions. Therefore, in this case and at the architectural level, the semiconductor device 100 is similar to the main program, and the circuit macro/module (hereinafter referred to as the macro) 102 and the circuit macro/module 103 are correspondingly similar to the sub-normal /program. In some embodiments, the macro 102 and the macro 103 are corresponding soft macros. In some embodiments, the macro 102 and the macro 103 are corresponding hard macros. In some embodiments, the macro 102 and the macro 103 are corresponding soft macros described/expressed by the corresponding register-transfer level (RTL) code. In some embodiments, synthesis, layout, and routing have not been performed on the macro 102 and the macro 103, so that the corresponding soft macro can be synthesized, placed, and routed to various process nodes. In some embodiments, the macro 102 and the macro 103 are corresponding hard macros described/expressed in a binary file format (for example, a graphic database system II (Graphic Database System II, GDSII) streaming format). The binary file format indicates that the plane geometric shapes, text labels, other information, etc. of the corresponding macro 102 and one or more layout diagrams of the macro 103 are corresponding in a hierarchical form. In some embodiments, the composition, layout, and routing performed on the macro 102 and the macro 103 are corresponding, so that the corresponding hard macro is specific to a particular process node.

In some embodiments, the macro 102 is a memory macro. In some embodiments, the macro 102 is a non-volatile memory macro (non-volatile memory macro). In some embodiments, the macro 102 is a read only memory (Read Only Memory, ROM) system macro. In some embodiments, the macro 102 is a memory system macro other than the ROM system macro. The macro 102 especially includes a memory cell array 104, a read/write (R/W) circuit 106, and an address decoding error detection system 108 (see FIG. 2). In some embodiments, the macro 103 is an address decoding error handling system. In some embodiments, the address decoding error handling system is not a macro, but is implemented as one or more components in the macro 102 (not shown). In some embodiments where the semiconductor device 100 itself is included in a system (not shown), the address decoding error handling system 103 is not a macro included in the semiconductor device 100, but is implemented as one or more of the systems. Devices (not shown).

2 is a block diagram of a semiconductor device 200 including a memory system 202 (including an address decoding error detection system 208) and an address decoding error handling system 203 according to at least one embodiment of the present invention.

In FIG. 2, in addition to the address decoding error detection system 208, the memory system 202 also includes a memory cell array 204 and an R/W circuit 206. In some embodiments, the memory system 202 is the macro 102 of FIG. 1. In some embodiments, the address decoding error detection system 208 is the address decoding error detection system 108 of FIG. 1. In some embodiments, the memory cell array 204 is the memory cell array 104 of FIG. 1. In some embodiments, the R/W circuit 206 is the R/W circuit 106 of FIG. 1.

In some embodiments, the address decoding error handling system 203 is not a macro, but is implemented as one or more components (not shown) in the memory system 202. In some embodiments where the semiconductor device 200 itself is included in a system (not shown), the address decoding error handling system 203 is not a system included in the semiconductor device 200, but is implemented as one or more of the systems. Devices (not shown).

The address decoding error detection system 208 includes: an address decoder 210; an encoder 212 and a comparator 214. In the context of a memory access operation for accessing one or more memory cells in the memory cell array 204, the address decoding error detection system 208 receives the original bits identifying one or more cells in the memory cell array 204 site. In Figure 2, the original address is shown as containing N binary bits, where N is a positive integer. In some embodiments, the original address includes bits other than N binary bits. Each of the address decoder 210 and the comparator 214 receives the N-bit original address. The address decoder 210 decodes the N-bit original address to form a corresponding decoded address. In some embodiments, the decoded address contains more bits than the original address. In Figure 2, the decoded address is shown as containing 2 ^N binary bits. In some embodiments, the decoding address includes ^{other bits except 2 N} binary bits. The 2 ^N- bit decoded address is provided to the memory cell array 204. If the memory access operation is a write operation, the R/W circuit 206 receives input data (DI) and provides the input data to the memory cell array 204. If the memory access operation is a read operation, the R/W circuit 206 receives the output data (DO) from the memory cell array 204 and outputs the data.

For the address decoding error detection system 208, a 2 ^N- bit decoding address is also provided to the encoder 212. The encoder 212 implements the mapping of the first set of possible values of the decoded address to the second set of possible values of the re-encoded address. In some embodiments, the encoder 212 implements a look-up table (LUT). In some embodiments, the encoder 212 is a read-only memory (ROM). In some embodiments, the encoder 212 is a non-volatile memory other than LUT or ROM. In some embodiments, the mapping provided by the encoder 212 is fixed when the address decoding error detection system 208 is manufactured.

In FIG. 2, the 2 ^N- bit decoded address is re-encoded by the encoder 212 into an N-bit re-encoded address. The comparator 214 receives the N-bit recoded address and compares it with the N-bit original address. In some embodiments, the comparator 214 is configured to perform a bit-wise (bit-by-bit) comparison between the N-bit recoded address and the N-bit original address. If the comparator 214 determines that the N-bit original address and the N-bit re-encoding address are different from each other, the comparator 214 sets the error flag ERR_FLAG to the error indication state, and outputs the error flag to the address decoding error处理系统203。 Treatment system 203.

In some embodiments, if the comparator 214 sets the error flag ERR_FLAG to the error indication state, the address decoding error handling system 203 handles/responses the response to the error (so that the error flag ERR_FLAG is set to the error indication state) is as follows : The system 203 resets the operation of the memory system 202; the system 203 determines whether the error is a soft/one-time type error or a hard/permanent type error; and, if the error is a soft/one-time type error, repetition will result Wrong operation. In some embodiments, if the error is a hard/permanent type of error, the error handling system 203 outputs a hard/permanent error signal outside the memory system 202. In some embodiments, the error handling system 203 outputs an external hard/permanent error signal from the outside to the semiconductor device 200. In some embodiments where the semiconductor device 200 itself is included in the system (not shown), the address decoding error handling system 203 generates a hard/permanent error signal to identify the semiconductor device 200 as defective, and triggers the system With the repair operations described above, defective instances of the semiconductor device 200 are replaced by non-defective instances of the semiconductor device 200.

Compared with another method using the first and second redundant decoding addresses (where the second redundant decoding address is obtained by using the second redundant address decoder), the encoder 212 is used to re-encode and decode the address. The benefit is that the coverage area of the encoder 212 is smaller than the coverage area of the redundant second address decoder. Therefore, the address decoding error detection system 208 has a smaller coverage area than the address decoding error detection system of another method (which uses redundant first and second decoders). For example, by using the encoder 212 instead of redundant second decoders to reduce the size of the components that make up the semiconductor device, one or more of the following benefits are provided: faster operation; reduction in the overall size of the IC; reduced material Cost; or similar.

3A is a block diagram of a memory system 302 including an address decoding error detection system 308 according to at least one embodiment of the present invention.

The memory system 302 of FIG. 3A is similar to the memory system 202 of FIG. 2. Compared with the components in FIG. 2, the corresponding components in FIG. 3A have reference numbers that have been increased by 100. For example, the memory system 302 corresponds to the memory system 202, the address decoding error detection system 308 corresponds to the address decoding error detection system 208, the memory cell array 304 corresponds to the memory cell array 204, and the R/W circuit 306 Corresponds to R/W circuit 206, or the like. For the sake of brevity, the discussion will focus on the differences between the memory system 302 and the memory system 202.

In FIG. 3A, the encoder 312 implements the mapping of the first possible value 313A (word line driver (WLDRV)) of the decoded address to the second possible value 313B of the re-encoded address. In some embodiments, the encoder 312 implements a LUT. In some embodiments, the encoder 312 is a ROM. In some embodiments, the encoder 312 is a non-volatile memory other than LUT or ROM. In some embodiments, the mapping provided by the encoder 312 is fixed when the address decoding error detection system 308 is manufactured.

In FIG. 3A, each of the possible values of the decoding address in the first group 313A includes 2 ^N bits (received by the encoder 312 from the address decoder 310), and the second group 313B is Each of the possible values of the code address contains N bits. In FIG. 3A, N is 7 so that each of the possible values (WLDRV[0]-WLDRV[127]) of the decoding address in the first group 313A includes 27=128 bits, and the second group 313B Each of the possible values of the recoded address in contains 7 bits. In some embodiments, N is a positive integer other than 7.

Compared with another method using the first and second redundant decoding addresses, the benefit of using the encoder 312 to re-encode and decode the addresses is that the coverage area of the encoder 312 is smaller than the coverage area of the redundant second address decoder. Therefore, the address decoding error detection system 308 has a smaller footprint than the address decoding error detection system of another method (which uses redundant first and second decoders). For example, reducing the size of the components that make up the semiconductor device by using the encoder 312 instead of the redundant second decoder provides one or more of the following benefits: faster operation; reduction in the overall size of the IC; reduced material Cost; or similar.

3B to 3C are circuit diagrams of a one-bit memory cell for storing corresponding logic one data and logic zero data according to at least one embodiment of the present invention.

In some embodiments, a bit cell of FIGS. 3B to 3C cooperates with the bit line BL to be used in the memory cell array 304. A bit memory cell in each of FIGS. 3B to 3C includes a transistor 320 and a switch 322 that can be electronically controlled. In FIGS. 3B to 3C, the transistor 320 is an NMOS transistor. In some embodiments, the transistor 320 is a PMOS transistor. In FIG. 3B, the switch 322 is a single pole double throw (SPDT) switch. In some embodiments, the switch 322 is a switch other than the SPDT switch. Regarding the NMOS transistor 320, the first drain/source terminal is connected to the bit line BL, the second drain/source terminal is connected to the input terminal of the switch 322, and its gate terminal is connected to the word line WL. Regarding the switch 322, its first output terminal is left floating without being connected to anything, and its second output is connected to the ground.

In FIG. 3B, the switch 322 is placed in the first state where the input terminal is connected to the first output terminal and therefore floats, which represents the storage of logical one data. In FIG. 3C, the switch 322 is placed in the second state where the input terminal is connected to the second output terminal and thereby grounded, which represents the storage of logic zero data.

3D to 3E are circuit diagrams of one-bit memory cell pairs storing corresponding logical one and logical zero data pairs and logical zero and logical one data pairs according to at least one embodiment of the present invention.

In some embodiments, one-bit memory cell pairs are used in the memory cell array 304 in cooperation with the bit line BL and the bit_bar line BLB (bit_bar line). The one-bit memory cell pair in each of FIGS. 3D to 3E includes not only a transistor 320 and a switch 322, but also a transistor 324 and an electronically controllable switch 326. In FIGS. 3D to 3E, the transistor 324 is an NMOS transistor. In some embodiments, the transistor 324 is a PMOS transistor. In FIGS. 3D to 3E, the switch 326 is a single pole double throw (SPDT) switch. In some embodiments, the switch 326 is a switch other than the SPDT switch. Regarding the NMOS transistor 324, the first drain/source terminal is connected to the bit line BLB, the second drain/source terminal is connected to the input terminal of the switch 326, and its gate terminal is connected to the word line WL. Regarding the switch 326, its first output terminal is left floating without being connected to anything, and its second output is connected to the ground.

In FIGS. 3D to 3E, one of the bit memory cells in a pair is controlled to store the data stored by each other in a logical inversion. In FIG. 3D, the switch 322 is placed in the first state where the input terminal is connected to the first output terminal and therefore floats, which represents the storage of a logical data, and the switch 326 is placed in the input terminal connected to the second output terminal and thus grounded. The second state, which means the storage of logic zero data. In FIG. 3E, the switch 322 is placed in the second state where the input terminal is connected to the second output terminal and is therefore grounded, which represents the storage of logic zero data, and the switch 326 is placed in the input terminal connected to the first output terminal and therefore floats. The first state, which represents the storage of logic one data.

4A is a block diagram of a memory system 402 including an address decoding error detection system 408 according to at least one embodiment of the present invention.

The memory system 402 of FIG. 4A is similar to the memory system 302 of FIG. 3A. Compared with the components in FIG. 3A, the corresponding components in FIG. 4A have reference numbers that have been increased by 100. For example, the memory system 402 corresponds to the memory system 302, the address decoding error detection system 408 corresponds to the address decoding error detection system 308, the memory cell array 404 corresponds to the memory cell array 304, and the R/W circuit 406 Corresponds to R/W circuit 306, or the like. For the sake of brevity, the discussion will focus on the differences between the memory system 402 and the memory system 302.

In FIG. 4A, the encoder 412 implements the mapping of the first possible value 413A (WLDRV[i]) of the decoded address to the second possible value 413B of the re-encoded address. Compared with the second group 313B of the encoder 312, each of the possible values of the re-encoding address includes N bits, and each of the possible values of the re-encoding address in the second group 413B includes N+1 bits. In Figure 4A, for simplicity of illustration, N is 4 so that each of the possible values (WLDRV[0]-WLDRV[15]) of the decoding address in the first group 413A contains 24=16 bits Element, each of the possible values of the recoded address in the second group 413B contains 5 bits. In some embodiments, N is a positive integer other than 4.

In addition to the mapping, the encoder 412 translates the corresponding possible values of the second group 413B of the re-encoded address into a predefined X format. The given example of the X formatted version of the recoded address is different from the corresponding unformatted version of the recoded address. An example of an unformatted version of a re-encoded address is the format of the second group 313B used by the encoder 312. In some embodiments, the X format (discussed in more detail below) is a low power (LP) format. Compared with the system 308 of FIG. 3A, the system 408 further includes an LP format de-translator 430.

In FIG. 4A, the 2 ^N- bit decoded address (received by the encoder 412 from the address decoder 410) is re-encoded by the encoder 412 and translated into an N+1-bit re-encoded address in the LP format. The LP format de-translator 430 receives the N+1 bits, the re-encoded address of the LP formatted version, and translates it into the corresponding N-bit of the re-encoded address of the unformatted version. The comparator 414 receives the N-bit, unformatted version of the re-encoded address from the LP format de-translator 430, and compares it with the N-bit original address.

Compared with another method using the first and second redundant decoding addresses, the benefit of using the encoder 412 to re-encode and decode the addresses is that the coverage area of the encoder 412 and the LP format de-translator 430 is smaller than the redundant second bit The coverage area of the address decoder. Therefore, the address decoding error detection system 408 has a smaller coverage area (using redundant first and second decoders) than the address decoding error detection system of another method. For example, by using the encoder 412 instead of redundant second decoders to reduce the size of the components that make up the semiconductor device, one or more of the following benefits are provided: faster operation; reduction in the overall size of the IC; reduction in material cost ; Or similar.

FIG. 4B is a table 450 showing an example of LP format translation according to at least one embodiment of the present invention.

An example of an encoder that can implement the LP format translation of the table 450 is the encoder 412 of FIG. 4A. For simplicity of illustration, table 450 shows N=4. In some embodiments, N is a positive integer other than 4.

In FIG. 4B, the unformatted re-encoded address bits are translated in table 450 as follows. For a given example of an unformatted re-encoded address: if the number of logical zeros/count Σ0 is greater than or equal to the number of logical ones/count Σ1 such that Σ0≥Σ1, then the flag bit b(N)=b4 is set to logic Zero; and bit b (N-1): the logical value of b0 is correspondingly inverted; and if the number of logical ones/count Σ1 is greater than the number of logical zeros/count Σ0 such that Σ1>Σ0, then the flag bit b (N)=b4 is set to logic one and the logic value of bit b(N-1): b0 is not changed. The benefit of this type of LP format is that more logical bits are stored in the second group 413B; therefore, more logical bits are read in order to read the content of the encoder 412.

As an example drawn from table 450, consider the column of table 450 in which the unformatted re-encoded address bit b3: b0=0110, Σ1=2 and Σ0=2 make Σ0≥Σ0. Therefore, bit b3: b0 is inverted from the state of the re-encoded address of its unformatted version, and the flag bit b4 is set to 0 so that the corresponding LP formatted re-encoded address bit row b4: b0=01001 .

As another example drawn from table 450, consider the column of table 450 with unformatted re-encoded address bit b3: b0=0111, where Σ1=3 and Σ0=1 make Σ1>Σ0. Therefore, no changes are made to the bits b3: b0 and the flag bit b4 is set to one, so that the corresponding LP formatted re-encoded address bit row b4: b0=10111.

FIG. 4C is a block diagram showing the format de-translator 430 in more detail according to at least one embodiment of the present invention.

In FIG. 4C, the format de-translator 430 includes N two-input XOR gates 432(0) to two-input XOR gates 432(N-1). The first input of each of the N XOR gates 432(N-1) to XOR gate 432(0) receives the N bits b(N-1 ): The corresponding one in b0. The second input of each of the XOR gates 432(N-1) to 432(0) receives the flag bit Flag_bit. In some embodiments, the format de-translator 430 includes a logical configuration different from the XOR gates 432(0) to 432(N-1) in FIG. 4C.

FIG. 4D is a table 460 showing an example of LP format interpretation according to at least one embodiment of the present invention.

An example of an LP format de-translator that can implement the LP format de-translator of the table 450 is the LP format de-translator 430 of FIG. 4A. In FIG. 4D, for simplicity of illustration, table 460 shows N=4. In some embodiments, N is a positive integer other than 4.

In FIG. 4D, the LP formatted re-encoded address bits are deciphered and translated as follows in table 460. For a given example of the LP format recoding address: if the flag bit b(N)=b4 is set to logic zero, then the bit b(N-1): the logical value of b0 is inverted correspondingly, and The flag bit b4 is discarded; and if the flag bit b(N)=b4 is set to logic one, no change is made to the logic value of bit b(N-1): b0 and the flag bit b4 is discarded .

As an example drawn from table 460, consider the column of table 460 with LP formatting re-encoding address bit b3: b0=0110 and flag bit b4=0. Therefore, the bits b3:b0 of the LP formatted recoded address are reversed to generate the bits b3:b0 of the unformatted recoded address, so that the bits b3:b0 of the unformatted recoded address are b3: b0=1001, and the flag bit b4 is discarded.

As another example drawn from table 460, consider the column of table 460 with LP formatting re-encoding address bit b3: b0=0111 and flag bit b4=1. Therefore, the bits b3:b0 of the LP formatted recoded address are not changed, so that the bits b3:b0 of the unformatted recoded address are b3:b0=0111, and the flag bit b4 is discarded.

FIG. 5 is a block diagram of a memory system 502 including an address decoding error detection system 508 according to at least one embodiment of the present invention.

The memory system 502 of FIG. 5A is similar to the memory system 402 of FIG. 4A. With respect to the components in FIG. 4A, the corresponding components in FIG. 5 have reference numbers that have been increased by 100. For example, the memory system 502 corresponds to the memory system 402, the address decoding error detection system 508 corresponds to the address decoding error detection system 408, the memory cell array 504 corresponds to the memory cell array 404, and the R/W circuit 506 Corresponds to R/W circuit 406, or the like. For the sake of brevity, the discussion will focus on the differences between the memory system 502 and the memory system 402.

In FIG. 5, the encoder 512 implements the mapping of the first possible value 513A (WLDRV[i]) of the decoded address to the second corresponding possible value 513B of the re-encoded address. In addition to the mapping, the encoder 512 translates the possible values corresponding to the second group 513B of the re-encoded address into a predefined X format. The given example of the X formatted version of the recoded address is different from the corresponding unformatted version of the recoded address. An example of an unformatted version of a re-encoded address is the format of the second group 313B used by the encoder 312. In some embodiments, the X format (discussed in more detail below) is a Q bit ROM (Q bit ROM, QBR) format, where Q is a positive integer and Q≧2. In some embodiments, Q=2. In some embodiments, Q is a positive integer greater than 2. Compared with the system 408 of FIG. 4A, the system 508 further includes a QBR format de-translator 530. The details of QBR translation and de-translation are found in (for example) US Patent No. 8,837,192 issued on September 16, 2014, the entire contents of which are incorporated herein by reference.

In FIG. 5, the 2 ^N- bit decoded address (received by the encoder 512 from the address decoder 510) is re-encoded by the encoder 512 and translated into the re-encoded bit of the QBR formatted version containing N/Q bits Address, where Q is a positive integer such that N/Q=U, and where U is a positive integer. The N+1 bit recoding address is in QBR format. The QBR format de-translator 530 receives the recoded address of the N+1 bit, QBR formatted version, and translates it into the corresponding N bit of the recoded address of the unformatted version. The comparator 514 receives the N-bit unformatted version of the recoded address from the QBR format de-translator 530, and compares the received N-bit unformatted version with the N-bit original address.

Compared with another method using the first and second redundant decoding addresses, the benefit of using the encoder 512 to re-encode the decoded addresses is that the coverage area of the encoder 512 and the QBR format de-translator 530 is smaller than the redundant second bit The coverage area of the address decoder. Therefore, the address decoding error detection system 508 has a smaller coverage area (using redundant first and second decoders) than the address decoding error detection system of another method. For example, by using the encoder 512 instead of redundant second decoders to reduce the size of the components that make up the semiconductor device, one or more of the following benefits are provided: faster operation; reduction of the overall size of the IC; reduction of material Cost; or similar.

6A is a flowchart of a method 600 for detecting address decoding errors of a semiconductor device according to at least one embodiment of the present invention.

An example of a semiconductor device to which the method 600 can be applied is the semiconductor device 100 of FIG. 1. Examples of the address decoding error detection system implementing the method 600 include the address decoding error detection system 208, the address decoding error detection system 308, the address decoding error detection system 408, the address decoding error detection system 508, or Similar.

In FIG. 6A, the method 600 includes blocks 602 to 612. At block 602, the original address is received. An example of the original address is the original address shown in FIG. 2. From block 602, the process proceeds to block 604. At block 604, the original address is decoded using the address decoder of the semiconductor device to form a corresponding decoded address. An example of the address decoder is the address decoder 210 of FIG. 2. From block 604, the process proceeds to block 606.

At block 606, the encoder of the semiconductor device is used to re-encode the decoded address to form a re-encoded address. Examples of encoders include encoder 212 of FIG. 2 and encoder 312 of FIG. 3A, each of which outputs an N-bit address. The encoder encodes the decoded address into a re-encoded address. In some embodiments, the encoder implements the LUT. In some embodiments, the encoder is a ROM. In some embodiments, the encoder is a non-volatile memory other than LUT or ROM. From block 606, the process proceeds to block 608.

At block 608 in FIG. 6, a comparator of the semiconductor device is used to compare the recoded address with the original address. An example of the comparator is the comparator 214 in FIG. 2. In some embodiments, the comparison is a bitwise comparison. From block 608, the process proceeds to block 610. At block 610, errors are detected based on the comparison. In some embodiments, if the re-encoded address and the original address are not the same, it is considered that a decoding error has occurred. From block 610, the process proceeds to block 612. At block 612, an address decoding error handling system is used to handle address decoding errors. An example of the address decoding error handling system is the address decoding error handling system 203 of FIG. 2.

FIG. 6B is a flowchart showing the block 606 of FIG. 6A in more detail according to at least one embodiment of the present invention.

In FIG. 6B, block 606 includes block 620 to block 622. The flow proceeds from block 606 to block 620, where the decoded address is used as an index. From block 620, the process proceeds to block 622. At block 622, the index (again, the decoding address) is used to access the map. The mapping associates the first set of possible values of the decoded address with the second set of corresponding possible values for the re-encoded address. The mapping is stored in the non-volatile memory of the semiconductor device. An example of the first set of possible values of the decoded address is the first set 313A of FIG. 3A. An example of the second set of possible values corresponding to the recoded address is the second set 313B of FIG. 3A. An example of non-volatile memory is the encoder 312 of FIG. 3A.

FIG. 6C is a flowchart showing the block 606 to the block 608 of FIG. 6A in more detail according to at least one embodiment of the present invention.

In FIG. 6C, block 606 includes block 630 to block 634. The flow proceeds from block 606 to block 630, where the decoded address is used as an index. From block 630, the process proceeds to block 632. At block 632, the index (also, the decoding address) is used to access the map to identify the re-encoded address of the X formatted version. The mapping associates the first set of possible values of the decoded address with the second set of corresponding possible values for the re-encoded address. The mapping is stored in the non-volatile memory of the semiconductor device. An example of the X format is the LP format used in Figure 4A, and the associated example of the non-volatile memory, the first set of possible values of the decoded address, and the second set of corresponding possible values of the re-encoded address is that of Figure 4A Corresponding to the encoder 412, the first group 413A and the second group 413B. Another example of the X format is the QBR format of Figure 5, and the associated example of the non-volatile memory, the first set of possible values of the decoded address, and the second set of corresponding possible values of the recoded address is the corresponding code of Figure 5 512, a first group 513A, and a second group 513B. From block 632, the process proceeds to block 634.

At block 634, the de-translator of the semiconductor device is used to decode the re-encoded address of the X formatted version. Examples of de-translators include the LP format de-translator 430 in FIG. 4A and the QBR de-translator 530 in FIG. 5. From block 634, the process proceeds to block 608 outside of block 606. In FIG. 6C, block 608 includes block 636. The process proceeds from block 608 to block 636. At block 636, the rewrite code address of the unformatted version is used for comparison.

FIG. 6D is a flowchart showing the block 606 to the block 608 of FIG. 6A in more detail according to at least one embodiment of the present invention.

In FIG. 6D, block 606 includes block 640 to block 644. The flow proceeds from block 606 to block 640, where the decoded address is used as an index. From block 640, the process proceeds to block 642. At block 642, the index (also, the decoded address) is used to access the map to identify the re-encoded address of the low-power formatted version. The mapping associates the first set of possible values of the decoded address with the second set of corresponding possible values of the re-encoded address. The recoded address of the unformatted version contains N bits. The recoded address of the LP formatted version includes N bits of the recoded address of the unformatted version plus additional flag bits for a total of N+1 bits. The mapping is stored in the non-volatile memory of the semiconductor device. An example of the LP format is the LP format used in Figure 4A, and the associated example of the non-volatile memory, the first set of possible values of the decoded address, and the second set of corresponding possible values of the re-encoded address is that of Figure 4A Corresponding to the encoder 412, the first set 413A and the second set 413B. From block 642, the process proceeds to block 644.

At block 644, the recoded address of the LP formatted version is decoded. An example of the de-translator is the LP format de-translator 430 of FIG. 4A. The block 644 includes a block 646 to a block 654. The flow proceeds to block 646 in block 644, where it is determined whether the flag bit is set to logic zero. An example of the flag bit is shown as bit b4 in the table 460 of FIG. 4D.

If the judgment result at block 646 is yes (that is, the flag bit is set to logic zero), the flow proceeds to block 648. At block 648, the N bits of the recoded address of the LP formatted version are inverted, and the flag bit is discarded. As an example of the case where the N bits of the recoded address of the LP formatted version are reversed, consider the LP formatted recoded address bit b3: b0=0110 and the flag bit b4=0 in the table 460 column . Therefore, the bit b3:b0 of the LP formatted recoded address is reversed to generate the bit b3:b0 of the unformatted recoded address, so that the bit b3:b0 of the unformatted recoded address becomes b3 : B0=1001, and the flag bit b4 is discarded. From block 648, the process proceeds to block 650. At block 650, the reversed N bits are regarded as the unformatted version of the re-encoded address. From block 650, the process proceeds to block 652. At block 652, the decoded address of the unformatted version is output.

If the judgment result at block 646 is no (that is, the flag bit is not set to a logic zero), the flow proceeds to block 654. At block 654, the N bits of the recoded address of the LP formatted version are unchanged, and the flag bits are discarded. As an example of the case where the N bits of the recoded address of the LP formatted version are not inverted, consider the table 460 of the LP formatted recoded address bit b3: b0=0111 and flag bit b4=1 List. Therefore, the bits b3:b0 of the LP formatted recoded address are not changed, so that the bits b3:b0 of the unformatted recoded address become b3:b0=0111, and the flag bit b4 is discarded. From block 654, the process proceeds to block 652 as described above.

From block 644, the process proceeds to block 608 outside of block 606. In FIG. 6D, block 608 includes block 636. The process proceeds to block 636 in block 608. At block 636, the recoded address of the unformatted version is used for comparison.

One aspect of the present invention relates to a method for detecting an address decoding error of a semiconductor device. The method includes: using an address decoder of the semiconductor device to decode an original address to form a corresponding decoded address; using the semiconductor device The encoder of the device re-encodes the decoded address to form a re-encoded address; compares the re-encoded address with the original address using the comparator of the semiconductor device; and detects the bit based on the comparison Address decoding error. Regarding the method, each of the original address and the re-encoded address has N bits, where N is a positive integer; and the decoded address has 2 ^N bits. Regarding the method, re-encoding the decoded address includes: using the decoded address as an index; accessing a map stored in a non-volatile memory of the semiconductor device according to the index, the map being The first set of possible values of the decoded address is associated with the second set of corresponding possible values of the re-encoded address. Regarding the method, re-encoding the decoded address includes: using the decoded address as an index; and accessing a map stored in a non-volatile memory of the semiconductor device according to the index; wherein the map is The first set of possible values of the decoded address is associated with the second set of corresponding possible values of the re-encoded address. Regarding the method, re-encoding the decoded address includes: using the decoded address as an index; and accessing a mapping in a non-volatile memory stored in a semiconductor device according to the index; wherein the mapping is The first set of possible values of the decoded address is associated with the second set of corresponding possible values of the re-encoded address; the mapping represents the second set of corresponding possible values of the re-encoded address for the X format , The given instance of the X formatted form of the recoded address is different from the unformatted version of the recoded address; the access identifies the recoded address of the corresponding X formatted version ; The re-encoding and decoding address further includes deciphering the re-encoding address of the X formatted version into the corresponding unformatted version; and the comparison includes using the re-encoding address of the unformatted version. Regarding the method, the X format is a low-power format; the re-encoded address of the unformatted version contains N bits, where N is a positive integer; the re-encoded address of the low-power formatted version The N bits including the re-encoded address of the unformatted version plus additional flag bits total N+1 bits; and the de-translation includes: the weight of the identified low-power formatted version In the first case where the flag bit of the encoding address is set to zero, the N bits of the re-encoding address of the recognized low-power formatted version are inverted, and the inverted N bits are output as The re-encoded address of the unformatted version; and for the second case where the flag bit of the re-encoded address of the identified low-power formatted version is set to one, the re-encoded bit of the identified low-power formatted version is set The N bits of the address are output as the unformatted version of the recoded address. Regarding the method, the X format is a Q-bit ROM (QBR) format. Regarding the method, the recoded address of the unformatted version includes N bits, where N is a positive integer; and the recoded address of the QBR formatted version includes N/Q bits, where Q is positive Integers make N/Q=U, where U is a positive integer. Regarding the method, the comparison includes: comparing the re-encoded address with the original address by bit.

Another aspect of the present invention relates to a system for detecting address decoding errors of a semiconductor device, the system comprising: a decoder of the semiconductor device configured to decode an original address to form a corresponding decoded address; The encoder of the semiconductor device is configured to use a look-up table to generate a re-encoded address based on the decoded address; and the comparison circuit of the semiconductor device is configured to compare the re-encoded address with the original address by bit, And based on the comparison, an address decoding error is detected. Regarding this type of system, the encoder includes non-volatile memory. Regarding this type of system, each of the original address and the re-encoded address has N bits, where N is a positive integer; and the decoded address has 2 ^N bits. Regarding this type of system, the decoded address has a larger number of bits than each of the original address and the re-encoded address. Regarding this type of system, the encoder is further configured to map the first set of possible values of the decoded address to the second set of corresponding possible values of the re-encoded address; the decoded address is provided to the encoder as an index; and the encoder It is further configured to output the corresponding decoding address based on the index. Regarding such systems, the encoder is further configured to map the first set of possible values of the decoded address to the second set of corresponding possible values of the re-encoded address; the mapping represents the said for the predefined X format The second set of possible values corresponding to the re-encoded address, the given example of the X-formatted version of the re-encoded address is different from the unformatted version of the re-encoded address; and the decoded bit The encoder is provided as an index to the encoder; the encoder is further configured to output the corresponding decoded address based on the index; with regard to such a system, the system further includes: a format de-translator is configured to Receives the re-encoded address of the X formatted version from the encoder, and decodes the re-encoded address of the X formatted version into the corresponding re-encoded address of the unformatted version; and the comparison circuit is further configured to use The recoded address of the unformatted version is used for comparison. Regarding this type of system, the X format is a low-power format; the recoded address of the unformatted version contains N bits, where N is a positive integer; the recoded bit of the low-power formatted version The address includes the N bits of the unformatted version of the re-encoded address plus additional flag bits for a total of N+1 bits; and the format de-translator is further configured to: In the first case where the flag bit of the re-encoding address of the low-power formatted version is set to zero, the N bits of the re-encoded address of the recognized low-power formatted version are inverted, and the inverted The output of N bits is the recoded address of the unformatted version, and the flag bit of the recoded address of the recognized low-power formatted version is set to one. In the second case, the recognized low-power The N bits of the recoded address of the formatted version are output as the recoded address of the unformatted version. Regarding this type of system, the format de-translator includes N XOR gates corresponding to the N bits of the re-encoded address of the identified low-power formatted version. Regarding this type of system, the X format is a Q-bit ROM format.

Another aspect of the present invention relates to a memory system of a semiconductor device, the system comprising: a decoder of the semiconductor device configured to decode an original address to form a corresponding decoded address; the non-volatile semiconductor device The memory cell array in the sexual memory is configured to receive the decoding address; the read/write circuit is configured to read data from the memory cell array or write data to the memory cell array; The encoder of the semiconductor device is configured to form a re-encoded address based on the decoded address; and the comparison circuit of the semiconductor device is configured to compare the re-encoded address with the original address, and detect based on the comparison Address decoding error. Regarding this type of system, the encoder is further configured to map the first set of possible values of the decoded address to the second set of corresponding possible values of the re-encoded address; the decoded address is provided as an index to the encoding The encoder is further configured to output the corresponding decoding address based on the index; the mapping represents the second set of corresponding possible values for the re-encoded address of the predefined X format , The given example of the formatted version of X of the re-encoded address is different from the unformatted version of the re-encoded address; the system further includes a format de-translator configured to receive X from the encoder The recoded address of the formatted version; and deciphering the recoded address of the X formatted version into the corresponding unformatted version of the recoded address; and wherein the comparison circuit is further configured The re-encoded address to use the unformatted version is used for the comparison. Regarding this type of system, the X format is a low-power format; the re-encoded address of the unformatted version contains N bits, where N is a positive integer; the re-encoded address of the low-power formatted version includes the The N bits plus additional flag bits of the unformatted version of the re-encoded address are N+1 bits in total; and the format de-translator is further configured to be the weight of the low-power formatted version In the first case where the flag bit of the encoded address is set to zero, the N bits of the re-encoded address of the low-power formatted version are inverted, and the inverted N bits are output as the unformatted version For the second case where the flag bit of the re-encoded address of the low-power formatted version is set to one, the N bits of the re-encoded address of the low-power formatted version are output as unformatted The recoded address of the modified version.

The foregoing summarizes the features of several embodiments, so that those skilled in the art can better understand various aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis for designing or modifying other processing procedures and structures for achieving the same purpose and/or achieving the same advantages of the embodiments introduced herein. Those familiar with the art should also realize that such equivalent structures do not depart from the spirit and scope of the present invention, and those familiar with the art can make changes in this text without departing from the spirit and scope of the present invention. , Substitution and modification.

100, 200: Semiconductor device 102: Circuit macro/module, macro 103: Circuit macro/module, macro, address decoding error handling system 104, 204, 304, 404, 504: memory cell array 106, 206, 306, 406, 506: read/write (R/W) circuit 108, 208, 308, 408, 508: address decoding error detection system, system 202, 302, 402, 502: memory system 203: Address decoding error handling system, error handling system, system 210, 310, 410, 510: address decoder 212, 312, 412, 512: encoder 214, 314, 414, 514: Comparator 313A, 413A, 513A: the first set of possible values, the first set 313B, 413B, 513B: The second group corresponds to possible values, the second group 320, 324: Transistor 322, 326: Switch 430: Low-power format de-translator, format de-translator, LP format de-translator 432(0)-432(N-1): XOR gate 450, 460: table 530: QBR format de-translator 600: method 602-654: block DI: Input data DO: output data BL, BLB: bit line WL: Character line b0-b3, b(0)-b(N-1): bit b4, Flag_bit: flag bit, bit ERR_FLAG: Error flag

The aspect of the present invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to standard practices in the industry, various features are not drawn to scale. In fact, for clarity of discussion, the size of various features can be increased or decreased arbitrarily. FIG. 1 is a block diagram of a semiconductor device according to at least one embodiment of the present invention. 2 is a block diagram of a memory system including an address decoding error detection system according to at least one embodiment of the present invention. 3A is another block diagram of a memory system including an address decoding error detection system according to at least one embodiment of the present invention. 3B to 3C are circuit diagrams of a one-bit memory cell for storing corresponding logic one data and logic zero data according to at least one embodiment of the present invention. 3D to 3E are circuit diagrams of one-bit memory cell pairs storing corresponding logical one and logical zero data pairs and logical zero and logical one data pairs according to at least one embodiment of the present invention. 4A is another block diagram of a memory system including an address decoding error detection system according to at least one embodiment of the present invention. 4B is a table showing an example of low power (LP) format translation according to at least one embodiment of the present invention. 4C is a block diagram showing a format detranslator in more detail according to at least one embodiment of the present invention. FIG. 4D is a table showing an example of LP format interpretation according to at least one embodiment of the present invention. 5 is another block diagram of a memory system including an address decoding error detection system according to at least one embodiment of the present invention. 6A is a flowchart of a method for detecting address decoding errors of a semiconductor device according to at least one embodiment of the present invention. FIG. 6B is a flowchart showing the first block of FIG. 6A in more detail according to at least one embodiment of the present invention. FIG. 6C is a flowchart showing the first block and the second block of FIG. 6A in more detail according to at least one embodiment of the present invention. FIG. 6D is another flowchart showing the first block and the second block of FIG. 6A in more detail according to at least one embodiment of the present invention.

200: Semiconductor device

202: Memory System

203: Address decoding error handling system, error handling system, system

204: Memory Cell Array

206: Read/write (R/W) circuit

208: Address decoding error detection system, system

210: address decoder

212: Encoder

214: Comparator

DI: Input data

DO: output data

ERR_FLAG: Error flag

Claims (10)

A system for detecting address decoding errors of a semiconductor device, the system comprising: a decoder of the semiconductor device configured to decode an original address to form a corresponding decoded address, the decoded address having a higher value than the original The number of bits in the address is greater; the encoder of the semiconductor device is configured to form a re-encoded address of the X formatted version based on the decoded address; the format de-translator of the semiconductor device is configured to Deciphering the recoded address of the X formatted version into a corresponding unformatted version of the recoded address; and the comparison circuit of the semiconductor device is configured to: compare the unformatted version The re-encoded address and the original address of the version; and detecting an address decoding error based on the comparison. The system according to claim 1, wherein: each of the original address and the re-encoded address has N bits, where N is a positive integer; and the decoded address has 2 ^{N bits} Bit. The system according to claim 1, wherein: the encoder is further configured to map the first set of possible values of the decoded address and the second set of corresponding possible values of the re-encoded address; The decoding address is provided to the encoder as an index; and the encoder is further configured to output the re-encoding address based on the index. The system according to claim 1, wherein: the encoder is further configured to map the first set of possible values of the decoded address and the second set of corresponding possible values of the re-encoded address; the The mapping represents the second set of corresponding possible values of the re-encoded address in a predefined X format, and a given example of the X-formatted version of the re-encoded address is different from the re-encoded address The unformatted version; providing the decoded address as an index to the encoder; the encoder is further configured to output the re-encoded address based on the index; and the format interpretation The device is further configured to receive the re-encoded address of the X formatted version from the encoder. A memory system of a semiconductor device, the memory system comprising: a decoder of the semiconductor device, configured to decode an original address to form a corresponding decoded address, the decoded address having a higher value than the original address A large number of bits; the memory cell array in the non-volatile memory of the semiconductor device is configured to receive the decoded address; the read/write circuit is configured to read from the memory cell array Information or resources The material is written to the memory cell array; the encoder of the semiconductor device is configured to form a re-encoded address of the X formatted version based on the decoded address; the format de-translator of the semiconductor device is configured To decipher the re-encoded address of the X formatted version into a corresponding unformatted version of the re-encoded address; and the comparison circuit of the semiconductor device is configured to: compare the unformatted version A modified version of the re-encoded address and the original address; and detecting an address decoding error based on the comparison. The memory system according to claim 5, wherein: the encoder is further configured to map the first set of possible values of the decoded address to the second set of corresponding possible values of the re-encoded address Provide the decoded address as an index to the encoder; the encoder is further configured to output the re-encoded address based on the index; the mapping represents the re-encoded address in a predefined X format The second set of coded addresses corresponds to possible values, and the given instance of the X formatted version of the recoded address is different from the unformatted version of the recoded address; and the format The de-translator is further configured to receive the re-encoded address of the X formatted version from the encoder. The memory system according to claim 5, wherein: The comparison circuit is further configured to compare the recoded address with the original address by bit. A system for detecting address decoding errors of a semiconductor device, the system comprising: a decoder of the semiconductor device configured to decode an original address to form a corresponding decoded address, the decoded address having a higher value than the original Address more bits; the encoder of the semiconductor device is configured to form a re-encoded address of the X formatted version based on the decoded address; the format de-translator of the semiconductor device is configured to The recoded address of the X formatted version is decoded into the recoded address of the corresponding unformatted version; and the comparison circuit of the semiconductor device is configured to: compare the unformatted version The re-encoded address and the original address; and detecting an address decoding error based on the comparison, wherein: the encoder is further configured to make the first set of possible values of the decoded address and the The second set of re-encoded addresses corresponds to a mapping related to possible values; the decoded address is provided as an index to the encoder; and the encoder is further configured to output the re-encoded bits based on the index site. The system according to claim 8, wherein: each of the original address and the re-encoded address has N bits, where N is a positive integer; and the decoded address has 2 ^{N bits} Bit. The system according to claim 8, wherein: the mapping represents the second set of corresponding possible values of the re-encoded address in a predefined X format, and the X-formatted version of the re-encoded address The given instance of is different from the unformatted version of the re-encoded address; and the format de-translator is further configured to receive the re-encoded address of the X formatted version from the encoder .

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