TWI744954B - Nand-type flash memory and manufacturing method thereof - Google Patents

Abstract

A NAND flash memory capable of reducing the planar size of a memory unit is provided. The three-dimensional NAND flash memory has a substrate, an insulating layer, a lower conductive layer (source), a three-dimensional memory cell structure, and a bit line. The memory cell structure includes: a plurality of strip-shaped gate stacks including stacks of insulators and conductors stacked in a vertical direction from the substrate; and a plurality of channel stacks arranged separately along one side of the gate stack. The upper end of the channel stack is electrically connected to the orthogonal bit line, and the lower end of the channel stack is electrically connected to the lower conductive layer.

Description

NAND flash memory and manufacturing method thereof

The invention relates to a NAND flash memory, and more particularly to a NAND flash memory with a three-dimensional structure and a manufacturing method thereof.

In recent years, in order to achieve an increase in the degree of integration of memory cells, a NAND-type flash memory with a three-dimensional structure in which memory cells are stacked in a vertical direction has been put into practical use. For example, the memory cell is formed using a semiconductor pillar extending in a vertical direction from a substrate (Patent Document 1).

In addition, in Non-Patent Document 1, as shown in FIG. 1, a plurality of rectangular-shaped gates are stacked on a substrate, and a charge storage layer (for example, silicon nitride Layer) insulator and film channel. The thin film channel contains polysilicon and has a U-shaped shape. A NAND string includes a U-shaped thin film channel, an insulator including a charge storage layer, and a gate. One upper end of the thin film channel is connected to the local source line via a plug, and the other upper end is connected to the bit line via a plug. 2A is a cross-sectional view when the thin film channel of the flash memory of FIG. 1 is cut in the horizontal direction, and FIG. 2B is a cross-sectional view when the thin film channel is cut in the vertical direction. The black elliptical portion shown in FIG. 2A is a hole formed by etching, and the hole is an insulating region that insulates the thin film channel formed along the multi-gate. The pitch is 100 nm. In addition, the pitch between adjacent multi-gates is 220 nm. [Prior Art Literature] [Patent Literature]

[Patent Document 1] Japanese Patent Laid-Open No. 2015-176870 [Non-Patent Document 1] A Novel Double-density, Single-Gate Vertical Channel (SGVC) 3D NAND Flash That Is Tolerant to Deep Vertical Etching CD Variation and Process Robust Read-disturb Immunity, Hang-Ting Lue et al, IEEE International Electron Devices Meeting (IEDM) 15-44, P321-324

[The problem to be solved by the invention]

The object of the present invention is to provide a NAND-type flash memory capable of reducing the planar size of memory cells compared with the prior art, and a manufacturing method thereof. [Technical means to solve the problem]

The NAND flash memory with a three-dimensional structure of the present invention includes: a substrate; a lower conductive layer formed in or on the substrate; a plurality of laminated bodies extending in a first direction on the lower conductive layer, And the plurality of laminates respectively include a laminate of an insulator and a conductor laminated in a vertical direction from the substrate; a plurality of channel laminates are separately arranged along one of the side surfaces of the plurality of laminates, and The plurality of channel laminates respectively include an insulating layer including a charge storage layer and a channel film, the insulating layer and the channel film extend from the substrate in a vertical direction, and the lower end of the channel film is electrically connected On the lower conductive layer; and a plurality of upper conductive layers extending in a second direction orthogonal to the first direction and having a strip shape, and the plurality of upper conductive layers are respectively arranged on the plurality of channel laminates And are electrically connected to the upper end of the intersecting trench film.

The method for manufacturing a NAND flash memory with a three-dimensional structure of the present invention includes: forming a lower conductive layer in or on a substrate; forming a stack of alternately stacked insulators and conductors on the lower conductive layer Step; the step of etching the stack to a depth that reaches the lower conductive layer to form a plurality of laminates extending in the first direction; forming a channel laminate on the entire surface of the substrate containing the plurality of laminates Step; the step of etching the channel laminate in a manner of being separately arranged along one of the side surfaces of each of the plurality of laminates; forming the channel laminate along the first direction perpendicular to the first direction on the channel laminate A step of a plurality of upper conductive layers extending in two directions; and a step of electrically connecting the plurality of upper conductive layers to the upper ends of the intersecting channel laminates. [Effects of the invention]

According to the present invention, separate channel stacks are arranged along one of the side surfaces of the stack, and the upper conductive layer is electrically connected to the crossing channel stacks. Therefore, the planar size of one memory cell can be reduced compared with the prior art. As a result, a high-integration NAND-type flash memory can be obtained.

The NAND flash memory with the three-dimensional structure of the present invention is used as a memory medium for various semiconductor devices (for example, microcontrollers, microprocessors, logics, etc. embedded in such flash memory). [Example]

Next, embodiments of the present invention will be described with reference to the drawings. It should be noted that the ratios of the drawings are exaggerated in order to facilitate the understanding of the invention, and do not necessarily represent the ratios of actual products.

The NAND flash memory 100 of this embodiment includes: a substrate 1, an insulating layer formed on the substrate 1, a lower conductive layer 3 formed on the insulating layer 2, and a memory laminated on the lower conductive layer 3 in a vertical direction The cell structure MC and the bit line 8 formed on the memory cell structure MC.

The substrate 1 is not particularly limited, and includes, for example, a silicon substrate. The silicon substrate can be any of true, n-type, and p-type. In addition, when a peripheral circuit (for example, a row selection drive circuit, or an integrated circuit such as a page buffer/readout circuit) is formed on the surface of the silicon substrate, the silicon substrate may include n-type or p-type. In the following description, a case where a silicon substrate is used as the substrate 1 is exemplified.

The insulating layer 2 formed on the silicon substrate 1 includes, for example, a silicon oxide film or a silicon nitride film. The lower conductive layer 3 includes, for example, n-type polysilicon, or a stack of metal materials and n-type polysilicon. The lower conductive layer 3 functions as a common source SL of the NAND string.

The memory cell structure MC includes a plurality of NAND strings formed on the lower conductive layer 3 in a vertical direction or a longitudinal direction. As is known, one NAND string includes a plurality of memory cells connected in series, a bit line side selection transistor connected to one end of the plurality of memory cells, and a source line connected to the other end. Select the transistor on the side. Furthermore, the NAND string may also include a dummy memory cell between the bit line side selection transistor and the memory cell or between the source line side selection transistor and the memory cell.

On the lower conductive layer 3, a gate laminate 110 in which insulators 4 and conductors 5 are alternately laminated is formed. As shown in FIG. 3(A) and FIG. 3(B), the gate laminate 110 is processed so as to have a band shape (rectangular shape) when viewed in the plan direction, and they extend in a stripe shape in the column direction. The uppermost layer of the gate stack 110 is an insulator 6 in contact with the bit line 8 via an insulator 7, and the lowermost layer is an insulator 4 in contact with the lower conductive layer 3. The insulator 4 and the insulator 6 include, for example, a silicon oxide film or a silicon nitride film. The conductor 5A directly below the insulator 6 constitutes the gate of the bit line side selection transistor, and the conductor 5B directly above the lowermost insulator 4 constitutes the gate of the source line side selection transistor. The plurality of conductors 5 between the conductor 5A and the conductor 5B respectively constitute the gate of the memory cell. Conductor 5, conductor 5A, and conductor 5B include, for example, n-type polysilicon. The conductor 5A constituting the gate of the bit line side selection transistor is connected to one or more selection gate lines SGD generated by a row selection drive circuit or the like not shown. The conductor 5B constituting the gate of the source line-side selection transistor is connected to one or more selection gate lines SGS generated by the same row selection drive circuit or the like, and the plurality of conductors 5 are connected to the corresponding word line WL .

The memory cell structure MC further includes a channel stack 9. As shown in FIG. 3(B), FIG. 4, and FIG. 6, the channel laminate 9 is formed separately in the column direction so as to be along one of the side surfaces of the gate laminate 110. One channel laminate 9 extends from the lower conductive layer 3 to the bit line 8 in the vertical direction. The upper end 9A of the channel laminate 9 is connected to the intersecting bit line 8, and the lower end 9B is connected to the lower conductive layer 3. In this example, the upper end portion 9A of the channel laminate 9 is formed so as to cover a part of the insulator 6 of the gate laminate 110. This is to increase the contact area between the channel laminate 9 and the bit line 8. However, this structure is an example, and it is not limited to this.

One NAND string includes one channel stack 9 extending in the vertical direction. The channel laminated body 9 includes a channel film constituting the channel and a gate insulator formed between the channel film and the gate 5. The channel film includes, for example, polysilicon. The gate insulator includes a charge storage layer that stores charges and a plurality of insulating layers sandwiching the charge storage layer. The gate insulator may be, for example, an ONO structure of silicon oxide film (O)/silicon nitride film (N)/silicon oxide film (O). It is also possible to use other semiconductor materials with a high dielectric constant instead of the silicon oxide film. In addition, the details of the channel laminate 9 will be described later.

As described above, on one side surface of the gate laminate 110, a plurality of channel laminates 9 are separately formed, and the insulator 7 is formed between these channel laminates 9. Furthermore, an insulator 7 is also formed on the other side surface of the gate laminate 110. In other words, the space between two adjacent gate stacks is filled with the insulator 7.

As shown in FIG. 3(A), above the memory cell structure MC, a plurality of bit lines 8 processed in a stripe shape (rectangular shape) when viewed in the plane direction extend in a stripe shape in the row direction . The plurality of bit lines 8 are respectively electrically connected to the upper end portion 9A of the channel laminate 9 corresponding to the position intersecting the gate laminate 110. The bit line 8 includes, for example, a metal material such as polysilicon or Al (aluminum).

Next, a method of manufacturing the NAND flash memory of this embodiment will be described with reference to FIGS. 7 to 18. First, as shown in FIG. 7, an insulating layer 2 is formed on the substrate 1, and a lower conductive layer 3 is formed on the insulating layer 2. Next, a stacked stack 110A including the insulator 4, the insulator 6, and the conductor 5 is formed on the lower conductive layer 3. The stack 110A is a precursor of the gate stack 110. The number of conductors 5 stacked in the stack 110A is determined according to the number of memory cells of the NAND string (for example, 32 or 64).

Next, a patterned etching mask (not shown) is formed on the insulator 6 by a photolithography step, and the insulator 4, the insulator 6, and the conductor 5 of the stack 110A are simultaneously anisotropically etched using the etching mask. The etching is performed until the lower conductive layer 3 is reached. The etching is performed, for example, by anisotropic etching or a combination of anisotropic etching and isotropic etching. The surface of the lower conductive layer 3 may be formed with a minute step or recess that is removed by etching, and the lower conductive layer 3 desirably has a film thickness large enough for such a step or recess. In this way, as shown in FIG. 8, a band-shaped gate stack 110 extending in the column direction is formed on the lower conductive layer 3. The pitch P between the gate stacks 110 is, for example, 180 nm. Fig. 9 is a cross-sectional view along the line A-A (the line A-A is the same position as the line A-A of Fig. 3(A)).

Next, as shown in FIG. 10, the channel laminate 9 is formed on the entire surface of the substrate so as to cover the gate laminate 110. The structure of the channel laminate 9 will be described with reference to FIGS. 10A to 10D. The enlarged cross-sectional views of FIGS. 10B to 10D correspond to the regions Q1 and Q2 shown in FIG. 10A, respectively.

As shown in FIG. 10B, the insulating layer 10, the charge storage layer 11, the insulating layer 12, and the polysilicon layer 13 are sequentially laminated on the entire surface of the substrate so as to cover the gate laminate 110. The method of forming these films is not particularly limited. For example, chemical vapor deposition (CVD) or sputtering can be used. The insulating layer 12 includes _{silicon dioxide (SiO 2} ), or _{a stack of silicon dioxide (SiO 2} ) and silicon nitride (SiN). The charge storage layer 11 includes a plurality of insulators, such as a stack of _{silicon nitride (SiN) or silicon dioxide (SiO 2) capable of storing charges.} The insulating layer 10 includes a number of insulators such as high dielectric constant (High K, Hi K) materials. The polysilicon layer 13 is not doped and therefore contains intrinsic silicon.

Next, as shown in FIG. 10C, the bottoms of the insulating layer 10, the charge storage layer 11, the insulating layer 12, and the polysilicon layer 13 are etched using an etching mask not shown here. The etching is performed, for example, by anisotropic etching or a combination of anisotropic etching and isotropic etching, and is performed until the surface of the lower conductive layer 3 is exposed. The surface of the lower conductive layer 3 may be formed with a minute step or recess that is removed by etching, and the lower conductive layer 3 desirably has a film thickness large enough for such a step or recess. Next, as shown in FIG. 10D, a polysilicon layer 14 is deposited on the entire surface of the substrate. The polysilicon layer 14 is also not doped, so it is intrinsic silicon. The two polysilicon layers 13 and 14 are electrically connected to each other, and the lower end of the polysilicon layer 14 is electrically connected to the lower conductive layer 3. In this way, the channel laminate 9 is formed so as to cover both side surfaces of the gate laminate 110. Fig. 11 is a cross-sectional view at the same position as the line C-C of Fig. 3(A).

Next, as shown in FIG. 12, the channel laminate 9 is processed into a plurality of stripes by etching to form a plurality of channel laminates 9 insulated from each other. As shown in FIG. 13, one channel laminate 9 extends in a direction orthogonal to the direction in which the gate insulator 110 extends, and a plurality of channel laminates 9 are arranged at regular intervals along the direction in which the gate insulator 110 extends.

Next, the channel laminated body 9 is further processed so as to be along one of the side surfaces of the gate insulator 110. The processing flow is shown in FIGS. 14 to 16. In addition, FIGS. 14 to 16 are cross-sectional views taken along the line A-A in FIG. 13. As shown in FIG. 14, a patterned etching mask 15 is formed so as to cover a part of the side and upper surface of the trench laminate 9 using a photolithography step.

Next, as shown in FIG. 15, etching is performed to partially remove the channel laminate 9 through the etching mask 15. The etching is performed, for example, by anisotropic etching or a combination of anisotropic etching and isotropic etching, and is performed until the surface of the lower conductive layer 3 is exposed. The surface of the lower conductive layer 3 may be formed with a minute step or recess that is removed by etching, and the lower conductive layer 3 desirably has a film thickness large enough for such a step or recess. Through the etching, the channel laminate 9 remains on one of the side surfaces of the gate insulator 110 and covers a part of the insulator 6 of the gate laminate 110. The reason for forming the channel laminate 9 so as to cover the insulator 6 is to increase the contact area with the bit line 8 or to increase the area for forming the contact hole for connection with the bit line. In addition, the bottom of the channel laminated body 9 is separated from the bottom of the channel laminated body 9 of the adjacent gate laminated body 110, and the lower conductive layer 3 is exposed here.

Next, as shown in FIG. 16, the etching mask 15 is removed. After the etching mask 15 is removed, the intermediate insulator 7 is deposited on the entire surface of the substrate so as to cover the channel laminated body 9 and the gate laminated body 110. As a result, the space between the adjacent gate stacks 110 is filled with the intermediate insulator 7.

Next, as shown in FIG. 17, the intermediate insulator 7 is planarized by chemical mechanical planarization (CMP) or the like. Through the flattening process, the top of the trench laminate 9 is exposed.

Next, as shown in FIG. 18, the bit line material is deposited on the entire surface of the substrate, and then the bit line 8 is patterned into a strip shape. The bit line 8 is electrically connected to the polysilicon layer 13 and the polysilicon layer 14 of the channel laminate 9 intersecting directly thereunder. Here, an example in which the bit line 8 is in direct contact with the upper end 9A of the channel laminate 9 is shown, but an interlayer insulating film may be formed after the planarization treatment, and contact holes may be formed in the interlayer insulating film to laminate the channels The upper end portion 9A of the body 9 is exposed, and the bit line 8 and the channel laminated body 9 are electrically connected through the contact hole.

In this way, a NAND string connected between the bit line 8 and the lower conductive layer (source) 3 is formed, and a memory cell array with a three-dimensional structure is obtained.

Next, the cell size of the NAND flash memory with the three-dimensional structure of this embodiment is compared with the cell size of existing products. FIG. 19(B) schematically shows a top view of the flash memory of this embodiment, and FIG. 19(A) schematically shows that there is no bit line 8 and the gap between the bit line 8 and the trench film 19 A top view of the bit line (BL) contact 16. In these figures, 18 is a gate insulating film (insulator 10, insulator 11, and insulator 12 shown in FIG. 10B), and 19 is a channel film (polysilicon 13, polysilicon 14 shown in FIG. 10D). In addition, the rectangular area R shown by the dashed line represents the planar size of one memory cell. When the pitch of the gate 5 is 180 nm and the pitch of the channel film 19 is 50 nm, the plane size R is 50×180 nm ² .

On the other hand, FIG. 20(B) schematically shows a plan view of the conventional memory cell structure shown in Non-Patent Document 1, and FIG. 20(A) schematically shows that there is no bit line 8 and bit line 8 is a plan view of the plug 17 for contact with the trench film 19. The rectangular area R1 represents the planar size of one memory cell, which is represented by the same scale as (A) of FIG. 20.

In the existing memory cell structure, two memory cells are formed on both sides of the gate 5, and the bit line 8 is connected to the two opposing memory cells in a shared manner. For example, the two memory cells MC1 and MC2 are connected to the bit line 8 via the plug 17. In order for the two memory cells to operate individually, the bit lines 8 connected to the two memory cells must be separated from each other. In contrast, in the memory cell structure of this embodiment, the memory cell is only arranged on one side of the gate 5. Therefore, the bit line 8 connected to the two memory cells can be shared. According to this difference, the pitch of the bit line 8 of this embodiment is about half of the pitch of the existing bit line 8, which can make the plane size R of the memory cell of this embodiment be larger than the plane size of the existing memory cell. R1 is small. Specifically, it can be seen that the planar size R1 of the conventional memory cell is about 160×100 nm ² , and the planar size R of the memory cell of this embodiment is smaller than the conventional one.

In the above-mentioned embodiment, an example is shown in which the lower conductive layer (source) 3 containing n-type polysilicon is formed on the substrate 1 with the insulating layer 2 interposed therebetween, but it is not limited to this. The lower conductive layer (source) may be It can be a highly doped n-type well region formed in a p-type silicon substrate.

The NAND-type flash memory includes a plurality of blocks, and each block includes a NAND string having a three-dimensional structure as described above. The memory cell can be either a single-level cell (SLC) type of 1 bit (binary data) of the memory, or a multi-bit type of the memory. In NAND flash memory, reading or programming is performed in units of pages, and erasing is performed in units of blocks. Since these operations are well-known, the description here is omitted.

The preferred embodiments of the present invention have been described in detail, but the present invention is not limited to specific embodiments, and various modifications and changes can be made within the scope of the gist of the invention described in the claims.

1: substrate 2: Insulation layer 3: Lower conductive layer (source) 4: Insulator 5: Conductor (gate) 5A, 5B: Conductor 6: Insulator 7: Insulator (intermediate insulator) 8: bit line 9: Trench stack 9A: Upper end 9B: Lower end 10, 12: Insulation layer (insulator) 11: Electric storage layer (insulator) 13, 14: Polysilicon layer (polysilicon) 15: Etching mask 16: Contact (BL contact) 17: Plug 18: Gate insulating film 19: Channel film 100: Flash memory (NAND flash memory) 110: Gate stack (gate insulator) 110A: Stack MC: Memory cell stack (memory cell structure) MC1, MC2: Memory unit P: Pitch Q1, Q2: area R, R1: Rectangular area (flat size) WL: Character line

FIG. 1 is a schematic perspective view of a conventional NAND flash memory with a three-dimensional structure. FIG. 2A is a top view of the flash memory shown in FIG. 1. FIG. FIG. 2B is a cross-sectional view of the flash memory shown in FIG. 1. FIG. FIG. 3(A) is a plan view of a NAND-type flash memory according to an embodiment of the present invention, and FIG. 3(B) is a plan view showing the positional relationship between the channel laminate and the gate laminate. FIG. 4 is a schematic cross-sectional view taken along the line A-A of the NAND flash memory according to the embodiment of the present invention. FIG. 5 is a schematic cross-sectional view taken along the line B-B of the NAND flash memory according to the embodiment of the present invention. FIG. 6 is a schematic cross-sectional view taken along the line C-C of the NAND flash memory according to the embodiment of the present invention. FIG. 7 is a schematic perspective view for explaining the manufacturing steps of the NAND flash memory according to the embodiment of the present invention. FIG. 8 is a schematic perspective view for explaining the manufacturing steps of the NAND flash memory according to the embodiment of the present invention. 9 is a schematic cross-sectional view in the direction of the A-A line for explaining the manufacturing steps of the NAND flash memory according to the embodiment of the present invention. 10 is a schematic cross-sectional view in the direction of the A-A line for explaining the manufacturing steps of the NAND flash memory according to the embodiment of the present invention. FIG. 10A is a schematic cross-sectional view for explaining the manufacturing steps of the trench stack shown in FIG. 10. FIG. 10B is a schematic cross-sectional view for explaining the manufacturing steps of the trench stack shown in FIG. 10. FIG. 10C is a schematic cross-sectional view for explaining the manufacturing steps of the trench stack shown in FIG. 10. FIG. 10D is a schematic cross-sectional view for explaining the manufacturing steps of the trench stack shown in FIG. 10. 11 is a schematic cross-sectional view in the direction of the C-C line for explaining the manufacturing steps of the NAND flash memory according to the embodiment of the present invention. 12 is a schematic cross-sectional view in the direction of the C-C line for explaining the manufacturing steps of the NAND flash memory according to the embodiment of the present invention. FIG. 13 is a schematic cross-sectional view in the direction of the C-C line for explaining the manufacturing steps of the NAND flash memory according to the embodiment of the present invention. FIG. 14 is a schematic cross-sectional view taken along the line A-A for explaining the manufacturing steps of the NAND flash memory according to the embodiment of the present invention. 15 is a schematic cross-sectional view taken along the line A-A for explaining the manufacturing steps of the NAND flash memory according to the embodiment of the present invention. 16 is a schematic cross-sectional view in the direction of the A-A line for explaining the manufacturing steps of the NAND flash memory according to the embodiment of the present invention. FIG. 17 is a schematic cross-sectional view taken along the line A-A for explaining the manufacturing steps of the NAND flash memory according to the embodiment of the present invention. 18 is a schematic cross-sectional view taken along the line A-A for explaining the manufacturing steps of the NAND flash memory according to the embodiment of the present invention. FIG. 19(A) is a top view of a NAND flash memory according to an embodiment of the present invention, and schematically shows a state without bit lines and contacts, and FIG. 19(B) schematically shows a state with bit lines The top view of the state of the contacts. FIG. 20(A) is a plan view of a conventional NAND flash memory, and schematically shows a state without bit lines and plugs, and FIG. 20(B) schematically shows a state with bit lines and plugs Top view.

1: substrate

100: Flash memory

110: Gate stack

2: Insulation layer

3: Lower conductive layer (source)

4, 6, 7: insulator

5, 5A, 5B: Conductor

8: bit line

9: Trench stack

9A: Upper end

9B: Lower end

MC: Memory cell structure

A-A: line

Claims (12)

A NAND flash memory with a three-dimensional structure, comprising: a substrate; a lower conductive layer formed in or on the substrate; a plurality of laminated bodies extending in a first direction on the lower conductive layer, And the plurality of laminates respectively include a laminate of an insulator and a conductor laminated in a vertical direction from the substrate; a plurality of channel laminates are separately arranged along one of the side surfaces of the plurality of laminates, and The plurality of channel laminates respectively include an insulating layer including a charge storage layer and a channel film, the insulating layer and the channel film extend from the substrate in a vertical direction, and the lower end of the channel film is electrically connected On the lower conductive layer, the upper end of the channel laminate partially covers the laminate; and a plurality of upper conductive layers extend in a second direction orthogonal to the first direction, and the plurality The upper conductive layers are respectively arranged on the plurality of channel laminates, and are electrically connected to the upper ends of the crossing channel films. The flash memory according to claim 1, wherein the plurality of channel stacked bodies are arranged at a first pitch along the first direction, and one NAND string includes the one channel stacked body. The flash memory according to claim 2, wherein the plurality of stacked bodies are arranged at a second pitch along the second direction, and the planar size of one memory cell is determined by the first pitch and the second pitch Regulation. The flash memory according to claim 1, wherein A laminated body includes one of the side faces and the other side face opposite to the one side face, and one side face of the first laminated body adjacent to the second direction and the other side face of the second laminated body The channel laminate and the insulator are arranged in between. The flash memory according to any one of claims 1 to 4, wherein the upper conductive layer is a bit line, the lower conductive layer is a source line, and the conductive layer of the laminate is formed on the uppermost layer. The body is the gate of the selection transistor on the bit line side, and the conductor formed in the lowermost layer is the gate of the selection transistor on the source line side. The flash memory according to claim 5, wherein the conductor between the conductor in the uppermost layer and the conductor in the lowermost layer of the laminated body is a gate electrode of a transistor of a memory cell, and Connect to the corresponding character line. A method for manufacturing a flash memory is a method for manufacturing a NAND flash memory with a three-dimensional structure. The method includes: forming a lower conductive layer in a substrate or on the substrate; The step of ground-laminating a stack of an insulator and a conductor; the step of etching the stack to a depth that reaches the lower conductive layer to form a plurality of laminates extending in the first direction; when the plurality of laminates are included A step of forming a channel laminate on the entire surface of the substrate of the body; The step of etching the trench laminate so as to be separately arranged along one of the side surfaces of each of the plurality of laminates, wherein the upper end of the trench laminate partially covers the laminate; The step of forming a plurality of upper conductive layers extending in a second direction orthogonal to the first direction on the channel laminate; Steps to connect. The method for manufacturing a flash memory according to claim 7, wherein the step of forming the channel laminate includes: a step of forming a first insulating layer; and a step of forming a charge storage layer on the first insulating layer; A step of forming a second insulating layer on the charge storage layer; and a step of forming a channel thin film on the second insulating layer. The method of manufacturing a flash memory according to claim 7, wherein the connecting step includes a step of forming a contact hole in an insulating film formed on the trench laminate, and the upper conductive layer passes through the contact hole. It is electrically connected to the upper end of the trench laminate. The method for manufacturing a flash memory according to claim 7, wherein the manufacturing method further includes: after the step of etching the channel laminate, to cover the plurality of channel laminates and the A step of forming an insulating film as a plurality of laminated bodies; and a step of planarizing the insulating film to expose the channel laminated body. The method of manufacturing a flash memory according to claim 7, wherein The film thickness of the lower conductive layer is sufficiently large compared to a step or a recess formed on the surface of the lower conductive layer when the stack is etched. The method of manufacturing a flash memory according to claim 7, wherein the film thickness of the lower conductive layer and the step or recess formed on the surface of the lower conductive layer when the channel laminate is etched Compared to large enough.

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