TWI740650B - Dual mode buck converter - Google Patents

Abstract

A dual mode buck converter includes a buck converter circuit, a ripple modulation fixed off time (FOT) control circuit, a pulse width modulation module, a multiplexer, a zero current detection circuit and a control circuit. The dual-mode buck converter adopts ripple modulation FOT control. Not only switching frequency can be adjusted under different output loads to make the system reach the best efficiency point, a variable frequency mechanism with input voltage, a peak voltage switching mechanism, and pulse width modulation control are also provided to improve conversion efficiency, such that the system switching frequency decreases as the input voltage increases, thereby greatly reducing the switching loss.

Description

Dual mode buck converter

The invention relates to a dual-mode buck converter, in particular to a dual-mode buck converter that uses a peak voltage switching mechanism and a frequency conversion mechanism with output load respectively under light load and heavy load.

In order to meet the requirements for efficiency and improve the transient response of the load, the existing switching power converter adopts ripple modulation control, which mainly stabilizes the circuit system by the amount of output voltage ripple, so as long as the output capacitor is large enough Equivalent Series Resistance (ESR), the overall circuit does not need a compensator to stabilize the system.

Among them, when the load current is a heavy load, the conduction loss of the switch needs to be considered, and in the case of a light load, the switching loss of the switch needs to be considered. However, the general switching mode is hard switching (Hard Switching), but this method will cause a large switching loss due to the large cross voltage during switching.

The technical problem to be solved by the present invention is to provide a dual-mode buck converter that uses a peak voltage switching mechanism and a variable frequency mechanism with output load under light load and heavy load, respectively, in view of the deficiencies of the prior art.

In order to solve the above technical problems, one of the technical solutions adopted by the present invention is A dual-mode buck converter is provided, which includes a buck converter circuit, a ripple modulation cut-off time control circuit, a pulse width modulation module, a multiplexer, a zero current detection circuit, and a control circuit. The buck converter circuit includes a first switch, a second switch, an output inductor, an output capacitor, a load resistance, and a feedback circuit. The first switch is connected between an input voltage source and a switching node, the second switch is connected between the switching node and the ground terminal, the output inductor is connected between the switching node and the output terminal, and the output capacitor is connected to the output Between the output terminal and the ground terminal, a load resistance is connected between the output terminal and the ground terminal, and a feedback circuit is connected between the output terminal and the ground terminal, and is configured to generate a feedback voltage according to an output voltage of the output terminal. The ripple modulation cut-off time control circuit includes a first comparator, a current detection circuit, a peak voltage switching circuit, a fixed cut-off time circuit, and a load-dependent frequency conversion circuit. The first comparator is configured to compare the feedback voltage with the first reference voltage, and correspondingly output a first comparison signal. The current detection circuit is configured to generate a current detection signal related to a load current according to an input voltage of the input voltage source and a switching voltage of the switching node. The peak voltage switching circuit receives the switching voltage, a second reference voltage, and a zero current detection signal, and is configured to generate a peak according to the relative relationship between the switching voltage and the second reference voltage and the zero current detection signal A switching signal, wherein the zero current detection signal is used to indicate whether the load current passes through a current zero point, and the second reference voltage corresponds to a resonance peak value of the switching voltage. The fixed cut-off time circuit is configured to: detect an input voltage range of the input voltage, and correspondingly generate a charge and discharge voltage to charge and discharge one of the cut-off capacitors, and generate a cut-off voltage at a cut-off node; The cut-off voltage, the peak switching signal and the first comparison signal perform a logic processing procedure to generate a working signal, wherein the working signal has a switching frequency. The frequency conversion circuit with load includes a sample-and-hold circuit, a current subtraction circuit, and a logic judgment circuit. The sample-and-hold circuit is configured to sample and hold the current detection signal according to the working signal to correspondingly generate a sample-and-hold voltage. The current subtraction circuit is configured to capture a third reference voltage and the sample-and-hold voltage to obtain a reference current and a reference current in response to receiving the load-dependent frequency conversion instruction signal indicating to enable a load-dependent frequency conversion mechanism. Sample the hold current, and subtract the reference current from the sample hold current to generate a subtraction current. The logic judgment circuit is configured to judge whether the load current is within a predetermined current range according to the sample and hold voltage, so as to determine whether to charge and discharge the cut-off capacitor with the subtraction current. The pulse width modulation module is configured to output a pulse width modulation signal when the feedback voltage is lower than a pulse width modulation reference voltage. The multiplexer is configured to receive the working signal and the pulse width modulation signal, and selectively output the working signal or the pulse width modulation signal according to the load current. The zero current detection circuit is configured to receive the working signal or the pulse width modulation signal output by the multiplexer, and detect a current zero point of the load current to generate the zero point current detection signal. The control circuit is configured to receive the zero current detection output signal to control the first switch and the second switch to turn on or off, respectively.

One of the beneficial effects of the present invention is that the dual-mode buck converter provided by the present invention adopts ripple modulation to set the cut-off time control. In addition to designing the switching frequency under different output loads to make the system reach the best efficiency point, In addition, the frequency conversion mechanism with the input voltage, the peak voltage switching mechanism and the pulse width modulation control are added to improve the conversion efficiency, so that the system switching frequency decreases with the increase of the input voltage, thereby greatly reducing the switching loss.

In addition, the dual-mode buck converter provided by the present invention uses a peak voltage switching mechanism at light load to allow the circuit to achieve soft switching control to reduce switching loss, and at heavy load, a variable frequency mechanism with output load is used to maintain the circuit at a higher level. Conversion efficiency.

In order to further understand the features and technical content of the present invention, please refer to the following detailed description and drawings about the present invention. However, the provided drawings are only for reference and description, and are not used to limit the present invention.

1: Dual mode buck converter

10: Buck converter circuit

11: Ripple modulation cut-off time control circuit

12: Pulse width modulation module

13: Multiplexer

14: Zero current detection circuit

15: Control circuit

100: feedback circuit

110: Current detection circuit

112: Peak voltage switching circuit

114: fixed cut-off time circuit

116: Variable frequency circuit with load

AND1, AND2: and gate

CHC: charge and discharge circuit

CMP1: The first comparator

CMP2: second comparator

CMP3: third comparator

CMP4: The fourth comparator

CMP5: Fifth comparator

CMP6: sixth comparator

CMP7: seventh comparator

Co: output capacitance

Coff: cut-off capacitance

COM: compensator

CP1: The first comparison signal

CP2: The second comparison signal

CP3: The third comparison signal

CP5: Fifth comparison signal

CP6: The sixth comparison signal

CP7: Seventh comparison signal

CS: current subtraction circuit

Csh: Sample and hold capacitor

Del: Delay circuit

DUTY: work signal

EAMP: Error amplifier

Hvlp: high voltage loop

Ibias: Bias current source

IL: Load current

Ioff: cut-off current

Iref: reference current

Ish: Sample hold current

Isub: subtraction current

L: output inductance

L1: The first logic signal

L2: The second logic signal

Log: logic judgment circuit

Lvlp: low voltage loop

M1, M2,..., M9, m1, m2,..., m13, M11, M12, M13: switch

Mn: second switch

Mp: First switch

MR1: The first current mirror circuit

MR2: Second current mirror

MR3: Third current mirror

MR4: Fourth current mirror

Msh: Sample Hold Switch

N2, N3: Node

Nd: voltage divider node

No: output terminal

Noff: cutoff node

OPA: Power amplifier

OPA1: the first amplifier

OPA2: second amplifier

OPA3: third amplifier

OR1: or gate

OTA: operational transconductance amplifier

PS: Peak switching signal

PWM: Pulse width modulation signal

Q: output

:反相輸出端

: Inverted output

R: Reset terminal

RAMP: Triangular wave generator

Rf1: The first voltage divider resistor

Rf2: second voltage divider resistor

RL: load resistance

Roff: cut-off resistance

Rsen: Detection resistance

S: Setting terminal

Sdel: Delayed signal

Sea: Error amplification signal

Sen: Enable signal

SH: sample and hold circuit

SR1, SR2: SR latch

Sramp: triangle wave signal

SW: Switch node

Va, Vb: voltage

Vc: Center voltage

VDD, Vdd: common voltage source

Vfb: feedback voltage

VH: Upper limit reference voltage

Vh: high signal

VI1: The first voltage to current circuit

VI2: The second voltage to current circuit

Vin: input voltage

VinH: High voltage control signal

VL: Lower limit reference voltage

Vl: low signal

Vo: output voltage

Vp: Peak voltage

Vref_pwm: Pulse width modulation reference voltage

Vref1: the first reference voltage

Vref2: second reference voltage

Vref3: third reference voltage

Vsen: Current detection signal

Vsw: switching voltage

ZCDout: Zero current detection signal

FIG. 1 is a circuit layout diagram of a buck converter according to an embodiment of the present invention.

FIG. 2 is a circuit layout diagram of a current detection circuit according to an embodiment of the invention.

FIG. 3 is a circuit layout diagram of a peak voltage switching circuit according to an embodiment of the present invention.

FIG. 4 is a simulation waveform diagram of the peak voltage switching mechanism of the embodiment of the present invention.

FIG. 5 is a circuit layout diagram of a fixed cut-off time circuit according to an embodiment of the present invention.

Fig. 6 is a simulation waveform diagram of a fixed cut-off time circuit according to an embodiment of the present invention.

FIG. 7 is a circuit layout diagram of a sample and hold circuit according to an embodiment of the present invention.

FIG. 8 is a circuit layout diagram of a current subtraction circuit and a logic judgment circuit according to an embodiment of the present invention.

The following is a specific embodiment to illustrate the implementation of the "dual-mode buck converter" disclosed in the present invention. Those skilled in the art can understand the advantages and effects of the present invention from the content disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and various details in this specification can also be based on different viewpoints and applications, and various modifications and changes can be made without departing from the concept of the present invention. In addition, the drawings of the present invention are merely schematic illustrations, and are not drawn according to actual dimensions, and are stated in advance. The following embodiments will further describe the related technical content of the present invention in detail, but the disclosed content is not intended to limit the protection scope of the present invention. In addition, the term "or" used in this document may include any one or a combination of more of the associated listed items depending on the actual situation.

FIG. 1 is a circuit layout diagram of a buck converter according to an embodiment of the present invention. Referring to FIG. 1, an embodiment of the present invention provides a dual-mode buck converter 1, which includes a buck converter circuit 10, a ripple modulation cut-off time control circuit 11, a pulse width modulation module 12, and a multiplexer 13. Zero current detection circuit 14 and control circuit 15.

The buck converter circuit 10 includes a first switch Mp, a second switch Mn, and an output inductor L, output capacitor Co, load resistance RL, and feedback circuit 100. The first switch Mp is connected between the input voltage Vin provided by the input voltage source and the switching node SW, the second switch Mn is connected between the switching node SW and the ground terminal, and the output inductor L is connected between the switching node SW and the output terminal No. , The output capacitor Co is connected between the output terminal No and the ground terminal, the load resistance RL is connected between the output terminal No and the ground terminal, and the feedback circuit 100 is connected between the output terminal No and the ground terminal, and is configured according to the output terminal The output voltage Vo of No generates the feedback voltage Vfb. Wherein, the input voltage source, the first switch Mp, the second switch Mn, the output inductor L, the output capacitor Co, the load RL, and the feedback circuit 100 form a step-down conversion circuit, and the first switch Mp and the second switch Mn can be respectively Power-level power switches of different conductivity types.

The feedback circuit 100 includes a first voltage dividing resistor Rf1 and a second voltage dividing resistor Rf2. The first voltage dividing resistor Rf1 is connected between the output terminal No and the voltage dividing node Nd, and the second voltage dividing resistor Rf2 is connected to the voltage dividing node Nd. Between the node Nd and the ground terminal, and the output voltage Vo generates a feedback voltage Vfb on the voltage dividing node Nd.

Furthermore, the ripple modulation cut-off time control circuit 11 includes a first comparator CMP1, a current detection circuit 110, a peak voltage switching circuit 112, a fixed cut-off time circuit 114, and a load-dependent frequency conversion circuit 116.

The control method of the step-down converter 1 will be briefly described below. In this embodiment, the dual-mode buck converter 1 is a buck converter with a dual-mode control mechanism and a variable frequency control mechanism with load, and is mainly divided into two control modes. The control mode is selected by the multiplexer 13 . When the data selection terminal of the multiplexer 13 is at a high level, the control mode is fixed off time (FOT), and the circuit action is to compare the feedback voltage Vfb with the first reference voltage Vref1 and send it to the ripple Modulation cut-off time control circuit 11. Whenever the feedback voltage Vfb is greater than the first reference voltage Vref1, the first comparator CMP1 will output a high level. This signal is sent to the input terminal of the AND gate in the ripple modulation cut-off time control circuit 11 and the gate The other input is the input delay signal. As long as the two signals are at high level, the gate will output the high level to the SR latch, so that the fixed time cut-off signal will be changed to the low level, and the power will be turned on at this time. In the off state, the first switch Mp is turned on, and the second switch Mn is turned off. The turn-off time of the second switch Mn depends on the turn-off time of the ripple modulation turn-off time control circuit 11. As long as the fixed turn-off time has elapsed, the first switch Mp is turned off and the second switch Mn is turned on. This state will continue to be maintained. Continue until the output voltage Vo is greater than the first reference voltage Vref1 again.

On the other hand, when the data selection terminal of the multiplexer 13 is at a low level, the control mode is a pulse width modulation (PWM) mode. The circuit action is that after the output voltage Vo passes through the compensator COMP, it performs error amplification with the pulse width modulation reference voltage Vref_pwm. The error amplification signal Sea is compared with the sawtooth wave output by the triangle wave generator RAMP, and then the comparison signal is output as a duty cycle signal, so that the first switch Mp and the second switch Mn are turned on or off. The above-mentioned PWM control mode is used to assist the peak voltage switching mechanism, so that the excessively high switching frequency at light load can be fixed. The operation of each circuit will be further described below.

The first comparator CMP1 is configured to compare the feedback voltage Vfb with the first reference voltage Vref1, and correspondingly output the first comparison signal CP1.

The current detection circuit 110 is configured to generate a current detection signal Vsen related to the load current IL according to the input voltage Vin of the input voltage source and the switching voltage Vsw of the switching node SW. The structure diagram of the upper arm switch current detection circuit 110 can be shown in FIG. 2, and FIG. 2 is a circuit layout diagram of the current detection circuit according to an embodiment of the present invention. The current detection circuit 110 includes switches M1, M2, M3, M4, M5, M6M7, M8, M9, a power amplifier OPA, a bias current source Ibias, and a common voltage source VDD. The main function of the circuit is to detect the switching current of the upper arm power level switch (that is, the first switch Mp). Among them, the switches M1, M2, and M3 are used as switches. The function of the switch M1 is similar to imitating the first switch Mp, so the switch M1 The size is reduced by the magnification of the first switch MP. The switches M2 and M3 have control terminals D and Db respectively, which are used as switches to allow the voltage Va to have the level of the switching voltage Vsw and the input voltage Vin. Negative feedback is performed through the power amplifier OPA to make the voltage Va approximate to the voltage Vb, and finally switch The drain of M1 has the same voltage change as the drain of the first switch Mp.

The power amplifier OPA has a positive feedback loop and a negative feedback loop, and the proportion of the negative feedback loop is greater than the proportion of the positive feedback loop. When the voltage Vb is greater than the voltage Va, the output terminal of the power amplifier OPA will pass through the negative feedback network formed by the switches M4 and M8 to form a negative feedback. When the voltage Va is greater than the voltage Vb, the output terminal of the power amplifier OPA will pass through the positive feedback network formed by the switch M5 to form a positive feedback. Among them, the gain of the switch M8 will be greater than that of M5, so the whole is negative feedback. Circuit. The drain of the switch M8 will eventually have a signal similar to the switching current, and the current detection signal Vsen related to the switching current can be obtained through the detection resistor Rsen.

The peak voltage switching circuit 112 receives the switching voltage Vsw, the second reference voltage Vref2 and the zero current detection signal ZCDout, and is configured to generate peak switching according to the relative relationship between the switching voltage Vsw and the second reference voltage Vref2 and the zero current detection signal ZCDout Signal PS.

Further reference may be made to FIG. 3, which is a peak voltage switching circuit according to an embodiment of the present invention. As shown in the figure, the peak voltage switching circuit 112 includes a first amplifier OPA1, a second comparator CMP2, and a gate AND1. The positive input terminal of the first amplifier OPA1 receives the switching voltage Vsw, and its negative input terminal is connected to its output terminal to form a voltage follower, and outputs the switching voltage Vsw at the output terminal. The second comparator CMP2 is configured to receive and compare the switching voltage Vsw and the second reference voltage Vref2 to output a second comparison signal CP2. The AND gate AND1 is configured to receive the zero current detection signal ZCDout and the second comparison signal CP2, and output the peak switching signal PS.

In detail, the main function of the peak voltage switching mechanism is to reduce the voltage across the first switch Mp and reduce the switching loss. If the value of the cross pressure is reduced, the switching loss will be greatly reduced by the square of the cross pressure. When the switching voltage Vsw resonates to the maximum peak value, the switching is performed, and the switching loss will be lower than the general hard switching. When using the peak voltage switching mechanism, the circuit will detect the highest peak of the switching voltage Vsw resonance and perform switching, forcibly ending the original working cycle of the overall circuit. At this time, the inductor current will start to be excited again due to the new duty cycle, and the current waveform will change from the original discontinuous conduction mode (DCM) to the boundary conduction mode (BCM).

In the architecture of FIG. 3, the zero current detection signal ZCDout comes from the zero current detection circuit 14 and is used to indicate whether the load current IL passes through the current zero point. As long as the switching voltage Vsw is higher than the second reference voltage Vref2 and the zero current detection output signal ZCDout is at a high level, the peak switching signal PS will output a high level to the fixed cut-off time circuit 114 to force the fixed-time cut-off signal DUTY Reset to low level. When the peak voltage switching mechanism is turned on, the switching voltage Vsw will stop resonating. In addition, the second reference voltage Vref2 can be designed to correspond to the highest resonance peak value that the switching voltage Vsw can generate.

Further refer to FIG. 4, which is a simulation waveform diagram of the peak voltage switching mechanism of the embodiment of the present invention. As shown in the figure, the output inductance L is 1uH and the total parasitic capacitance is 400pF through the circuit simulation software, and the output voltage Vo is 1V. When the load current IL is almost zero, after the peak voltage switching mechanism is activated by the peak switching signal PS, the switching voltage Vsw will switch at the first resonance peak, as shown in Figure 4, where the switching frequency can be known from the switching voltage Vsw About 3.16MHz.

On the other hand, the fixed off-time circuit 114 is mainly used to detect the input voltage range of the input voltage Vo, and correspondingly generate charging and discharging voltages to charge and discharge the off capacitor Coff therein, and generate the off voltage Voff on the off node Noff. In addition, the fixed cut-off time circuit 114 can further generate a working signal DUTY having a switching frequency by performing a logic processing procedure on the cut-off voltage Voff, the peak switching signal PS, and the first comparison signal CP1.

In detail, regardless of operating in continuous conduction mode (CCM) or discontinuous conduction mode (Discontinuous Conduction Mode, DCM), the overall system frequency will rise as the input voltage rises. As the frequency increases, the switching loss of the overall circuit will increase, so two different circuits are designed to optimize this situation.

Please refer to FIG. 5, which is a circuit layout diagram of a fixed cut-off time circuit according to an embodiment of the present invention. As shown in the figure, the fixed off time circuit 114 includes a second amplifier OPA2, a third comparator CMP3, a charging and discharging circuit CHC, a first current mirror circuit MR1, an off capacitor Coff, and a fourth comparator. CMP4, OR gate OR1, SR latch SR1, delay circuit Del, gate AND2, and switch m13.

The second amplifier OPA2 performs negative feedback on the input voltage Vin to generate an off current Ioff on the off resistor Roff through the switch m1. The third comparator CMP3 is used to determine whether the input voltage Vin is higher than the center voltage Vc, and correspondingly output a third comparison signal CP3.

The charging and discharging circuit CHC essentially includes a switch m11 and a switch m12, which are respectively controlled by the high-voltage control signal VinH and the low-voltage control signal VinL to be turned on or off. For example, in response to the third comparison signal CP3 indicating that the input voltage Vin is higher than the center voltage Vc, the third comparison signal CP3 can be used as the high voltage control signal VinH to control the switch m11 to turn on, and as the low voltage control signal VinL to control the switch m12 to turn off. The high-voltage loop Hvlp is realized by a switch m11, which is connected between the high-voltage input terminal and the cut-off node Noff, and the low-voltage loop Lvlp is realized by a switch m12, which is connected between the low-voltage input terminal and the cut-off node Noff. As previously described for the third comparison signal CP3, in response to the input voltage Vin being higher than the center voltage Vc, the high voltage loop Hvlp is turned on, and in response to the input voltage Vin being less than the center voltage Vc, the low voltage loop Lvlp is turned on. Among them, the low-voltage control signal VinL and the high-voltage control signal VinH are judgment signals for indicating the range of the input voltage Vin. The third comparator CMP3 is used to compare the input voltage Vin with the central voltage Vc (for example, 4V), and then select the path to perform the cut-off capacitor Coff Charge to reach the designed switching frequency point.

The first current mirror circuit MR1, connected to the high-voltage input terminal and the low-voltage input terminal, is configured to mirror the off current Ioff to the low-voltage circuit Lvlp of the charge and discharge circuit CHC, and to calculate the difference between the constant current Icnst and the off current Ioff The value current is mirrored to the high voltage loop Hvlp.

Taking FIG. 5 as an example, the first current mirror circuit MR1 may include a current mirror composed of switches m2 and m10 to mirror the off current Ioff to the switch m10, and then input the low voltage loop Lvlp. On the other hand, the first current mirror circuit MR1 may also include a current mirror formed by switches m2 and m3, a current mirror formed by switches m4 and m5, a current mirror formed by switches m6 and m7, and a current mirror formed by switches m8 and m9. The current mirror. The cut-off current Ioff is mirrored to the switch m3 through the switch m2, and flows downward through the switch m4, It is mirrored to the switch m5 and the constant current Icnst is subtracted to generate a difference current, and then gradually mirrored to the high voltage loop Hvlp through the switches m6, m7, m8, and m9.

The off capacitor Coff is connected between the off node Noff and the ground terminal, and is charged and discharged by the mirrored off current Ioff or the difference current. The fourth comparator CMP4 further compares the cut-off voltage Voff of the cut-off node Noff with the peak voltage Vp, and correspondingly generates a fourth comparison signal CP4.

The fixed cut-off time circuit 114 also includes a logic circuit for executing the aforementioned logic processing program, including an OR gate OR1, an SR latch SR1, a delay circuit Del, and a gate AND2. The OR gate OR1 performs an OR operation on the peak switching signal PS and the fourth comparison signal CP4 to output the first logic signal L1.

，其中，重置端R經配置以接收第一邏輯訊號L1。延遲電路Del連接於輸出端Q，經配置以將輸出端Q的輸出訊號進行延遲以產生延遲訊號Sdel。及閘AND2經配置以對第一比較訊號CP1及延遲訊號Sdel進行及(AND)運算，以輸出第二邏輯訊號L2至設定端S。其中，SR拴鎖器SR1經配置以依據第一邏輯訊號L1及第二邏輯訊號L2於反相輸出端

輸出工作訊號DUTY。開關m13相對於截止節點Noff及接地端與截止電容Coff並聯，且經配置以由工作訊號DUTY控制而導通或關斷。 The SR latch SR1 has a reset terminal R, a setting terminal S, an output terminal Q and an inverted output terminal

, Wherein the reset terminal R is configured to receive the first logic signal L1. The delay circuit Del is connected to the output terminal Q and is configured to delay the output signal of the output terminal Q to generate a delay signal Sdel. The AND gate AND2 is configured to perform an AND operation on the first comparison signal CP1 and the delay signal Sdel to output the second logic signal L2 to the setting terminal S. Wherein, the SR latch SR1 is configured to be at the inverting output terminal according to the first logic signal L1 and the second logic signal L2

Output work signal DUTY. The switch m13 is connected in parallel with the cut-off capacitor Coff with respect to the cut-off node Noff and the ground terminal, and is configured to be turned on or off under the control of the working signal DUTY.

When the feedback voltage Vfb is greater than the first reference voltage Vref1, the first comparison signal CP1 will be at a high level. As long as the first comparison signal CP1 and the delay signal Sdel are both at a high level, the gate AND2 will output a high level. To the setting terminal S of the SR latch SR1, the working signal DUTY is changed to a low level. At this time, the voltage peak of the cut-off voltage Voff reaches the peak voltage Vp. After a fixed cut-off time, the working signal DUTY will show a high level, and the cut-off capacitor Coff will be discharged through the switch m13, and the cut-off voltage Voff is similar to a sawtooth wave. The peak switching signal PS is the output terminal of the peak voltage switching circuit 112. Generally, the operation will not be high in the continuous conduction mode, and the delay circuit Del is for Keep the minimum on-time limit. For the circuit simulation result, refer to FIG. 6, which is a simulation waveform diagram of the fixed cut-off time circuit according to the embodiment of the present invention. As shown in the figure, as the input voltage Vin rises to the center voltage Vc (4V), the switching frequency will increase with the increase of the input voltage Vin, and when the input voltage Vin is greater than the center voltage Vc, the switching frequency will increase with the input voltage Vin. And it reduces, so the switching loss of the whole circuit can be reduced.

On the other hand, in the architecture of the step-down converter circuit 10 of the present invention, under the condition that the input voltage Vin, the output voltage Vo, and the non-ideal components and other parameters are fixed, it can be seen that the cut-off time of the ripple modulation is controlled at the load current IL. When it changes, the switching frequency will change accordingly. If the load current IL is larger, the switching frequency will be lower, on the contrary, the load current IL will be lower, and the switching frequency will be higher. In addition, the switching frequency of the cut-off time design for ripple modulation is inversely proportional to the load current IL. In order to achieve better performance under heavy loads, the present invention uses a load-dependent frequency conversion circuit 116 to reduce the switching frequency and change the original switching frequency. The slope of the curve. As shown in FIG. 1, the load-dependent frequency conversion circuit 116 includes a sample-and-hold circuit SH, a current subtraction circuit CS, and a logic judgment circuit Log.

Among them, the sample-and-hold circuit SH can sample and hold the current detection signal Vsen according to the working signal DUTY to correspondingly generate the sample-and-hold voltage Vsh.

FIG. 7 is a circuit layout diagram of a sample and hold circuit according to an embodiment of the present invention. Please further refer to FIG. 7, the sample-and-hold circuit SH includes a sample-and-hold switch Msh, a sample-and-hold capacitor Csh, and an operational transconductance amplifier OTA. The first terminal of the sample-and-hold switch Msh receives the current detection signal Vsen, the second terminal thereof is connected to the ground terminal through the sample-and-hold capacitor Csh, and the control terminal thereof receives the working signal DUTY. Among them, the sample and hold capacitor Csh is charged by the current detection signal Vsen. The positive input terminal of the operational transconductance amplifier OTA is connected to the second terminal of the sample-and-hold switch Msh, and the negative input terminal is connected to the output terminal to output the sample-and-hold voltage Vsh at its output terminal.

On the other hand, the current subtraction circuit CS can extract the third reference voltage Vref3 and the sample-and-hold voltage Vsh respectively to obtain the reference current Iref and the sample-and-hold current Ish, and hold the sample and hold. The current Ish subtracts the reference current Iref to generate the subtracted current Isub.

Further reference may be made to FIG. 8, which is a circuit layout diagram of the current subtraction circuit and the logic judgment circuit according to the embodiment of the present invention. As shown in FIG. 8, the current subtraction circuit CS includes a first voltage-to-current circuit VI1, a second current mirror MR2, a second voltage-to-current circuit VI2, and a third current mirror MR3 and a fourth current circuit connected to a common voltage source Vdd. Mirror MR4.

The first voltage-to-current circuit VI1 includes a third amplifier OPA3 and a switch M11. The positive input terminal of the third amplifier OPA3 receives the third reference voltage Vref3, the control terminal of the switch M11 is connected to the output terminal of the third amplifier OPA3, and the first terminal of the switch M11 is connected to the ground terminal through the first drop resistor Rred1. The OPA3 is configured to generate a reference current Iref on the switch M11 according to the third reference voltage Vref3.

The second current mirror MR2 can be composed of two switches. The first end of the second current mirror MR2 (ie, the node N1) is connected to the second end (ie, the node N2) of the switch M11, and is configured to mirror the reference The current Iref is also output at the second end of the second current mirror MR2.

On the other hand, the second voltage-to-current circuit VI2 includes a fourth amplifier OPA4 and a switch M12. The positive input terminal of the fourth amplifier OPA4 receives the sample-and-hold voltage Vsh, the control terminal of the switch M12 is connected to the output terminal of the fourth amplifier OPA4, the first terminal of the switch M12 is connected to the ground terminal through the second drop resistor Rred2, and the first terminal of the switch M12 The two ends are connected to the second end of the second current mirror MR2. Wherein, the fourth amplifier OPA4 is configured to generate a sample-and-hold current Ish on the switch M12 according to the sample-and-hold voltage Vsh.

In the above structure, the third reference voltage Vref3 is obtained by dividing the negative feedback by the resistance value of the first falling resistor Rred1 to obtain the reference current Iref, and the sample and holding voltage Vsh is obtained by dividing the negative feedback by the resistance value of the second falling resistor Rred2 Sample hold current Ish. The reference current Iref converges with the sample-and-hold current Ish through the second current mirror MR2, and due to the current confluence, the subtracted current Isub can be obtained at the node N2 (that is, the second end of the second current mirror MR2) as the sample-and-hold current Ish minus the reference power Stream Iref.

The third current mirror MR3 is also composed of two switches, the first end of which is connected to the second end of the second current mirror MR2, and the subtraction current Isub flows from the second end of the second current mirror MR2 to the third current mirror MR3 , The third current mirror MR3 mirrors the subtraction current Isub and outputs it to the second end of the third current mirror MR3.

The fourth current mirror MR4 is composed of four switches. The first end of the fourth current mirror MR4 is connected to the second end of the third current mirror MR3, and the second end (ie, the node N3) is connected to the logic judgment circuit Log.

The logic judgment circuit Log can be used to judge whether the load current IL is within a predetermined current range according to the sample-and-hold voltage Vsh, so as to determine whether to charge and discharge the cut-off capacitor Coff with the subtraction current Isub.

As shown in FIG. 8, the logic judgment circuit Log includes a fifth comparator CMP5, a sixth comparator CMP6, a switch M13, and an SR latch SR2. The fifth comparator CMP5 is used to compare the sample-and-hold voltage Vsh and the lower limit reference voltage VL, and correspondingly output a fifth comparison signal CP5. The sixth comparator CMP6 is used to compare the sample-and-hold voltage Vsh and the upper limit reference voltage VH, and correspondingly output a sixth comparison signal CP6.

The switch M13 is connected between the cut-off capacitor Coff and the second end (ie node N3) of the fourth current mirror MR4. SR latch SR2, its reset terminal R receives the sixth comparison signal CP6, its setting terminal S receives the fifth comparison signal CP5, and its output terminal Q is connected to the control terminal of the switch M13, wherein the lower limit reference voltage VL and the upper limit reference The voltage VH is used to determine whether the load current IL corresponding to the sample-and-hold voltage Vsh is within the predetermined current range, and in response to the load current IL being within the predetermined current range, the SR latch SR2 controls the switch M13 to turn on through the enable signal Sen to turn on the current subtraction circuit The subtraction current Isub generated by CS can charge and discharge the cut-off capacitor Coff.

In some embodiments, the load current IL greater than 500 mA can be designed to be in a heavy load situation. Therefore, when the load is 500mA, the value of the sampling and holding current Ish and the reference current can be designed If Iref is equal, the subtraction current Isub at this time will be almost zero, which means that the amount of current used to change the switching frequency is almost zero when the load current IL is 500mA. As the load current IL increases, the sample-and-hold voltage Vsh will increase, and the sample-and-hold current Ish will also increase. At this time, the switching frequency will linearly decrease due to the sample-and-hold current Ish.

In the logic judgment circuit Log, the purpose of the switch M13 is to use logic judgment to determine the timing of enabling the variable frequency mechanism with the load. Continuing the previous example, when the load current IL is lower than 500mA, the lower limit voltage of the sample-and-hold voltage Vsh will be less than the lower limit reference voltage VL, and the upper limit voltage of the sample-and-hold voltage Vsh is also less than the upper limit reference voltage VH. The latch SR2 is set, and the switch M13 is kept off because the output terminal Q is at a low level. At this time, the switch M13 is in the off state and cannot draw current to the off capacitor Coff on the fixed off time circuit 114.

On the other hand, when the load current IL is higher than 500mA, the upper limit voltage of the sample-and-hold voltage Vsh will be greater than the upper limit reference voltage VH. Therefore, the SR latch SR2 is set, and the switch M13 is turned on because the output terminal QQ is at a high level. At this time, the turned-on switch M13 will draw current to the cut-off capacitor Coff on the fixed cut-off time circuit 114 to reduce the switching frequency.

Please refer to FIG. 1 again. The pulse width modulation module 12 is configured to output a pulse width modulation signal PWM when the feedback voltage Vfb is lower than the pulse width modulation reference voltage Vref_pwm. As shown in FIG. 1, the pulse width modulation module 12 may include an error amplifier EAMP, a compensator COM, a triangle wave generator RAMP, and a seventh comparator CMP7. The positive input terminal of the error amplifier EAMP receives the pulse width modulation reference voltage Vref_pwm, the negative input terminal receives the feedback voltage Vfb, and the output terminal outputs the error amplification signal Sea. The compensator COM is connected between the negative input terminal and the output terminal of the error amplifier EAMP, so that the overall circuit can achieve better stability. In order to ensure that the overall loop gain has sufficient phase margin (PM), it is better to use a Type 3 compensator for compensation. This compensator provides three poles and two zeros, commonly known as 3P2Z compensator, which can be further passed through The pole and zero placement method is used to make the loop gain have enough phase margin and the desired crossover frequency.

The triangle wave generator RAMP is configured to generate a triangle wave signal Sramp based on the high signal Vh and the low signal V1. The purpose is to provide a triangle wave signal to the pulse width modulation control loop so that the output level of the compensator COM can be compared with the triangle wave, and Output pwm signal. The seventh comparator CMP7 is configured to receive and compare the error amplification signal Sea and the triangle wave signal Sramp, and generate the seventh comparison signal CP7 as the pulse width modulation signal PWM. The dual-mode buck converter 1 of the present invention can use the pulse width modulation module 12 to control the switching frequency when the load current IL is less than 100mA, so that the switching frequency is limited to a fixed value.

The multiplexer MUX receives the fixed cut-off time signal DUTY and the pulse width modulation signal PWM, and selectively outputs the working signal DUTY or the pulse width modulation signal PWM according to the magnitude of the feedback voltage Vfb (or output voltage Vo). The multiplexer MUX can have a data selection terminal. When it is at a high level, the control mode is FOT and selects the output working signal DUTY. When the data selection terminal is at a low level, the control mode is pulse width modulation (PWM) mode , Select the output pulse width modulation signal PWM.

The zero current detection circuit 14 is configured to receive the fixed cut-off time signal DUTY or the pulse width modulation signal PWM output by the multiplexer MUX, and correspondingly generate the zero current detection output signal ZCDout. Finally, the control circuit 18 receives the zero current detection output signal ZCDout to control the first switch Mp and the second switch Mn to turn on or off, respectively.

[Beneficial effects of the embodiment]

One of the beneficial effects of the present invention is that the dual-mode buck converter provided by the present invention adopts ripple modulation to set the cut-off time control. In addition to designing the switching frequency under different output loads to make the system reach the best efficiency point, In addition, the frequency conversion mechanism with the input voltage, the peak voltage switching mechanism and the pulse width modulation control are added to improve the conversion efficiency, so that the system switching frequency decreases with the increase of the input voltage, thereby greatly reducing the switching loss.

In addition, the dual-mode buck converter provided by the present invention uses peak power at light load. The voltage switching mechanism allows the circuit to achieve soft switching control to reduce the switching loss, and the use of a variable frequency mechanism with the output load under heavy load enables the circuit to maintain a higher conversion efficiency.

The content disclosed above is only the preferred and feasible embodiments of the present invention, and does not limit the scope of the patent application of the present invention. Therefore, all equivalent technical changes made using the description and schematic content of the present invention are included in the application of the present invention. Within the scope of the patent.

1: Dual mode buck converter

10: Buck converter circuit

11: Ripple modulation cut-off time control circuit

12: Pulse width modulation module

13: Multiplexer

14: Zero current detection circuit

15: Control circuit

100: feedback circuit

110: Current detection circuit

112: Peak voltage switching circuit

114: fixed cut-off time circuit

116: Variable frequency circuit with load

CMP1: The first comparator

CMP7: seventh comparator

Co: output capacitance

COM: compensator

CP1: The first comparison signal

CP7: Seventh comparison signal

CS: current subtraction circuit

DUTY: work signal

EAMP: Error amplifier

IL: Load current

L: output inductance

Log: logic judgment circuit

Mn: second switch

Mp: First switch

Nd: voltage divider node

No: output terminal

PWM: Pulse width modulation signal

RAMP: Triangular wave generator

Rf1: The first voltage divider resistor

Rf2: second voltage divider resistor

RL: load resistance

Sea: Error amplification signal

SH: sample and hold circuit

Sramp: triangle wave signal

SW: Switch node

Vfb: feedback voltage

Vh: high signal

V1: low signal

Vo: output voltage

Vref_pwm: Pulse width modulation reference voltage

Vref1: the first reference voltage

Vref2: second reference voltage

Vref3: third reference voltage

Vsw: switching voltage

ZCDout: Zero current detection signal

Claims (8)

A dual-mode buck converter includes: a buck converter circuit, including: a first switch connected between an input voltage source and a switching node; a second switch connected to the switching node and ground Between the terminals; an output inductor connected between the switching node and an output terminal; an output capacitor connected between the output terminal and the ground terminal; a load resistor connected between the output terminal and the ground terminal; And a feedback circuit connected between the output terminal and the ground terminal, configured to generate a feedback voltage according to an output voltage of the output terminal; a ripple modulation cut-off time control circuit, which includes: a first comparison A device configured to compare the feedback voltage with a first reference voltage, and correspondingly output a first comparison signal; a current detection circuit, configured to be based on an input voltage of the input voltage source and the switching node A switching voltage generates a current detection signal related to a load current; a peak voltage switching circuit receives the switching voltage, a second reference voltage and a zero current detection signal, which is configured to be based on the switching voltage and the The relative relationship of the second reference voltage and the zero current detection signal generate a peak switching signal, wherein the zero current detection signal is used to indicate whether the load current passes through a current zero point, and the second reference voltage corresponds to the switching voltage A resonant peak value; a fixed cut-off time circuit, configured to: detect an input voltage range of the input voltage, and correspondingly generate a charge and discharge voltage to charge and discharge one of the cut-off capacitors, and on a cut-off node Generate a cut-off voltage; perform a cut-off voltage, the peak switching signal, and the first comparison signal A logic processing program to generate a working signal, wherein the working signal has a switching frequency; a load-dependent frequency conversion circuit, which includes: a sample-and-hold circuit configured to sample and hold the current detection signal according to the working signal, To correspondingly generate a sample-and-hold voltage; a current subtraction circuit configured to extract a third reference voltage and the sample-and-hold voltage to obtain a reference current and a sample-and-hold current, and subtract the sample-and-hold current The reference current generates a phase subtraction current; a logic judgment circuit configured to judge whether the load current is within a predetermined current range according to the sample and hold voltage to determine whether to charge and discharge the cut-off capacitor with the phase subtraction current ; A pulse width modulation module, configured to output a pulse width modulation signal when the feedback voltage is lower than a pulse width modulation reference voltage; a multiplexer, configured to receive the working signal and the Pulse width modulation signal, and selectively outputting the working signal or the pulse width modulation signal according to the load current; a zero current detection circuit configured to receive the working signal or the pulse width output by the multiplexer Modulate the signal, and detect a current zero point of the load current to generate the zero current detection signal; and a control circuit configured to receive the zero current detection output signal to control the first switch and the The second switch is turned on or off. The dual-mode buck converter according to claim 1, wherein the feedback circuit includes: a first voltage dividing resistor connected between the output terminal and a voltage dividing node; and a second voltage dividing resistor connected to Between the voltage dividing node and the ground terminal, the output voltage generates the feedback voltage on the voltage dividing node. The dual-mode buck converter according to claim 1, wherein the peak voltage switching The circuit includes: a first amplifier whose positive input terminal receives the switching voltage, and its negative input terminal is connected to its output terminal to form a voltage follower to output the switching voltage at its output terminal; a second comparator, via Configured to receive and compare the switching voltage and the second reference voltage to output a second comparison signal; a first and gate configured to receive the zero current detection signal and the second comparison signal, and output the peak A switching signal, wherein, when the switching voltage is higher than the second reference voltage and the zero current detection signal is at a high level, the peak switching signal has a high level. The dual-mode buck converter according to claim 1, wherein the fixed cut-off time circuit includes: a second amplifier that performs negative feedback on the input voltage to generate a cut-off current on a cut-off resistor through a third switch ; A third comparator, configured to determine whether the input voltage is higher than a center voltage, and correspondingly output a third comparison signal; a charging and discharging circuit, including: a high-voltage circuit, connected to a high-voltage input terminal and the Between cut-off nodes; and a low-voltage loop connected between a low-voltage input terminal and the cut-off node, wherein, in response to the input voltage being higher than the center voltage, the high-voltage loop is turned on, and in response to the input voltage being less than the Center voltage, the low-voltage loop is turned on; a first current mirror circuit, connected to the high-voltage input terminal and the low-voltage input terminal, is configured to mirror the cut-off current to the low-voltage loop of the charging and discharging circuit, and A difference current between a certain current and the cut-off current is mirrored to the high voltage loop; The cut-off capacitor is connected between the cut-off node and the ground terminal, and is charged and discharged by the cut-off current or the difference current reflected by the mirror; a fourth comparator is configured to compare a cut-off voltage of the cut-off node with A peak voltage is compared and a fourth comparison signal is generated correspondingly; an OR gate is configured to perform an OR operation on the peak switching signal and the cut-off voltage to output a first logic signal; a first SR latch The device has a reset terminal, a setting terminal, an output terminal and an inverted output terminal, wherein the reset terminal is configured to receive the first logic signal; a delay circuit is connected to the output terminal and is configured to Delay an output signal of the output terminal to generate a delay signal; a gate is configured to perform an AND operation on the first comparison signal and the delay signal to output a second logic signal to the setting terminal, wherein The SR latch is configured to output a working signal at the inverting output terminal according to the first logic signal and the second logic signal; a fourth switch is connected in parallel with the cut-off capacitor with respect to the cut-off node and the ground terminal, And it is configured to be turned on or off under the control of the working signal. The dual-mode buck converter according to claim 1, wherein the sample-and-hold circuit includes: a sample-and-hold switch, the first terminal of which receives the current detection signal, the second terminal of which is connected to the ground terminal, and the control terminal of which receives The working signal; a sample-and-hold capacitor connected between the second end of the sample-and-hold switch and the ground terminal to be charged by the current detection signal; an operational transconductance amplifier whose positive input is connected to the sample The negative input terminal of the second terminal of the holding switch is connected to the output terminal, so as to output the sample and hold voltage at the output terminal. The dual-mode buck converter according to claim 1, wherein the current subtraction circuit It includes: a first voltage-to-current circuit, including: a third amplifier, the positive input terminal of which receives the third reference voltage; and a fifth switch, the control terminal of which is connected to the output terminal of the third amplifier, and the first Terminal is connected to a ground terminal through a first drop resistor, wherein the third amplifier is configured to generate the reference current on the fifth switch according to the third reference voltage; a second current mirror, the first terminal of which is connected to The second terminal of the fifth switch is configured to mirror the reference current and output it at the second terminal; a second voltage-to-current circuit includes: a fourth amplifier whose positive input terminal receives the sample-and-hold voltage And a sixth switch, the control terminal of which is connected to the output terminal of the fourth amplifier, the first terminal of which is connected to the ground terminal through a second drop resistor, and the second terminal of which is connected to the second current mirror of the second current mirror Terminal, wherein the fourth amplifier is configured to generate the sample-and-hold current on the sixth switch according to the sample-and-hold voltage; a third current mirror, the first terminal of which is connected to the second terminal of the second current mirror, wherein The subtraction current generated by subtracting the reference current from the sample and hold current flows from the second end of the second current mirror to the third current mirror, and the third current mirror is configured to mirror the subtraction current and output it to The second end of the third current mirror; a fourth current mirror, the first end of which is connected to the second end of the third current mirror, and the second end of which is connected to the logic judgment circuit. The dual-mode buck converter according to claim 6, wherein the logic judgment circuit includes: a fifth comparator configured to compare the sample-and-hold voltage with a lower limit reference voltage, and correspondingly output a fifth comparison signal; A sixth comparator, configured to compare the sample-and-hold voltage and an upper limit reference voltage, and correspondingly output a sixth comparison signal; A seventh switch is connected between the cut-off capacitor and the second terminal of the fourth current mirror; and a second SR latch, the reset terminal of which receives the sixth comparison signal, and the set terminal of which receives the fifth The output terminal of the comparison signal is connected to the control terminal of the seventh switch, wherein the lower limit reference voltage and the upper limit reference voltage are used to determine whether the load current corresponding to the sample-and-hold voltage is within the predetermined current range, and responds to the When the load current is within the predetermined current range, the second SR latch controls the seventh switch to turn on so that the subtraction current generated by the current subtraction circuit charges and discharges the cut-off capacitor. The dual-mode buck converter according to claim 1, wherein the pulse width modulation module includes: an error amplifier, the positive input terminal of which receives the pulse width modulation reference voltage, and the negative input terminal of which receives the feedback voltage , Its output terminal outputs an error amplification signal; a compensator connected between the negative input terminal and the output terminal of the error amplifier; a triangle wave generator configured to generate a triangle wave signal based on a high signal and a low signal; A seventh comparator is configured to receive and compare the error amplification signal and the triangular wave signal, and generate the pulse width modulation signal.

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