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TWI606498B - 具鰭式結構之半導體裝置及其製造方法（一） - Google Patents

具鰭式結構之半導體裝置及其製造方法（一） Download PDF

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TWI606498B
TWI606498B TW105104945A TW105104945A TWI606498B TW I606498 B TWI606498 B TW I606498B TW 105104945 A TW105104945 A TW 105104945A TW 105104945 A TW105104945 A TW 105104945A TW I606498 B TWI606498 B TW I606498B
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湯瑪斯 霍夫曼
史考特Ｅ 湯普森
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三重富士通半導體股份有限公司
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H10D30/6212—Fin field-effect transistors [FinFET] having fin-shaped semiconductor bodies having non-rectangular cross-sections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/351—Substrate regions of field-effect devices
    • H10D62/357—Substrate regions of field-effect devices of FETs
    • H10D62/364—Substrate regions of field-effect devices of FETs of IGFETs
    • H10D62/371—Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current
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    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0158—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including FinFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/011—Manufacture or treatment comprising FinFETs

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Description

具鰭式結構之半導體裝置及其製造方法(一) 發明領域
本揭示內容一般係關於半導體裝置，且更特定地關於包含鰭式結構之半導體裝置以及一整合方案以在與基於鰭之電晶體相同之基板上併入平面電晶體。
本申請案主張2011年8月5日申請且題為「Multigate Transistors」之美國臨時專利申請案第61/515,452號之優先權，其之全文內容以引用之方式併入本文中。
發明背景
隨著半導體工業將目光投向22nm技術節點且超過22nm技術節點，一些製作者正在考慮從平面CMOS電晶體轉變為三維(3D)FinFET裝置架構。對比於一平面電晶體中位於通道上方之閘極，一FinFET之閘極環繞該通道，提供從多個側的靜電控制。相對於平面電晶體，此等FinFET給予改良之通道控制及因此減小短通道效應。由於FinFET之固有的優越靜電控制，FinFET之裝置靜電隨著裝置(鰭) 之寬度積極縮放(通常對於次22nm之節點應用係約10nm至15nm)而改良。此係所謂「雙閘極」場效應之一結果，且隨著鰭寬度(Wfin)減小，可藉由以小閘極長度(Lg)之顯著DIBL縮減而量化。
在塊體矽上特殊整合FinFET(塊體FinFET)，已研究恰好在Si鰭下方使用一「接地平面」。提供此接地平面以防止源極與汲極之間之低摻雜且不在閘極之直接控制下之任何區域中之一潛在的洩漏路徑。在習知塊體FinFET中，該接地平面經由以充分高以造成摻雜物穿隧通過基板之垂直長度且在井區中形成接地平面之一能量植入一摻雜層而形成。該接地平面形成步驟在形成隔離特徵部之後所做。然而，由於多個因素(例如，所植入之摻雜物分佈之有限梯度、WPE及來自植入至隔離氧化物層中之背向散射)，可非刻意地摻雜Si鰭。該非刻意摻雜可使電效能劣化，表現於匹配問題(由於隨機摻雜物波動)或驅動電流變動(由於來自雜質散射之遷移率損失)。
此外，在鰭形成之後執行此接地平面植入之情況中，實際鰭高度之任何變動將轉化為摻雜物位置相對於鰭之頂部之一變化。因此，該裝置之有效(或電)鰭高度亦變動。最壞的是，可能無法適當形成接地平面。鰭高度之變動不僅係由於程序條件之變動，而且由於負載效應及其他圖案相依性。此等變動將直接衝擊與裝置有效寬度直接成比例之裝置之關鍵效益指數(閘極電容及驅動電流)。由於此等限制，製作者亦考慮利用SOI-FinFET裝置架構，其藉由 僅在一絕緣體之頂部上提供Si鰭而消除對於重摻雜接地平面之需要。
發明概要
依據本文揭示之一實施例，係特地提出一種半導體裝置，其包含：形成於一半導基板中之一重摻雜層；形成於該重摻雜層上方之一實質上未摻雜鰭式結構；形成於該實質上未摻雜鰭式結構的多個側與一上表面上之一閘極介電體層；形成於該閘極介電體層上之一閘極電極。
10‧‧‧半導體裝置
12、512‧‧‧半導基板
13、513‧‧‧磊晶層
14、15、515‧‧‧鰭式結構
16、516‧‧‧隔離介電體
18‧‧‧重摻雜層
19‧‧‧井區域
40‧‧‧硬掩膜
42‧‧‧介電層
60‧‧‧通道區域
514、554‧‧‧結構
518‧‧‧重摻雜區域/重摻雜層區 域
530、560‧‧‧閘極介電體
532、562‧‧‧閘極電極
542‧‧‧介電體
570‧‧‧源極及汲極區域
572‧‧‧間隔物特徵部
圖1繪示根據一特定實施例之一半導體裝置之一截面圖；圖2至圖4繪示用於製造圖1之半導體裝置之一方法中之各種步驟；及圖5A至圖5D繪示根據一特定實施例之用於在一相同基板上形成FinFET及平面MOSFET裝置之各種步驟。
較佳實施例之詳細說明
為更完整理解實施例及其等之優點，現與隨附圖式結合而參考以下描述。
實施例參考附圖而描述，其中相似參考數字貫穿該等圖而用於指明類似或等效元件。該等圖並非按比例繪製，且其等僅提供於繪示實施例。下文參考實例應用而描述實施例之若干態樣以用於繪示。應理解，闡明許多特定 細節、關係及方法。一般技術者將容易地認識到本發明可在沒有一個或多個該等特定細節之下實踐，或用其他方法實踐。在其他例子中，熟知結構或操作並不詳細展示，以避免模糊實施例。本發明不受繪示之動作或事件之順序限制，因為一些動作可以不同順序出現，及/或與其他動作或事件併發地出現。此外，並非需要所有繪示之動作或事件以實施根據本發明之一方法。
各種實施例提供一塊體FinFET裝置架構，其限制或消除不期望之鰭摻雜量及有效鰭高度變動兩者，以致使鰭實質上不摻雜，藉此減小發生自鰭中之隨機摻雜物波動之臨限電壓之變動程度。特定言之，各種實施例提供一整合方案，其由以下組成：在隔離及鰭形成模組之前，(1)經由植入或其他摻雜技術在一基板之一表面中形成井及重摻雜層；(2)在形成該重摻雜區域之後在該基板上生長一未摻雜之磊晶層(epi層)；及(3)圖案化該磊晶層，以定義鰭。其後，該等鰭接著用於形成FinFET裝置。
上文描述之整合方案提供SOI-FinFET之若干優點(但是在一塊體FinFET結構中)。首先，可在一高摻雜層上形成一真正未摻雜之鰭，因為在形成該磊晶層之後未執行通道植入。結果，電特性之改良(諸如改良之匹配特性及來自較少雜質散射的更高遷移率)係可能的。
第二，此整合方案使得塊體FinFET之匹配係數到達約1.0至1.2mV/um，密切地匹配對於未摻雜的SOI-FinFET裝置所報告之係數。此外，電效能之整體均勻 度通過從蝕刻及植入程序之變動將有效(或電)鰭高度去耦合而改良。相反，鰭高度主要取而代之由磊晶膜厚度設定，為此，可達成0.1%或更好的均勻度。例如，對於30nm至40nm之一矽磊晶層，該磊晶層厚度晶圓均勻度可在+/-1nm(1均方偏差)內，其比經由蝕刻程序及植入程序之習知組合對於實體鰭高度可達成之均勻度更緊密。
其他可能益處包含增強之臨限電壓(Vth)調諧敏感度，其藉由接地平面集中度變化，及增強之本體係數。此外，因為不需要暈植入，且井/接地井植入在STI之前執行，該整合方案亦期望減小井近接效應。
現轉向圖1，展示根據一特定實施例之在形成閘極之前之一例示性半導體裝置10之一截面圖。半導體裝置10包含藉由平版印刷及蝕刻程序之一組合而形成於一半導基板12上之一鰭式結構14。在所繪示之實施例中，半導體裝置10包含藉助於上覆一重摻雜區域18及視需要的一井區域19之一實質上未摻雜之半導體層而形成於鰭式結構14中之一通道區域60。鄰近於鰭式結構14在任一側上的是隔離氧化物16。半導體裝置10可於較高速度及/或以減小的功率消耗操作。如本文中所使用，術語「半導基板」指其上安置一層或多層半導體材料之任何類型之基板或支撐層。此等可包含絕緣體上矽基板、塊體矽基板或磊晶矽基板，等等。
如由圖1所繪示，鰭式結構14形成於半導基板12上。在此實施例中之基板結構12表示具有其內形成之一重 摻雜層18之半導體材料之一基板。重摻雜層18表示一層重濃度摻雜之半導體材料(5×1018至1020原子/cm3)。如圖1中所展示，此層可被組態為一抗衝穿層(APT)。
鰭式結構14表示由半導基板12之頂部上之半導體材料形成之一結構，其從半導基板12向外及/或向上延伸。在圖1之特定組態中，該鰭式結構14至少通過該通道區域且較佳地通過該重摻雜層18而延伸。在一些組態中，該鰭式結構14可進一步通過該井層19而延伸。如上文所注意，該鰭式結構14較佳地藉由沈積實質上未摻雜之(<1017原子/cm3)一磊晶層且隨後圖案化以形成該鰭式結構14而形成。在特定實施例中，鰭式結構之寬度可介於5nm與50nm之間，諸如10nm。
如上文所注意，通道區域60亦表示鰭式結構14之一區域。特定言之，藉由定義鰭式結構14之一部分而由在鰭式結構14中之半導體材料形成通道區域60，在該部分中不添加任何類型之雜質。結果，通道區域60定義實質上未摻雜之一通道區域。
因為通道區域60形成為從半導基板12及重摻雜層18延伸之鰭式結構14之一部分，所以形成閘極(未展示)以沿著通道區域60之多個邊界、面、側及/或部分而鄰接通道區域60。藉由在此等邊界處首先沈積或生長一層氧化物而形成閘極。接著，較佳地，形成一堆疊之金屬以提供一閘極電極。然而，各種實施例並不在這方面限制，且亦可使用其他類型之閘極電極材料。
如上文所注意，在形成隔離區域之前形成該重摻雜層18(及井區域19)。此外，該重摻雜層18可以多種方式形成。在特定實施例中，藉由植入適當物種而形成該重摻雜層18，以形成一個或多個重摻雜區域。類似地，藉由植入適當物種而形成井區域19，以形成一個或多個井區域。此程序示意地繪示於圖2中。在一個例示性程序中，該半導基板12係一p型導電率基板。接著，可提供p型摻雜材料，諸如硼(B)、鎵(Ga)、銦(In)或任何其他適宜p型摻雜物。在一個例示性程序中，提供一硼井植入及額外硼植入。該等植入可經組態以在表面處導致介於5×1018至1×1020原子/cm3之間之一p型摻雜濃度。取決於程序條件，亦可提供額外植入以限制在隨後步驟期間允許擴散至該磊晶層中之B(或其他p型摻雜物)的量。例如，可利用一Ge非晶化植入及一C+植入，以提供取代C之一表面層，以在隨後處理步驟期間減小或消除B擴散。對於另一FinFET，可提供n型摻雜材料，諸如銻、砷、磷或任何其他適當n型摻雜物。例如，可提供一磷井植入及一砷植入。該等植入可分層以提供相異摻雜物濃度之區域，以達成期望之電特性。再次，該等植入可經選擇以在表面處提供介於5×1018至1×1020原子/cm3之間之一n型摻雜濃度。
緊接形成重摻雜層18及井區域19後，可形成未摻雜之通道。圖3繪示在已在重摻雜層18之頂部上形成未摻雜之半導體材料之一磊晶層13之後之半導基板12。在一特定實施例中，該磊晶層13可為一層30nm至40nm之矽。磊晶 層13將隨後被用於形成鰭式結構14。該磊晶層13使用任何適當磊晶生長技術沈積該磊晶層13而形成於重摻雜層18之頂部上。在一些實施例中，該半導基板12係一包括矽之基板，且該磊晶層13係一層矽。在此等實施例中，可使用各種化學氣相沈積技術以形成該磊晶層13。此等包含超高真空CVD、低壓CVD及遠端電漿CVD，等等。然而，各種實施例並不在這方面限制，且可等同地應用任何其他技術以形成矽磊晶層。
本揭示內容亦預期磊晶層13可使用與矽基板相容之其他材料形成。例如，磊晶層可為一層之矽鍺合金、矽鍺碳合金、矽碳合金或鍺碳合金。此外，本揭示內容亦預期該半導基板12及該磊晶層13之組合物並不限制於第IV行元素。相反，本文中描述之方法及來自其之裝置可沒有限制地基於任何其他類型之半導體材料。
現參考圖4，此繪示一鰭圖案化程序，其在特定實施例中在已在重摻雜層18之頂部上形成磊晶層13之後執行。一硬掩膜40施覆至半導基板12之適當部分，以劃定鰭式結構14。掩膜40可包括氧化矽、氮氧化矽、氮化矽層、此等材料之一組合，及/或用於保護直接在掩膜40下方之磊晶層13之部分免受蝕刻的任何其他適當材料。在已施覆掩膜40之後，一層光阻劑施覆於掩膜40之頂部上，且接著蝕刻半導基板12以形成鰭式結構14。各種程序(諸如光學微影術、浸潤式微影術、壓印微影術、直接寫入電子束微影術、x射線微影術或極端紫外線微影術)可用於在光阻劑中定義 此圖案。接著使用一蝕刻程序，諸如電漿蝕刻以結束圖案化程序，以形成鰭式結構14。在各種實施例中亦可使用任何其他蝕刻程序。接著可基於被利用之特定技術而適當地將掩膜40移除或保留於隨後步驟。
如上文所注意，用於形成磊晶層13之一些程序可提供0.5%或更好之數量級之均勻度之變動。相應地，跨該半導基板12之該磊晶層13之厚度係熟知的。此外，亦可使用提供高位準之均勻度之選擇之蝕刻程序。例如，可用提供2nm至5nm精確度之乾式蝕刻程序、電漿蝕刻程序。相應地，此等兩個位準之均勻度之組合允許蝕刻程序精確地定目標為對於所得鰭實質上達成一期望厚度之磊晶層13之一蝕刻程序。
在形成該鰭式結構14之蝕刻程序之後，在整個結構之上形成作為一毯覆層膜之一介電層42。在一特定實施例中，使用一化學氣相沈積方法以經選擇以避免來自重摻雜區域18之摻雜物移動上至通道60中之一溫度沈積氧化矽。其後，使用一蝕刻程序以移除介電層42之一部分下至一預選擇位準，以定義隔離介電體16。較佳地，該蝕刻程序經組態使得所得隔離介電體16之頂部表面在重摻雜區域18之頂部表面處或接近重摻雜區域18之頂部表面，如圖1中所繪示。
在一些實施例中，在蝕刻介電層42之前，可執行一平坦化蝕刻或拋光程序作為一第一步驟，使得該介電層42可被移除至鰭式結構14之頂部表面之位準。適宜拋光程 序之實例包含化學機械拋光或機械拋光。接著該蝕刻可通過該鰭式結構14之垂直長度進行，使得結果暴露該鰭式結構14之至少未摻雜之部分(通道60)，產生一暴露之鰭式結構15，且該鰭式結構14之剩餘部分被該隔離介電體16圍繞。在蝕刻介電體42之後，導致暴露通道60，可形成閘極結構(未展示)使得閘極材料(例如，閘極介電體及閘極電極)環繞鰭式結構14之暴露表面(即，繞暴露之鰭式結構15)。
此程序之結果為暴露之鰭式結構15之電高度(即，通道60之高度，由Hfin_eff表示)及暴露之鰭式結構15之實際高度相同或實質上相同。由於上文描述之程序，該暴露之鰭式結構15與重摻雜層18相關聯之部分相對較小。結果，通道60之所有未摻雜之區域在隨後形成之閘極結構之直接控制下。此外，即使重摻雜層18之一些部分在隨後形成之閘極結構之控制下，其內之高摻雜將防止此部分鰭式結構14顯著地影響裝置10之操作。
本揭示內容亦預期上文描述之方法可經利用以允許平面CMOS及FinFET裝置併發地在相同基板上形成。明確言之，上文描述之方法對於將深空乏通道(DDC)電晶體裝置與FinFET裝置整合可為有用的。DDC電晶體裝置順從上文描述之程序流程，因為其等亦對於形成於一個或多個高摻雜層之頂部上之通道使用一實質上未摻雜之層。
例如藉由將摻雜物植入一基板中以形成一重摻雜網篩層(5×1018至1×1020原子/cm3)而藉由對於該等CMOS裝置形成一井而形成DDC電晶體。緊接此之後可為一未摻 雜或輕微摻雜(統稱為「實質上未摻雜」)之毯覆層磊晶層(<5×1017)，其沈積在網篩層之上(跨多個晶粒及電晶體晶粒塊延伸)。應形成此一毯覆層磊晶層，以便減小井植入期間置入之散射摻雜物向上移動。在一些組態中，輕摻雜臨限電壓(Vth)調整層(介於5×1017與2×1019原子/cm3之間)亦可形成於網篩層中或鄰近於該網篩層，以允許調整臨限電壓之更精細及對抗不需要之洩漏電流的控制。較佳地，藉助於通道植入或暈植入之習知臨限電壓設定方法並不使用於DDC電晶體之製造中。然而，存在其他各種實施例。
關於例示性DDC電晶體結構之細節更完整地描述於題為「ELECTRONIC DEVICES AND SYSTEMS,AND METHODS FOR MAKING AND USING THE SAME」且於2010年2月18日申請之美國專利申請案第12/708,497號、題為「LOW POWER SEMICONDUCTOR TRANSISTOR STRUCTURE AND METHOD OF FABRICATION THEREOF」且於2010年12月17日申請之美國專利申請案第12/971,884號、題為「TRANSISTOR WITH THRESHOLD VOLTAGE SET NOTCH AND METHOD OF FABRICATION THEREOF」且於2010年12月17日申請之美國專利申請案第12/971,955號、題為「ADVANCED TRANSISTORS WITH THRESHOLD VOLTAGE SET DOPANT STRUCTURES」且於2010年9月30日申請之美國專利申請案第12/895,785號(其等全文之揭示內容以引用之方式併入本文中)，及題為「ADVANCED TRANSISTORS WITH PUNCH THROUGH SUPPRESSION」且於2010年9月30日申請之美國專利申請案第12/895,813號中。
現參考圖5A，程序可首先開始於在半導基板512之表面處形成一重摻雜層區域518。視需要，亦可形成一井區域(未展示)，如前文所描述。該重摻雜層區域518係用於將要形成之FinFET裝置，及用於將要形成之DDC裝置。儘管該重摻雜區域518中之摻雜濃度可出於對於一FinFET提供一足夠本體之目的經選擇，該摻雜濃度亦可對於一CMOS裝置(諸如一DDC裝置)而選擇。例如，在一DDC裝置之情況中，該重摻雜區域518可經組態以對於該DDC裝置提供一高摻雜之網篩層(圖5A至圖5D中之「網篩」)及Vth調整層(圖5A至圖5D中之「VT」)。對於每個裝置選擇重摻雜層區域518之摻雜物位準及材料，且其等可相同或可相異。若摻雜物位準及/或材料相異，則使用掩膜步驟以阻擋差別摻雜之區。
可接著形成實質上未摻雜之磊晶層513，如圖5B中所展示。該磊晶層513可以與前文所描述實質上相同的方式形成。其後，可使用微影術及蝕刻步驟而圖案化該磊晶層513，以同時形成結構514及554，如圖5C中所展示。在圖5C中繪示之實施例中，結構514係一鰭式結構，而結構554係一裝置島狀物或一作用區結構或區域(用於在其上形成平面裝置)。在圖5C中，為便於繪示，不展示井植入。值得注意的是，亦可利用磊晶層513之蝕刻，以定義結構514與544之間之隔離特徵部。因此，該蝕刻程序可經組態以便蝕 刻該磊晶層513之特定區域，重摻雜區域518之下面部分，及半導基板512之部分。
其次，沈積一介電體542以覆蓋於所有蝕刻部分之上。此可較佳地使用化學氣相沈積而在低於最大溫度之一程序中執行，以避免摻雜物移動上至實質上未摻雜之磊晶層513中。接著，該介電體542蝕刻回至一期望深度，以工作為FinFET與平面裝置兩者之隔離，以產生隔離介電體516。由於介電體542之蝕刻，該介電隔離516將在定義一暴露之鰭式結構515之底部之一深度，以用於定義FinFET裝置，且將與作用區區域554之一上表面對準，以對於其上形成之平面裝置提供隔離。
接著可執行額外處理，以形成平面及FinFET裝置，亦如圖5D中所展示。特定言之，閘極介電體530形成於暴露之鰭式結構515之暴露側上。一閘極介電體560亦形成於該等作用區區域554之上表面上。該等閘極介電體530及560可相同或不同，且可使用相同或不同程序形成。較佳地，閘極介電體530及560兩者在一熔爐中使用一熱氧化程序使用適宜於避免摻雜物移動上至實質上未摻雜之通道區中之一溫度而形成。接著較佳地使用一物理氣相沈積程序而從金屬形成每個裝置之閘極電極532及562。材料可包含TiN、Al合金、W及其他材料或其組合，以達成一期望之工作功能。對於平面裝置，可使用一閘極第一途徑或閘極最後途徑而形成閘極電極。額外地，對於平面裝置形成源極及汲極區域570。在一特定實施例中，此等區域可經由植入 至該作用區區域554中形成。此一程序可包含對於源極/汲極延伸植入，在該作用區區域554中形成間隔物特徵部572。
本揭示內容亦預期可對於平面CMOS裝置提供額外程序步驟。例如，該等平面CMOS裝置之通道區域可要求比該等FinFET裝置更高之一摻雜濃度，且因此將使用額外摻雜步驟。在還有另外實例中，可在形成閘極介電體560及閘極電極562之前執行選擇性蝕刻該作用區結構554，以減小用於該等平面CMOS裝置之磊晶層之厚度。
本揭示內容亦預期緊接圖5C之結構之形成後，該程序流程可以一分歧之方式進行。即，可單獨執行不同裝置類型之許多或所有處理步驟。此可經由使用掩膜層而完成，以防止在某些裝置上執行程序步驟。例如，可利用掩膜層以允許用於閘極介電體、閘極電極及裝置植入之不同程序及材料，等等。然而，各種實施例並不在這方面限制，且亦可對於不同裝置將任何其他程序分歧。
雖然已在上文描述各種實施例，但是應理解，其等僅藉助於實例且並非限制而展現。可在未脫離實施例之精神或範疇之下根據本文中之揭示內容對所揭示之實施例作出許多變化。因此，本發明之廣度及範疇不應由上文描述之實施例之任何者限制。相反，本發明之範疇應根據以下申請專利範圍及其等效物定義。
儘管已相對於一個或多個實施繪示及描述實施例，然而熟習此項技術者在閱讀及理解本說明書及所附圖式時將出現等效改變及修改。再者，雖然一實施例之一特 定特徵部可能已相對於若干實施之僅一者而揭示，但是當可能期望及有利於任何給定或特定應用時，此特徵部可與其他實施之一個或多個其他特徵部組合。
本文中使用之專門名詞僅係出於描述特定實施例之目的，且並不意欲限制本發明。如本文中所使用，除非內文明確地另有指示，否則單數形式「一(「a」、「an」)」及「該」(「the」)意欲亦包含複數形式。此外，對術語「包含(「including」、「includes」)」、「具有(「having」、「has」、「with」)」或其等之變體使用於實施方式及/或申請專利範圍中之限度，此等術語意欲以類似於術語「包括」之一方式作為包含性的。
除非另外定義，否則本文中使用之所有術語(包含技術及科學術語)具有與一般技術者普遍所理解之相同意義。將進一步理解，術語(諸如在普遍使用之辭典中定義之術語)應解譯為具有與其等在相關技術之內文中之意義一致之一意義，且將不以一理想化或過度正式之意思解譯，除非在本文中明確如此定義。
10‧‧‧半導體裝置
12‧‧‧半導基板
14、15‧‧‧鰭式結構
16‧‧‧隔離介電體
18‧‧‧重摻雜層
19‧‧‧井區域
60‧‧‧通道區域

Claims (10)

  1. 一種半導體裝置，其包含：形成於一半導基板中之一重摻雜層；形成於該重摻雜層上方之一障壁層，其用於防止該重摻雜層之摻雜物擴散進入該實質上未摻雜鰭式結構；形成於該障壁層上方之一實質上未摻雜鰭式結構；形成於該實質上未摻雜鰭式結構的多個側與一上表面上之一閘極介電體層；形成於該閘極介電體層上之一閘極電極。
  2. 一種半導體裝置，其包含：形成於一半導基板中之一重摻雜層；形成於該重摻雜層上方之一實質上未摻雜鰭式結構；形成於該實質上未摻雜鰭式結構與該重摻雜層之間的一摻雜層，該摻雜層之一摻雜濃度係低於該重摻雜層之該摻雜濃度；形成於該實質上未摻雜鰭式結構的多個側與一上表面上之一閘極介電體層；形成於該閘極介電體層上之一閘極電極。
  3. 如請求項1或2之半導體裝置，其中該重摻雜層之一濃度為約5×1018至1×1020原子/cm3。
  4. 如請求項1或2之半導體裝置，其中該實質上未摻雜鰭式結構包含一層磊晶矽。
  5. 一種半導體裝置，其包含：一第一電晶體，其包括形成於一半導基板中之一第一重摻雜層、形成於該第一重摻雜層上方之一實質上未摻雜鰭式結構、形成於該實質上未摻雜鰭式結構的多個側與一上表面上之一第一閘極介電體層、形成於該第一閘極介電體層上之一第一閘極電極；以及一第二電晶體，其包括形成於該半導基板中之一第二重摻雜層、形成於該第二重摻雜層上方之一實質上未摻雜層、形成於該實質上未摻雜層上之一第二閘極介電體層、形成於該第二閘極介電體層上之一第二閘極電極；其中從該半導基板之一表面起的該第一重摻雜層之一深度係實質上相同於從該半導基板之該表面起的該第二重摻雜層之一深度，該第一重摻雜層之一摻雜濃度係實質上相同於該第二重摻雜層之一摻雜濃度。
  6. 如請求項5之半導體裝置，其中該實質上未摻雜層之一厚度係實質上相同於該實質上未摻雜鰭式結構之一厚度。
  7. 如請求項5之半導體裝置，其中該等第一及第二重摻雜層之一濃度為約5×1018至1×1020原子/cm3。
  8. 如請求項5之半導體裝置，其進一步包含：形成於該第一重摻雜層上方之一第一障壁層，其用於防止該第一重摻雜層之摻雜物擴散進入該實質上未摻雜鰭式結構； 形成於該第二重摻雜層上方之一第二障壁層，其用於防止該第二重摻雜層之摻雜物擴散進入該實質上未摻雜層。
  9. 如請求項5之半導體裝置，其進一步包含：形成於該實質上未摻雜層與該第一重摻雜層之間的一第一摻雜層，該第一摻雜層之一摻雜濃度係低於該第一重摻雜層之該摻雜濃度，以及形成於該實質上未摻雜鰭式結構與該第二重摻雜層之間的一第二摻雜層，該第二摻雜層之一摻雜濃度係低於該第二重摻雜層之該摻雜濃度。
  10. 如請求項5之半導體裝置，其中該實質上未摻雜鰭式結構包含一層磊晶矽。
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