TWI690026B - Method of using simulation software to generate circuit layout - Google Patents

Abstract

A method of using simulation software to generate circuit layout includes: (A). determining a plurality of blocks on a circuit board, wherein each block within the blocks includes: operating space and preserved space; (B). determining the size of the preserved space of the blocks according to at least one specific condition; (C). Determining whether the size of the preserved space of the blocks should be adjusted according to at least one determining condition; and (D). When it is determined in Step (C) that the preserved space of the blocks should not be adjusted, generating the circuit layout according to the size of the preserved space of the blocks.

Description

Method for generating circuit layout using simulation software

This case relates to the application of power integrity (PI), in particular to a method that can properly determine the circuit layout to improve the problem that the circuit cannot operate normally.

Circuit layout, such as printed circuit board layout (PCB layout), considering the problem of voltage decay (also known as IR Drop), space is usually reserved between components to place capacitors (this operation is also called DCAP), as the circuit works abnormally s solution. The above-mentioned voltage decay is divided into static voltage decay and dynamic voltage decay. The static voltage decay is mainly related to the structure and connection details of the power supply network. Therefore, the static voltage decay mainly considers the resistance effect and analyzes the influence of the resistance. Dynamic voltage decay is the voltage drop caused by current fluctuations when the power supply is switched. This phenomenon occurs at the triggering edge of the clock, and often generates a large current on the entire wafer in a short time. This momentary large current causes a voltage decay phenomenon. At the same time, the greater the number of transistors on the switch, the easier it is to trigger dynamic voltage decay.

However, the prior art lacks a proper mechanism to determine how much space should be reserved between the components for placing capacitors. For example, the existing mechanism does not take into account the toggle rate of the circuit, and simply From the existing space, try to find as much space as possible for capacitors. Please refer to Figure 1. Figure 1 is a schematic diagram of the circuit layout that reserves DCAP space for the conventional technology. To reserve space at random or guess based on experience, this is very inefficient for reducing voltage decay. For example, if some areas have been placed very full (space utilization is high), there is not enough space to place a DCAP with a higher capacitance (capacitance of the capacitor is proportional to the volume) to suppress dynamic voltage degradation However, the dual-state thixotropy rate is usually higher in areas where the density of such devices is higher, such as some hotspot areas near the processing chip (CPU), display chip (GPU) and memory (DDR) ( (Circled in the picture). In contrast, in the open area where the component placement density is not high, there is plenty of room for DCAP, but such an area usually has a low two-state thixotropic rate.

In summary, the prior art is very poor in the circuit layout efficiency of the voltage attenuation prevention, which also causes a decrease in performance and a substantial increase in cost.

In view of the fact that the traditional circuit design method does not consider the influence of toggle rate on circuit planning, the present invention proposes a method for determining the reserved DCAP space based on the degree of toggle rate, and through software Analyze the information to properly determine the DCAP space plan to achieve the goal of reducing the dynamic voltage and optimizing the circuit configuration.

An embodiment of the present invention provides a method for generating a circuit layout using simulation software, including the following steps: (A). Planning a plurality of blocks on a circuit board, wherein each of the blocks includes: An operation space and a reserved space; (B). Determine the size of the reserved space in the blocks according to at least one specific condition; (C). Decide whether to adjust the step (B) according to at least one judgment condition The size of the reserved space in the blocks determined; and (D). When it is determined in step (C) that no adjustment is required, the size of the reserved space in the blocks determined in step (B) To generate the circuit layout.

202~212, 502~508: steps

FFG1~FFG8: block group

Cell(n)~Cell(n-31): block

DCAP2~DCAP16: reserved capacitor placement space

Figure 1 is a schematic diagram of a circuit layout that reserves DCAP space for conventional technology.

Figure 2 is a block diagram of the circuit layout generated by the present invention.

Figure 3 is a block classification table generated according to the size of the two-state thixotropic rate of the block.

Figure 4 is a schematic diagram of a circuit layout obtained using the architecture shown in Figure 2.

FIG. 5 is a method for generating a circuit layout using simulation software according to an embodiment of the present invention.

Please refer to FIG. 2, which is a block diagram of the circuit layout generated by the present invention. First, in step 202, the bi-state thixotropy data of each area on the circuit board is provided (which can be aggregated into the bi-state thixotropic data) Data sheet). Step 204 is to generate a preliminary block allocation scheme based on the collected two-state thixotropy data and netlist information. At this time, a plurality of blocks are planned on the circuit board, among which Each block contains the operation space for setting components and the DCAP reserved space. The access rate of each block can be obtained through the bi-state thixotropic rate data table.

For step 204, please refer to FIG. 3, which is a block classification table generated according to the size of the two-state thixotropic rate of the block, which is classified into the block cell(n) of the block group FFG1, cell(n-1), cell(n-2), cell(n-3) have the highest two-state thixotropic rate, so it is set to DCAP16 (the larger the number matched with "DCAP", the reserved More space for capacitors). For example, the capacity reserved space allocated to the block set to DCAP8 will be smaller than the capacity reserved space allocated to the block set to DCAP16, and the capacity reserved space allocated to the block set to DCAP4 It will be less than the reserved space of the capacitor allocated to the block set to DCAP8, and so on. Please note that although the example of the present invention uses a capacitor as a solution for voltage decay, the present invention is not limited to this, as long as it can To achieve the same effect, the capacitor can also be replaced with other passive components.

The dotted line in the middle of Figure 3 indicates that the current grouping only uses the four block groups FFG1~FFG4. When finer grouping is required, the dotted line can be used as a pull-down. For example, when the dotted line moves down one column, the grouping of blocks becomes 5 groups. Considering that the total area of the reserved space does not account for too much of the entire block, how small the grouping should be divided (that is, the red line to be pulled down) must be traded off (Trade off). Please note that step 206 can further optimize the placement of components through software functions such as sdc and floorplan to generate candidate circuit layouts.

The above sequence of the blocks is based on the two-state thixotropic rate corresponding to multiple blocks, wherein the reserved space allocated to the block is proportional to its two-state thixotropic rate, that is, the two-state thixotropic rate Probably higher areas will be allocated to larger DCAP areas. In addition, the present invention can also consider whether the block is located at a hot spot (eg, adjacent to the CPU, GPU, DDR, etc.) or adjacent to the hot spot, such as the distance between each block and the hot spot.

In order to make use of the extra circuit space as possible for the purpose of DCAP, and in addition to taking into account DCAP, it can not occupy the important component placement space. In step 208, the present invention can additionally use the "DCAP area does not occupy all blocks "1%~3% of the area (eg 2%)" is used as the judgment condition. This is to consider that if the reserved DCAP space is too large, the efficiency of the overall circuit will be affected. When it is determined that the reserved space exceeds the predetermined value (or predetermined percentage) of the total block surface, the flow must return to steps 204 and 206 to regenerate the candidate circuit layout.

Then, step 210 continues to further examine the candidate circuit layout, if the determined DCAP space of the corresponding block can make the overall dynamic voltage drop (dynamic IR drop) reach The predetermined target uses the current circuit layout as the final output layout, where the predetermined target may be a range that enables the circuit layout to work normally, etc. The present invention is not limited to this.

Please refer to Figure 4. Figure 4 is a schematic diagram of the circuit layout obtained by using the architecture shown in Figure 2. Compared with Figure 1, the circled hot spot location has sufficient DCAP area, and the overall layout There are no large unused areas.

Please refer to FIG. 5, which is a method for generating a circuit layout using simulation software according to an embodiment of the present invention. Please note that if substantially the same results are obtained, these steps do not necessarily need to be executed in the order shown in Figure 5. The method in FIG. 5 can be simply summarized as follows: 502: Plan a plurality of blocks on a circuit board, where each block includes: an operation space and a reserved space; 504: determine this according to at least one specific condition The size of the reserved space in these blocks; 506: According to at least one judgment condition, it is determined whether the determined size of the reserved space in the blocks needs to be corrected. If so, the process returns to step 504; if not, the process enters Step 508; 508: Generate a circuit layout according to the determined size of the reserved space in the blocks.

The skilled person should be able to easily understand the details of each step in Figure 5 after reading the above paragraphs. For the sake of brevity, further description will be omitted here.

In summary, by implementing the technical features of the present invention, the extra space on the circuit board can be properly utilized. In addition, since the present invention uses software to generate the corresponding circuit layout based on the two-state thixotropy data table, it is extremely fast in generation speed and extremely accurate in space utilization, without Large areas that cannot be used are left without sacrificing the placement of important circuit components.

The above are only the preferred embodiments of the present invention, and all changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention.

502~508: steps

Claims (9)

A method for generating circuit layout using simulation software includes the following steps: (A). Plan a plurality of blocks on a circuit board, wherein each of the blocks includes: an operation space and a reserved space ; (B). Determine the size of the reserved space in the blocks according to at least one specific condition; (C). Determine whether to adjust the blocks determined in step (B) according to at least one judgment condition The size of the reserved space; and (D). When step (C) determines that no adjustment is required, the circuit layout is generated according to the size of the reserved space in the blocks determined in step (B); wherein the At least one specific condition includes: a plurality of toggle rates corresponding to the blocks, and the at least one judgment condition includes whether the total reserved space in the blocks exceeds a predetermined value. A method for generating circuit layout using simulation software includes the following steps: (A). Plan a plurality of blocks on a circuit board, wherein each of the blocks includes: an operation space and a reserved space ; (B). Determine the size of the reserved space in the blocks according to at least one specific condition; (C). Determine whether to adjust the blocks determined in step (B) according to at least one judgment condition The size of the reserved space; and (D). When step (C) determines that no adjustment is required, the circuit layout is generated according to the size of the reserved space in the blocks determined in step (B); wherein the At least one specific condition includes: a plurality of toggle rates corresponding to the blocks, and the at least one judgment condition includes: the reserved space in the blocks determined in step (B) Whether the size makes the overall dynamic voltage attenuation reach the predetermined goal. A method for generating circuit layout using simulation software includes the following steps: (A). Plan a plurality of blocks on a circuit board, wherein each of the blocks includes: an operation space and a reserved space ; (B). Determine the size of the reserved space in the blocks according to at least one specific condition; (C). Determine whether to adjust the blocks determined in step (B) according to at least one judgment condition The size of the reserved space; and (D). When step (C) determines that no adjustment is required, the circuit layout is generated according to the size of the reserved space in the blocks determined in step (B); wherein the At least one specific condition further includes: whether the blocks are located in hotspots, or the distance between each block in the blocks and the hotspot, and the at least one judgment condition includes: the total Whether the reserved space exceeds a predetermined value. A method for generating circuit layout using simulation software includes the following steps: (A). Plan a plurality of blocks on a circuit board, wherein each of the blocks includes: an operation space and a reserved space ; (B). Determine the size of the reserved space in the blocks according to at least one specific condition; (C). Determine whether to adjust the blocks determined in step (B) according to at least one judgment condition The size of the reserved space; and (D). When step (C) determines that no adjustment is required, the circuit layout is generated according to the size of the reserved space in the blocks determined in step (B); wherein the At least one specific condition further includes: whether the blocks are located in a hotspot, or the distance between each of the blocks and the hotspot, and the at least one judgment condition includes: the determination in step (B) Does the size of the reserved space in these blocks make the overall dynamic Whether the voltage attenuation has reached the predetermined target. The method according to claims 1 to 4, wherein when it is determined in step (C) that adjustment is necessary, skip to step (A). The method according to claim 1 to 2, wherein step (B) further comprises: sorting the blocks according to the magnitude of the two-state thixotropy corresponding to the blocks, wherein the blocks are allocated to The reserved space is proportional to its two-state thixotropic rate. The method of claim 1, wherein the predetermined value is a predetermined percentage of the total area of the blocks, and the predetermined percentage is 1%~3%. The method according to claim 2, wherein the predetermined target is a state where the circuit layout can maintain normal operation. The method according to claim 1 to 4, wherein the reserved space in the blocks is used to set a capacitor.

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