TWI684017B - Bump testing apparatus and method - Google Patents
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- 238000012360 testing method Methods 0.000 title claims abstract description 63
- 238000000034 method Methods 0.000 title claims description 10
- 239000000758 substrate Substances 0.000 claims abstract description 51
- 239000000463 material Substances 0.000 claims description 27
- 238000010998 test method Methods 0.000 claims description 14
- 238000005259 measurement Methods 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 claims description 10
- 229910000679 solder Inorganic materials 0.000 claims description 8
- 230000008569 process Effects 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 238000005516 engineering process Methods 0.000 description 7
- 230000007246 mechanism Effects 0.000 description 6
- 238000005336 cracking Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000001179 sorption measurement Methods 0.000 description 3
- 230000009471 action Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000003801 milling Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009658 destructive testing Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
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Abstract
Description
本發明係關於一種應用於封裝製程之測試設備,特別是關於一種凸塊測試設備及方法。 The invention relates to a testing device applied in a packaging process, in particular to a bump testing device and method.
習知覆晶式球柵陣列(Flip-Chip Ball Grid Array,簡稱FCBGA)接合封裝技術係如第1圖所示,主要於一半導體晶片11之作用面11a上藉由複數導電凸塊13電性連接至封裝基板10上,以縮減整體半導體封裝件1之體積。
The conventional Flip-Chip Ball Grid Array (FCBGA) bonding and packaging technology is shown in FIG. 1, mainly on the
於進行覆晶接合製程前,會先判定該封裝基板10之銲墊12上的導電凸塊13之結構強度是否足夠。習知判定該導電凸塊13之結構強度之作業係藉由如第2A至2D圖之推力試驗(shear test)以確認每一個導電凸塊13之結構強度。
Before the flip chip bonding process is performed, it is determined whether the structural strength of the
具體地,如第2A圖所示,利用一推力機構8對結合在該銲墊12上的導電凸塊13進行推力試驗之破壞性檢測。
Specifically, as shown in FIG. 2A, a
因此,當該導電凸塊13與銲墊12之間的結合性良好時(即該導電凸塊13可承受較大的應力作用),該導電凸塊13受力推落時之破壞模式(failure mode)會發生在該導電凸塊13之本體處,亦即會有部分導電凸塊13a之材料殘
留在該銲墊12上,如第2B圖所示。另一方面,若該導電凸塊13與該銲墊12之間的結合性差時(即該導電凸塊13無法承受較大應力作用),該導電凸塊13受力推落時之破壞模式會發生在該導電凸塊13與該銲墊12之交界處,亦即該導電凸塊13會自該銲墊12上整塊性脫落,而不會殘留任何該導電凸塊13之材料於該銲墊12上,如第2C圖所示。
Therefore, when the bonding between the
惟,習知推力機構8一次只能針對一個導電凸塊13進行推力試驗,故若針對一組陣列排設之多個導電凸塊13進行推力試驗作業,將極為耗時。
However, the
再者,於進行推力試驗時,該推力機構8容易碰撞該封裝基板10上之防銲層(soder mask),致使該封裝基板10破裂。
Furthermore, during the thrust test, the
又,該封裝基板10會有翹曲現象,如第2D圖所示,使得該封裝基板10上之每一個導電凸塊13並非位在同一水平高度上,故於推力試驗過程中,並無法精確地針對每一個導電凸塊13進行同一部位之推力破壞,導致測試結果不準確。例如,該推力機構8對於其中一部分的導電凸塊13係僅於其頂部1/3部位A發生推壓,而對於另一部分的導電凸塊13係於其頂部2/3部位B發生推壓,其中,由於該推力機構8係僅於該導電凸塊1/3部位A發生推壓,故即使該導電凸塊13與該銲墊12之間的結合性差,仍不會發生如第2C圖所示之情況,因而無法有效發現結合性不佳的狀況。
In addition, the
因此,如何克服上述習知技術中之種種問題,實已成目前亟欲解決的課題。 Therefore, how to overcome the various problems in the above-mentioned conventional technologies has become an urgent problem to be solved at present.
鑑於上述習知技術之種種缺失,本發明遂提供一種凸塊測試設備,係包括:承載裝置,係用以承載結合有複數導電凸塊之基板結構;量測裝置,係用以量測各該導電凸塊之高度;以及移除裝置,係用以移除至少一該導電凸塊之部分材質。 In view of the above-mentioned defects of the prior art, the present invention provides a bump testing device, which includes: a carrying device for carrying a substrate structure incorporating a plurality of conductive bumps; a measuring device for measuring each The height of the conductive bump; and the removal device, which is used to remove at least a part of the material of the conductive bump.
本發明亦提供一種凸塊測試方法,係包括:提供一結合有複數導電凸塊之基板結構;量測各該導電凸塊之高度;以及移除至少一該導電凸塊之部分材質。 The invention also provides a bump testing method, which includes: providing a substrate structure combined with a plurality of conductive bumps; measuring the height of each conductive bump; and removing at least a part of the material of the conductive bump.
前述之凸塊測試方法及設備中,該基板結構係為封裝基板、矽中介板或半導體晶片。 In the aforementioned bump test method and device, the substrate structure is a package substrate, a silicon interposer, or a semiconductor chip.
前述之凸塊測試方法及設備中,該導電凸塊係為銲球或金屬柱。 In the aforementioned bump testing method and device, the conductive bump is a solder ball or a metal pillar.
前述之凸塊測試方法及設備中,該基板結構係以真空吸附方式定位。例如,該承載裝置係以真空吸附方式定位該基板結構。 In the aforementioned bump test method and equipment, the substrate structure is positioned by vacuum adsorption. For example, the carrier device positions the substrate structure by vacuum suction.
前述之凸塊測試方法及設備中,各該導電凸塊之高度係以光感方式量測。例如,該量測裝置係以光感方式量測各該導電凸塊之高度。 In the aforementioned bump testing method and device, the height of each conductive bump is measured by light sensing. For example, the measuring device measures the height of each conductive bump in a light-sensitive manner.
前述之凸塊測試方法及設備中,該導電凸塊之部分材質係藉由切削方式移除。例如,該移除裝置係以切削方式移除至少一該導電凸塊之部分材質。 In the aforementioned bump test method and equipment, part of the material of the conductive bump is removed by cutting. For example, the removing device removes at least one part of the material of the conductive bump by cutting.
前述之凸塊測試方法及設備中,先依據量測結果進行該導電凸塊之高度補償,再移除至少一該導電凸塊之部分材質。例如,該移除裝置於移除至少一該導電凸塊之部分材質後,各該導電凸塊之高度係相同。 In the aforementioned bump test method and device, the height of the conductive bump is compensated according to the measurement result, and then at least a part of the material of the conductive bump is removed. For example, after the removal device removes at least one part of the material of the conductive bump, the height of each conductive bump is the same.
前述之凸塊測試方法及設備中,於移除至少一該導電凸塊之部分材質之過程中同時進行推力試驗。例如,該移除裝置於移除至少一該導電凸塊之部分材質之過程中同時併進行推力試驗。 In the aforementioned bump test method and device, a thrust test is performed simultaneously during the process of removing at least one material of the conductive bump. For example, the removal device simultaneously performs a thrust test while removing at least one material of the conductive bump.
由上可知,本發明之凸塊測試方法及設備中,主要藉由移除該些導電凸塊之部分材質,同時一併進行推力試驗,故相較於習知技術之一次只能針對一個導電凸塊進行推力試驗之方法,本發明之凸塊測試方法能一次針對全部導電凸塊進行推力試驗作業,因而能大幅縮減時程。 It can be seen from the above that in the bump testing method and apparatus of the present invention, the material of these conductive bumps is mainly removed, and the thrust test is also performed at the same time, so compared to the conventional technology, only one conductive A method for performing a thrust test on a bump. The bump test method of the present invention can perform a thrust test operation on all conductive bumps at one time, thereby greatly reducing the time course.
再者,本發明係可依據量測裝置之量測結果進行該導電凸塊之高度補償,使該移除裝置能沿著該基板結構之翹曲表面移動,故相較於習知技術,本發明於進行推力試驗時,該移除裝置不會碰撞該基板結構,因而能避免該基板結構破裂。 Furthermore, the present invention can compensate the height of the conductive bump according to the measurement result of the measurement device, so that the removal device can move along the warped surface of the substrate structure, so compared with the conventional technology, the present According to the invention, when the thrust test is performed, the removal device does not collide with the substrate structure, so that the substrate structure can be prevented from cracking.
又,本發明之移除裝置係沿著該基板結構之翹曲表面移動,故相較於習知技術,該移除裝置於推力試驗過程中,能精確地針對每一個導電凸塊進行同一部位之推力破壞,因而大幅提高測試結果之準確性。 In addition, the removal device of the present invention moves along the warped surface of the substrate structure, so compared with the conventional technology, the removal device can accurately perform the same part for each conductive bump during the thrust test The thrust is destroyed, thus greatly improving the accuracy of the test results.
1‧‧‧半導體封裝件 1‧‧‧Semiconductor package
10‧‧‧封裝基板 10‧‧‧Package substrate
11‧‧‧半導體晶片 11‧‧‧Semiconductor chip
11a‧‧‧作用面 11a‧‧‧action surface
12,90‧‧‧銲墊 12,90‧‧‧solder pad
13,13a,3,4‧‧‧導電凸塊 13,13a,3,4‧‧‧ conductive bump
2‧‧‧凸塊測試設備 2‧‧‧Bump testing equipment
20‧‧‧承載裝置 20‧‧‧Bearing device
20a‧‧‧真空平台 20a‧‧‧Vacuum platform
21‧‧‧量測裝置 21‧‧‧Measuring device
22‧‧‧移除裝置 22‧‧‧Remove device
8‧‧‧推力機構 8‧‧‧Thrust mechanism
9‧‧‧基板結構 9‧‧‧Substrate structure
A,B‧‧‧部位 A, B‧‧‧ parts
F‧‧‧吸附力方向 F‧‧‧Adsorption force direction
H,h‧‧‧高度 H, h‧‧‧ height
L‧‧‧基準平面 L‧‧‧Datum plane
P‧‧‧光線 P‧‧‧Light
S‧‧‧移動路徑 S‧‧‧Moving path
X,Z‧‧‧移動方向 X,Z‧‧‧Movement direction
第1圖係為習知覆晶式半導體封裝件之剖視示意圖; 第2A圖係為習知推力試驗之側面示意圖;第2B及2C圖係為習知推力試驗之各種結果之側面示意圖;第2D圖係為習知封裝基板發生翹曲並進行推力試驗之剖視示意圖;第3A至3C圖係為本發明之凸塊測試方法之流程之側面示意圖;以及第3D圖係為第3C圖之局部放大示意圖。 Figure 1 is a schematic cross-sectional view of a conventional flip chip semiconductor package; Figure 2A is a schematic side view of a conventional thrust test; Figures 2B and 2C are schematic side views of various results of a conventional thrust test; Figure 2D is a cross-sectional view of a conventional package substrate warping and performing a thrust test Schematic diagrams; Figures 3A to 3C are side schematic diagrams of the flow of the bump testing method of the present invention; and Figure 3D is a partially enlarged schematic diagram of Figure 3C.
以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。 The following describes the implementation of the present invention by specific specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.
須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用於配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用於限定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中所引用之如「上」及「一」等之用語,亦僅為便於敘述之明瞭,而非用於限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。 It should be noted that the structure, proportion, size, etc. shown in the drawings in this specification are only used to match the contents disclosed in the specification, for those who are familiar with this skill to understand and read, not to limit the implementation of the present invention The limited conditions do not have technical significance. Any modification of structure, change of proportional relationship or adjustment of size should still fall within the scope of the invention without affecting the efficacy and the purpose of the invention. The technical content disclosed by the invention can be covered. At the same time, the terms such as "上" and "一" cited in this specification are only for the convenience of description, and are not used to limit the scope of the invention. The relative relationship is changed or adjusted. Substantially changing the technical content should also be regarded as the scope of the invention.
請參閱第3A至3C圖,係為本發明之凸塊測試方法之側面示意圖。 Please refer to FIGS. 3A to 3C, which are schematic side views of the bump testing method of the present invention.
如第3A圖所示,提供一結合有複數導電凸塊3之基板結構9,且將該基板結構9置放於一承載裝置20上。接著,藉由一量測裝置21量測各該導電凸塊3之高度h。
As shown in FIG. 3A, a
於本實施例中,該基板結構9係為覆晶式封裝基板、矽中介板或覆晶式半導體晶片,且該導電凸塊3係為銲球或如銅柱之金屬柱。
In this embodiment, the
再者,該承載裝置20係包含一承載該基板結構9之真空平台20a,且以定位推桿(圖略)將該基板結構9定位,並以真空吸附方式(如第3A圖所示之吸附力方向F)固定住該基板結構9。
Furthermore, the carrying
又,該量測裝置21係以如第3A圖所示之移動方向X透過光感方式(如第3A圖所示之光線P)量測各該導電凸塊3之高度h。具體地,該量測裝置21以雷射光依據該基板結構9之各部位之翹曲(warpage)程度量測各該導電凸塊3相對同一平面(如基準平面L或該真空平台20a)之高度h。
In addition, the measuring
如第3B至3C圖所示,藉由一移除裝置22移除該些導電凸塊3之部分材質(如第3B圖所示之移動方向Z)。
As shown in FIGS. 3B to 3C, part of the material of the
於本實施例中,該移除裝置22係以切削方式(如銑刀之銑削)移除至少一該導電凸塊3之部分材質。
In this embodiment, the removing
再者,該移除裝置22係依據該量測裝置21之量測結果進行該導電凸塊3之高度補償,使該移除裝置22沿著該基板結構9之翹曲表面移動(如第3B圖所示之移動路徑S),以於移除作業後,各該導電凸塊4之高度H相同,如
第3D圖所示之整平結果。
Furthermore, the
又,於移除該些導電凸塊3之部分材質之過程中,該移除裝置22會接觸該些導電凸塊3,故可一併進行推力試驗,以確認每一個導電凸塊3之結構強度。
In addition, in the process of removing part of the materials of the
因此,本發明之凸塊測試方法係藉由移除該些導電凸塊3之部分材質,同時一併進行推力試驗,故相較於習知技術之一次只能針對一個導電凸塊13進行推力試驗之方法,本發明之凸塊測試方法能一次針對一組陣列排設之全部導電凸塊3進行推力試驗作業,因而能大幅縮減時程。
Therefore, the bump testing method of the present invention removes part of the materials of the
再者,本發明之凸塊測試方法係依據量測裝置21之量測結果進行該導電凸塊3之高度補償,使該移除裝置22能沿著該基板結構9之翹曲表面移動,故相較於習知技術,本發明之凸塊測試方法於進行推力試驗時,該移除裝置22不會碰撞該基板結構9,因而能避免該基板結構9破裂。
Furthermore, the bump testing method of the present invention performs height compensation of the
又,本發明之凸塊測試方法所用之移除裝置22係沿著該基板結構9之翹曲表面移動,故相較於習知技術,該移除裝置22於推力試驗過程中,能精確地針對每一個導電凸塊3進行同一部位之推力破壞,因而大幅提高測試結果之準確性。例如,該移除裝置22對於每一個導電凸塊3均於其頂面2/3部位發生推壓,故當該導電凸塊3與該基板結構9之銲墊90之間的結合性較差時,將發生該導電凸塊3會自該銲墊90上整塊性脫落(如第2C圖所示之情況),因而能有效發現結合性不佳的狀況。
In addition, the
本發明亦提供一種凸塊測試設備2,係包括:一承載裝置20、一量測裝置21以及一移除裝置22。
The invention also provides a
所述之承載裝置20係用以承載一結合有複數導電凸塊3,4之基板結構9。
The carrying
所述之量測裝置21係用以量測各該導電凸塊3之高度h。
The measuring
所述之移除裝置22係用以移除至少一該導電凸塊3之部分材質。
The
於一實施例中,該基板結構9係為封裝基板、矽中介板或半導體晶片,且該導電凸塊3,4係為銲球或金屬柱。
In one embodiment, the
於一實施例中,該承載裝置20係以真空吸附方式定位該基板結構9。
In one embodiment, the
於一實施例中,該量測裝置21係以光感方式量測各該導電凸塊3之高度h。
In one embodiment, the measuring
於一實施例中,該移除裝置22係以切削方式移除至少一該導電凸塊3之部分材質,且該移除裝置22於移除至少一該導電凸塊3之部分材質後,各該導電凸塊4之高度H係相同。
In one embodiment, the
於一實施例中,該移除裝置22於移除至少一該導電凸塊3之部分材質之過程中係一併進行推力試驗。
In an embodiment, the
綜上所述,本發明之凸塊測試方法及設備中,係藉由移除該些導電凸塊之部分材質,同時一併進行推力試驗,故能一次針對全部導電凸塊進行推力試驗作業,因而能大幅縮減時程。 In summary, in the bump testing method and apparatus of the present invention, by removing part of the materials of the conductive bumps and simultaneously performing the thrust test, the thrust test operation can be performed on all conductive bumps at once, Therefore, the time course can be greatly reduced.
再者,本發明能依據量測裝置之量測結果進行該導電凸塊之高度補償,故於進行推力試驗時,該凸塊測試設備不僅不會碰撞該基板結構而能避免該基板結構破裂,且能精確地針對所有導電凸塊進行同部位之推力破壞而令測試結果為正確。 Furthermore, the present invention can compensate for the height of the conductive bump according to the measurement result of the measurement device, so that during the thrust test, the bump test equipment not only does not collide with the substrate structure but can avoid the substrate structure from cracking, And it can accurately destroy the thrust of the same part of all conductive bumps to make the test result correct.
上述實施例係用於例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。 The above embodiments are used to exemplify the principles and effects of the present invention, rather than to limit the present invention. Anyone who is familiar with this skill can modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the rights of the present invention should be as listed in the scope of patent application mentioned later.
2‧‧‧凸塊測試設備 2‧‧‧Bump testing equipment
20‧‧‧承載裝置 20‧‧‧Bearing device
20a‧‧‧真空平台 20a‧‧‧Vacuum platform
21‧‧‧量測裝置 21‧‧‧Measuring device
22‧‧‧移除裝置 22‧‧‧Remove device
4‧‧‧導電凸塊 4‧‧‧ conductive bump
9‧‧‧基板結構 9‧‧‧Substrate structure
F‧‧‧吸附力方向 F‧‧‧Adsorption force direction
Claims (15)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW107105257A TWI684017B (en) | 2018-02-13 | 2018-02-13 | Bump testing apparatus and method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW107105257A TWI684017B (en) | 2018-02-13 | 2018-02-13 | Bump testing apparatus and method |
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| TW201935022A TW201935022A (en) | 2019-09-01 |
| TWI684017B true TWI684017B (en) | 2020-02-01 |
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| Application Number | Title | Priority Date | Filing Date |
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| TW107105257A TWI684017B (en) | 2018-02-13 | 2018-02-13 | Bump testing apparatus and method |
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| Country | Link |
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| TW (1) | TWI684017B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6078387A (en) * | 1997-11-20 | 2000-06-20 | Dage Precision Industries, Ltd. | Test apparatus |
| US20010053197A1 (en) * | 2000-06-14 | 2001-12-20 | Kei Murayama | Method and apparatus for measuring a bump on a substrate |
| TW200723419A (en) * | 2005-12-01 | 2007-06-16 | Siliconware Precision Industries Co Ltd | Lead-free solder bump |
-
2018
- 2018-02-13 TW TW107105257A patent/TWI684017B/en active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6078387A (en) * | 1997-11-20 | 2000-06-20 | Dage Precision Industries, Ltd. | Test apparatus |
| US20010053197A1 (en) * | 2000-06-14 | 2001-12-20 | Kei Murayama | Method and apparatus for measuring a bump on a substrate |
| TW200723419A (en) * | 2005-12-01 | 2007-06-16 | Siliconware Precision Industries Co Ltd | Lead-free solder bump |
Also Published As
| Publication number | Publication date |
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| TW201935022A (en) | 2019-09-01 |
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