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TWI684017B - Bump testing apparatus and method - Google Patents

Bump testing apparatus and method Download PDF

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Publication number
TWI684017B
TWI684017B TW107105257A TW107105257A TWI684017B TW I684017 B TWI684017 B TW I684017B TW 107105257 A TW107105257 A TW 107105257A TW 107105257 A TW107105257 A TW 107105257A TW I684017 B TWI684017 B TW I684017B
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bump
conductive bump
conductive
item
patent application
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TW107105257A
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TW201935022A (en
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林恩立
王維賓
陳金發
李聰明
鄭坤一
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矽品精密工業股份有限公司
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Abstract

A bump testing method is provided, including measuring the height of a plurality of conductive bumps disposed on a substrate structure, removing a portion of the conductive bumps, and conducting a thrust experiment, to allow all the conducive bumps to have the same height. The bump testing method conducts the thrust experiment on all of the conductive bumps at the same time, and the required to conduct the test is greatly reduced. The present invention also provides a bump testing apparatus.

Description

凸塊測試設備及方法 Bump test equipment and method

本發明係關於一種應用於封裝製程之測試設備,特別是關於一種凸塊測試設備及方法。 The invention relates to a testing device applied in a packaging process, in particular to a bump testing device and method.

習知覆晶式球柵陣列(Flip-Chip Ball Grid Array,簡稱FCBGA)接合封裝技術係如第1圖所示,主要於一半導體晶片11之作用面11a上藉由複數導電凸塊13電性連接至封裝基板10上,以縮減整體半導體封裝件1之體積。 The conventional Flip-Chip Ball Grid Array (FCBGA) bonding and packaging technology is shown in FIG. 1, mainly on the action surface 11a of a semiconductor chip 11 by a plurality of conductive bumps 13 electrically Connected to the package substrate 10 to reduce the volume of the overall semiconductor package 1.

於進行覆晶接合製程前,會先判定該封裝基板10之銲墊12上的導電凸塊13之結構強度是否足夠。習知判定該導電凸塊13之結構強度之作業係藉由如第2A至2D圖之推力試驗(shear test)以確認每一個導電凸塊13之結構強度。 Before the flip chip bonding process is performed, it is determined whether the structural strength of the conductive bumps 13 on the bonding pads 12 of the package substrate 10 is sufficient. The conventional operation to determine the structural strength of the conductive bump 13 is to confirm the structural strength of each conductive bump 13 by a shear test as shown in FIGS. 2A to 2D.

具體地,如第2A圖所示,利用一推力機構8對結合在該銲墊12上的導電凸塊13進行推力試驗之破壞性檢測。 Specifically, as shown in FIG. 2A, a thrust mechanism 8 is used to conduct destructive testing of the conductive bump 13 bonded to the pad 12 by a thrust test.

因此,當該導電凸塊13與銲墊12之間的結合性良好時(即該導電凸塊13可承受較大的應力作用),該導電凸塊13受力推落時之破壞模式(failure mode)會發生在該導電凸塊13之本體處,亦即會有部分導電凸塊13a之材料殘 留在該銲墊12上,如第2B圖所示。另一方面,若該導電凸塊13與該銲墊12之間的結合性差時(即該導電凸塊13無法承受較大應力作用),該導電凸塊13受力推落時之破壞模式會發生在該導電凸塊13與該銲墊12之交界處,亦即該導電凸塊13會自該銲墊12上整塊性脫落,而不會殘留任何該導電凸塊13之材料於該銲墊12上,如第2C圖所示。 Therefore, when the bonding between the conductive bump 13 and the pad 12 is good (that is, the conductive bump 13 can withstand a large stress), the failure mode of the conductive bump 13 when it is pushed down by force (failure mode) will occur at the body of the conductive bump 13, that is, part of the material of the conductive bump 13a will remain It remains on the pad 12 as shown in FIG. 2B. On the other hand, if the bonding between the conductive bump 13 and the pad 12 is poor (ie, the conductive bump 13 cannot bear a large stress), the failure mode of the conductive bump 13 when pushed down Occurs at the junction of the conductive bump 13 and the pad 12, that is, the conductive bump 13 will be completely detached from the pad 12 without leaving any material of the conductive bump 13 in the solder On the pad 12, as shown in FIG. 2C.

惟,習知推力機構8一次只能針對一個導電凸塊13進行推力試驗,故若針對一組陣列排設之多個導電凸塊13進行推力試驗作業,將極為耗時。 However, the conventional thrust mechanism 8 can only perform a thrust test on one conductive bump 13 at a time. Therefore, if a thrust test is performed on a plurality of conductive bumps 13 arranged in a group, it will be extremely time-consuming.

再者,於進行推力試驗時,該推力機構8容易碰撞該封裝基板10上之防銲層(soder mask),致使該封裝基板10破裂。 Furthermore, during the thrust test, the thrust mechanism 8 is likely to collide with the soder mask on the package substrate 10, causing the package substrate 10 to crack.

又,該封裝基板10會有翹曲現象,如第2D圖所示,使得該封裝基板10上之每一個導電凸塊13並非位在同一水平高度上,故於推力試驗過程中,並無法精確地針對每一個導電凸塊13進行同一部位之推力破壞,導致測試結果不準確。例如,該推力機構8對於其中一部分的導電凸塊13係僅於其頂部1/3部位A發生推壓,而對於另一部分的導電凸塊13係於其頂部2/3部位B發生推壓,其中,由於該推力機構8係僅於該導電凸塊1/3部位A發生推壓,故即使該導電凸塊13與該銲墊12之間的結合性差,仍不會發生如第2C圖所示之情況,因而無法有效發現結合性不佳的狀況。 In addition, the package substrate 10 may have a warping phenomenon, as shown in FIG. 2D, so that each conductive bump 13 on the package substrate 10 is not at the same level, so it is not accurate during the thrust test For each conductive bump 13, ground thrust destruction is performed at the same location, resulting in inaccurate test results. For example, the thrust mechanism 8 pushes a portion of the conductive bump 13 only at the top 1/3 part A, and pushes another part of the conductive bump 13 at the top 2/3 part B. Wherein, since the thrust mechanism 8 only presses at the 1/3 part A of the conductive bump, even if the bonding between the conductive bump 13 and the pad 12 is poor, it will not occur as shown in FIG. 2C As shown, it is not possible to effectively detect the situation of poor binding.

因此,如何克服上述習知技術中之種種問題,實已成目前亟欲解決的課題。 Therefore, how to overcome the various problems in the above-mentioned conventional technologies has become an urgent problem to be solved at present.

鑑於上述習知技術之種種缺失,本發明遂提供一種凸塊測試設備,係包括:承載裝置,係用以承載結合有複數導電凸塊之基板結構;量測裝置,係用以量測各該導電凸塊之高度;以及移除裝置,係用以移除至少一該導電凸塊之部分材質。 In view of the above-mentioned defects of the prior art, the present invention provides a bump testing device, which includes: a carrying device for carrying a substrate structure incorporating a plurality of conductive bumps; a measuring device for measuring each The height of the conductive bump; and the removal device, which is used to remove at least a part of the material of the conductive bump.

本發明亦提供一種凸塊測試方法,係包括:提供一結合有複數導電凸塊之基板結構;量測各該導電凸塊之高度;以及移除至少一該導電凸塊之部分材質。 The invention also provides a bump testing method, which includes: providing a substrate structure combined with a plurality of conductive bumps; measuring the height of each conductive bump; and removing at least a part of the material of the conductive bump.

前述之凸塊測試方法及設備中,該基板結構係為封裝基板、矽中介板或半導體晶片。 In the aforementioned bump test method and device, the substrate structure is a package substrate, a silicon interposer, or a semiconductor chip.

前述之凸塊測試方法及設備中,該導電凸塊係為銲球或金屬柱。 In the aforementioned bump testing method and device, the conductive bump is a solder ball or a metal pillar.

前述之凸塊測試方法及設備中,該基板結構係以真空吸附方式定位。例如,該承載裝置係以真空吸附方式定位該基板結構。 In the aforementioned bump test method and equipment, the substrate structure is positioned by vacuum adsorption. For example, the carrier device positions the substrate structure by vacuum suction.

前述之凸塊測試方法及設備中,各該導電凸塊之高度係以光感方式量測。例如,該量測裝置係以光感方式量測各該導電凸塊之高度。 In the aforementioned bump testing method and device, the height of each conductive bump is measured by light sensing. For example, the measuring device measures the height of each conductive bump in a light-sensitive manner.

前述之凸塊測試方法及設備中,該導電凸塊之部分材質係藉由切削方式移除。例如,該移除裝置係以切削方式移除至少一該導電凸塊之部分材質。 In the aforementioned bump test method and equipment, part of the material of the conductive bump is removed by cutting. For example, the removing device removes at least one part of the material of the conductive bump by cutting.

前述之凸塊測試方法及設備中,先依據量測結果進行該導電凸塊之高度補償,再移除至少一該導電凸塊之部分材質。例如,該移除裝置於移除至少一該導電凸塊之部分材質後,各該導電凸塊之高度係相同。 In the aforementioned bump test method and device, the height of the conductive bump is compensated according to the measurement result, and then at least a part of the material of the conductive bump is removed. For example, after the removal device removes at least one part of the material of the conductive bump, the height of each conductive bump is the same.

前述之凸塊測試方法及設備中,於移除至少一該導電凸塊之部分材質之過程中同時進行推力試驗。例如,該移除裝置於移除至少一該導電凸塊之部分材質之過程中同時併進行推力試驗。 In the aforementioned bump test method and device, a thrust test is performed simultaneously during the process of removing at least one material of the conductive bump. For example, the removal device simultaneously performs a thrust test while removing at least one material of the conductive bump.

由上可知,本發明之凸塊測試方法及設備中,主要藉由移除該些導電凸塊之部分材質,同時一併進行推力試驗,故相較於習知技術之一次只能針對一個導電凸塊進行推力試驗之方法,本發明之凸塊測試方法能一次針對全部導電凸塊進行推力試驗作業,因而能大幅縮減時程。 It can be seen from the above that in the bump testing method and apparatus of the present invention, the material of these conductive bumps is mainly removed, and the thrust test is also performed at the same time, so compared to the conventional technology, only one conductive A method for performing a thrust test on a bump. The bump test method of the present invention can perform a thrust test operation on all conductive bumps at one time, thereby greatly reducing the time course.

再者,本發明係可依據量測裝置之量測結果進行該導電凸塊之高度補償,使該移除裝置能沿著該基板結構之翹曲表面移動,故相較於習知技術,本發明於進行推力試驗時,該移除裝置不會碰撞該基板結構,因而能避免該基板結構破裂。 Furthermore, the present invention can compensate the height of the conductive bump according to the measurement result of the measurement device, so that the removal device can move along the warped surface of the substrate structure, so compared with the conventional technology, the present According to the invention, when the thrust test is performed, the removal device does not collide with the substrate structure, so that the substrate structure can be prevented from cracking.

又,本發明之移除裝置係沿著該基板結構之翹曲表面移動,故相較於習知技術,該移除裝置於推力試驗過程中,能精確地針對每一個導電凸塊進行同一部位之推力破壞,因而大幅提高測試結果之準確性。 In addition, the removal device of the present invention moves along the warped surface of the substrate structure, so compared with the conventional technology, the removal device can accurately perform the same part for each conductive bump during the thrust test The thrust is destroyed, thus greatly improving the accuracy of the test results.

1‧‧‧半導體封裝件 1‧‧‧Semiconductor package

10‧‧‧封裝基板 10‧‧‧Package substrate

11‧‧‧半導體晶片 11‧‧‧Semiconductor chip

11a‧‧‧作用面 11a‧‧‧action surface

12,90‧‧‧銲墊 12,90‧‧‧solder pad

13,13a,3,4‧‧‧導電凸塊 13,13a,3,4‧‧‧ conductive bump

2‧‧‧凸塊測試設備 2‧‧‧Bump testing equipment

20‧‧‧承載裝置 20‧‧‧Bearing device

20a‧‧‧真空平台 20a‧‧‧Vacuum platform

21‧‧‧量測裝置 21‧‧‧Measuring device

22‧‧‧移除裝置 22‧‧‧Remove device

8‧‧‧推力機構 8‧‧‧Thrust mechanism

9‧‧‧基板結構 9‧‧‧Substrate structure

A,B‧‧‧部位 A, B‧‧‧ parts

F‧‧‧吸附力方向 F‧‧‧Adsorption force direction

H,h‧‧‧高度 H, h‧‧‧ height

L‧‧‧基準平面 L‧‧‧Datum plane

P‧‧‧光線 P‧‧‧Light

S‧‧‧移動路徑 S‧‧‧Moving path

X,Z‧‧‧移動方向 X,Z‧‧‧Movement direction

第1圖係為習知覆晶式半導體封裝件之剖視示意圖; 第2A圖係為習知推力試驗之側面示意圖;第2B及2C圖係為習知推力試驗之各種結果之側面示意圖;第2D圖係為習知封裝基板發生翹曲並進行推力試驗之剖視示意圖;第3A至3C圖係為本發明之凸塊測試方法之流程之側面示意圖;以及第3D圖係為第3C圖之局部放大示意圖。 Figure 1 is a schematic cross-sectional view of a conventional flip chip semiconductor package; Figure 2A is a schematic side view of a conventional thrust test; Figures 2B and 2C are schematic side views of various results of a conventional thrust test; Figure 2D is a cross-sectional view of a conventional package substrate warping and performing a thrust test Schematic diagrams; Figures 3A to 3C are side schematic diagrams of the flow of the bump testing method of the present invention; and Figure 3D is a partially enlarged schematic diagram of Figure 3C.

以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。 The following describes the implementation of the present invention by specific specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用於配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用於限定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中所引用之如「上」及「一」等之用語,亦僅為便於敘述之明瞭,而非用於限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。 It should be noted that the structure, proportion, size, etc. shown in the drawings in this specification are only used to match the contents disclosed in the specification, for those who are familiar with this skill to understand and read, not to limit the implementation of the present invention The limited conditions do not have technical significance. Any modification of structure, change of proportional relationship or adjustment of size should still fall within the scope of the invention without affecting the efficacy and the purpose of the invention. The technical content disclosed by the invention can be covered. At the same time, the terms such as "上" and "一" cited in this specification are only for the convenience of description, and are not used to limit the scope of the invention. The relative relationship is changed or adjusted. Substantially changing the technical content should also be regarded as the scope of the invention.

請參閱第3A至3C圖,係為本發明之凸塊測試方法之側面示意圖。 Please refer to FIGS. 3A to 3C, which are schematic side views of the bump testing method of the present invention.

如第3A圖所示,提供一結合有複數導電凸塊3之基板結構9,且將該基板結構9置放於一承載裝置20上。接著,藉由一量測裝置21量測各該導電凸塊3之高度h。 As shown in FIG. 3A, a substrate structure 9 incorporating a plurality of conductive bumps 3 is provided, and the substrate structure 9 is placed on a carrier device 20. Next, the height h of each conductive bump 3 is measured by a measuring device 21.

於本實施例中,該基板結構9係為覆晶式封裝基板、矽中介板或覆晶式半導體晶片,且該導電凸塊3係為銲球或如銅柱之金屬柱。 In this embodiment, the substrate structure 9 is a flip chip package substrate, a silicon interposer or a flip chip semiconductor chip, and the conductive bump 3 is a solder ball or a metal pillar such as a copper pillar.

再者,該承載裝置20係包含一承載該基板結構9之真空平台20a,且以定位推桿(圖略)將該基板結構9定位,並以真空吸附方式(如第3A圖所示之吸附力方向F)固定住該基板結構9。 Furthermore, the carrying device 20 includes a vacuum platform 20a carrying the substrate structure 9, and the substrate structure 9 is positioned by a positioning pusher (not shown), and is vacuum adsorbed (as shown in FIG. 3A). The force direction F) fixes the substrate structure 9.

又,該量測裝置21係以如第3A圖所示之移動方向X透過光感方式(如第3A圖所示之光線P)量測各該導電凸塊3之高度h。具體地,該量測裝置21以雷射光依據該基板結構9之各部位之翹曲(warpage)程度量測各該導電凸塊3相對同一平面(如基準平面L或該真空平台20a)之高度h。 In addition, the measuring device 21 measures the height h of each conductive bump 3 by a light-sensing method (light P as shown in FIG. 3A) in the moving direction X shown in FIG. 3A. Specifically, the measuring device 21 measures the height of each conductive bump 3 relative to the same plane (such as the reference plane L or the vacuum platform 20a) according to the degree of warpage of each part of the substrate structure 9 using laser light h.

如第3B至3C圖所示,藉由一移除裝置22移除該些導電凸塊3之部分材質(如第3B圖所示之移動方向Z)。 As shown in FIGS. 3B to 3C, part of the material of the conductive bumps 3 is removed by a removing device 22 (as shown in the moving direction Z in FIG. 3B).

於本實施例中,該移除裝置22係以切削方式(如銑刀之銑削)移除至少一該導電凸塊3之部分材質。 In this embodiment, the removing device 22 removes at least one part of the material of the conductive bump 3 by cutting (such as milling by a milling cutter).

再者,該移除裝置22係依據該量測裝置21之量測結果進行該導電凸塊3之高度補償,使該移除裝置22沿著該基板結構9之翹曲表面移動(如第3B圖所示之移動路徑S),以於移除作業後,各該導電凸塊4之高度H相同,如 第3D圖所示之整平結果。 Furthermore, the removal device 22 compensates for the height of the conductive bump 3 according to the measurement result of the measurement device 21, so that the removal device 22 moves along the warped surface of the substrate structure 9 (e.g. 3B The moving path S) shown in the figure, after the removal operation, the height H of each conductive bump 4 is the same, as Leveling results shown in Figure 3D.

又,於移除該些導電凸塊3之部分材質之過程中,該移除裝置22會接觸該些導電凸塊3,故可一併進行推力試驗,以確認每一個導電凸塊3之結構強度。 In addition, in the process of removing part of the materials of the conductive bumps 3, the removal device 22 will contact the conductive bumps 3, so a thrust test can be performed together to confirm the structure of each conductive bump 3 strength.

因此,本發明之凸塊測試方法係藉由移除該些導電凸塊3之部分材質,同時一併進行推力試驗,故相較於習知技術之一次只能針對一個導電凸塊13進行推力試驗之方法,本發明之凸塊測試方法能一次針對一組陣列排設之全部導電凸塊3進行推力試驗作業,因而能大幅縮減時程。 Therefore, the bump testing method of the present invention removes part of the materials of the conductive bumps 3 and simultaneously performs the thrust test, so compared to the conventional technology, only one conductive bump 13 can be thrust at a time. The test method, the bump test method of the present invention can perform thrust test operation on all conductive bumps 3 arranged in a group of arrays at a time, thereby greatly reducing the time course.

再者,本發明之凸塊測試方法係依據量測裝置21之量測結果進行該導電凸塊3之高度補償,使該移除裝置22能沿著該基板結構9之翹曲表面移動,故相較於習知技術,本發明之凸塊測試方法於進行推力試驗時,該移除裝置22不會碰撞該基板結構9,因而能避免該基板結構9破裂。 Furthermore, the bump testing method of the present invention performs height compensation of the conductive bump 3 according to the measurement result of the measuring device 21, so that the removing device 22 can move along the warped surface of the substrate structure 9, so Compared with the conventional technology, when the bump test method of the present invention performs a thrust test, the removal device 22 does not collide with the substrate structure 9, so the substrate structure 9 can be prevented from cracking.

又,本發明之凸塊測試方法所用之移除裝置22係沿著該基板結構9之翹曲表面移動,故相較於習知技術,該移除裝置22於推力試驗過程中,能精確地針對每一個導電凸塊3進行同一部位之推力破壞,因而大幅提高測試結果之準確性。例如,該移除裝置22對於每一個導電凸塊3均於其頂面2/3部位發生推壓,故當該導電凸塊3與該基板結構9之銲墊90之間的結合性較差時,將發生該導電凸塊3會自該銲墊90上整塊性脫落(如第2C圖所示之情況),因而能有效發現結合性不佳的狀況。 In addition, the removal device 22 used in the bump testing method of the present invention moves along the warped surface of the substrate structure 9, so compared to the conventional technology, the removal device 22 can be accurately performed during the thrust test For each conductive bump 3, the thrust of the same part is destroyed, thereby greatly improving the accuracy of the test result. For example, the removal device 22 pushes each conductive bump 3 at the top 2/3 of its top surface, so when the bonding between the conductive bump 3 and the pad 90 of the substrate structure 9 is poor As a result, the conductive bump 3 will be completely detached from the solder pad 90 (as shown in FIG. 2C), so that the poor adhesion can be effectively detected.

本發明亦提供一種凸塊測試設備2,係包括:一承載裝置20、一量測裝置21以及一移除裝置22。 The invention also provides a bump testing device 2 which includes: a carrying device 20, a measuring device 21 and a removing device 22.

所述之承載裝置20係用以承載一結合有複數導電凸塊3,4之基板結構9。 The carrying device 20 is used to carry a substrate structure 9 combined with a plurality of conductive bumps 3 and 4.

所述之量測裝置21係用以量測各該導電凸塊3之高度h。 The measuring device 21 is used to measure the height h of each conductive bump 3.

所述之移除裝置22係用以移除至少一該導電凸塊3之部分材質。 The removal device 22 is used to remove at least one part of the material of the conductive bump 3.

於一實施例中,該基板結構9係為封裝基板、矽中介板或半導體晶片,且該導電凸塊3,4係為銲球或金屬柱。 In one embodiment, the substrate structure 9 is a package substrate, silicon interposer or semiconductor chip, and the conductive bumps 3 and 4 are solder balls or metal pillars.

於一實施例中,該承載裝置20係以真空吸附方式定位該基板結構9。 In one embodiment, the carrier device 20 positions the substrate structure 9 by vacuum suction.

於一實施例中,該量測裝置21係以光感方式量測各該導電凸塊3之高度h。 In one embodiment, the measuring device 21 measures the height h of each conductive bump 3 in a light-sensitive manner.

於一實施例中,該移除裝置22係以切削方式移除至少一該導電凸塊3之部分材質,且該移除裝置22於移除至少一該導電凸塊3之部分材質後,各該導電凸塊4之高度H係相同。 In one embodiment, the removal device 22 removes at least one part of the material of the conductive bump 3 by cutting, and after the removal device 22 removes at least one part of the material of the conductive bump 3, each The height H of the conductive bump 4 is the same.

於一實施例中,該移除裝置22於移除至少一該導電凸塊3之部分材質之過程中係一併進行推力試驗。 In an embodiment, the removal device 22 performs a thrust test together during the process of removing at least one part of the material of the conductive bump 3.

綜上所述,本發明之凸塊測試方法及設備中,係藉由移除該些導電凸塊之部分材質,同時一併進行推力試驗,故能一次針對全部導電凸塊進行推力試驗作業,因而能大幅縮減時程。 In summary, in the bump testing method and apparatus of the present invention, by removing part of the materials of the conductive bumps and simultaneously performing the thrust test, the thrust test operation can be performed on all conductive bumps at once, Therefore, the time course can be greatly reduced.

再者,本發明能依據量測裝置之量測結果進行該導電凸塊之高度補償,故於進行推力試驗時,該凸塊測試設備不僅不會碰撞該基板結構而能避免該基板結構破裂,且能精確地針對所有導電凸塊進行同部位之推力破壞而令測試結果為正確。 Furthermore, the present invention can compensate for the height of the conductive bump according to the measurement result of the measurement device, so that during the thrust test, the bump test equipment not only does not collide with the substrate structure but can avoid the substrate structure from cracking, And it can accurately destroy the thrust of the same part of all conductive bumps to make the test result correct.

上述實施例係用於例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。 The above embodiments are used to exemplify the principles and effects of the present invention, rather than to limit the present invention. Anyone who is familiar with this skill can modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the rights of the present invention should be as listed in the scope of patent application mentioned later.

2‧‧‧凸塊測試設備 2‧‧‧Bump testing equipment

20‧‧‧承載裝置 20‧‧‧Bearing device

20a‧‧‧真空平台 20a‧‧‧Vacuum platform

21‧‧‧量測裝置 21‧‧‧Measuring device

22‧‧‧移除裝置 22‧‧‧Remove device

4‧‧‧導電凸塊 4‧‧‧ conductive bump

9‧‧‧基板結構 9‧‧‧Substrate structure

F‧‧‧吸附力方向 F‧‧‧Adsorption force direction

Claims (15)

一種凸塊測試設備,係包括:承載裝置,係用以承載結合有複數導電凸塊之基板結構;量測裝置,係用以依據該基板結構各部位之翹曲程度量測各該導電凸塊相對同一平面之高度;以及移除裝置,係依據該導電凸塊之高度量測結果進行該導電凸塊之高度補償,並根據該高度補償之結果決定一移動路徑,且該移除裝置沿該移動路徑移除至少一該導電凸塊之部分材質。 A bump testing device includes: a carrying device for carrying a substrate structure combined with a plurality of conductive bumps; a measuring device for measuring each conductive bump according to the degree of warpage of each part of the substrate structure The height relative to the same plane; and the removal device, which compensates for the height of the conductive bump according to the height measurement result of the conductive bump, and determines a moving path according to the result of the height compensation, and the removal device moves along the The moving path removes at least a part of the material of the conductive bump. 如申請專利範圍第1項所述之凸塊測試設備,其中,該基板結構係為封裝基板、矽中介板或半導體晶片。 The bump test equipment as described in item 1 of the patent application scope, wherein the substrate structure is a package substrate, a silicon interposer, or a semiconductor chip. 如申請專利範圍第1項所述之凸塊測試設備,其中,該導電凸塊係為銲球或金屬柱。 The bump testing device as described in item 1 of the patent application scope, wherein the conductive bump is a solder ball or a metal pillar. 如申請專利範圍第1項所述之凸塊測試設備,其中,該承載裝置係以真空吸附方式定位該基板結構。 The bump test equipment as described in item 1 of the patent application scope, wherein the carrier device positions the substrate structure by vacuum suction. 如申請專利範圍第1項所述之凸塊測試設備,其中,該量測裝置係以光感方式量測各該導電凸塊之高度。 The bump testing device as described in item 1 of the patent application scope, wherein the measuring device measures the height of each conductive bump in a light-sensitive manner. 如申請專利範圍第1項所述之凸塊測試設備,其中,該移除裝置係以切削方式移除至少一該導電凸塊之部分材質。 The bump testing equipment as described in item 1 of the patent application scope, wherein the removing device removes at least a part of the material of the conductive bump by cutting. 如申請專利範圍第1項所述之凸塊測試設備,其中,該移除裝置於移除至少一該導電凸塊之部分材質後,各該導電凸塊之高度係相同。 The bump testing equipment as described in item 1 of the patent application range, wherein after the removal device removes at least one part of the material of the conductive bump, the height of each conductive bump is the same. 如申請專利範圍第1項所述之凸塊測試設備,其中,該移除裝置於移除至少一該導電凸塊之部分材質之過程中同時進行推力試驗。 The bump testing equipment as described in item 1 of the patent application scope, wherein the removing device simultaneously performs a thrust test during the process of removing at least one part of the material of the conductive bump. 一種凸塊測試方法,係包括:提供一結合有複數導電凸塊之基板結構;依據該基板結構各部位之翹曲程度量測各該導電凸塊相對同一平面之高度;依據該導電凸塊之高度量測結果進行該導電凸塊之高度補償;根據該高度補償之結果決定一移動路徑;以及沿該移動路徑移除至少一該導電凸塊之部分材質。 A bump test method includes: providing a substrate structure combined with a plurality of conductive bumps; measuring the height of each conductive bump relative to the same plane according to the warpage of each part of the substrate structure; based on the conductive bump The height measurement result performs height compensation of the conductive bump; determines a moving path according to the result of the height compensation; and removes at least a part of the material of the conductive bump along the moving path. 如申請專利範圍第9項所述之凸塊測試方法,其中,該基板結構係為封裝基板、矽中介板或半導體晶片。 The bump test method as described in item 9 of the patent application scope, wherein the substrate structure is a package substrate, a silicon interposer, or a semiconductor chip. 如申請專利範圍第9項所述之凸塊測試方法,其中,該導電凸塊係為銲球或金屬柱。 The bump test method as described in item 9 of the patent application scope, wherein the conductive bump is a solder ball or a metal pillar. 如申請專利範圍第9項所述之凸塊測試方法,其中,該基板結構係以真空吸附方式定位。 The bump test method as described in item 9 of the patent application scope, wherein the substrate structure is positioned by vacuum suction. 如申請專利範圍第9項所述之凸塊測試方法,其中,該導電凸塊之高度係以光感方式量測。 The bump testing method as described in item 9 of the patent application scope, wherein the height of the conductive bump is measured by light sensing. 如申請專利範圍第9項所述之凸塊測試方法,其中,該導電凸塊之部分材質係藉由切削方式移除。 The bump test method as described in item 9 of the patent application scope, wherein part of the material of the conductive bump is removed by cutting. 如申請專利範圍第9項所述之凸塊測試方法,其中,於移除至少一該導電凸塊之部分材質之過程中同時進行推力試驗。 The bump testing method as described in item 9 of the patent application scope, wherein the thrust test is performed simultaneously during the process of removing at least a part of the material of the conductive bump.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6078387A (en) * 1997-11-20 2000-06-20 Dage Precision Industries, Ltd. Test apparatus
US20010053197A1 (en) * 2000-06-14 2001-12-20 Kei Murayama Method and apparatus for measuring a bump on a substrate
TW200723419A (en) * 2005-12-01 2007-06-16 Siliconware Precision Industries Co Ltd Lead-free solder bump

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6078387A (en) * 1997-11-20 2000-06-20 Dage Precision Industries, Ltd. Test apparatus
US20010053197A1 (en) * 2000-06-14 2001-12-20 Kei Murayama Method and apparatus for measuring a bump on a substrate
TW200723419A (en) * 2005-12-01 2007-06-16 Siliconware Precision Industries Co Ltd Lead-free solder bump

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