TWI678687B - Method for realizing sub-pixel rendering effect by displaying data jitter and display device using same - Google Patents

Abstract

A method for realizing sub-pixel rendering effect by using display data jitter is used in a sub-pixel rendering panel, the panel has a plurality of sub-pixel repeating units, each of the sub-pixel repeating units has a plurality of pixel units, and each of the pixels Each unit has m sub-pixels, and m is equal to 1, 1.5, or 2. The method includes: performing a data dithering procedure on a frame of source pixel data to generate N-frame component pixel data, where the component pixel data in each frame has a plurality of sub-pixels. Pixel data block, each row of each of said subpixel data blocks has a red subpixel ratio Q _R or a green sub pixel ratio Q _G or a blue sub pixel ratio Q _B , Q _R , Q _G and Q _B is less than or equal to 1, N is a positive integer, and N * Q _R , N * Q _G, and N * Q _B are all positive integers.

Description

Method for realizing sub-pixel rendering effect by displaying data jitter and display device using same

The invention relates to a picture display method, in particular to a sub-pixel rendered picture display method.

To increase the display resolution of a general display panel, the number of sub-pixels must be increased on the display screen. However, this will increase the manufacturing cost of the display panel.

In order to solve the above problem, a sub-pixel rendering (SPR) method has been proposed. In the described sub-pixel rendering method, each pixel unit has only two sub-pixels of different colors. Therefore, in order to display a pixel having red, blue, and green, only two colors (for example, red and green) are included. A pixel unit must complete display of the pixel together with an adjacent pixel unit including sub-pixels of a color (in this example, blue) that the pixel unit lacks. That is, the sub-pixel rendering method uses at least two adjacent pixel units to cooperate to display one pixel.

In addition, there are conventional sub-pixel rendering methods that are suitable for low-power operation modes. In the sub-pixel rendering method applicable to the low-power operation mode, any sub-pixel having a specific color in each sub-pixel block is driven by a same corresponding voltage, and the same corresponding voltage is based on having the specific corresponding The proportion of all sub-pixels of a color in a sub-pixel block is determined to maintain display quality and save power consumption.

However, since the sub-pixel rendering method applicable to the low-power operation mode must additionally use a corresponding voltage generating unit, not only circuit complexity is increased, but power consumption is also increased.

To solve the aforementioned problems, we urgently need a novel sub-pixel rendering display scheme.

An object of the present invention is to disclose a method for dividing a frame display data into multiple frame component pixel data by a data dithering program to achieve a sub-pixel rendering effect.

Another object of the present invention is to disclose a display device capable of dividing a frame of display data into a plurality of frames of component pixel data by implementing a data dithering program to achieve a sub-pixel rendering effect.

Another object of the present invention is to disclose a display device that can drive sub-pixels with only the lowest gray-scale voltage or the highest gray-scale voltage in a low-power operation mode to provide good sub-pixel rendering effects.

In order to achieve the foregoing object, the present invention provides a method for realizing a sub-pixel rendering effect by using display data dithering in a sub-pixel rendering panel, wherein the sub-pixel rendering panel has a plurality of sub-pixel repeating units, and each of the sub-pixel repeating units Each has a plurality of pixel units, and each of the pixel units has m sub-pixels, where m is 1, 1.5, or 2, the method includes the following steps:

A data dithering process is performed on a frame of source pixel data to generate N-frame component pixel data, where each component pixel data in the frame has a plurality of sub-pixel data blocks, and each of the sub-pixel data blocks is rendered with the sub-pixel One of the sub-pixel repeating units corresponds to one of the panels, and each row of each of the sub-pixel data blocks has a red sub-pixel ratio Q _R or a green sub-pixel ratio Q _G or a blue sub-pixel ratio Q _B , Q _R , Q _G and Q _B are all less than or equal to 1, N is a positive integer, and N * Q _R , N * Q _G and N * Q _B are all positive integers; and

Driving the sub-pixel rendering panel during the N frames according to the N-frame component pixel data.

In one embodiment, the data dithering program includes a dithering dithering program on both sides.

In one embodiment, the data dithering program includes a one-sided dithering dithering program.

In a possible embodiment, the sub-pixel rendering panel is a triangularly arranged sub-pixel rendering panel, a two-in-one sub-pixel rendering panel, or an RGBG sub-pixel rendering panel.

To achieve the foregoing object, the present invention further provides a display device having a driving circuit for driving a sub-pixel rendering panel. The sub-pixel rendering panel has a plurality of sub-pixel repeating units, and each of the sub-pixel repeating units has a plurality of pixels. Unit, each pixel unit has m sub-pixels, m is equal to 1, 1.5 or 2, and the driving circuit has a power saving mode, wherein when the driving circuit works in the power saving mode, it executes a Sub-pixel dither rendering program, which includes the following steps:

A data dithering process is performed on a frame of source pixel data to generate N-frame component pixel data, where each component pixel data in the frame has a plurality of sub-pixel data blocks, and each of the sub-pixel data blocks is rendered with the sub-pixel One of the sub-pixel repeating units corresponds to one of the panels, and each row of each of the sub-pixel data blocks has a red sub-pixel ratio Q _R or a green sub-pixel ratio Q _G or a blue sub-pixel ratio Q _B , Q _R , Q _G and Q _B are all less than or equal to 1, N is a positive integer, and N * Q _R , N * Q _G and N * Q _B are all positive integers; and

Driving the sub-pixel rendering panel during the N frames according to the N-frame component pixel data.

In a possible embodiment, the data dithering program includes a two-sided dithering dithering program or a single-sided dithering dithering program.

In a possible embodiment, the sub-pixel rendering panel is a triangularly arranged sub-pixel rendering panel, a two-in-one sub-pixel rendering panel, or an RGBG sub-pixel rendering panel.

In one embodiment, the driving circuit has a binary data generating unit, a data dithering unit, and a voltage selection unit. The binary data generating unit is used to convert the source pixel data into binary data. The data dithering unit is The data jittering program is executed on the binary data to generate output data, and the voltage selection unit is used to provide a minimum grayscale voltage or a maximum grayscale voltage according to the output data.

In one embodiment, the driving circuit has a normal mode, and when the driving circuit operates in the normal mode, it uses a gamma voltage generating unit to generate a gamma voltage to drive the sub-pixel rendering panel.

In one embodiment, the gamma voltage generating unit has a gray-scale voltage correction function.

In order to enable the expensive review committee to further understand the structure, characteristics and purpose of the present invention, the detailed description of the drawings and preferred embodiments are attached as follows.

Please refer to FIG. 1, which is a flowchart of an embodiment of a method for dithering display data to achieve a sub-pixel rendering effect in a sub-pixel rendering panel according to the present invention. The sub-pixel rendering panel has a plurality of sub-pixel repeating units. Each of the sub-pixel repeating units has a plurality of pixel units, and each of the pixel units has m sub-pixels, and m is equal to 1 or 1.5 or 2. As shown in FIG. 1, the method includes the following steps: a data dithering process is performed on a frame of source pixel data to generate N-frame component pixel data, where the component pixel data in each frame has a plurality of sub-pixel data blocks, Each of the sub-pixel data blocks corresponds to one of the sub-pixel repeating units of the sub-pixel rendering panel, and each row of each of the sub-pixel data blocks has a red sub-pixel ratio Q _R or a green sub-pixel ratio Q _G or a blue sub-pixel ratio Q _B , Q _R , Q _G, and Q _B are all less than or equal to 1, N is a positive integer, and N * Q _R , N * Q _G, and N * Q _B are all positive integers ( Step a); and driving the sub-pixel rendering panel during N frames according to the N-frame component pixel data (step b).

In the method shown in FIG. 1, the sub-pixel rendering panel may be a triangularly arranged sub-pixel rendering panel, a two-in-one sub-pixel rendering panel, or an RGBG sub-pixel rendering panel.

In addition, in a possible embodiment, the data dithering program may include a two-sided dithering dithering program or a single-sided dithering dithering program. The dithering dithering procedure on both sides is a data dithering procedure that borrows data from a subpixel to adjacent subpixel data blocks on the left and right sides during the left and right dithering process of a subpixel data block; and The one-sided dithering dithering program is a data dithering program that borrows data from a sub-pixel only to the left or right adjacent sub-pixel data block during the left and right dithering process of a sub-pixel data block.

According to the above description, the present invention further provides a display device. Please refer to FIG. 2, which is a block diagram illustrating an embodiment of a display device that implements sub-pixel rendering effects by using display data dithering according to the present invention. As shown in FIG. 2, the display device has a driving circuit for driving a sub-pixel rendering panel 200, wherein the driving circuit has a demultiplexer 110, a gamma voltage generating unit 120, a power saving mode driving unit 130, and a Select switch 140.

The demultiplexer 110 transmits the source pixel data D _IN to the gamma voltage generating unit 120 or the power saving mode driving unit 130 according to the control of a selection signal SEL.

The gamma voltage generating unit 120 is configured to generate a gamma voltage V _D1 according to the source pixel data D _IN to drive the sub-pixel rendering panel 200. The gamma voltage generating unit 120 has a gray _color in the process of generating the gamma voltage V _D1 . Step voltage correction function to enable the sub-pixel rendering panel 200 to produce an ideal display effect.

The power saving mode driving unit 130 has a binary data generating unit 131, a data dithering unit 132, and a voltage selecting unit 133. The binary data generating unit 131 is used to convert source pixel data D _IN into binary data; the data dithering unit 132 is used to execute a data dithering procedure on the binary data to generate output data, and the voltage selection unit 133 is used to provide an output voltage V _D2 (which is a minimum gray level voltage or a maximum gray level) according to the output data Voltage) to drive the sub-pixel rendering panel 200.

The selection switch 140 is used to provide a gamma voltage V _D1 or an output voltage V _D2 to the sub-pixel rendering panel 200.

The sub-pixel rendering panel 200 may be a triangularly arranged sub-pixel rendering panel, a two-in-one sub-pixel rendering panel, or an RGBG sub-pixel rendering panel. The sub-pixel rendering panel 200 has a plurality of sub-pixel repeating units (not shown in FIG. 2), and each of the sub-pixels repeats. Each unit has a plurality of pixel units, and each of the pixel units has m sub-pixels, and m may be 1, 1.5, or 2.

During operation, when the driving circuit works in a normal mode, the gamma voltage generating unit 120 generates a gamma voltage V _D1 and the selection switch 140 outputs the gamma voltage V _D1 to the sub-pixel rendering panel 200; and when the driving circuit Working in a power-saving mode, the selection switch 140 outputs the output voltage V _D2 to the sub-pixel rendering panel 200, and the driving circuit executes a sub-pixel dither rendering process, which includes the following steps: The source pixel data D of a frame _IN executes a data dithering process to generate N-frame component pixel data, where each component pixel data in the frame has a plurality of sub-pixel data blocks, and each of the sub-pixel data blocks is described with one of the sub-pixel rendering panels 200 The sub-pixel repeating unit corresponds to each row of each of the sub-pixel data blocks has a red sub-pixel ratio Q _R or a green sub-pixel ratio Q _G or a blue sub-pixel ratio Q _B , Q _R , Q _G and Q _B is less than or equal to 1, N is a positive integer, and N * Q _R , N * Q _G, and N * Q _B are all positive integers; and the driver for N frames during the N frames according to the N frame component pixel data Pixel rendering panel 200.

In addition, in a possible embodiment, the data dithering program may include a two-sided dithering dithering program or a single-sided dithering dithering program. The dithering dithering procedure on both sides is a data dithering procedure that borrows data from a subpixel to adjacent subpixel data blocks on the left and right sides during the left and right dithering process of a subpixel data block; and The one-sided dithering dithering program is a data dithering program that borrows data from a sub-pixel only to the left or right adjacent sub-pixel data block during the left and right dithering process of a sub-pixel data block.

The principle of data dithering of the present invention will be described below with specific sub-pixel blocks.

Please refer to FIG. 3, which is a schematic diagram of preparing a dithering procedure for the first row after dividing a sub-pixel data block of a delta sub-pixel rendering panel of m = 2 into multiple rows according to the present invention; and FIG. 4 is the block content obtained by dividing the sub-pixel data block shown in FIG. 3 with the first line center, and the first to fourth columns are (B, R, G, B), ( G, B, R), (B, R, G, B), (G, B, R); and columns 1 and 3 of the divided block content are applicable to the dithering dithering procedure on both sides , And the second and fourth columns of the divided block content are applicable to the one-sided dithering dithering program.

Please refer to FIG. 5a, which is a schematic diagram of an embodiment of the first column of the block content of FIG. As shown in FIG. 5a, after the dithering dithering process on the two sides, the first column generates (B, R,-,-), (-, R, G,-), (-,-, G, B), (-,-, G, B), (-, R, G,-), and (B, R,-,-), where "-" represents a blank, and the first The sub-pixel ratios of the first to fourth sub-pixel positions in a column of 6 frames are 1/3, 2/3, 2/3, and 1/3, respectively.

Please refer to FIG. 5b, which is a schematic diagram of an embodiment of the two-side dithering dithering program acting on the second column of the block content of FIG. As shown in FIG. 5b, after the dithering dithering process on the two sides, the second column generates (G, B,-), (-, B, R), (G,- , R), (G, B,-), (-, B, R), and (G,-, R), where the second column is in the first to third sub-pixel positions of the six frames The sub-pixel ratios are 2/3, 2/3, and 2/3, respectively.

Please refer to FIG. 5c, which is a schematic diagram of an embodiment of the content dithering dithering procedure on the third column of the block content of FIG. As shown in FIG. 5c, after the dithering dithering process on both sides, the third column generates (B, R,-,-), (B, R, G,-), (-,-, G,-), (-,-, G,-), (-, R, G, B), and (-, R,-, B), where the third column is in 6 The sub-pixel ratios of the first to fourth sub-pixel positions in the frame are 1/3, 2/3, 2/3, and 1/3, respectively.

Please refer to FIG. 5d, which is a schematic diagram of an embodiment of the content dithering dithering procedure on the fourth column of the block content of FIG. As shown in FIG. 5d, after the dithering dithering process on both sides, the fourth column generates (-, B, R), (G, B, R), (G,-) in 6 frames, respectively. ,-), (G,-,-), (G, B, R), and (-, B, R), where the 4th column is at the 1st to 3rd sub-pixel positions of the 6 frames The sub-pixel ratios are 2/3, 2/3, and 2/3, respectively.

Please refer to FIG. 6, which is a schematic diagram of preparing a dithering procedure for the second row after dividing a sub-pixel data block of a triangle-arranged sub-pixel rendering panel of m = 2 into multiple rows according to the present invention; and FIG. 7, It is the block content obtained by dividing the sub-pixel data block shown in Fig. 6 with the center of the second line. The first to fourth columns are (G, B, R, G) and (R, G). , B), (G, B, R, G), (R, G, B); and the first and third columns of the divided block content are applicable to the dithering dithering procedures on both sides, and the The second and fourth columns of the divided block content are applicable to the one-sided dithering dithering procedure.

Please refer to FIG. 8a, which is a schematic diagram of an embodiment of the first column of the block content of FIG. As shown in FIG. 8a, after the dithering dithering process on the two sides, the first column generates (G, B,-,-), (-, B, R,-), (-,-, R, G), (-,-, R, G), (-, B, R,-), and (G, B,-,-), where the first column is in 6 messages The sub-pixel ratios of the first to fourth sub-pixel positions in the frame are 1/3, 2/3, 2/3, and 1/3, respectively.

Please refer to FIG. 8b, which is a schematic diagram of an embodiment of the two-side dithering dithering program acting on the second column of the block content of FIG. As shown in FIG. 8b, after the dithering dithering process on the two sides, the second column generates (R, G,-), (-, G, B), (R,-) in 6 frames, respectively. , B), (R, G,-), (-, G, B), and (R,-, B), where the second column is in the first to third sub-pixel positions of the six frames The sub-pixel ratios are 2/3, 2/3, and 2/3, respectively.

Please refer to FIG. 8c, which is a schematic diagram of an example of the third column of the block content of FIG. 7 applied by the dither dithering program on both sides. As shown in FIG. 8c, after the dithering dithering process on the two sides, the third column generates (G, B,-,-), (G, B, R,-), (-,-, R,-), (-,-, R,-), (-, B, R, G), and (-, B,-, G), where the 3rd column is in 6 messages The sub-pixel ratios of the first to fourth sub-pixel positions in the frame are 1/3, 2/3, 2/3, and 1/3, respectively.

Please refer to FIG. 8d, which is a schematic diagram of an embodiment of the content dithering dithering procedure on the fourth column of the block content of FIG. As shown in FIG. 8d, after the dithering dithering process on both sides, the fourth column generates (R,-, B), (R, G, B), (-, G) in 6 frames, respectively. ,-), (-, G,-), (R, G, B), and (R,-, B), where the 4th column is at the 1st to 3rd sub-pixel positions of the 6 frames The sub-pixel ratios are 2/3, 2/3, and 2/3, respectively.

Please refer to FIG. 9, which is a schematic diagram of preparing a dithering procedure for the third row after dividing a sub-pixel data block of a triangle-arranged sub-pixel rendering panel of m = 2 into multiple rows according to the present invention; and FIG. 10, It is the block content obtained by dividing the sub-pixel data block shown in FIG. 9 by the center of the third row. The columns from the first column to the fourth column are (R, G, B, R), (B, R). , G), (R, G, B, R), (B, R, G); and columns 1 and 3 of the divided block content are applicable to the dithering dithering procedures on both sides, and the The second and fourth columns of the divided block content are applicable to the one-sided dithering dithering procedure.

Please refer to FIG. 11a, which is a schematic diagram of an embodiment of the first column of the block content of FIG. As shown in FIG. 11a, after the dithering dithering process on the two sides, the first column generates (R, G,-,-), (-, G, B,-), 6 in 6 frames, respectively. (-,-, B, R), (-,-, B, R), (-, G, B,-), and (R, G,-,-), where the first column is listed in 6 messages The sub-pixel ratios of the first to fourth sub-pixel positions in the frame are 1/3, 2/3, 2/3, and 1/3, respectively.

Please refer to FIG. 11b, which is a schematic diagram of an embodiment of the two-side dithering dithering program acting on the second column of the block content of FIG. As shown in FIG. 11b, after the dithering dithering process on the two sides, the second column generates (B, R,-), (-, R, G), (B,- , G), (B, R,-), (-, R, G), and (B,-, G), where the second column is in the first to third sub-pixel positions of the six frames The sub-pixel ratios are 2/3, 2/3, and 2/3, respectively.

Please refer to FIG. 11c, which is a schematic diagram of an embodiment of the third column of the content of the block shown in FIG. As shown in FIG. 11c, after the dithering dithering process on both sides, the third column generates (R,-,-,-), (R, G,-,-), (-, G, B,-), (-, G, B,-), (-, G, B, R), and (-,-, B, R), of which, the third column is in 6 messages The sub-pixel ratios of the first to fourth sub-pixel positions in the frame are 1/3, 2/3, 2/3, and 1/3, respectively.

Please refer to FIG. 11d, which is a schematic diagram of an example of the fourth column of the block content of FIG. As shown in FIG. 11d, after the dithering dithering process on both sides, the fourth column generates (B,-,-), (B, R,-), (B, R) in 6 frames, respectively. , G), (B, R, G), (-, R, G), and (-,-, G), where the fourth column is at the first to third sub-pixel positions of the six frames. The sub-pixel ratios are 2/3, 2/3, and 2/3, respectively.

Please refer to FIG. 12a, which is a schematic diagram of preparing a dithering procedure for the first line after dividing a subpixel data block of one RGBG subpixel rendering panel of m = 2 into multiple lines according to the present invention; FIG. 12b, which is The sub-pixel data block shown in FIG. 12a is the block content obtained from the first row center after segmentation. The first to fourth columns are (R, G, B,-), (B, G, R). ,-), (R, G, B,-), (B, G, R,-); and FIG. 12c, which is the 1st column of the content of the block of FIG. 12b by the one-sided dithering dithering program. A schematic diagram of an embodiment. As shown in FIG. 12c, after the one-sided dithering dithering function is applied, the first column generates (R, G,-,-) and (-, G, B,-) in 2 frames, respectively. "-" Represents blank, and the sub-pixel ratios of the first to third sub-pixel positions of the first column in the two frames are 1/2, 1, and 1/2, respectively.

Please refer to FIG. 13a, which is a schematic diagram of preparing a dithering procedure for the fourth row after dividing a subpixel data block of a triangle-arranged subpixel rendering panel of m = 1.5 into multiple rows according to the present invention; FIG. 13b, which The sub-pixel data block shown in FIG. 13a is the block content obtained by the fourth row center after segmentation. The first to fourth columns are (B, RG, B), (RG, B, RG). , (B, RG, B), (RG, B, RG); FIG. 13c is a schematic diagram of an embodiment of the first column of the block content of FIG. 13b by the dither dithering program on both sides; FIG. 13d , Which is a schematic diagram of an embodiment of the single-sided dithering dithering program acting on the first column of the block content of FIG. 13b; FIG. 13e, which is the single-side dithering dithering program acting on the block content of FIG. 13b Schematic diagram of another embodiment of the first column.

As shown in FIG. 13c, after the dithering dithering process on the two sides, the first column generates (-, RG,-), (B, R-,-), (-, -G, B), (-,-G, B), (-, RG,-), and (B, R-,-), where "-" stands for blank, and the first column is in 6 frames The sub-pixel ratios of the first to third sub-pixel positions in are 2/3, 2/3, and 2/3, respectively.

As shown in FIG. 13d, after the one-sided dithering dithering function is applied, the first column will generate (-, R-,-), (-, RG,-), (- , -G, B), (-,-G, B), (-, RG,-), and (B, R-,-), where "-" stands for blank, and the first column is in 6 messages The sub-pixel ratios of the first to third sub-pixel positions in the frame are 2/3, 2/3, and 2/3, respectively.

As shown in FIG. 13e, after the one-sided dithering dithering procedure is applied, the first column will generate (-, -G, B), (-, RG,-), (B , R-,-), (B, R-,-), (-, RG,-), and (-,-G, B), where "-" stands for blank, and the first column is in 6 messages The sub-pixel ratios of the first to third sub-pixel positions in the frame are 2/3, 2/3, and 2/3, respectively.

Please refer to FIG. 14a, which is a sub-pixel data block of a 2-in-1 (2-in-1) sub-pixel rendering panel in which m = 2 is divided into multiple lines according to the present invention, and a dither is prepared for the first line. A schematic diagram of the program; and FIG. 14b, which is the block content obtained by dividing the sub-pixel data block shown in FIG. 14a with the first line center, and the first to fourth columns are (R, G, B) ), (B, G, R), (R, G, B), (B, G, R); and FIG. 14c, which is the first part of the content of the block of FIG. A schematic diagram of an embodiment of one column. As shown in FIG. 14c, after the one-sided dithering dithering function is applied, the first column generates (R, G,-) and (-, G, B) in two frames, where "-" Represents blank space, and the sub-pixel ratios of the first to third sub-pixel positions of the first column in the two frames are 1/2, 1, and 1/2, respectively.

Please refer to FIG. 14d, which is a sub-pixel data block of a 2-in-1 (2-in-1) sub-pixel rendering panel of m = 2, which is divided into multiple lines according to the present invention. A schematic diagram of the program; and FIG. 14e, which is the block content obtained by dividing the sub-pixel data block shown in FIG. 14d with the second line center, which is respectively (B, G, R from column 1 to column 4). ), (R, G, B), (B, G, R), (R, G, B); and FIG. 14f, which is the first part of the content of the block of FIG. A schematic diagram of an embodiment of one column. As shown in FIG. 14f, after the one-sided dithering dithering procedure is applied, the first column generates (B, G,-) and (-, G, R) in two frames, where "-" Represents blank space, and the sub-pixel ratios of the first to third sub-pixel positions of the first column in the two frames are 1/2, 1, and 1/2, respectively.

Please refer to FIG. 15a, which is a schematic diagram of preparing a dithering procedure for the second row after dividing a subpixel data block of a triangularly arranged subpixel rendering panel of m = 1.5 into multiple rows according to the present invention; and FIG. 15b, It is the block content obtained by dividing the sub-pixel data block shown in Figure 15a with the second line center. The first to fourth columns are (G, B, R, G) and (R, G). , B), (G, B, R, G), (R, G, B); and FIG. 15c, which is one of the first column of the block content of FIG. Example schematic. As shown in FIG. 15c, after the dithering dithering process on the two sides, the first column generates (-B, R,-), (G,-,-,-), (- -B, R,-), (-,-,-, G), where "-" stands for blank, and the sub-pixel ratio of the 1st to 4th sub-pixel positions of the 1st column in the 4 frames They are 1/2, 1/2, 1/2, and 1/2.

Please refer to FIG. 15d, which is a schematic diagram of preparing a dithering procedure for the third row after dividing a subpixel data block of a triangle-aligned subpixel rendering panel of m = 1.5 into multiple rows according to the present invention; and FIG. 15e, It is the block content obtained by dividing the sub-pixel data block shown in Figure 15d with the center of the third row. The columns from the first column to the fourth column are (R, G, B), (G, B, R). , G), (R, G, B), (G, B, R, G); and FIG. 15f, which is a first of the first column of the block content of FIG. Example schematic. As shown in FIG. 15f, after the dithering dithering process on the two sides, the first column generates (R,-, B), (-, G,-), (R,- , B), (-, G,-), where "-" represents blank, and the sub-pixel ratios of the first to third sub-pixel positions of the first column in the four frames are 1/2, 1/2 and 1/2.

With the design disclosed above, the present invention has the following advantages:

1. The screen display method of the present invention only needs to drive the sub-pixels with the lowest gray-scale voltage or the highest gray-scale voltage to provide a good sub-pixel rendering effect in a low-power consumption working mode.

2. The display device of the present invention only needs to drive the sub-pixels with the lowest gray-scale voltage or the highest gray-scale voltage to provide a good sub-pixel rendering effect in a low power consumption working mode.

What is disclosed in this case is a preferred embodiment. For example, those who have partial changes or modifications that are derived from the technical ideas of this case and are easily inferred by those skilled in the art, do not depart from the scope of patent rights in this case.

In summary, regardless of the purpose, method and effect, this case is showing its technical characteristics that are quite different from the conventional ones, and its first creation is suitable for practical use, and it is also in line with the patent requirements of the invention. Granting patents at an early date will benefit society and feel good.

Step a‧‧‧ executes a data dithering procedure on a frame of source pixel data to generate N frame component pixel data, wherein each component pixel data in the frame has a plurality of subpixel data blocks, and each of the subpixel data blocks is Corresponding to the subpixel repeating unit of one of the subpixel rendering panels, each row of each subpixel data block has a red subpixel ratio QR or a green subpixel ratio QG or a blue subpixel ratio QB , QR, QG, and QB are all less than or equal to 1, N is a positive integer, and N * QR, N * QG, and N * QB are all positive integers

Step b‧‧‧ drives the sub-pixel rendering panel during the N frames according to the N-frame component pixel data

110‧‧‧Demultiplexer

120‧‧‧Gamma voltage generating unit

130‧‧‧ Power-saving mode drive unit

131‧‧‧ binary data generating unit

132‧‧‧Data Dithering Unit

133‧‧‧Voltage selection unit

140‧‧‧selection switch

200‧‧‧ sub-pixel rendering panel

FIG. 1 is a flowchart of an embodiment of a method for implementing sub-pixel rendering effects by using display data jitter in a sub-pixel rendering panel according to the present invention. FIG. 2 is a block diagram of an embodiment of a display device for realizing sub-pixel rendering effect by using display data dithering according to the present invention. FIG. 3 is a schematic diagram of preparing a dithering procedure for the first row after dividing a sub-pixel data block of a delta sub-pixel rendering panel of m = 2 into multiple rows according to the present invention. FIG. 4 is the block content obtained by dividing the sub-pixel data block shown in FIG. 3 with the first row center. 5a is a schematic diagram of an embodiment of the first column of the content of the block in FIG. 4 with the dither dithering program on both sides. FIG. 5b is a schematic diagram of an example of the second column dithering dithering program acting on the second column of the block content of FIG. 4. FIG. FIG. 5c is a schematic diagram of an embodiment of the content dithering dithering procedure on the third column of the block content of FIG. 4. FIG. 5d is a schematic diagram of an embodiment of the content dithering dithering procedure on the fourth column of the block content of FIG. 4. FIG. 6 is a schematic diagram of preparing a dithering procedure for the second row after dividing a sub-pixel data block of a triangle-arranged sub-pixel rendering panel of m = 2 into multiple rows according to the present invention. FIG. 7 is the block content obtained by dividing the sub-pixel data block shown in FIG. 6 with the second line center. FIG. 8a is a schematic diagram of an embodiment of the first column of the block content of FIG. 7 with the dither dithering program on both sides. FIG. 8b is a schematic diagram of an embodiment of the two-side dithering dithering program acting on the second column of the block content of FIG. 7. FIG. FIG. 8c is a schematic diagram of an example of the third-side dithering dithering program acting on the third column of the block content of FIG. 7. FIG. FIG. 8d is a schematic diagram of an embodiment of the content dithering dithering program acting on the fourth column of the block content of FIG. 7. FIG. 9 is a schematic diagram of preparing a dithering procedure for the third row after dividing a sub-pixel data block of a triangle-arranged sub-pixel rendering panel of m = 2 into multiple rows according to the present invention. FIG. 10 is a block content obtained by dividing the sub-pixel data block shown in FIG. 9 with a third row center. FIG. 11 a is a schematic diagram of an embodiment of the first column of the block content of FIG. 10 by the dither dithering program on both sides. FIG. 11b is a schematic diagram of an example of the second column of the block content of FIG. 10 applied by the dither dithering program on both sides. FIG. 11 c is a schematic diagram of an example of the third column of the block content in FIG. 10 applied by the dither dithering program on both sides. FIG. 11d is a schematic diagram of an example of the fourth column of the block content of FIG. 10 applied by the dither dithering program on both sides. FIG. 12a is a schematic diagram of preparing a dithering procedure for the first row after dividing a sub-pixel data block of one of the RGBG sub-pixel rendering panels of m = 2 into multiple rows according to the present invention. FIG. 12b is the block content obtained by dividing the sub-pixel data block shown in FIG. 12a with the first line center. FIG. 12c is a schematic diagram of an embodiment of the single-side dithering dithering program acting on the first column of the block content in FIG. 12b. 13a is a schematic diagram of preparing a dithering procedure for the fourth row after dividing a sub-pixel data block of a triangle-arranged sub-pixel rendering panel of m = 1.5 into multiple rows according to the present invention. FIG. 13b is the block content obtained by dividing the sub-pixel data block shown in FIG. 13a with the fourth row center. FIG. 13c is a schematic diagram of an embodiment of the first column of the block content of FIG. 13b by the dither dithering program on both sides. FIG. 13d is a schematic diagram of an example of the one-side dithering dithering program acting on the first column of the block content of FIG. 13b. FIG. 13e is a schematic diagram of another embodiment of the one-side dithering dithering program acting on the first column of the block content of FIG. 13b. FIG. 14a is a schematic diagram of preparing a dithering procedure for the first row after dividing a sub-pixel data block of one of the 2-in-1 sub-pixel rendering panels of m = 2 into multiple rows according to the present invention. FIG. 14b is the block content obtained by dividing the sub-pixel data block shown in FIG. 14a with the first row center. FIG. 14c is a schematic diagram of an example of the one-side dithering dithering program acting on the first column of the block content in FIG. 14b. FIG. 14d is a schematic diagram of preparing a dithering procedure for the second row after dividing a sub-pixel data block of one of the 2-in-1 sub-pixel rendering panels of m = 2 into multiple rows according to the present invention. FIG. 14e is the block content obtained by dividing the sub-pixel data block shown in FIG. 14d with the second line center after segmentation. FIG. 14f is a schematic diagram of an embodiment of the single-side dithering dithering program acting on the first column of the block content of FIG. 14e. FIG. 15a is a schematic diagram of preparing a dithering procedure for the second row after dividing a sub-pixel data block of a triangle-arranged sub-pixel rendering panel of m = 1.5 into multiple rows according to the present invention. FIG. 15b is the block content obtained by dividing the sub-pixel data block shown in FIG. 15a with the second line center. FIG. 15c is a schematic diagram of an embodiment of the first column of the block content of FIG. 15b by the dither dithering program on both sides. FIG. 15d is a schematic diagram of preparing a dithering procedure for the third row after dividing a sub-pixel data block of a triangle-arranged sub-pixel rendering panel of m = 1.5 into multiple rows according to the present invention. FIG. 15e is the block content obtained by dividing the sub-pixel data block shown in FIG. 15d with the third row center after segmentation. FIG. 15f is a schematic diagram of an embodiment of the first column of the block content of FIG. 15e by the dither dithering program on both sides.

Claims (7)

A method for realizing sub-pixel rendering effect by using display data jitter, used in a sub-pixel rendering panel, wherein the sub-pixel rendering panel has a plurality of sub-pixel repeating units, and each of the sub-pixel repeating units has a plurality of pixel units, and Each of the pixel units has m sub-pixels, and m is equal to 1 or 1.5 or 2. The method includes the following steps: performing a data dithering procedure on a frame of source pixel data to generate N-frame component pixel data, where each frame has the component Each pixel data has a plurality of sub-pixel data blocks, each of the sub-pixel data blocks corresponds to the sub-pixel repeating unit of one of the sub-pixel rendering panels, and each row of each of the sub-pixel data blocks has a The red sub-pixel ratio Q _R or a green sub-pixel ratio Q _G or a blue sub-pixel ratio Q _B , Q _R , Q _G, and Q _B are all less than or equal to 1, N is a positive integer, and N * Q _R , N * Q _G and N * Q _B are positive integers; and the sub-pixel rendering panel is driven during N frames according to the N-frame component pixel data; wherein the data dithering procedure includes a dithering dithering procedure on both sides or Unilateral dithering dithering program. The method for achieving sub-pixel rendering effect by using display data dithering as described in item 1 of the scope of patent application, wherein the sub-pixel rendering panel is a triangularly arranged sub-pixel rendering panel, a two-in-one sub-pixel rendering panel, and an RGBG sub-pixel rendering A panel selected by the panel group. A display device has a driving circuit for driving a sub-pixel rendering panel, the sub-pixel rendering panel has a plurality of sub-pixel repeating units, each of the sub-pixel repeating units has a plurality of pixel units, and each of the pixel units has m Sub-pixels, m is equal to 1 or 1.5 or 2, and the driving circuit has a power saving mode, wherein when the driving circuit works in the power saving mode, it executes a sub-pixel dither rendering program, the program includes the following Step: A data dithering process is performed on a frame of source pixel data to generate N-frame component pixel data, where each component pixel data in the frame has a plurality of sub-pixel data blocks, and each of the sub-pixel data blocks is related to the sub-pixel data block. One of the pixel rendering panels corresponds to the sub-pixel repeating unit, and each row of each sub-pixel data block has a red sub-pixel ratio Q _R or a green sub-pixel ratio Q _G or a blue sub-pixel ratio Q _B , Q _R , Q _G, and Q _B are all less than or equal to 1, N is a positive integer, and N * Q _R , N * Q _G, and N * Q _B are all positive integers; N During driving the sub-pixel rendering block panel; wherein the program data comprises dithering a dithering jitter on both sides or a single side application program dithering jitter. The display device according to item 3 of the scope of patent application, wherein the sub-pixel rendering panel is one selected from the group consisting of a triangularly arranged sub-pixel rendering panel, a 2-in-1 sub-pixel rendering panel, and an RGBG sub-pixel rendering panel. panel. The display device according to item 3 of the scope of patent application, wherein the driving circuit has a binary data generating unit, a data dithering unit, and a voltage selecting unit, and the binary data generating unit is used to convert the source pixel data Into binary data, the data dithering unit is configured to perform the data dithering procedure on the binary data to generate output data, and the voltage selection unit is configured to provide a minimum grayscale voltage or a maximum according to the output data Gray-scale voltage. The display device according to item 3 of the scope of patent application, wherein the driving circuit has a normal mode, and when the driving circuit operates in the normal mode, it uses a gamma voltage generating unit to generate a gamma Voltage to drive the sub-pixel rendering panel. The display device according to item 6 of the scope of patent application, wherein the gamma voltage generating unit has a grayscale voltage correction function.