TWI676988B - Readout circuit applied to a memory - Google Patents

Abstract

A readout circuit applied to a memory. When a current passing through a memory cell in the memory is not greater than a first boundary current, the memory cell has a first output value. When the unit current of the memory unit is not less than the second boundary current, the memory unit has a second output value. The readout circuit includes a receiving circuit and a control circuit. The receiving circuit is used to receive the unit passing through the memory unit. Current, and the control circuit is coupled to the receiving circuit and used for generating a control current according to the unit current passing through the memory unit and a reference current, and further generating one of the first output value or the second output value according to the control current. , Wherein the reference current is located between the first boundary current and the second boundary current.

Description

Reading circuit applied to memory

The invention relates to a memory system, and more particularly to a readout circuit applied to a memory.

Traditionally, in a memory that judges the state of data by detecting the current, especially a magnetoresistive random access memory (MRAM), which is used to determine whether the state of the data is "0" or "1" The two limit currents are too close to each other, so that a slight process deviation will cause the memory to judge the data status error. Therefore, a new memory system is needed to solve the above problems.

An object of the present invention is to provide a memory readout circuit to solve the above problems.

According to an embodiment of the present invention, a readout circuit applied to a memory is disclosed. When a cell current passing through a memory cell in the memory is not greater than a first boundary current, the memory cell has A first output value, when the cell current passing through the memory cell in the memory is not less than the second boundary current, the memory cell has a second output value, the readout circuit includes: a receiving circuit And a control circuit, wherein the receiving circuit is used for receiving And the control circuit is coupled to the receiving circuit and used for generating a control current according to the unit current and a reference current passing through the memory unit, and generating the first output value according to the control current. Or one of the second output values, wherein the reference current is between the first boundary current and the second boundary current.

Icell‧‧‧cell current

I1, I2, I3, I4‧‧‧ boundary current

Iref1, Iref2‧‧‧ reference current

10‧‧‧Memory

100‧‧‧readout circuit

110‧‧‧Receiving circuit

120‧‧‧Control circuit

Do‧‧‧Data Status

Ictrl‧‧‧Control current

Ipro1-Ipro2‧‧‧ Handle current

M1-M4‧‧‧Transistors

FIG. 1 is a schematic diagram of the operation of a magnetoresistive random access memory.

FIG. 2 is a schematic diagram of a readout circuit of a memory according to an embodiment of the invention.

FIG. 3 is a schematic diagram of a control circuit according to an embodiment of the present invention.

FIG. 4 is a schematic diagram of a current generating circuit according to an embodiment of the present invention.

FIG. 5 is a schematic diagram of a control circuit according to another embodiment of the present invention.

Certain terms are used in the description and the scope of subsequent patent applications to refer to specific elements. It should be understood by those with ordinary knowledge in the art that hardware manufacturers may use different names to refer to the same component. The scope of this specification and subsequent patent applications does not take the difference in names as a way to distinguish components, but rather uses the difference in functions of components as a criterion for distinguishing components. "Inclusion" mentioned throughout the specification and subsequent claims is an open-ended term and should be interpreted as "including but not limited to." In addition, the term "coupled" includes any direct and indirect electrical connection means. Therefore, if the text describes a first device coupled to a second device, it means that the first device can be directly and electrically connected to the second device. The second device is indirectly electrically connected to the second device through other devices or connection means.

Figure 1 shows the cell current distribution and operation of a magnetoresistive random access memory. In Figure 1, the currents I1 and I2 are the cell currents when the data state is "0". ) Distributed boundary current, and the currents I3 and I4 are the boundary currents of the cell current distribution when the data state is "1", that is, the cell current Icell flowing through the memory cell is located at the reference current I1 and the reference current Between I2, the memory can be judged that the data state is "0", and when the cell current Icell flowing through the memory cell is between the boundary current I3 and the boundary current I4, the memory can be judged that the data state is "1" In order to ensure the tolerance rate of process deviation, a reference current Iref is usually defined so that the reference current Iref and the boundary current I2 and the reference current Iref and the boundary current I3 can have the same interval. Traditionally, the memory The readout circuit compares the reference current Iref with the cell current Icell. When the cell current Icell of the memory cell is less than the reference current Iref, the memory is judged to have a data state of "0". However, Under the condition of cell current distribution, the maximum value of the cell current Icell is the boundary current I2, and the interval between the cell current and the reference current Iref is only (I3-I2) / 2; Similarly, when the cell current Icell passing the memory cell is larger than the reference current When Iref, the memory is judged to have a data state of "1". Under this condition, the minimum value of the cell current Icell is the boundary current I3, and the interval between the reference current Iref is also only (I3-I2) / 2. Therefore, for a magnetoresistive random access memory, such a small interval causes a slight process deviation to cause the memory to judge the data status error. Therefore, the present invention proposes a new memory system to solve this problem.

FIG. 2 is a schematic diagram of a readout circuit 100 applied to a memory 10 according to an embodiment of the present invention. In this embodiment, the memory 10 may be one but not limited to a magnetoresistive random access A memory (Magnetoresistive Random Access Memory, MRAM), any other memory that judges the state of data by detecting a current, can belong to the scope of the present invention. As shown in FIG. 2, the readout circuit 100 includes a receiving circuit 110 and a control circuit 120. The receiving circuit 110 is configured to receive a cell current Icell flowing through a memory cell included in the memory 10, and The unit current Icell is transmitted to the control circuit 120, and the control circuit 120 is based on the unit current Icell and the two reference currents shown in FIG. Iref1 and Iref2 generate a control current Ictrl, and generate a data state Do of the memory unit according to the control current Ictrl, such as outputting a logic value "0" or "1". In this embodiment, for convenience of subsequent description, the reference current Iref1 is equal to the boundary current I2, and the reference current Iref2 is equal to the boundary current I3, but the present invention is not limited thereto. In other embodiments, the reference currents Iref1 and Iref2 may be any appropriate current values between the boundary currents I2 and I3.

FIG. 3 is a schematic diagram of a control circuit 120 according to an embodiment of the present invention. As shown in FIG. 3, the control circuit 120 includes current generating circuits 210 and 220 and a comparison circuit 230. The current generating circuit 210 is configured to receive the cell current Icell and the boundary current I2 and generate a processing current Ipro1. In this embodiment, the processing current Ipro1 may be an integer multiple of a difference between the cell current Icell and the boundary current I2, that is, Ipro 1 = A ( Icell - I 2), where A is a positive integer. In addition, the current generating circuit 220 is configured to receive the cell current Icell and the boundary current I3 and generate a processing current Ipro2. In this embodiment, the processing current Ipro2 may be an integer multiple of a difference between the boundary current I3 and the cell current Icell. , That is, Ipro 2 = A ( I 3- Icell ). The comparison circuit 230 is used to compare the processing currents Ipro1 and Ipro2 to generate a control current Ictrl. When the control current Ictrl indicates that the processing current Ipro1 is greater than the processing current Ipro2, that is, when Ipro1-Ipro2> 0, the data state Do output by the comparison circuit 230 is The logic value "1", and when the control current Ictrl indicates that the processing current Ipro1 is smaller than the processing current Ipro2, that is, when Ipro1-Ipro2 <0, the data state Do output by the comparison circuit 230 is a logic value "0".

According to the embodiment of FIG. 3, it can be known that the comparison circuit 230 compares the processing currents Ipro1 and Ipro2 to generate a data state Do, where the control current Ictrl can be summarized as a mathematical formula as follows: Ictrl = Ipro 1- Ipro 2, Ictrl = ( Icell-I 2 )-( I 3- Icell ), assuming A = 1

I ctrl = 2 Icell- ( I 2+ I 3)

The comparison circuit 230 outputs data by comparing whether the control current Ictrrl is greater than 0 or less than 0. The material state Do, however, it can be known from the above mathematical formula and the embodiment in FIG. 1 that if the output data state Do is a logical value “0”, the maximum cell current Icell can be the boundary current I2. The current Ictrl will be I2-I3; if the output data state Do is a logic value "1", the minimum unit current Icell is the boundary current I3, and the control current Ictrl at this time will be I3-I2. Obviously, Compared with the embodiment shown in FIG. 1, the structure proposed by the present invention can increase the current interval by a factor of two, so that the error rate of the data state interpretation by the memory can be greatly reduced. It should be noted that in this embodiment, it is assumed that A is a positive integer 1. In other embodiments, A may be a positive integer greater than 1 and any number greater than 1. In this way, a larger current interval will be obtained. Reduce the error rate of memory for data state interpretation.

FIG. 4 is a schematic diagram of a current generating circuit 210 according to an embodiment of the present invention. As shown in FIG. 4, the current generating circuit 210 includes a metal oxide semiconductor field effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET). ) M1-M4 (hereinafter referred to as transistors M1-M4), in which transistors M1 and M2 form a current mirror structure and transistors M3 and M4 form another current mirror structure. A source terminal of the transistor M1 is used to receive the boundary current I2, and a source terminal of the transistor M2 is used to receive the unit current I2, so that the current flowing through a source terminal of the transistor M3 will be (Icell-I2) By adjusting the area ratio of the transistors M4 and M3, the processing current Ipro1 = A (Icell-I2) can be obtained at one source terminal of the transistor M4. The current generating circuit 220 can also be implemented according to the current generating circuit 210 in FIG. 4. It is only necessary to replace the currents received by the source terminals of the transistors M1 and M2 with the cell current Icell and the boundary current I3, respectively. One should be able to easily understand other embodiments of the current mirror, and detailed descriptions are omitted here to save space.

FIG. 5 is a schematic diagram of the control circuit 120 according to another embodiment of the present invention. In this embodiment, it is assumed that the current distribution of the memory element is easily smaller than the boundary current I2. As a result, the control circuit 120 defines the reference current as the boundary current I2 (that is, uses the reference current Iref1), so the control circuit 120 can compare the cell current Icell flowing through the memory cell and the boundary current I2 through the comparison circuit 510 to generate the control current Ictrl. When the current Ictrl indicates that the cell current Icell is greater than the boundary current I2, the data state Do is output as a logical value “1”, and when the control current Ictrl indicates that the cell current Icell is less than the boundary current I2, the data state Do is output as a logic value “0”. In this state, if the output data state Do is a logical value "1", the minimum value of the unit current is I3, so it can be known that the interval from the reference current Iref1 = I2 is (I3-I2), which is the same as in Figure 1. Comparing the embodiments, the current interval can also be doubled to reduce the probability that the memory judges the data status error. Similarly, if the current distribution of the memory element is easily larger than the boundary current I3, the reference current is defined the same as the boundary current I3 (that is, the reference current Iref2 is used), and the control circuit 120 may be replaced by comparing the current flowing through the memory unit through the comparison circuit 510. The cell current Icell and the boundary current I3 are used to generate the control current Ictrl. When the control current Ictrl indicates that the cell current Icell is greater than the boundary current I3, the data status Do is a logical value "1". When the control current Ictrl indicates that the cell current Icell is less than the boundary current When I3, the output data state Do is logic value "0". In this state, if the output data state Do is a logic value "0", the maximum value of the unit current is I2, so it can be seen that the interval between the reference current Iref2 = I3 is also (I3-I2), which is the same as the first Comparing the embodiment of the figure, the current interval can also be doubled to reduce the probability that the memory judges the data status error.

To briefly summarize the present invention, the present invention proposes a readout circuit applied to a memory, which increases the interval between currents for judging the data state as "0" or "1", thereby greatly reducing the error of the memory judging data state Chance. The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the scope of patent application of the present invention shall fall within the scope of the present invention.

Claims (10)

A readout circuit applied to a memory, wherein when a cell current passing through a memory cell in the memory is not greater than a first boundary current, the memory cell has a first output value. When the cell current of the memory cell in the memory is not less than the second boundary current, the memory cell has a second output value, and the readout circuit includes: a receiving circuit for receiving the passing through the memory cell The unit current; and a control circuit coupled to the receiving circuit, wherein the control circuit generates a first processing current based on the unit current and a first reference current, and generates a first processing current based on the unit current and a second reference current. Generating a second processing current, and comparing the first processing current and the second processing current to determine whether the memory unit has the first output value or the second output value, wherein the first reference current and the second The reference currents are different current values between the first boundary current and the second boundary current. For example, the first readout circuit of the patent application scope, wherein the first reference current is the first boundary current, and the second reference current is the second boundary current. For example, the readout circuit of the first patent application range, wherein when the first processing current is greater than the second processing current, the control circuit determines that the memory unit has the second output value; and when the first processing current is less than During the second processing current, the control circuit determines that the memory unit has the first output value. For example, the readout circuit of the first patent application range, wherein the control circuit includes: a first current generating circuit for receiving the unit current and the first reference current to generate the first processing current, wherein the first processing A current value of the current is a multiple of a difference between the unit current and the first reference current. For example, the readout circuit according to item 4 of the patent application, wherein the first current generating circuit includes a current mirror circuit to receive the unit current and the reference current to generate the first processing current. For example, the readout circuit of claim 4 of the patent application scope, wherein the control circuit further includes: a second current generating circuit for receiving the unit current and the second reference current to generate the second processing current, wherein the second processing current A current value of the processing current is a multiple of a difference between the unit current and the second reference current. For example, the readout circuit of claim 6 in the patent application, wherein the second current generating circuit includes a current mirror circuit to receive the unit current and the second reference current to generate the second processing current. For example, the readout circuit of claim 6 of the patent application scope, wherein the control circuit further includes: a comparison circuit for comparing the first processing current and the second processing current to generate a control current, and generating the control current according to the control current. Either the first output value or the second output value. For example, the readout circuit of the eighth patent application range, wherein when the control current indicates that the first processing current is greater than the second processing current, the comparison circuit outputs the second output value, and when the control current indicates the second When the processing current is greater than the first processing current, the comparison circuit outputs the first output value. For example, the readout circuit of the first patent application scope, wherein the memory is a magnetoresistive random access memory (Magnetoresistive Random Access Memory, MRAM).