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TWI676250B - Optical sensor - Google Patents

Optical sensor Download PDF

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Publication number
TWI676250B
TWI676250B TW107133614A TW107133614A TWI676250B TW I676250 B TWI676250 B TW I676250B TW 107133614 A TW107133614 A TW 107133614A TW 107133614 A TW107133614 A TW 107133614A TW I676250 B TWI676250 B TW I676250B
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Taiwan
Prior art keywords
sensing
chip
wafer
substrate
insulator
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TW107133614A
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Chinese (zh)
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TW202013648A (en
Inventor
洪立群
Li Chun Hung
李建成
Chien Chen Lee
杜修文
Hsiu Wen Tu
Original Assignee
勝麗國際股份有限公司
Kingpak Technology Inc.
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Priority to TW107133614A priority Critical patent/TWI676250B/en
Application granted granted Critical
Publication of TWI676250B publication Critical patent/TWI676250B/en
Publication of TW202013648A publication Critical patent/TW202013648A/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/162Disposition
    • H01L2924/16235Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

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  • Solid State Image Pick-Up Elements (AREA)
  • Light Receiving Elements (AREA)

Abstract

本發明公開一種光學感測器,包含基板、設置於基板的重佈式晶片結構、設置於重佈式晶片結構的感測晶片、位於感測晶片上方的透光片、電性連接基板與感測晶片的多條金屬線、及設置於基板上的封裝體。重佈式晶片結構包含絕緣體、埋置於絕緣體的第一電子晶片、及連接於絕緣體與第一電子晶片底部的重置線路。重置線路電性連接於第一電子晶片、並通過覆晶固定於基板。感測晶片的感測區朝向重佈式晶片結構正投影所形成的投影區域位於重佈式晶片結構的外輪廓內。重佈式晶片結構、感測晶片、部分的透光片、及金屬線埋置於封裝體內。 The invention discloses an optical sensor, which includes a substrate, a redistributed wafer structure disposed on the substrate, a sensing wafer disposed on the redistributed wafer structure, a light-transmitting sheet located above the sensing wafer, and an electrical connection substrate and a sensor. A plurality of metal lines of the wafer are measured, and a package body disposed on the substrate. The redistributed wafer structure includes an insulator, a first electronic chip buried in the insulator, and a reset circuit connected between the insulator and the bottom of the first electronic chip. The reset circuit is electrically connected to the first electronic chip and fixed to the substrate through a flip chip. The projection area formed by the sensing area of the sensing chip facing the redistribution wafer structure is located within the outer contour of the redistribution wafer structure. The redistribution-type wafer structure, the sensing wafer, a part of the light-transmitting sheet, and the metal wire are buried in the package body.

Description

光學感測器 Optical sensor

本發明涉及一種感測器,尤其涉及一種光學感測器。 The invention relates to a sensor, in particular to an optical sensor.

現有的光學感測器包含有大尺寸晶片堆疊於小尺寸晶片上方的態樣,並且現有光學感測器的大尺寸晶片周緣通過打線而電性連接於基板。然而,現有光學感測器在上述打線的過程中,由於大尺寸晶片周緣是呈懸空狀,所以打線過程所施予大尺寸晶片周緣的外力易導致缺陷產生。 The existing optical sensor includes a state in which a large-sized wafer is stacked over a small-sized wafer, and the periphery of the large-sized wafer of the existing optical sensor is electrically connected to the substrate by wire bonding. However, during the above-mentioned bonding process of the existing optical sensor, since the periphery of the large-sized wafer is suspended, the external force applied to the periphery of the large-sized wafer by the bonding process is likely to cause defects.

於是,本發明人認為上述缺陷可改善,乃特潛心研究並配合科學原理的運用,終於提出一種設計合理且有效改善上述缺陷的本發明。 Therefore, the present inventor believes that the above-mentioned defects can be improved, and with special research and cooperation with the application of scientific principles, he finally proposes an invention with a reasonable design and effective improvement of the above-mentioned defects.

本發明實施例在於提供一種光學感測器,其能有效地改善現有光學感測器所可能產生的缺陷。 An embodiment of the present invention is to provide an optical sensor, which can effectively improve defects that may occur in the existing optical sensors.

本發明實施例公開一種光學感測器,包括:一基板;一重佈式晶片結構,包含有一絕緣體、埋置於該絕緣體的一第一電子晶片、及連接於該絕緣體與該第一電子晶片底部的一重置線路;其中,該重置線路電性連接於該第一電子晶片,並且該重佈式晶片結構通過該重置線路覆晶固定於該基板;一感測晶片,具有大於該第一電子晶片的尺寸,並且該感測晶片設置於該重佈式晶片結構上;其中,該感測晶片的一頂面包含有一感測區,並且該感測區朝向該重佈式晶片結構正投影所形成的一投影區域位於該重佈 式晶片結構的外輪廓之內;一透光片,位於該感測晶片的上方;多條金屬線,電性連接該基板與該感測晶片;以及一封裝體,設置於該基板上,並且該重佈式晶片結構、該感測晶片、及該些金屬線埋置於該封裝體內;其中,該封裝體固定該透光片於該感測晶片上方、並裸露該透光片的部分表面。 An embodiment of the present invention discloses an optical sensor, including: a substrate; a heavy-duty wafer structure including an insulator, a first electronic chip embedded in the insulator, and a bottom connected to the insulator and the first electronic chip. A reset circuit; wherein the reset circuit is electrically connected to the first electronic chip, and the redistribution-type wafer structure is fixed to the substrate by flip chip resetting; a sensing chip having a size larger than the first chip; The size of an electronic chip, and the sensing chip is disposed on the redistributed wafer structure; wherein a bread of the sensing chip includes a sensing region, and the sensing region faces the redistributed wafer structure; A projection area formed by the projection is located at the re-layout Within the outer contour of the wafer structure; a light-transmitting sheet located above the sensing wafer; a plurality of metal wires electrically connecting the substrate and the sensing wafer; and a package disposed on the substrate, and The redistribution-type wafer structure, the sensing chip, and the metal wires are embedded in the package body; wherein the package body fixes the light transmitting sheet above the sensing chip and exposes a part of the surface of the light transmitting sheet .

綜上所述,本發明實施例所公開的光學感測器,其將該第一電子晶片埋置於該重佈式晶片結構的絕緣體中,並使該重佈式晶片結構與該感測晶片之間存在特定的配置關係(如:該感測區朝向該重佈式晶片結構正投影所形成的投影區域位於該重佈式晶片結構的外輪廓之內),所以該重佈式晶片結構能夠有效地支撐感測晶片,據以在感測晶片進行打線的過程中,有效地抵抗施加於感測晶片的外力,並避免產生缺陷。 In summary, the optical sensor disclosed in the embodiment of the present invention embeds the first electronic chip in the insulator of the redistributed wafer structure, and makes the redistributed wafer structure and the sensing wafer There is a specific configuration relationship between them (for example, the projection area formed by the sensing area being orthographically projected toward the redistributed wafer structure is located within the outer contour of the redistributed wafer structure), so the redistributed wafer structure can The sensor chip is effectively supported, thereby effectively resisting the external force applied to the sensor chip and avoiding defects during the wire bonding process of the sensor chip.

為能更進一步瞭解本發明的特徵及技術內容,請參閱以下有關本發明的詳細說明與附圖,但是此等說明與附圖僅用來說明本發明,而非對本發明的保護範圍作任何的限制。 In order to further understand the features and technical contents of the present invention, please refer to the following detailed description and drawings of the present invention, but these descriptions and drawings are only used to illustrate the present invention, and not to make any limitation to the scope of the present invention limit.

100‧‧‧光學感測器 100‧‧‧optical sensor

1‧‧‧基板 1‧‧‧ substrate

11‧‧‧晶片固定區 11‧‧‧Chip fixed area

12‧‧‧第一接墊 12‧‧‧The first pad

13‧‧‧第三接墊 13‧‧‧The third pad

2‧‧‧重佈式晶片結構 2‧‧‧ Heavy cloth chip structure

21‧‧‧絕緣體 21‧‧‧ insulator

211‧‧‧側邊緣 211‧‧‧side edge

212‧‧‧延伸部 212‧‧‧ extension

213‧‧‧承載部 213‧‧‧bearing department

22‧‧‧第一電子晶片 22‧‧‧The first electronic chip

221‧‧‧接點 221‧‧‧Contact

23‧‧‧重置線路 23‧‧‧Reset line

231‧‧‧新接點 231‧‧‧New contacts

24‧‧‧焊球 24‧‧‧Solder Ball

25‧‧‧第二電子晶片 25‧‧‧Second electronic chip

3‧‧‧感測晶片 3‧‧‧ sensor chip

31‧‧‧頂面 31‧‧‧Top

311‧‧‧感測區 311‧‧‧sensor area

312‧‧‧第二接墊 312‧‧‧Second pad

313‧‧‧非打線區 313‧‧‧Unwired area

32‧‧‧底面 32‧‧‧ underside

33‧‧‧側邊緣 33‧‧‧Side edge

4‧‧‧透光片 4‧‧‧Translucent sheet

5‧‧‧金屬線 5‧‧‧ metal wire

5a‧‧‧導線 5a‧‧‧Wire

6‧‧‧封裝體 6‧‧‧ Package

61‧‧‧支撐體 61‧‧‧ support

62‧‧‧底部填充劑 62‧‧‧ Underfill

63‧‧‧包覆體 63‧‧‧ Cover

64‧‧‧模製體 64‧‧‧ molded body

65‧‧‧延伸體 65‧‧‧ extension

7‧‧‧第三電子晶片 7‧‧‧Third electronic chip

Da、Db‧‧‧距離 Da, Db‧‧‧ distance

S‧‧‧密封空間 S‧‧‧Sealed space

圖1為本發明實施例一的光學感測器的剖視示意圖。 FIG. 1 is a schematic cross-sectional view of an optical sensor according to a first embodiment of the present invention.

圖2為圖1的部位II的局部放大示意圖。 FIG. 2 is a partially enlarged schematic diagram of a part II in FIG. 1.

圖3為本發明實施例一的光學感測器另一態樣的剖視示意圖。 3 is a schematic cross-sectional view of another aspect of the optical sensor according to the first embodiment of the present invention.

圖4為本發明實施例二的光學感測器的剖視示意圖。 4 is a schematic cross-sectional view of an optical sensor according to a second embodiment of the present invention.

請參閱圖1至圖4,其為本發明的實施例,需先說明的是,本實施例對應附圖所提及的相關數量與外型,僅用來具體地說明本發明的實施方式,以便於了解本發明的內容,而非用來侷限本發明的保護範圍。 Please refer to FIGS. 1 to 4, which are embodiments of the present invention. It should be noted that this embodiment corresponds to the related quantities and appearances mentioned in the drawings, and is only used to specifically describe the embodiments of the present invention. In order to facilitate understanding of the content of the present invention, it is not intended to limit the protection scope of the present invention.

[實施例一] [Example 1]

請參閱圖1至圖3所示,其為本發明的實施例一。如圖1和圖2所示,本實施例公開一種光學感測器100,包含有一基板1、設置於該基板1的一重佈式晶片結構2、設置於該重佈式晶片結構2的一感測晶片3、位於該感測晶片3上方的一透光片4、電性連接該基板1與該感測晶片3的多條金屬線5、及設置於該基板1上的一封裝體6。 Please refer to FIG. 1 to FIG. 3, which is a first embodiment of the present invention. As shown in FIG. 1 and FIG. 2, this embodiment discloses an optical sensor 100 including a substrate 1, a redistributed wafer structure 2 disposed on the substrate 1, and a sensor disposed on the redistributed wafer structure 2. The test chip 3, a light-transmitting sheet 4 located above the sensor chip 3, a plurality of metal wires 5 electrically connecting the substrate 1 and the sensor chip 3, and a package 6 disposed on the substrate 1.

需先闡明的是,為便於說明本實施例光學感測器100,圖式是以剖視圖呈現,但可以理解的是,在圖式所未呈現的光學感測器100部位也會形成有相對應的構造。例如:圖1僅呈現兩條金屬線5,但在圖1所未呈現的光學感測器100部位還包含其他金屬線5。以下將分別就本實施例光學感測器100的各個元件構造與連接關係作一說明。 It should be clarified that, in order to facilitate the description of the optical sensor 100 in this embodiment, the drawing is shown in a cross-sectional view, but it can be understood that corresponding parts of the optical sensor 100 not shown in the drawing may also be formed The construction. For example, FIG. 1 shows only two metal wires 5, but other metal wires 5 are also included in the part of the optical sensor 100 not shown in FIG. 1. The following will describe the structure and connection relationship of each element of the optical sensor 100 in this embodiment.

該基板1於本實施例中呈方形或矩形,並且該基板1於其頂面的大致中央處設有一晶片固定區11,而於該晶片固定區11的外側部位設置有多個第一接墊12。再者,該基板1於底面可進一步設有多個焊接球(未標示),通過基板1的該些焊接球而焊接固定於一電子構件(圖未示,如:印刷電路板)上,據以使該光學感測器100能電性連接該電子構件。 The substrate 1 is square or rectangular in this embodiment, and the substrate 1 is provided with a wafer fixing area 11 at a substantially center of a top surface thereof, and a plurality of first pads are provided on an outer part of the wafer fixing area 11. 12. In addition, the substrate 1 may further be provided with a plurality of solder balls (not labeled) on the bottom surface, which are soldered and fixed to an electronic component (not shown, such as a printed circuit board) through the solder balls of the substrate 1. In this way, the optical sensor 100 can be electrically connected to the electronic component.

該重佈式晶片結構2包含有一絕緣體21、埋置於該絕緣體21的一第一電子晶片22、連接於該絕緣體21與該第一電子晶片22底部的一重置線路23(redistribution layer,RDL)、及多個焊球24。其中,該第一電子晶片22於本實施例中是以一影像信號處理器(image signal processor)來說明,但不以此為限。 The redistributed wafer structure 2 includes an insulator 21, a first electronic chip 22 embedded in the insulator 21, and a reset line 23 (redistribution layer, RDL) connected between the insulator 21 and the bottom of the first electronic chip 22. ), And a plurality of solder balls 24. The first electronic chip 22 is described with an image signal processor in this embodiment, but is not limited thereto.

進一步地說,該絕緣體21於本實施例中是通過模製成形而包 圍在該第一電子晶片22的周圍,並且該絕緣體21的頂面與底面分別切齊於該第一電子晶片22的頂面與底面。該重置線路23則是成形於該絕緣體21的底面與該第一電子晶片22的底面,並且該重置線路23電性連接於該第一電子晶片22。其中,位於該第一電子晶片22底部的多個接點221可以通過該重置線路23而連接到位於該重佈式晶片結構2底部且具有較大間距的多個新接點231。也就是說,該重置線路23相當於一種線路扇出結構(circuit fan-out structure)。另,位於該絕緣體21下方的該重置線路23部位較佳是設置有至少部分的該些新接點231,但本發明不受限於此。 Furthermore, in this embodiment, the insulator 21 is covered by molding. It surrounds the first electronic chip 22, and the top surface and the bottom surface of the insulator 21 are respectively aligned with the top surface and the bottom surface of the first electronic chip 22. The reset circuit 23 is formed on a bottom surface of the insulator 21 and a bottom surface of the first electronic chip 22, and the reset circuit 23 is electrically connected to the first electronic chip 22. Wherein, the plurality of contacts 221 located at the bottom of the first electronic chip 22 may be connected to the plurality of new contacts 231 located at the bottom of the redistribution-type wafer structure 2 and having a larger pitch through the reset circuit 23. That is, the reset circuit 23 is equivalent to a circuit fan-out structure. In addition, the reset circuit 23 located below the insulator 21 is preferably provided with at least part of the new contacts 231, but the present invention is not limited thereto.

再者,該重佈式晶片結構2通過該重置線路23覆晶固定於該基板1(的晶片固定區11)。於本實施例中,該重置線路23通過該些焊球24而焊接於該基板1的晶片固定區11(上述焊接於本實施例中包含有結構上與電性上的連接)。 Furthermore, the redistributed wafer structure 2 is flip-chip-fixed to the substrate 1 (wafer-fixing region 11) through the reset circuit 23. In this embodiment, the reset circuit 23 is soldered to the wafer fixing area 11 of the substrate 1 through the solder balls 24 (the soldering in this embodiment includes a structural and electrical connection).

該感測晶片3於本實施例中是以一影像感測晶片來說明,但不以此為限。其中,該感測晶片3包含有位於相反兩側的一頂面31及一底面32,並且該感測晶片3於其頂面31的大致中央處設有一感測區311,而於該感測區311的外側部位設置有多個第二接墊312,並且該些第二接墊312的位置與數量對應於該些第一接墊12的位置與數量。 The sensing chip 3 is described with an image sensing chip in this embodiment, but is not limited thereto. Wherein, the sensing chip 3 includes a top surface 31 and a bottom surface 32 on opposite sides, and the sensing chip 3 is provided with a sensing area 311 at approximately the center of the top surface 31 thereof. A plurality of second pads 312 are provided on the outer part of the area 311, and the positions and numbers of the second pads 312 correspond to the positions and numbers of the first pads 12.

再者,該感測晶片3具有大於該第一電子晶片22的尺寸,並且該感測晶片3設置於該重佈式晶片結構2上;例如:該感測晶片3的底面32以黏著層(未標示)固定於該絕緣體21的頂面與該第一電子晶片22的頂面。換個角度來看,該感測晶片3的該感測區311朝向該重佈式晶片結構2正投影所形成的一投影區域,其位於該重佈式晶片結構2的外輪廓(如:圖1中的該絕緣體21的側邊緣211)之內,並且該投影區域於本實施例中較佳是覆蓋該 第一電子晶片22,但本發明不受限於此。 Furthermore, the sensing wafer 3 has a size larger than that of the first electronic wafer 22, and the sensing wafer 3 is disposed on the redistributed wafer structure 2; for example, a bottom surface 32 of the sensing wafer 3 is provided with an adhesive layer ( (Not shown) is fixed on the top surface of the insulator 21 and the top surface of the first electronic chip 22. From another perspective, the sensing region 311 of the sensing chip 3 faces a projection area formed by the orthographic projection of the redistributed wafer structure 2, which is located on the outer contour of the redistributed wafer structure 2 (eg, FIG. 1). Within the side edge 211) of the insulator 21, and the projection area in this embodiment preferably covers the The first electronic wafer 22, but the present invention is not limited to this.

更詳細地說,該絕緣體21的至少局部側邊緣211相對於該感測晶片3的鄰近側邊緣33(如:圖1中的該絕緣體21左側邊緣211相對於該感測晶片3的左側邊緣33)突伸出一距離Da,並且該距離Da小於1毫米,但本發明不受限於此。舉例來說,在本發明未繪示的其他實施例中,該絕緣體21的各個側邊緣211可以是相對於該感測晶片3的對應側邊緣33皆突伸出該距離Da。 In more detail, at least a partial side edge 211 of the insulator 21 is relative to the adjacent side edge 33 of the sensing chip 3 (eg, the left edge 211 of the insulator 21 is opposite to the left edge 33 of the sensing chip 3 in FIG. 1). ) Protrudes a distance Da, and the distance Da is less than 1 mm, but the present invention is not limited thereto. For example, in other embodiments not shown in the present invention, each side edge 211 of the insulator 21 may protrude from the corresponding side edge 33 of the sensing chip 3 by the distance Da.

再者,該絕緣體21的至少局部側邊緣211相對於該感測晶片3的鄰近側邊緣33(如:圖1中的該絕緣體21右側邊緣211相對於該感測晶片3的右側邊緣33)內縮有一距離Db,並且該距離Db小於1毫米,但本發明不受限於此。舉例來說,在本發明未繪示的其他實施例中,該絕緣體21的各個側邊緣211可以是相對於該感測晶片3的對應側邊緣33皆內縮有該距離Db。 Furthermore, at least a partial side edge 211 of the insulator 21 is relative to the adjacent side edge 33 of the sensing chip 3 (eg, the right edge 211 of the insulator 21 is opposite to the right edge 33 of the sensing chip 3) The distance Db is reduced, and the distance Db is less than 1 mm, but the present invention is not limited thereto. For example, in other embodiments not shown in the present invention, each side edge 211 of the insulator 21 may be within a distance Db from the corresponding side edge 33 of the sensing chip 3.

該些金屬線5的一端分別連接該基板1的該些第一接墊12,而該些金屬線5的另一端分別連接於該感測晶片3的該些第二接墊312,據以使該基板1與該感測晶片3能通過該些金屬線5而達成電性連接。 One end of the metal wires 5 are respectively connected to the first pads 12 of the substrate 1, and the other ends of the metal wires 5 are respectively connected to the second pads 312 of the sensing chip 3. The substrate 1 and the sensing chip 3 can be electrically connected through the metal wires 5.

依上所述,由於該第一電子晶片22於本實施例中是被埋置於該重佈式晶片結構2的絕緣體21中,並且該重佈式晶片結構2與該感測晶片3之間存在特定的配置關係(如:該感測區311朝向該重佈式晶片結構2正投影所形成的投影區域位於該重佈式晶片結構2的外輪廓之內),所以該重佈式晶片結構2能夠有效地支撐感測晶片3,據以在感測晶片3進行打線的過程中,有效地抵抗施加於感測晶片3的外力,避免造成缺陷。 According to the above, since the first electronic chip 22 is buried in the insulator 21 of the redistributed wafer structure 2 in this embodiment, and the redistributed wafer structure 2 and the sensing wafer 3 There is a specific configuration relationship (for example, the projection area formed by the sensing area 311 facing the redistribution wafer structure 2 is located within the outer contour of the redistribution wafer structure 2), so the redistribution wafer structure 2 can effectively support the sensing wafer 3, so that during the wire bonding process of the sensing wafer 3, it can effectively resist the external force applied to the sensing wafer 3 and avoid causing defects.

進一步地說,該絕緣體21的側邊緣211與該感測晶片3的鄰近側邊緣33之間形成有小於等於1毫米的距離Da、Db,以避免 該感測晶片3與基板1之間形成過於狹長的縫隙,進而使該感測晶片3與基板1之間不易產生氣泡。 Further, a distance Da, Db of 1 mm or less is formed between the side edge 211 of the insulator 21 and the adjacent side edge 33 of the sensing chip 3 to avoid An excessively long gap is formed between the sensing wafer 3 and the substrate 1, so that it is difficult for air bubbles to be generated between the sensing wafer 3 and the substrate 1.

再者,該重佈式晶片結構2於本實施例中以覆晶方式固定於該基板1的晶片固定區11,也就是說,該重佈式晶片結構2是位於該些第一接墊12的內側。據此,本實施例的該重佈式晶片結構2因為非使用打線方式,因而能夠有效地降低成本、並避免該重佈式晶片結構2與位於其上方的該感測晶片3之間產生短路的問題。 Furthermore, in this embodiment, the redistributed wafer structure 2 is fixed to the wafer fixing area 11 of the substrate 1 in a flip-chip manner. That is, the redistributed wafer structure 2 is located on the first pads 12. Inside. According to this, because the redistributed wafer structure 2 of this embodiment does not use a wire bonding method, the cost can be effectively reduced, and a short circuit between the redistributed wafer structure 2 and the sensing wafer 3 located above it can be avoided. The problem.

該透光片4於本實施例中是以呈透明狀的一平板玻璃來說明,但本發明不受限於此。其中,該透光片4通過封裝體6(如:下述封裝體6所包含的支撐體61)而設置於該感測晶片3的頂面31上方,該透光片4面向該感測晶片3的感測區311,並且該透光片4、該支撐體61、及該感測晶片3共同包圍形成有一密封空間S。 In this embodiment, the transparent sheet 4 is described by using a transparent glass plate, but the present invention is not limited thereto. Wherein, the light-transmitting sheet 4 is disposed above the top surface 31 of the sensing chip 3 through a packaging body 6 (such as a support 61 included in the following packaging body 6), and the light-transmitting sheet 4 faces the sensing chip. 3, the sensing region 311, and the light-transmitting sheet 4, the support body 61, and the sensing wafer 3 are enclosed together to form a sealed space S.

再者,該透光片4的尺寸於本實施例中是小於該感測晶片3的尺寸。其中,該透光片4朝向該感測晶片3頂面31正投影所形成的投影區域,其覆蓋該感測區311並位於該感測晶片3的外輪廓之內,但本發明不受限於此。 Moreover, the size of the transparent sheet 4 in this embodiment is smaller than the size of the sensing wafer 3. Wherein, the light-transmitting sheet 4 is a projection area formed by orthographic projection of the top surface 31 of the sensing chip 3, which covers the sensing area 311 and is located within the outer contour of the sensing chip 3, but the present invention is not limited. herein.

該封裝體6設置於該基板1上,並且該重佈式晶片結構2、該感測晶片3、及該些金屬線5皆埋置於該封裝體6內;而該封裝體6固定該透光片4於該感測晶片3上方、並裸露該透光片4的部分表面(如:圖1中的透光片4頂面)。 The package body 6 is disposed on the substrate 1, and the redistribution wafer structure 2, the sensing chip 3, and the metal wires 5 are buried in the package body 6; and the package body 6 fixes the transparent substrate 6. The light sheet 4 is above the sensing wafer 3 and exposes a part of the surface of the light transmitting sheet 4 (eg, the top surface of the light transmitting sheet 4 in FIG. 1).

更詳細地說,該封裝體6主要由一包覆體63及一模製體64(molding compound)構成。但該封裝體6於本實施例中是包含有一支撐體61(如:膠材)、一底部填充劑62(underfill epoxy)、一包覆體63、及一模製體64(molding compound)來說明;也就是說,支撐體61及底部填充劑62也可以視為是該封裝體6的一部 分。其中,該支撐體61夾持於該感測晶片3的頂面31以及該透光片4之間,並且該支撐體61位於該感測區311的外側及該些第二接墊312的內側。該底部填充劑62佈滿於該重佈式晶片結構2與該基板1之間的一間隙;也就是說,該重佈式晶片結構2的該些焊球24埋置於該底部填充劑62內。 In more detail, the package body 6 is mainly composed of a covering body 63 and a molding compound 64. However, in this embodiment, the package body 6 includes a support body 61 (such as an adhesive material), an underfill epoxy 62, an overcoat body 63, and a molding compound 64. In other words, the support body 61 and the underfill material 62 can also be regarded as a part of the package body 6 Minute. Wherein, the support body 61 is sandwiched between the top surface 31 of the sensing chip 3 and the transparent sheet 4, and the support body 61 is located outside the sensing area 311 and inside the second pads 312. . The underfill 62 is filled in a gap between the redistributed wafer structure 2 and the substrate 1; that is, the solder balls 24 of the redistributed wafer structure 2 are buried in the underfill 62. Inside.

再者,該包覆體63設置於該基板1上,並且該重佈式晶片結構2、該感測晶片3、及該支撐體61埋置於該包覆體63內,並且該包覆體63裸露該透光片4的該部分表面。也就是說;該包覆體63是包圍在該底部填充劑62、該重佈式晶片結構2、該感測晶片3、該支撐體61、及該透光片4的外側。再者,每條金屬線5在本實施例中完全埋置於該包覆體63內。 In addition, the covering body 63 is disposed on the substrate 1, and the redistributed wafer structure 2, the sensing wafer 3, and the support body 61 are embedded in the covering body 63, and the covering body 63 exposes part of the surface of the light transmitting sheet 4. That is, the covering body 63 surrounds the outer side of the underfill material 62, the redistribution wafer structure 2, the sensing wafer 3, the support body 61, and the transparent sheet 4. Furthermore, in this embodiment, each metal wire 5 is completely embedded in the covering body 63.

另,本實施例的該包覆體63是由液態封膠(liquid compound)所固化形成,並且該模製體64是模製成形於該包覆體63的頂面,但本發明不受限於此。舉例來說,於本發明未繪示的其他實施例中,該封裝體6也可以省略該模製體64。 In addition, the covering body 63 in this embodiment is formed by curing a liquid compound, and the molding body 64 is molded on the top surface of the covering body 63, but the present invention is not limited thereto. herein. For example, in other embodiments not shown in the present invention, the package body 6 may also omit the molded body 64.

此外,在本實施例的圖1中,該封裝體6是以包含有支撐體61、包覆體63、及底部填充劑62來說明,但本發明不受限於此。舉例來說,如圖3所示的光學感測器100另一態樣,該封裝體6也可以省略底部填充劑62,並且該封裝體6以其包覆體63佈滿於該重佈式晶片結構2與該基板1之間的一間隙。其中,該包覆體63較佳是通過模製方式而成形,以利於填入該重佈式晶片結構2與該基板1之間的間隙。 In addition, in FIG. 1 of the present embodiment, the package body 6 is described as including a support body 61, a cover body 63, and an underfill 62, but the present invention is not limited thereto. For example, as shown in another aspect of the optical sensor 100 shown in FIG. 3, the package body 6 may also omit the underfill 62, and the package body 6 is covered with the covering body 63 in the redistribution type. A gap between the wafer structure 2 and the substrate 1. Wherein, the covering body 63 is preferably formed by a molding method, so as to facilitate filling the gap between the redistributed wafer structure 2 and the substrate 1.

[實施例二] [Example 2]

請參閱圖4所示,其為本發明的實施例二,本實施例類似於上述實施例一,所以兩個實施例的相同處則不再加以贅述,而本實施例與實施例一的差異主要如下所載: 於本實施例中,該重佈式晶片結構2進一步包含有一第二電子晶片25。其中,該第一電子晶片22與該第二電子晶片25間隔地埋置於該絕緣體21內,並且該感測晶片3的該感測區311朝向該重佈式晶片結構2正投影所形成的一投影區域,其較佳是覆蓋該第一電子晶片22與該第二電子晶片25,但本發明不受限於此。再者,該重置線路23則是成形於該絕緣體21的底面、該第一電子晶片22的底面、及該第二電子晶片25的底面,並且該第一電子晶片22與該第二電子晶片25各自電性連接於該重置線路23。 Please refer to FIG. 4, which is a second embodiment of the present invention. This embodiment is similar to the first embodiment described above, so the same points of the two embodiments are not described again, and the differences between this embodiment and the first embodiment Mainly as follows: In this embodiment, the redistributed wafer structure 2 further includes a second electronic wafer 25. Wherein, the first electronic wafer 22 and the second electronic wafer 25 are buried in the insulator 21 at intervals, and the sensing area 311 of the sensing wafer 3 faces the rear projection of the redistributed wafer structure 2. A projection area preferably covers the first electronic chip 22 and the second electronic chip 25, but the present invention is not limited thereto. Furthermore, the reset circuit 23 is formed on the bottom surface of the insulator 21, the bottom surface of the first electronic chip 22, and the bottom surface of the second electronic chip 25, and the first electronic chip 22 and the second electronic chip Each of 25 is electrically connected to the reset line 23.

進一步地說,該光學感測器100可以進一步包括有非埋置於該重佈式晶片結構2的一第三電子晶片7,該基板1與該絕緣體21則對應該第三電子晶片7而形成有下述構造。 Further, the optical sensor 100 may further include a third electronic wafer 7 which is not embedded in the redistribution wafer structure 2, and the substrate 1 and the insulator 21 are formed corresponding to the third electronic wafer 7. It has the following structure.

該絕緣體21包含有突伸出該感測晶片3的一延伸部212,並且該基板1在該些第一接墊12的內側且鄰近該延伸部212的部位設置有一第三接墊13;也就是說,該第三接墊13大致位於該些第一接墊12與該延伸部212之間,但本發明不受限於此。 The insulator 21 includes an extension portion 212 protruding from the sensing chip 3, and the substrate 1 is provided with a third pad 13 inside the first pads 12 and adjacent to the extension portion 212; That is, the third pad 13 is located between the first pads 12 and the extending portion 212, but the present invention is not limited thereto.

再者,該第三電子晶片7設置於該延伸部212上,並且該第三電子晶片7是通過導線5a而電性連接於該基板1(的第三接墊13)。其中,該第三電子晶片7鄰近於該感測晶片3,並且該第三電子晶片7相較於該絕緣體21的高度較佳是低於該感測晶片3頂面31相較於該絕緣體21的高度,避以避免第三電子晶片7的訊號干擾到金屬線5的訊號。 Furthermore, the third electronic chip 7 is disposed on the extension portion 212, and the third electronic chip 7 is electrically connected to the substrate 1 (the third pad 13) through a wire 5 a. The third electronic chip 7 is adjacent to the sensing chip 3, and the height of the third electronic chip 7 relative to the insulator 21 is preferably lower than the top surface 31 of the sensing chip 3 compared to the insulator 21. To avoid the signal of the third electronic chip 7 from interfering with the signal of the metal wire 5.

另,該感測晶片3的頂面31可以包含有位於該感測區311外側且未接觸該些金屬線5的一非打線區313,而該絕緣體21與該封裝體6則對應該非打線區313而形成有下述構造。 In addition, the top surface 31 of the sensing chip 3 may include a non-wired area 313 located outside the sensing area 311 and not in contact with the metal wires 5, and the insulator 21 and the package body 6 should be non-wired. The region 313 is formed with the following structure.

該透光片4的尺寸大於該感測晶片3的尺寸,並且該重佈式晶片結構2的尺寸大於該透光片4的尺寸,該絕緣體21包含有突伸出該感測晶片3的非打線區313的一承載部213。其中,該封裝 體6進一步包含有設置於該承載部213上且鄰近於該非打線區313的一延伸體65,並且該延伸體65於本實施例中是相連於鄰近該非打線區313的該感測晶片3側邊緣33(如:圖4中的該感測晶片3的右側邊緣33),並且該延伸體65相對於該絕緣體21的高度較佳是等於該非打線區313相對於該絕緣體21的高度。 The size of the light-transmitting sheet 4 is larger than the size of the sensing chip 3, and the size of the redistribution-type wafer structure 2 is larger than the size of the light-transmitting sheet 4. The insulator 21 includes A carrying portion 213 of the wiring area 313. Wherein the package The body 6 further includes an extension 65 disposed on the supporting portion 213 and adjacent to the non-wired region 313, and in this embodiment, the extension 65 is connected to the sensing chip 3 side adjacent to the non-wired region 313. The edge 33 (eg, the right edge 33 of the sensing chip 3 in FIG. 4), and the height of the extension body 65 relative to the insulator 21 is preferably equal to the height of the non-wired area 313 relative to the insulator 21.

更詳細地說,該支撐體61的一部分夾持於該感測晶片3的頂面31以及該透光片4之間(如圖4中的感測晶片3之左側位置),而該支撐體61的另一部分夾持於該透光片4以及該延伸體65之間(如圖4中的感測晶片3之右側位置),並且該支撐體61埋置於該包覆體63內。然而,在本發明未繪示的其他實施例中,該封裝體6也可以省略該延伸體65;也就是說,圖4中的該感測晶片3左、右側的構造是對稱的,所以該支撐體61可以是完全夾持於該感測晶片3的頂面31以及該透光片4之間。依上所載,本發明的該支撐體61可以是至少部分夾持於該感測晶片3的頂面31以及該透光片4之間。 In more detail, a part of the supporting body 61 is sandwiched between the top surface 31 of the sensing wafer 3 and the light transmitting sheet 4 (as shown on the left side of the sensing wafer 3 in FIG. 4), and the supporting body Another part of 61 is sandwiched between the transparent sheet 4 and the extended body 65 (as shown on the right side of the sensing wafer 3 in FIG. 4), and the support body 61 is embedded in the covering body 63. However, in other embodiments not shown in the present invention, the package body 6 may also omit the extension body 65; that is, the structure of the left and right sides of the sensing chip 3 in FIG. 4 is symmetrical, so the The supporting body 61 may be completely sandwiched between the top surface 31 of the sensing wafer 3 and the transparent sheet 4. According to the above, the support body 61 of the present invention may be at least partially sandwiched between the top surface 31 of the sensing wafer 3 and the transparent sheet 4.

再者,於本實施例中,每條金屬線5的一部分(及其相連接的第二接墊312)埋置於該支撐體61內,而每條金屬線5的另一部分(及其相連接的第一接墊12)埋置於該包覆體63內,但本發明不以此為限。 Moreover, in this embodiment, a part of each metal wire 5 (and the second pad 312 connected to it) is buried in the supporting body 61, and another part of each metal wire 5 (and its phase) The connected first pads 12) are buried in the covering body 63, but the invention is not limited thereto.

此外,在本發明未繪示的其他實施例中,實施例一與實施例二的該光學感測器100可以依據設計需求而彼此參酌置換內部構造,例如:實施例一的該光學感測器100也可以設有該第三電子晶片7,並且該基板1與該絕緣體21對應該第三電子晶片7而形成有如同實施例二記載的構造。 In addition, in other embodiments not shown in the present invention, the optical sensor 100 of the first embodiment and the second embodiment may mutually replace the internal structure according to design requirements, for example, the optical sensor of the first embodiment 100 may be provided with the third electronic wafer 7, and the substrate 1 and the insulator 21 may have a structure as described in the second embodiment corresponding to the third electronic wafer 7.

[本發明實施例的技術效果] [Technical effect of the embodiment of the present invention]

綜上所述,本發明實施例所公開的光學感測器100,其將該第 一電子晶片22埋置於該重佈式晶片結構2的絕緣體21中,並使該重佈式晶片結構2與該感測晶片3之間存在特定的配置關係(如:該感測區311朝向該重佈式晶片結構2正投影所形成的投影區域位於該重佈式晶片結構2的外輪廓之內),所以該重佈式晶片結構2能夠有效地支撐感測晶片3,據以在感測晶片3進行打線的過程中,有效地抵抗施加於感測晶片3的外力。 In summary, the optical sensor 100 disclosed in the embodiment of the present invention An electronic chip 22 is buried in the insulator 21 of the redistribution wafer structure 2, and a specific configuration relationship exists between the redistribution wafer structure 2 and the sensing wafer 3 (for example, the sensing area 311 faces The projection area formed by the orthographic projection of the redistribution wafer structure 2 is located within the outer contour of the redistribution wafer structure 2), so the redistribution wafer structure 2 can effectively support the sensing wafer 3, so that During the wire bonding process of the test chip 3, it effectively resists the external force applied to the test chip 3.

再者,在該絕緣體21的側邊緣211與該感測晶片3的鄰近側邊緣33之間形成有小於等於1毫米的距離Da、Db,可以避免該感測晶片3與基板1之間形成過於狹長的縫隙,進而使該感測晶片3與基板1之間不易產生氣泡。 Furthermore, a distance Da, Db of 1 mm or less is formed between the side edge 211 of the insulator 21 and the adjacent side edge 33 of the sensing wafer 3, which can prevent the formation of excessive distance between the sensing wafer 3 and the substrate 1. The narrow gap makes it difficult for air bubbles to be generated between the sensing wafer 3 and the substrate 1.

以上所述僅為本發明的優選可行實施例,並非用來侷限本發明的保護範圍,凡依本發明專利範圍所做的均等變化與修飾,皆應屬本發明的權利要求書的保護範圍。 The above description is only the preferred and feasible embodiments of the present invention, and is not intended to limit the protection scope of the present invention. Any equivalent changes and modifications made according to the patent scope of the present invention shall fall within the protection scope of the claims of the present invention.

Claims (10)

一種光學感測器,包括:一基板;一重佈式晶片結構,包含有一絕緣體、埋置於該絕緣體的一第一電子晶片、及連接於該絕緣體與該第一電子晶片底部的一重置線路;其中,該重置線路電性連接於該第一電子晶片,並且該重佈式晶片結構通過該重置線路覆晶固定於該基板,該絕緣體的頂面與底面分別切齊於該第一電子晶片的頂面與底面;一感測晶片,具有大於該第一電子晶片的尺寸,並且該感測晶片設置於該重佈式晶片結構上;其中,該感測晶片的一頂面包含有一感測區,並且該感測區朝向該重佈式晶片結構正投影所形成的一投影區域位於該重佈式晶片結構的外輪廓之內,該感測晶片的底面固定於該絕緣體的該頂面與該第一電子晶片的該頂面;一透光片,位於該感測晶片的上方;多條金屬線,電性連接該基板與該感測晶片;以及一封裝體,設置於該基板上,並且該重佈式晶片結構、該感測晶片、及該些金屬線埋置於該封裝體內;其中,該封裝體固定該透光片於該感測晶片上方、並裸露該透光片的部分表面。An optical sensor includes: a substrate; a redistributed wafer structure, including an insulator, a first electronic chip embedded in the insulator, and a reset circuit connected between the insulator and the bottom of the first electronic chip ; Wherein the reset circuit is electrically connected to the first electronic chip, and the redistribution chip structure is fixed to the substrate through the reset circuit flip chip, and the top surface and the bottom surface of the insulator are respectively aligned with the first A top surface and a bottom surface of the electronic chip; a sensing chip having a size larger than that of the first electronic chip, and the sensing chip is disposed on the redistributed wafer structure; wherein a top bread of the sensing chip contains a A sensing area, and a projection area formed by the orthographic projection of the sensing area toward the redistributed wafer structure is located within the outer contour of the redistributed wafer structure, and the bottom surface of the sensing wafer is fixed to the top of the insulator Surface and the top surface of the first electronic chip; a light-transmitting sheet located above the sensing chip; a plurality of metal wires electrically connecting the substrate and the sensing chip; and a package body disposed on the On the substrate, and the redistribution wafer structure, the sensing chip, and the metal wires are buried in the package body; wherein the package body fixes the light transmitting sheet above the sensing chip and exposes the light transmission Part of the surface of the sheet. 如請求項1所述的光學感測器,其中,該重佈式晶片結構包含有一第二電子晶片,並且該第一電子晶片與該第二電子晶片間隔地埋置於該絕緣體內,該第一電子晶片與該第二電子晶片各自電性連接於該重置線路。The optical sensor according to claim 1, wherein the redistributed wafer structure includes a second electronic wafer, and the first electronic wafer and the second electronic wafer are buried in the insulator at intervals, and the first An electronic chip and the second electronic chip are each electrically connected to the reset circuit. 如請求項2所述的光學感測器,其中,該絕緣體包含有突伸出該感測晶片的一延伸部,該光學感測器進一步包括有設置於該延伸部上的一第三電子晶片,並且該第三電子晶片通過打線而電性連接於該基板。The optical sensor according to claim 2, wherein the insulator includes an extension portion protruding from the sensing chip, and the optical sensor further includes a third electronic chip disposed on the extension portion. And the third electronic chip is electrically connected to the substrate by wire bonding. 如請求項1所述的光學感測器,其中,該絕緣體的至少局部側邊緣相對於該感測晶片的鄰近側邊緣突伸出一距離,並且該距離小於1毫米。The optical sensor according to claim 1, wherein at least a partial side edge of the insulator protrudes a distance relative to an adjacent side edge of the sensing wafer, and the distance is less than 1 mm. 如請求項1所述的光學感測器,其中,該絕緣體的至少局部側邊緣相對於該感測晶片的鄰近側邊緣內縮有一距離,並且該距離小於1毫米。The optical sensor according to claim 1, wherein at least a partial side edge of the insulator is retracted within a distance from an adjacent side edge of the sensing wafer, and the distance is less than 1 mm. 如請求項1所述的光學感測器,其中,該重佈式晶片結構包含有多個焊球,該重置線路通過該些焊球而焊接於該基板;該封裝體包含有一底部填充劑,並且該底部填充劑佈滿於該重佈式晶片結構與該基板之間的一間隙。The optical sensor according to claim 1, wherein the redistributed wafer structure includes a plurality of solder balls, and the reset circuit is soldered to the substrate through the solder balls; the package includes an underfill And the underfill agent is covered in a gap between the redistributed wafer structure and the substrate. 如請求項1所述的光學感測器,其中,該封裝體包含有:一支撐體,至少部分夾持於該感測晶片的該頂面以及該透光片之間;及一包覆體,設置於該基板上;其中,該重佈式晶片結構、該感測晶片、及該支撐體埋置於該包覆體內,並且該包覆體裸露該透光片的該部分表面。The optical sensor according to claim 1, wherein the package includes: a support body, which is at least partially sandwiched between the top surface of the sensing chip and the transparent sheet; and a cover body Is disposed on the substrate; wherein the redistribution-type wafer structure, the sensing wafer, and the support are buried in the covering body, and the covering body exposes a part of the surface of the transparent sheet. 如請求項7所述的光學感測器,其中,每條該金屬線的一部分埋置於該支撐體內,而每條該金屬線的另一部分埋置於該包覆體內。The optical sensor according to claim 7, wherein a part of each of the metal wires is embedded in the support body, and another part of each of the metal wires is embedded in the cover body. 如請求項7所述的光學感測器,其中,該感測晶片的該頂面包含有位於該感測區外側且未接觸該些金屬線的一非打線區,該絕緣體包含有突伸出該感測晶片的該非打線區的一承載部,該封裝體進一步包含有設置於該承載部上且鄰近於該非打線區的一延伸體;其中,該支撐體的一部分夾持於該感測晶片的該頂面以及該透光片之間,而該支撐體的另一部分夾持於該透光片以及該延伸體之間,並且該支撐體埋置於該包覆體內。The optical sensor according to claim 7, wherein the top bread of the sensing chip includes a non-wired area located outside the sensing area and not in contact with the metal wires, and the insulator includes a protrusion protruding from the wire. A carrying portion of the non-wired area of the sensing chip, the package further includes an extension disposed on the carrying portion and adjacent to the non-wired area; wherein a portion of the support is clamped by the Between the top surface and the light-transmitting sheet, another part of the support is sandwiched between the light-transmitting sheet and the extension, and the support is embedded in the covering body. 如請求項7所述的光學感測器,其中,該重佈式晶片結構包有多個焊球,該重置線路通過該些焊球而焊接於該基板,並且該包覆體佈滿於該重佈式晶片結構與該基板之間的一間隙。The optical sensor according to claim 7, wherein the redistributed wafer structure includes a plurality of solder balls, the reset circuit is soldered to the substrate through the solder balls, and the cover is covered with A gap between the redistributed wafer structure and the substrate.
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CN2470959Y (en) * 2001-02-26 2002-01-09 胜开科技股份有限公司 stacked image sensor
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Patent Citations (3)

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Publication number Priority date Publication date Assignee Title
CN2470959Y (en) * 2001-02-26 2002-01-09 胜开科技股份有限公司 stacked image sensor
CN104752236A (en) * 2013-12-30 2015-07-01 台湾积体电路制造股份有限公司 Two step molding grinding for packaging applications
TW201806140A (en) * 2016-05-31 2018-02-16 半導體組件工業公司 Image sensor semiconductor packages and related methods

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