TWI672695B - Non-volatile transistor element including a buried ferroelectric material based storage mechanism - Google Patents

Abstract

The present disclosure provides a storage element, such as a storage transistor, wherein at least one storage mechanism is provided based on the ferroelectric material formed in the buried insulating layer of the SOI transistor architecture. In a further exemplary embodiment, an additional storage mechanism is implemented in the gate electrode structure to provide an increased overall information density. In some example embodiments, the storage mechanism in the gate electrode structure is provided in the form of a ferroelectric material.

Description

 a non-volatile transistor element comprising a storage mechanism based on buried ferroelectric materials  

The present disclosure generally relates to techniques for utilizing the characteristics of ferroelectric materials to provide a non-volatile storage mechanism in circuit elements such as field effect transistors.

In many types of electronic components, data storage techniques may have to be implemented to ensure proper functioning of the corresponding technical system. For example, in many applications, different types of information must be processed and therefore stored, which is typically implemented based on digital data. A basic information entity can be viewed as an entity that is capable of presenting different logical states such that implementation of a corresponding logical state in the hardware requires the ability to "occupy" a correspondingly different physical state, such as a different voltage state, current state, etc. An electronic configuration, which can accordingly be associated with the respective logical state.

Thus, when a suitable electronic architecture is provided, these different physical states (implemented primarily in different electronic states in complex integrated circuits) can be effectively detected to allow reliable detection of corresponding different characteristics, such as the state of charge of the capacitor. The corresponding conductor, such as the amount of current in the channel region of the field effect transistor, and the like. Therefore, when appropriate electronic characteristics such as charge state, current drive capability, etc. are appropriately manipulated, the corresponding electronic state, and thus the logic state, can be programmed into the lower electronic structure, wherein the corresponding electronic properties are based on the overall configuration of the basic electronic structure and Thus the logic state can be programmed to be permanently stored, that is, after the power supply is turned off and re-powered to the corresponding structure, the corresponding electronic characteristic can be effectively recovered, and in other cases, the corresponding electronic characteristic and thus associated with it The logic state can only be obtained when the supply voltage is present, and the corresponding information may be lost when the supply voltage is turned off. The previous storage mechanism may also be referred to as "non-volatile", and in the context of this case, the term may be used primarily to describe the storage mechanism, and the corresponding programming of the information may be based on a substantially irreversible process. This "non-volatile" storage mechanism also allows for frequent re-programming of the corresponding storage mechanism as compared to the one-time program mechanism. To implement the non-volatile storage mechanisms and volatile storage mechanisms as defined above, a wide variety of electronic configurations such as registers, storage units, storage transistors, and the like are well known in the art, wherein various types of storage structures can present particular operations. Advantages and disadvantages.

For example, if a large amount of data is to be temporarily stored in an electronic device such as a computer, a microprocessor, or the like, it may be necessary to frequently access the material. If extremely high access speeds are not the most preferred, so-called "dynamic storage devices" may often be used, which can be effectively implemented as a single storage capacitor and a transistor to achieve unit information integration. Circuit area. In this regard, unit information will be understood as any electronic mechanism capable of assuming two different electronic states, which are associated with two different logic states, respectively. Due to the fact that the charge in the corresponding storage capacitor must be periodically refreshed, and because of the need to migrate a higher amount of charge when programming the corresponding storage capacitor, the achievable delay is greater compared to the so-called "static memory structure" . In these static memory structures, a particular logic state can be determined by the conductive state of a circuit component, such as a transistor, and the change in logic state is implemented by changing the state of the circuit component such that substantially the switching time of the associated circuit component is determined. Delay. Thus, in this case, the change in the logic state of the static memory cells can be implemented on the order of the switching time of the respective transistor elements of the technology node under consideration. Although the above described storage techniques may represent an efficient mechanism that is easily implemented in any type of integrated circuit, due to the volatile nature of this mechanism, data storage is limited to the number of times the voltage is supplied to the device, since any information is cutting off the Lost when supplying voltage.

Since permanent storage of logic states (in combination with their programmable capabilities) is often necessary, many non-volatile data storage technologies have been developed, in particular, many large-capacity storage systems based on magnetic storage devices, optical storage technologies, etc. due to A large amount of overhead in terms of hardware and software, especially long access times, may not be compatible with multiple applications. Therefore, a great deal of effort has been made to implement non-volatile storage mechanisms to supplement or replace time-efficient storage structures. For example, flash memory can be used as a non-volatile storage structure in which a suitably designed capacitive structure with the potential to be dynamically reconfigured is used in the transistor configuration to specifically affect transistor characteristics, such as thresholds ( Threshold) voltage, etc.

The threshold voltage of a field effect transistor can be understood as a device specific voltage applied to a portion of the channel region to achieve a significant change in the current drive capability of the channel region. For example, the threshold voltage can represent a point at which further control voltage is applied when no or only a very low voltage is applied between the terminals of the channel region (commonly referred to as source/drain terminals or regions). The increase can result in a significant increase in current through the channel region or a significant decrease in channel resistance.

For example, in the above described storage mechanism used in flash memory, charge carriers can be injected into or removed from a dielectric material near the channel of the transistor to be based on the charge within the dielectric material. The flow control controls the characteristics of the transistor. That is, the presence or absence of charge carriers injected into the dielectric material can significantly affect the channel region, for example, in the form of respective threshold voltages, thereby effectively allowing detection of transistor characteristics when operating the transistor. difference. Thus, the particular state of the capacitor configuration (including dielectric materials with varying line charge carriers) can reflect the desired logic state and can therefore be effectively "read". Alternatively, by varying the amount of charge carriers in the dielectric material, the desired logic state can be stored therein, typically by establishing a particular operating environment to inject or remove the line charge carriers. In this way, a single transistor can be sufficient to store unit information, thereby significantly facilitating the superior information density of electronically programmable non-volatile storage devices. Although such a storage transistor of a flash memory structure in which a charge can be captured or released from a particular portion of the gate's electrical structure can represent a very efficient solution for storing unit information, the results indicate that In particular, the constant shrinkage of advanced semiconductor devices may lead to greater difficulties. For example, further shrinking of the overall gate size of such storage transistors may require highly sophisticated techniques to form corresponding gate electrode structures. Therefore, implementing such a floating gate type storage transistor can lead to greater challenges, requiring additional effort and increasing process complexity.

Therefore, other methods have recently been proposed in which a ferroelectric effect is utilized to set circuit elements such as resistors, transistors, etc., wherein the ferroelectric material can be polarized to appropriately affect the operational behavior. The respective polarization states can then be considered as corresponding logic states, so they can be written to or read from corresponding circuit elements comprising the polarizable ferroelectric material. For example, in a complex ferroelectric crystal, a ferroelectric material can be included in or near the dielectric material of the gate electrode structure, thereby significantly affecting the electronic properties of the channel region depending on the polarization state of the ferroelectric material.

Referring to Figures 1A through 1D, a typical conventional ferroelectric prior art transistor is described in detail, wherein the transistor as described above can be used as a non-volatile storage transistor.

1A is a cross-sectional view showing the transistor 100, which may be provided in the form of an SOI (insulator on insulator or semiconductor on insulator) architecture in which a buried insulating layer such as a ceria layer 102 is buried. The actual "active" semiconductor material 103, such as tantalum material, tantalum/niobium material, etc., is separated from the semiconductor substrate material 101 disposed in the form of tantalum, niobium or the like. It will be appreciated that in complex applications, when a substantially depleted SOI configuration is to be provided, the active semiconductor layer 103 can be provided with a suitably reduced thickness of only a few nanometers. In other cases, any other suitable thickness of the semiconductor layer 103 can be used, depending on overall design requirements. Moreover, in other cases, the SOI architecture may not be implemented and the semiconductor layer 103 may be formed over or as part of the portion of the substrate material 101.

The transistor 100 can also include a gate electrode structure 110 that is configured and configured to control the channel region 106 formed in the semiconductor layer 103, depending on the overall configuration of the transistor 100 and the source formed in the semiconductor layer 103. The voltage of the gate electrode structure 110 between the region 104 and the germanium region 105 provides a conductive channel. It should be understood that the terms "source zone" and "deuterium zone" are interchangeable depending on the particular environment in which the transistor 100 can be operated. Moreover, any corresponding details regarding the source germanium regions 104, 105 are not shown, such as with respect to dopant concentration and the like. As noted above, in complex applications, the source germanium regions 104, 105 in combination with the channel region 106 can represent a fully depleted transistor architecture, wherein the channel region 106 can remain substantially undoped or can exhibit very low dopants. The concentration, such that when a corresponding control voltage is applied to the gate electrode structure 110, the corresponding depletion region can occupy substantially the entire channel region.

In general, the gate electrode structure 110 can comprise an electrode material having any suitable configuration based on a semiconductor material such as polysilicon, germanium, etc., possibly in combination with a metal-containing electrode material. For example, in any particular state in which the gate electrode structure 110 is fabricated, a portion of the semiconductor material can be converted into a metal-semiconductor-compound, such as a metal telluride or the like, which is a mature concept for enhancing the overall conductivity of a semiconductor-based region. . Moreover, in complex applications, a combination of semiconductor-based materials can be provided with corresponding metal-containing materials, such as titanium nitride. For convenience, only the electrode materials 111 and 112 are shown in Fig. 1A, however, any other configuration may be applied as described above. Moreover, a dielectric material 113 (partially disposed in the form of a ferroelectric material) may be provided to separate the conductive electrode material 111 from the channel region 106, as is well known for typical field effect transistor architectures. It will be appreciated that a complex application with a reduced overall transistor size (especially with a reduced gate length (i.e., horizontal extension of gate electrode material 113 in Figure 1A) may require a gate electrode (i.e., a conductive material, For example, superior capacitive coupling between the electrode material 111) and the channel region 106 is included to allow sufficient and reliable control of the channel region 106. Therefore, so-called "high-k" dielectric materials (that is, dielectric materials having a dielectric constant of 10.0 or significantly higher) are often used, possibly in combination with "conventional" dielectric materials such as hafnium oxide, tantalum nitride, Niobium oxynitride and the like. For example, yttria-based dielectric materials are often used in the context of high-k gate electrode structures, wherein, at the same time, yttria-based dielectric materials can also exhibit ferroelectric properties, thereby making these materials included in ferroelectrics. A viable candidate material in a crystal element. However, it should be understood that other ferroelectric materials may also be used to implement the ferroelectric crystal. The final composition of the gate dielectric material 113 and its thickness can be suitably selected to meet the overall device requirements. In particular, the location, thickness, and composition of the dielectric material 113 are selected to provide the ability to establish the desired polarization state, that is, to establish a crystal configuration having the possibility of having at least two different crystal states to form substantially perpendicular to the channel region. A permanent electric field in the direction of current in 106. The direction of current flow in channel region 106 may substantially coincide with the horizontal direction of Figure 1A.

Moreover, the gate electrode structure 110 can generally comprise a spacer structure 114 formed of any suitable dielectric material and having any suitable dimensions along the length of the transistor (ie, the horizontal direction in FIG. 1A) to conform to the overall device. Claim.

The transistor 100 of FIG. 1A can be formed based on a well-established fabrication technique in which the semiconductor layer 103 can be formed by an epitaxial growth technique or the like to have a desired overall configuration in terms of material composition, initial doping, and the like. Buried insulating layer 102 may already be present or may be formed in accordance with well-established process techniques. Subsequently, a corresponding programming sequence can be performed to deposit and/or otherwise form a dielectric substrate, such as hafnium oxide, hafnium oxynitride, etc., followed by formation and processing of other dielectric components, such as yttria-based. A dielectric material in which a metal-containing material is usually also provided to appropriately limit the underlying sensitive dielectric material. After deposition of one or more additional electrode materials, patterning of the gate electrode structure 110 can be performed based on complex lithography and etching techniques depending on the desired overall transistor size. The gate electrode structure 110 can also house the spacer structure 114 and an additional process can be performed to set the source germanium regions 104, 105 with appropriate electronic characteristics. For example, the dopant species can be incorporated by, for example, epitaxial growth techniques, implantation, and the like. Moreover, other suitable processes, such as an annealing process, etc., can be performed to obtain the final electronic configuration of the transistor 100. Next, an additional process can be performed to provide the package 107 for the underlying transistor structure and the high conductive contact with the source germanium regions 104, 105 and the gate electrode structure 110 and possibly the semiconductor layer 103 (if desired).

Figure 1B is a schematic illustration of a transistor 100 in an operational mode in which a ferroelectric material formed adjacent the dielectric material 113 has a first polarization state 113A, wherein, as described above, a crystal configuration can be established A particular electric field is obtained that is substantially perpendicular to the direction of current flow in channel region 106. It can be assumed that the polarization state 113A can result in the attraction of negative charge carriers such that the channel region 106 can be rich in negative charge carriers, such as electrons, to significantly affect the electronic behavior of the transistor 100. For example, when a substantially N-type configuration is assumed, the polarization state 113A may result in reduced overall channel resistance or earlier current generation for a given voltage applied to the gate electrode structure 110. That is, for an N-type transistor, when the polarization state 113A is active, in order to achieve the desired current through the channel region 106, a reduced gate voltage needs to be applied.

That is, the polarization state 113A can be established in the material 113 by applying a suitable programming voltage between the terminal 110T of the gate electrode structure 110 and the "ground" terminal 103T connecting the semiconductor material 103. It should be understood that FIG. 1B only schematically illustrates the programming mechanism, assuming a bulk configuration in which a ground terminal 103T may be required to obtain the desired electric field on the channel region 106. In other cases, when a fully depleted device configuration (also described above) is used, the drain and/or source 105, 104 may be connected to a suitable reference voltage through respective terminals 105T, 104T, such as a ground potential, thereby also A corresponding desired electric field is established on the channel region 106.

1C schematically shows a transistor 100 in which an electric field having a reverse polarity is applied to the dielectric material 113, for example, by a suitable voltage at terminals 110T, 103T and/or terminals 105T, 104T as described above. The state 113A is opposite to the second polarization state 113B. In this case, positive charge carriers can be attracted into the channel region 106, for example by removing electrons, thereby contributing to an increase in channel resistance for a given gate voltage of the N-type transistor. That is, the formation of the conductive channel in the channel region 106 can be significantly suppressed for a given gate voltage as compared with the case described with reference to FIG. 1B. Thus, the formation of the conductive channel in the trench region 106 can only be achieved at significantly higher gate voltages than in the case of Figure 1B. That is, the threshold voltages of the transistors 100 having two different polarization states (i.e., states 113A, 113B) can be significantly different from each other, and this difference can be reliably used to detect different thresholds based on, for example, different current drive capabilities. Voltage. It will be appreciated that during "normal" operation of the transistor, the channel region 106 can be controlled using a significantly reduced gate voltage as compared to a programmed voltage that can cause the crystal configuration to align with an externally applied programming electric field. For example, the programming voltage can be on the order of 5V, while the standard operating voltage can be about 1V or less.

Figure 1D schematically illustrates the different behavior of apparatus 100 having different electronic configurations of Figures 1B and 1C. Figure 1D shows source/drain currents for different gate voltages, where the gate voltage is plotted along the horizontal axis and the current is plotted along the vertical axis. As can be seen from Figure 1D and as described above, for the N-type configuration, at the low gate voltage, a significant increase in source/drain current is observed for the polarization state 113A, resulting in curve A. On the other hand, for the same gate voltage, the polarization state 113B can result in substantially no current, and therefore, a significantly higher gate voltage may be required to ultimately induce a significant increase in source/drain current. Thus, the gate voltage that causes a significant increase in current can be referred to as a corresponding threshold voltage to indicate that polarization state 113A results in a low threshold voltage, while polarization state 113B results in a high threshold voltage of the N-type transistor configuration. It should be understood that corresponding functional behavior can also be obtained for P-type ferroelectric crystals, however, any associated polarity and polarization are reversed. However, in this case, a significant difference in the resulting threshold voltage can also be achieved and used as a storage mechanism. It should be understood that this state is sustainable once a particular polarization state is established, even after the supply voltage is turned off, thereby providing a non-volatile storage mechanism. Alternatively, by applying a corresponding programming voltage, the polarization state can be adjusted at any time during operation of the transistor 100 in accordance with the desired logic state to be implemented in the transistor 100.

The results show that, as described above, although a variety of possible methods for non-volatile programmable storage mechanisms can be used, wherein, in particular, the ferroelectric crystal concept can be highly compatible with complex overall manufacturing techniques, there is still an increase in overall bits. Density and/or the need to provide superior operating environment and flexibility in setting up non-volatile storage mechanisms. For example, it has been proposed to differentially manipulate the charge trapped at each end of the floating gate dielectric material by appropriately controlling the injection and removal of charge carriers into the floating gate of the transistor, thereby enabling flashing The bit density of the storage transistor is doubled. That is, at one end of the floating gate along the length of the transistor, a specific control scheme can be applied to allow injection or removal of charge carriers in this region, while the opposite of the floating gate At the end, charge carriers can be injected or removed independently from the other end, providing the possibility of independently storing two bits within a single transistor. For reading the two different bits, for example, currents in two opposite directions can be observed, and the respective current values and directions can be associated with respective logic states.

Although this concept of independent charge carrier trapping and removal in different regions of the floating gate configuration can provide increased overall bit density, the results indicate that a significant amount of additional effort is required to implement the dual bit configuration while still having to Consider only moderate compatibility with complex device technology, as also described above with reference to the unit fast lightning crystal.

Accordingly, in view of the above, the present disclosure is directed to techniques in which a non-volatile storage element, such as a field effect transistor, can be disposed based, at least in part, on a ferroelectric material while avoiding or at least alleviating the effects of one or more of the above problems.

A brief summary of the invention is provided below to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is not intended to identify key or critical elements or the scope of the invention. Its sole purpose is to present some concepts in the form of a

Basically, it has been recognized that in an SOI architecture, an efficient storage mechanism based on ferroelectric materials can be implemented in the buried insulating layer of the SOI configuration, thereby contributing to superior flexibility in designing the corresponding SOI storage transistor. For example, this superior flexibility associated with the implementation of the storage mechanism in the buried insulating layer can result in less critical process techniques for forming a reduced gate electrode structure, resulting in a substantially constant overall The electrode configuration potentially contributes to superior operational behavior while still providing a non-volatile storage mechanism. In other example embodiments, the storage mechanism implemented based on the buried insulating layer can be effectively combined with additional non-volatile storage mechanisms such that an increased bit density is generally achieved. In some example embodiments, the storage mechanism based on the buried insulating layer may be combined with a storage mechanism implemented in the gate electrode structure (based on the ferroelectric material disposed therein), while in other example embodiments, the mature floating The gate configuration can be supplemented by the ferroelectric material based storage mechanism in the buried insulating layer, thereby also enhancing the overall efficiency of these conventional floating gate methods.

One example embodiment disclosed herein relates to a non-volatile storage element. The storage element includes a channel region formed in the semiconductor material and a control electrode structure disposed to control current flow through the channel region. The non-volatile storage element further includes a first storage mechanism configured to adjust a value of a threshold voltage of the channel region. Moreover, a second storage mechanism is provided to adjust the value of the threshold voltage, wherein the second storage mechanism comprises a ferroelectric material and is configured to be capable of selecting the threshold voltage of the channel region in conjunction with the first storage mechanism More than one different value.

In accordance with another example embodiment disclosed herein, a non-volatile storage transistor component includes a channel region and a gate electrode structure configured to control current in the channel region. The non-volatile storage transistor component further includes a buried insulating layer formed under the channel region, wherein the buried insulating layer comprises a ferroelectric material to provide a storage mechanism for storing information in a non-volatile manner.

In yet another example embodiment disclosed herein, a method is provided. The method includes selecting a first polarization state of a ferroelectric material formed adjacent a channel region of the transistor element. Moreover, the method includes selecting a first storage state of at least one of the charge trapping material and the second ferroelectric material formed adjacent the channel region. Moreover, the method includes assigning a first logic state to the first channel environment induced by the first polarization state and the first storage state. Additionally, the method includes selecting a second storage state of the at least one of the charge trapping material and the second ferroelectric material. Moreover, a second logic state is assigned to the second channel environment induced by the first polarization state and the second storage state. Moreover, the method includes assigning at least one additional logic state to one of the first and second storage states when the second polarization state of the ferroelectric material is combined, wherein the first and second poles The state is reciprocal.

100‧‧‧Optoelectronics

101‧‧‧Semiconductor substrate material

102‧‧‧Insulation

103‧‧‧Semiconductor layer

103T, 104T, 105T, 110T‧‧‧ terminals

104‧‧‧ source area

105‧‧‧汲

106‧‧‧Channel area

107‧‧‧Package

110, 210‧‧‧ gate electrode structure

111, 112, 211‧‧‧ electrode materials

113‧‧‧ dielectric materials

113A‧‧‧First polarization state

113B‧‧‧second polarization state

114‧‧‧ spacer structure

200‧‧‧Optoelectronic components

201‧‧‧Substrate material

201V, 210V‧‧‧ voltage

202‧‧‧Insulation

202A, 202B‧‧‧ dielectric materials

202F‧‧‧ Ferroelectric materials

203‧‧‧Semiconductor layer

204, 205‧‧‧ semiconductor area

206‧‧‧Channel area

207‧‧‧Isolation structure

212‧‧‧ Coverage

213‧‧‧ dielectric materials

214‧‧‧ spacer structure

300‧‧‧ components

300A‧‧‧First storage mechanism

300B‧‧‧Second storage mechanism

302A, 302B, 313A, 313B‧‧‧Polarization status

302F‧‧‧buried ferroelectric materials

306‧‧‧Channel area

310‧‧‧Gate electrode structure

311F‧‧‧ Ferroelectric materials

The disclosure may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals indicate like elements, and wherein: Figure 1A shows a cross-sectional view of a conventional prior art ferroelectric transistor element; 1C is a cross-sectional view showing a conventional prior art ferroelectric transistor element in two different polarization states; FIG. 1D is a view schematically showing a prior art ferroelectric transistor element corresponding to the different polarization states of FIGS. 1B and 1C. Different driving current capabilities and resulting threshold voltages; FIG. 2 is a cross-sectional view schematically showing a storage transistor element including at least one storage mechanism based on ferroelectric material disposed in a buried insulating layer in accordance with an exemplary embodiment of the present disclosure; 3A through 3D are schematic cross-sectional views showing a storage transistor element including two storage mechanisms in accordance with further example embodiments of the present disclosure, at least one of which is based on iron disposed in a buried insulating layer Electrical material; and FIG. 3E schematically shows different electronic shapes corresponding to different electronic configurations of the storage transistor elements shown in FIGS. 3A to 3D FIG e.g. different threshold voltage values.

The specific embodiments of the inventive subject matter are shown by way of example in the drawings and are described in detail herein. It should be understood, however, that the description of the specific embodiments of the present invention is not intended to be limited to the specific forms disclosed. Equal and alternative.

Various exemplary embodiments of the invention are described below. For the sake of clarity, not all features of an actual implementation are described in this specification. Of course, it should be understood that in the development of any such actual embodiment, a large number of specific implementation decisions must be made to achieve a developer's specific goals, such as compliance with system-related and business-related constraints, which will vary from one decision to another. Implementation varies. Moreover, it should be appreciated that such development efforts can be complex and time consuming, but still be conventional routines performed by one of ordinary skill in the art in view of the present disclosure.

The disclosure will now be described with reference to the drawings. The drawings illustrate various structures, systems, and devices that are for the purpose of explanation and are not to be construed as a limitation of the details of the disclosure. The meaning of the words and phrases used herein should be understood and interpreted as being consistent with the understanding of those words and phrases. The coherent use of the terms or phrases herein is not intended to imply a particular definition, i.e., a definition that is different from what is conventionally understood by those skilled in the art. If a term or phrase is intended to have a specific meaning, that is, different from the meaning as understood by those skilled in the art, such a particular definition will be clearly indicated in the specification in a manner that clearly defines the specific definition of the term or phrase. .

The present disclosure is based on the concept of improving the information density and/or design flexibility of a non-volatile storage element, such as a transistor element, by utilizing the overall configuration of the SOI architecture in the transistor element, wherein the buried insulating material layer may be partially or completely Ferroelectric materials are substituted to provide a mechanism for storing information in a non-volatile manner that can be read during operation of the transistor element. That is, while substantially maintaining the SOI architecture, additional non-volatile control and resulting storage mechanisms can be provided that in principle support mature gate electrode structures that do not significantly change compared to conventional transistors. Formed to provide an additional degree of design flexibility because the configuration of the respective gate electrode structure can be selected in accordance with design criteria other than the criteria to be considered when designing complex transistor components. In some example embodiments disclosed herein, this additional design flexibility may be advantageously used to provide non-volatile that provides increased bit density by providing additional storage mechanisms, such as those formed in respective gate electrode structures. Store components. That is, in some example embodiments, the additional storage mechanism may be disposed in the gate electrode structure to appropriately affect the channel region, which may thus be sandwiched between ferroelectrics disposed in the buried insulating layer. The material is between the storage mechanism disposed in the gate electrode structure. In some example embodiments, the storage mechanism may be implemented based on a ferroelectric material during the provision of the additional storage mechanism in or near the gate electrode structure. In this way, efficient manufacturing techniques available for complex transistor elements can be applied to, for example, the gate electrode structures described with reference to Figures 1A through 1D, while the storage mechanism based on the ferroelectric material in the buried insulating layer can be used. This results in a higher number of different electronic configurations that can be assigned to the corresponding logical state. Thus, the two separately controllable storage mechanisms can provide increased bit density, for example, at least two different bits can be "stored" in the respective storage transistor elements, and on the other hand, the overall transistor Dimensions and basic transistor configurations may not require significant modifications.

In other example embodiments, the storage mechanism associated with the gate electrode structure may be based on a charge trapping layer (ie, based on a floating gate type gate structure), while the ferroelectric based material is located in the buried insulating layer. A storage mechanism can additionally provide additional different electronic states of the transistor and the resulting logic states. For example, as described above, a mature floating gate type transistor can accommodate a storage mechanism based on a ferroelectric material contained in a buried insulating layer, thereby possibly doubling the information density provided by the mechanism based on the charge trap layer . As noted above, the gate electrode structure including the charge trapping layer can provide unit information, or in other cases, a dual bit configuration can be provided. By combining this mechanism with buried ferroelectric materials, a corresponding doubling of the bit density can be achieved.

In some example embodiments, the storage mechanism based on the buried ferroelectric material and the storage mechanism based on the ferroelectric material implemented in or near the gate electrode structure may have different "strength" related control mechanisms of current in the channel region. Or "efficiency", for example due to the different composition of the ferroelectric material, the different regions occupied by the corresponding ferroelectric material, and the like. Due to this mechanism, the overall control effect of the two ferroelectric material-based storage mechanisms can be effectively adjusted to achieve sufficiently different drive current behavior in the channel region. For example, the region of the ferroelectric material disposed in the buried insulating material and in contact with or in the vicinity of the channel region may be at least partially in contact with or disposed adjacent to the source region of the transistor due to the arrangement of the ferroelectric material. Increase the impact. In other cases, the effective distance of the ferroelectric material located in the buried insulating layer and within the gate electrode structure can be adjusted differently to provide fine adjustment of the channel region to the gate electrode structure and the buried insulating layer. Additional control mechanisms for the overall response of the corresponding ferroelectric materials.

Thus, for a given overall transistor configuration, when the ferroelectric material in the buried insulating layer is in the first polarization state, corresponding transistor characteristics such as threshold voltage and/or current drive capability, etc., can be assigned to the corresponding number. The logical state. Similarly, when the ferroelectric material in the buried insulating layer is in the second polarization state, the corresponding transistor states can be assigned to corresponding logic states as long as the resulting transistor states are sufficiently distinguishable from each other, thereby allowing storage of electricity. Different transistor states and resulting logic states are reliably detected during normal operation of the crystal element. For example, when two storage mechanisms can be set up, each storage mechanism having two different electronic states and the resulting logical state, the combined effect of the separately controlled storage mechanism can result in four different transistor states as well as The resulting logic state, when properly configured for the overall transistor configuration, can be sufficiently differentiated to provide two-dimensional information in the device region corresponding to a single transistor component. In this way, the bit density can be doubled without over-modifying the overall transistor configuration.

Referring to Figures 2 and 3A through 3E, additional exemplary embodiments will now be described in detail, wherein, as appropriate, reference may also be made to Figures 1A through 1D.

2 is a cross-sectional view showing a non-volatile storage element, which in some exemplary embodiments is a transistor element 200, which may be formed in a suitable semiconductor layer 203 and suitably doped The semiconductor regions 204, 205 are laterally surrounded by a channel region 206, which may also be referred to herein as a source germanium region, respectively. In this case and as described above, the terms "source zone" and "deuterium zone" are also interchangeable depending on the overall circuit configuration in which component 200 can be used. With respect to the semiconductor material 203 used to form the source germanium regions 205, 204 and the channel region 206 therein, substantially any suitable material and dopant profile can be used to meet overall device requirements. For example, as previously discussed, in complex applications, the initial layer thickness of the semiconductor layer 203 may be between about 10 nanometers and 3 nanometers, depending on design requirements. Moreover, the semiconductor layer 203 may include any suitable material such as ruthenium, osmium, iridium, iridium/carbon, a Group III-V semiconductor compound, and the like. The specific dopant distribution of the source germanium regions 205, 204 is not shown for convenience.

Moreover, so-called "lift-up source-drain configurations" are often applied in which additional semiconductor material (not shown) may be formed in or on the starting material of the semiconductor layer 203 to provide suitable contact with the desired high dopant concentration. Area. Any such raised source region can be formed based on epitaxial growth techniques or the like. Moreover, to control the conductivity and current in the channel region 206 along the current direction (ie, the horizontal direction in FIG. 2), the gate electrode structure 210 can be provided with a suitable size and composition to interface with the channel region. 206 has a suitable capacitive coupling to properly control the current therein. In some example embodiments, the gate electrode structure 210 may represent a complex gate electrode structure, possibly including a high-k dielectric material, typically in combination with a metal-containing electrode material disposed adjacent to the high-k dielectric material to be in the channel region Provide suitable environment at 206 and within. That is, in these exemplary embodiments, the gate electrode structure 210 can substantially represent a "traditional" complex gate electrode structure designed primarily to achieve proper transistor operation, while the required non-volatile storage mechanism can be implemented. The buried insulating layer 202 formed under the channel region 206 and over the substrate material 201 is described in detail later.

For a standard gate electrode structure that does not require an additional storage mechanism, the gate electrode structure 210 can include, for example, a dielectric material 213 formed based on a conventional dielectric material such as hafnium oxide, tantalum nitride, hafnium oxynitride, or the like, possibly combined Any type of high-k dielectric material in which the high-k dielectric material type can be selected in accordance with device requirements that are independent of the ferroelectric storage mechanism. Moreover, in such a case, a specific cover layer 212, such as titanium nitride or the like, may be provided in combination with an additional semiconductor-based electrode material 211 which may be partially comprised of another highly conductive metal-containing material Material substitution, as described above in the context of Figure 1A. Moreover, a spacer structure 214 can generally be provided to properly cover the sensitive material of the gate electrode structure 210 and provide a mask for distributing the dopant concentration in the source regions 205, 204, if desired.

Moreover, component 200 can include buried insulating material 202, which can include ferroelectric material 202F having any suitable crystals needed to properly affect channel region 206 after establishing a corresponding polarization state in ferroelectric material 202F. Configuration and thickness. For example, the buried insulating layer 202 can have an overall thickness of about 10 to 50 nanometers or more, wherein at least in a region of the component 200 (defined by a suitable isolation structure 207, such as a shallow trench isolation laterally), a particular portion can be Ferroelectric material 202F is formed or may include ferroelectric material 202F. In some example embodiments, buried insulating layer 202 may comprise a conventional dielectric material, such as hafnium oxide, tantalum nitride, hafnium oxynitride, which may be suitably disposed to sandwich ferroelectric material 202F such that relative channel region 206 And/or substrate material 201 provides superior interface characteristics. For example, conventional dielectric material 202A can be formed under ferroelectric material 202F to form a substantially inert interface with substrate material 201. Similarly, in some example embodiments, conventional dielectric material 202B may be formed on ferroelectric material 202F to also provide superior interfacial properties with adjacent channel region 206 and source germanium regions 205, 204. In other cases, interface characteristics achieved by substantially direct contact of ferroelectric material 202F with regions in semiconductor layer 203 and/or substrate material 201 may be acceptable, and thus interface dielectric materials 202A, 202B may be omitted. One or both. In some example embodiments, ferroelectric material 202F may be provided based on a yttria material, which is a mature dielectric material that may also be used as a high-k dielectric material in a complex gate electrode structure. Accordingly, suitable techniques for depositing, patterning, and processing ferroelectric material 202F to establish a desired crystal configuration are well established and can be used to form ferroelectric material 202F. It will be appreciated that the ferroelectric material 202F can be formed such that the respective polarization states can have a direction that is substantially perpendicular to the direction of current flow in the channel region 206, thereby efficiently controlling the channel after establishing the desired polarization state in the ferroelectric material 202F. The conductive state or current in region 206. In some embodiments, other ferroelectric materials may be used in addition to or instead of the yttria-based material.

When the semiconductor material 203 is disposed and the gate electrode structure 210 and the source germanium regions 205, 204 are formed, the component 200 can be formed based on mature materials in accordance with well-established process techniques, wherein, as described above, other formation of the bonding component 200 can be specifically observed Design criteria required for complex transistor components. Prior to forming the gate electrode structure 210, the ferroelectric material 202F can be incorporated into the buried insulating material 202, which can be performed before or after the isolation structure 207 is formed, while in other cases, some process steps can be performed prior to forming the structure 207. Other process steps can be performed after the isolation structure 207 is completed. For example, when starting from a substantially bulk type substrate configuration, buried insulating material 202 can be formed, such as by forming layer 202A, for example, based on oxidation, deposition, etc., followed by deposition of a substrate of ferroelectric material 202F. This deposition can be performed based on well-established deposition techniques, which are also commonly used to form complex high-k dielectric layers of gate electrode structures. For example, chemical vapor deposition, physical vapor deposition, atomic layer deposition, or the like can be applied. Subsequently, layer 202B may be formed, if desired, for example by deposition, followed by epitaxial growth techniques in which the semiconductor material 203 may be grown using a laterally disposed seed material, which may then be planarized based on mature polishing techniques and Thin to a suitable thickness.

In other example embodiments, portions of the buried insulating material 202 may be removed, such as by a selective etch technique, which may selectively remove the buried insulating layer 202 by forming a corresponding trench of the isolation structure 207 and introducing a highly selective etch. Materials to implement. Next, ferroelectric material 202F can be deposited in corresponding openings of isolation structure 207, and thus can also be at least partially deposited in any of the cavities previously formed by the selective etching process. In other cases, a plurality of openings (not shown) may be formed in the initial semiconductor material 203, such as a plurality of trenches, wherein the substantially buried insulating material 202 may be removed and replaced by ferroelectric material 202F, possibly in combination with conventional Dielectric material 202A and/or 202B. In this case, the ferroelectric material 202F may not be continuously disposed under the channel region 206 and the source germanium regions 205, 204, but may be provided with corresponding islands, however, the islands are sufficient to properly support the control of the channel region 206. .

In other exemplary embodiments, the substrate material 201 may be a carrier substrate, and the buried insulating layer 202 may be formed by oxidation, deposition, or the like, and at least in a specific region, the ferroelectric material 202F may be formed based on any mature process scheme. . Subsequently, the initial semiconductor layer 203 can be formed, for example, by applying a wafer bonding technique. In this case, the provision of dielectric material 202B, for example in the form of a hafnium oxide layer, can provide substantially similar to conventional wafer bonding techniques for forming desired germanium-based semiconductor materials on yttria-based dielectric materials. Surface environment.

Thus, after the ferroelectric material 202F is disposed in the buried insulating layer 202, a further process (as described above) can be continued to form the remainder of the component 200.

When operating element 200, the desired gate voltage 210V can be applied to control the current in channel region 206, which is also typically the case in conventional transistor components. Moreover, additional control can be achieved by applying a corresponding voltage 201V across the buried insulating material 202, thereby achieving superior control of the channel region 206 (if desired). It will be appreciated that during normal operation, the voltages 210V and 201V may be selected within a range that significantly exceeds any voltage range required to establish a particular polarization state in the ferroelectric material 202F, as also above in Section 1A and As described in the context of Figure 1B. For example, for normal operation of component 200, the voltage controlling channel region 206 can be in the range of about 2V and significantly less, such as about 1V, and the voltage 201V used to establish the desired polarization state in material 202F can be Within a range of a few volts, for example about 5V. It will be appreciated that when the "programming" component 200 (i.e., the desired polarization state is established in the ferroelectric material 202F), the polarity of the voltage 201V can be varied depending on the desired polarization state. Thus, the programming of component 200 can be implemented by selecting a sufficiently high voltage 201V of suitable polarity, and then based on a voltage 210V over a conventional supply voltage range and possibly based on a significantly lower voltage 201V compared to the programmed voltage, Regular operation is possible.

In another example embodiment, the gate electrode structure 210 can be configured to implement an additional storage mechanism, that is, in addition to being combined by the ferroelectric material 202F to apply an amplitude sufficient to program the ferroelectric material 202F (ie, to establish a particular pole) In addition to the storage mechanism provided by the configuration of the voltage 201V, as described above. In an exemplary embodiment, the storage mechanism in the context of the gate electrode structure 210 can be implemented based on additional ferroelectric material, that is, the dielectric layer 213 can have a ferroelectric material contained therein, such as based on yttrium oxide. The ferroelectric material is also as described above in the context of Figure 1A. Thus, a dielectric layer 213 comprising the ferroelectric material in conjunction with the control voltage 210V can be applied to correspond to a programming voltage for the dielectric layer 213 comprising the dielectric material to provide an additional storage mechanism. Thus, the ferroelectric material in layer 213 and the ferroelectric material 202F in buried insulating layer 202 can be independently polarized (ie, programmed) to provide a superimposed electric field within the channel region, which can result in correspondingly different Channel conductivity or drive current (e.g., expressed by a corresponding difference in threshold voltage values) provides the possibility to establish more than two different channel states and resulting logic states.

It will be appreciated that a dielectric layer 213 comprising the ferroelectric material can be formed in accordance with well-established process techniques, as described above with reference to transistor element 100 of FIG. 1A.

In further example embodiments, the gate electrode structure can include an additional storage mechanism formed based on a floating gate configuration, wherein at least a portion of the dielectric layer 213 can include a layer or region to capture charge carriers The charge carrier can be injected into or removed from the charge carrier capture region by applying an appropriate programming voltage or erase voltage, as is well known for floating gate type transistors. Therefore, also in this case, in conjunction with the corresponding ability to apply a voltage of 210V of sufficient height, the dielectric layer 213 can represent an additional storage mechanism to provide more than two different transistor states in combination with the ferroelectric material 202F and thereby The logical state.

It should be understood that the floating gate type electrode structure can be formed based on a well-established process scheme, such as providing a suitable dielectric layer stack, such as an oxide-nitride-oxide, etc., wherein one of the layers (usually The intermediate layer) can serve as a charge trapping layer. In other cases, the storage mechanism provided by the dielectric material 213 (including the charge trapping layer) can have a configuration that itself can provide two or more transistor states and resulting logic states, wherein the ferroelectric material 202F is passed. The corresponding polarization state may suitably modify at least some of these states to further increase the number of different transistor states. For example, as described above, the complex fast lightning crystal technique can include a gate electrode structure and a corresponding mode for applying an appropriate gate voltage to establish two-bit information, wherein the pole of the ferroelectric material 202F is appropriately adjusted and thus selected The state can increase the information density.

Figures 3A through 3D schematically show cross-sectional views of a storage element, such as a field effect transistor, that includes two independent storage mechanisms to implement one bit or more of information.

3A is a cross-sectional view showing the display element 300, which may represent a storage transistor having a gate electrode structure 310 and a buried ferroelectric material 302F, and the gate electrode structure 310 and the buried ferroelectric material 302F may sandwich corresponding channel regions. 306, the conduction state or drive current capability of the channel region will be controlled by a corresponding storage mechanism. In an example embodiment, the gate electrode structure 310 can include a storage mechanism 300A that can be based on a ferroelectric material 311F disposed in the gate electrode structure 310. Moreover, the second storage mechanism 300B formed based on the ferroelectric material 302F can be set as an independent mechanism for establishing more than one information bit in the component 300. It will be appreciated that element 300 is shown in a schematic manner, and when referring to a configuration including at least two independent storage mechanisms, may have the configuration as previously described in the context of element 200 of FIG. In the embodiment shown in FIG. 3A, both storage mechanisms may be based on ferroelectric materials, such as ferroelectric material 311F and buried ferroelectric material 302F. In other example embodiments (not shown), the first storage mechanism 300A can be implemented based on charge carrier capture material, as described above with reference to FIG.

Thus, the ferroelectric material 311F can have a suitable configuration to enable the creation of two different (i.e., opposite) polarization states, the direction of which can be substantially perpendicular to the direction of current flow of the channel region 306. This current direction (as described above in the context of Figures 1A and 2) may represent the horizontal direction in Figure 3A. The basic concept of establishing the desired polarization state can be the same as described above with reference to elements 100 and 200. Thus, the storage mechanism 300A can have a first polarization state 313A obtained by properly programming the ferroelectric material 311F as described above, and the storage mechanism 300B can have a first polarization state 302A, which can also be based on the above reference. The scenario described in Figure 2 is established. In the case shown in Figure 3A, the two polarization states 313A, 302A can be directed in the same direction to provide a particular conductive state or current drive capability, as also described above.

Figure 3B illustrates display element 300 in which polarization state 302A of mechanism 300B is retained and polarization state of inversion mechanism 300A is indicated by 313B. Thus, polarization states 313B and 302A can be partially compensated for each other, resulting in a conductive state that is different from the combined polarization in Figure 3A.

3C illustrates display element 300 in which the polarization state of inversion mechanism 300B is indicated by 302B, and thus, the two polarization states have the same direction, thereby increasing the electric field in channel region 306.

Figure 3D shows display element 300 in which polarization state 300B relating to polarization in Figure 3C is retained, and mechanism 300A is programmed to be opposite polarization state 313A as shown in Figures 3B and 3C. In this case, the polarization state thus corresponds to the state shown in FIG. 3A. In this case, the combination of the respective polarizations may also differ in the channel region 306 as compared to the combined polarization effect of the element 300 shown in Figures 3A through 3C.

It will be appreciated that, as described above, in an exemplary embodiment, the respective "efficiency" or "intensity" of the polarization states 313A, 313B on the one hand may be different from 302A, 302B on the other hand, such that in the 3B and 3D diagrams The respective "mixed" states shown can produce different final effects on channel region 306. For example, it can be assumed that, substantially, the polarization states 313A, 313B are less effective in affecting the channel region 306 because the overall area covered by the corresponding ferroelectric material 311F is smaller than the buried ferroelectric material 302F. In other cases, the efficiency or intensity of the respective polarization may be adjusted based on other parameters, such as the effective distance of the respective ferroelectric material to channel region 306, which may be by selecting any interface material (eg, material 202A shown in FIG. 2, A suitable thickness of 202B) and/or by any conventional dielectric material that can be placed in conjunction with the ferroelectric material in the gate electrode structure 310, as also described in the context of FIGS. 1A and 2 .

Thus, multiple mechanisms can be used to adjust the efficiency or strength of the respective ferroelectric material to achieve a sufficient difference between the mixed states shown in Figures 3B and 3D.

Fig. 3E is a view schematically showing a graph of current behavior corresponding to four different states shown in Figs. 3A to 3D. That is, curve AA corresponds to the configuration shown in FIG. 3A, where the two storage mechanisms 300A, 300B have "downward" polarization states 313A, 302A. Thus, for the N-type configuration of component 300, a minimum threshold voltage can be obtained because in this case, the resistance of channel region 306 is the lowest.

Curve BB corresponds to the configuration of element 300 shown in Figure 3C. That is, in this configuration, the two polarization states may correspond to the "upward" direction, and thus, the combined effect on the channel region 306 may result in the highest threshold voltage value, since in this case, that is, for N In a configuration, positive charge carriers may tend to accumulate in channel region 306, resulting in the highest channel resistance.

The curve AB corresponds to the configuration shown in the 3D diagram, wherein it is apparent that the effect of the polarization state 302B can be compensated for by the effect portion of the polarization state 313A. However, due to the different efficiencies or intensities of these polarization states as described above, the shift to the reduced threshold voltage value (i.e., offset to the left hand side in Figure 3E) is offset to the right of the curve BA (and The configuration shown in Figure 3B corresponds to) is less obvious. That is, the polarization state 313B cancels the polarization state 302A. However, due to the different intensities, the resulting threshold voltage value can still be distinguished from the threshold voltage value of curve AB. Therefore, the mixed states represented by the 3B and 3D maps are easily distinguished from each other, and the "pure" states represented by the 3A and 3D graphs can represent the maximum and minimum threshold voltage values that are available.

Thus, by setting the appropriate peripheral components to establish voltages 210V and 201V (see FIG. 2), the memory mechanisms 300A, 300B can be programmed independently of one another to provide different combinations of effective overall polarizations in the channel region 306. After appropriate selection of the individual efficiencies or intensities of the polarization states, the arbitrary mixing states can also be sufficiently different from one another to obtain, for example, four different states of the functional behavior of the component 300, represented by four different threshold voltage values. Thus, when the component 300 is operated based on conventional operating voltages, the corresponding current drive capability is readily identifiable and can be associated with a corresponding logic state. That is, polarization state 313A may be associated with a logic state corresponding to a threshold voltage value represented by curves AA, AB for different polarization states of buried ferroelectric material 302F. Similarly, polarization state 313B of material 311F can be assigned to a respective logic state corresponding to a threshold voltage value represented by curves BA, BB for different polarization states of material 302F.

It should be appreciated that the above considerations apply equally to the P-type configuration of component 300. For example, a P-type ferroelectric crystal can be obtained by any doping used by appropriate inversion, and the corresponding polarization direction can also have an inverse effect on the corresponding threshold voltage as compared with the case shown in FIG. 3E.

Accordingly, the present disclosure provides storage elements, such as storage transistors, wherein at least one storage mechanism can be provided based on buried ferroelectric materials (eg, by incorporating ferroelectric materials into the buried insulating layer of the SOI transistor architecture). In this way, overall design flexibility can be enhanced. Moreover, in an exemplary embodiment, at least one additional storage mechanism may be provided, for example based on a charge trapping layer (as is commonly used in floating gate type storage transistors), while in other example embodiments, Additional ferroelectric materials can be placed in the gate electrode structure to help increase information density while still retaining high compatibility with today's complex high-k metal gate electrode structures used in complex fully depleted SOI transistors. .

The specific embodiments disclosed above are merely exemplary in nature, as the invention may be modified and carried out in a different and equivalent manner. For example, the above process steps can be performed in different steps. Moreover, the invention is not intended to be limited to the details of the architecture or design shown herein, but as described in the following claims. Therefore, it is apparent that modifications and variations can be made to the specific embodiments disclosed above, and all such modifications are within the scope and spirit of the invention. It is to be noted that the use of terms such as "first", "second", "third" or "fourth", used to describe various processes or structures in the specification and the appended claims, is only used. Making a quick reference to such steps/structures does not necessarily mean that such steps/structures are performed/formed in order. Of course, depending on the exact language of the patent application, the order of such processes may or may not be required. Accordingly, the scope of the claimed invention is as described in the following claims.

Claims (20)

A non-volatile storage element comprising: a channel region formed in a semiconductor material; a control electrode structure configured to control current flow through the channel region; a first storage mechanism configured to adjust a threshold of the channel region a value of the voltage; and a second storage mechanism configured to adjust the value of the threshold voltage, the second storage mechanism comprising a ferroelectric material and configured to select the threshold voltage of the channel region in conjunction with the first storage mechanism Two or more different values. The non-volatile storage element of claim 1, wherein the first storage mechanism and the ferroelectric material of the second storage mechanism are disposed to be substantially perpendicular to a direction of current flow relative to the channel region. The channel region is sandwiched. The non-volatile storage element of claim 1, wherein the ferroelectric material of the second storage mechanism is disposed in a buried insulating layer formed in contact with the channel region. The non-volatile storage element of claim 1, wherein the first storage mechanism comprises an additional ferroelectric material. The non-volatile storage element of claim 1, wherein the first storage mechanism comprises a charge trapping layer. The non-volatile storage element of claim 1, wherein the ferroelectric material of the second storage mechanism is formed on the control electrode In the structure. The non-volatile storage element of claim 1, wherein the first storage mechanism has a first efficiency for adjusting the value of the threshold voltage and the second storage mechanism has a threshold voltage for adjusting the threshold voltage The second efficiency of the value, and wherein the first efficiency is different from the second efficiency. The non-volatile storage element of claim 1, wherein the first storage mechanism is implemented in the control electrode structure. The non-volatile storage element of claim 1, further comprising a germanium region and a source region connected to the channel region to form a transistor configuration based on the buried insulating layer. A non-volatile storage transistor component, comprising: a channel region; a gate electrode structure disposed to control current in the channel region; and a buried insulating layer formed under the channel region, the buried insulating layer including Ferroelectric materials to provide a storage mechanism for storing information in a non-volatile manner. The non-volatile storage transistor component of claim 10, wherein the gate electrode structure comprises an additional storage mechanism that provides more than two non-volatile logic states in conjunction with the storage mechanism. The non-volatile storage transistor component of claim 10, wherein the gate electrode structure comprises a ferroelectric material as the additional storage The components of the deposit mechanism. The non-volatile storage transistor component of claim 10, wherein the gate electrode structure comprises at least one of a ferroelectric material and a charge trapping material as a component of the additional storage mechanism. The non-volatile storage transistor component of claim 11, wherein the storage mechanism has a first efficiency to adjust a value of a threshold voltage of the channel region and the additional storage mechanism has a A second efficiency of the value of the threshold voltage, and wherein the first efficiency is different from the second efficiency. The non-volatile storage transistor element of claim 10, further comprising an electrode material formed under the buried insulating layer to apply an electric field in the ferroelectric material. A method of operating a non-volatile storage element, the method comprising: selecting a first polarization state of a ferroelectric material formed adjacent a channel region of a transistor element; selecting a charge trapping material formed adjacent the channel region And a first storage state of at least one of the second ferroelectric materials; assigning a first logic state to the first channel environment induced by the first polarization state and the first storage state; selecting a charge trapping material and a second storage state of the at least one of the ferroelectric materials; assigning a second logic state to the second channel environment induced by the first polarization state and the second storage state; and when bonding the ferroelectric material The second polarization state, to the first And one of the second storage states is assigned at least one additional logic state, the first and second polarization states being reciprocal. The method of claim 16, wherein the first and second storage states respectively correspond to the first and second polarization states of the second ferroelectric material. The method of claim 16, wherein the first and second storage states respectively correspond to first and second charge trapping states of the charge trapping material. The method of claim 16, wherein the first and second channel environments are determined by values of threshold voltages of the channel region. The method of claim 19, wherein the logic state is assigned to at least four different values of the threshold voltage.