TWI661423B - Detecting method for a resistive random access memory cell - Google Patents

Abstract

The invention provides a method for detecting a resistive random access memory cell, which includes: obtaining a resistive random access memory cell and measuring a current of the resistive random access memory cell; when the current value of the memory cell current is greater than a first When the threshold value is set, at least one of a plurality of reset operations and setting operations is performed on the resistive random access memory cell, and it is determined whether the resistance state of the resistive random access memory cell is undergoing the foregoing reset operation and At least one of the setting operations is then switched accordingly. If not, perform a restoration operation on the resistive random access memory cell to restore the resistive random access memory cell; if so, determine that the resistive random access memory cell is in a healthy state.

Description

Detection method of resistance type random access memory cell

The invention relates to a method for detecting a memory, and in particular to a method for detecting a resistive random access memory (RRAM).

RRAM is a non-volatile memory. The RRAM cells therein each include an upper electrode plate, a lower electrode plate, and a resistive switching layer sandwiched between the upper and lower electrode plates. The resistance conversion layer can form a memory cell by applying a suitable voltage on the upper electrode plate, and can form a conductive path of the resistance conversion layer in the resistance conversion layer (commonly referred to as conductive filament (CF)) . Once the conductive wire is formed, it can be reset by applying an appropriate voltage on the upper electrode plate (that is, the conductive wire is disconnected or broken, resulting in a high resistance state on the RRAM cell. state (HRS). After that, the RRAM cell can be set by applying an appropriate voltage on the upper electrode plate (that is, the conductive wire is re-formed, resulting in a low resistance state on the RRAM cell. , LRS)). LRS and HRS can be used to indicate a "0" or "1" digital signal to provide related memory functions.

However, in the prior art, if the resistance state of the memory cell is repeatedly switched between LRS and HRS by repeatedly resetting and setting the memory cell in the RRAM, the resistance state of the memory cell It is very likely that stuck in the LRS. That is, the resistance state of the memory cell will be normally in the LRS, and cannot be normally switched to the HRS in response to a subsequent reset operation.

Therefore, it is an important issue for those skilled in the art to provide a method to find out the memory cells that will be stuck in the LRS, so as to avoid the above situation.

In view of this, an embodiment of the present invention provides a method for detecting an RRAM memory cell, which can find an RRAM memory cell that is about to be stuck in an LRS early, and perform a recovery operation accordingly.

The invention provides a method for detecting an RRAM memory cell, comprising: obtaining a resistive random access memory cell and measuring a current of the resistive random access memory cell; when a current value of the memory cell current is greater than a first At the threshold, at least one of multiple reset operations and a setting operation is performed on the resistive random access memory cell; determining whether a resistance state of the resistive random access memory cell is undergoing the foregoing reset operation And at least one of the setting operations is switched accordingly. If not, perform a restoration operation on the resistive random access memory cell to restore the resistive random access memory cell; if so, determine that the resistive random access memory cell is in a healthy state.

Based on the foregoing, the method for detecting an RRAM memory cell according to the embodiment of the present invention may determine a test operation (for example, several reset operations and / or setting operations) performed on the RRAM memory cell according to the current value of the RRAM memory cell. And observe whether the current value of the RRAM memory cell can change significantly. If not, it means that the RRAM memory cell may soon be stuck in the LRS. Therefore, the recovery operation can be performed accordingly to restore the conductive wires in it, so as to prevent the RRAM memory cell from losing the ability to memorize data due to being stuck in the LRS.

In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.

As shown in Figure 1, if the memory cell current of an RRAM memory cell has undergone multiple cycles (one cycle represents a reset operation and a set operation), it can still be normally operated at a large current (such as 20 μA) and a small current ( For example, if it is switched between 0 μA), it means that the resistance state of the RRAM memory cell can be switched to the corresponding resistance state according to the reset operation and the setting operation. That is, this RRAM memory cell does not get stuck in the LRS (it may be referred to as the RRAM memory cell in a healthy state in this case).

Please refer to FIG. 2, if the memory cell current of an RRAM memory cell can only normally present a large current (for example, higher than 20 μA) after multiple cycles, it cannot be changed to a small current (for example, low by a reset operation) Switching between 10μA) means that the resistance state of the RRAM memory cell can no longer be switched to HRS due to the reset operation. In other words, the RRAM memory cell is stuck in the LRS.

Referring to FIG. 3, it is assumed that the RRAM memory cell 31 is in a healthy state, the RRAM memory cell 32 is about to be stuck in the LRS, and the RRAM memory cell 33 is already stuck in the LRS.

As shown in FIG. 3, in the RRAM memory cell 31, the structure of the conductive wire 31a is relatively compact and the gap between the conductive wire 31a and the upper electrode plate is large, so that the resistance state of the RRAM memory cell 31 can present HRS. In addition, after the RRAM memory cell 31 undergoes a setting operation, the conductive wire 31a should be changed to a state connected to the upper electrode plate accordingly, so that the RRAM memory cell 31 is normally switched to an LRS.

However, in the RRAM memory cell 32, although the conductive wire 32a is not connected to the upper electrode plate, the RRAM memory cell 32 still displays HRS, but because the structure of the conductive wire 32a is relatively loose and the gap with the upper electrode plate is small, Therefore, it may be stuck in the LRS after going through several subsequent cycles.

In the RRAM memory cell 33, the conductive wire 33a is normally connected to the upper electrode plate, and may not be changed to, for example, the state of the conductive wire 31a or 32a in response to a reset operation. In other words, the resistance state of the RRAM memory cell 33 cannot be switched to HRS in response to the reset operation, and is continuously stuck in the LRS. What's more, after the RRAM memory cell 33 undergoes a reset operation, the current of the memory cell 33 may not increase and decrease, thereby causing a problem of complementary switching (CS). In this case, the RRAM memory cell 33 will lose the ability to memorize data because it cannot switch between HRS and LRS, and it will be treated as an invalid bit.

In view of this, an embodiment of the present invention proposes a method for detecting RRAM, which can find an RRAM memory cell that is about to be stuck in LRS early and perform a recovery operation accordingly to avoid the RRAM memory cell being stuck in LRS. The ability to lose data is detailed below.

In an embodiment, the method shown in FIG. 4A can be performed every time before performing a setting operation and / or a reset operation on an RRAM memory cell, so as to determine whether the RRAM memory cell can normally switch the resistance state. But it is not limited to this.

As shown in FIG. 4A, in step S410, the RRAM memory cell can be obtained and the memory cell current of the RRAM memory cell can be measured. In step S420, when the current value of the memory cell current (referred to as I) is greater than the first threshold value (Hereinafter referred to as T1), at least one of multiple reset operations and setting operations is performed on the RRAM memory cell; in step S430, it can be determined whether the resistance state of the RRAM memory cell is undergoing the foregoing reset operation and setting At least one of the operations is then switched accordingly. If not, the RRAM memory cell may be restored in step S440 to restore the RRAM memory cell, otherwise it may be determined in step S450 that the RRAM memory cell is in a healthy state.

In an embodiment, the first threshold value (T1) is, for example, a reference current value that can be used to determine whether the RRAM memory cell is in the HRS. It can be set by the designer based on experience and process capability. The smaller the value, the better. Specifically, when the current value (I) of the memory cell current is less than the first threshold value (T1), it means that the RRAM memory cell is definitely in the HRS, that is, the possibility that the RRAM memory cell will soon be stuck in the LRS is not high.

However, in step S420, when the current value (I) of the memory cell current is determined to be greater than T1, it means that the RRAM memory cell is more likely to get stuck in the LRS in the future. Therefore, test operations such as subsequent reset operations and / or setting operations can be performed on this RRAM memory cell, and whether the resistance state of the RRAM memory cell can be switched accordingly. If the resistance state of the RRAM memory cell can be switched between HRS and LRS, it means that the RRAM memory cell line is in a healthy state. On the other hand, if the resistance state of the RRAM memory cell cannot be switched obviously during the above-mentioned test operation, the conductive wire representing the RRAM memory cell may have shown the state of the conductive wire 32a of FIG. 3 and will soon be stuck in the LRS. In this case, the embodiment of the present invention may perform a recovery operation on the RRAM memory cell to restore the conductive wire in the RRAM memory cell.

Referring to FIG. 4B, in this embodiment, the restoration operation may include a specific reset operation, a molding operation, and another reset operation in this order. When the RRAM memory cell 40 is determined to be stuck in the LRS, a specific reset operation may be performed on the RRAM memory cell 40. Different from the general reset operation, the specific reset operation in this embodiment uses a higher gate voltage (for example, higher than 5V) and a higher source line voltage (for example, higher than 5V). And a longer pulse wave width (for example, longer than 5 μs) is applied to the lower electrode plate of the RRAM memory cell 40, thereby generating a stronger electric field between the upper electrode plate and the lower electrode plate. In this case, a large amount of electrons (in e ^- Represents a) oxygen ions will be accelerated down the back electrode plate and the RRAM memory cell to fill the oxygen vacancies in the conductive wire 40 of 40a (shown as circles) in Electrical neutrality is formed, so that only a part of the oxygen vacancies closer to the lower electrode plate remain in the conductive wire 40a. After that, the RRAM memory cell 40 may be subjected to a molding operation again, so as to form a conductive wire 40b with a better appearance on the RRAM memory cell 40. Then, another reset operation can be performed on the RRAM memory cell 40 (which can be performed based on a general reset voltage) to change the conductive wire 40b to the state of the conductive wire 40c shown (which is similar to that in FIG. 3). The conductive wire 31a). In this way, the RRAM memory cell 40 can be healthy in the HRS and can be used again to provide a memory function.

In other words, after the RRAM memory cell 40 undergoes the above-mentioned restoration operation, the host to which it belongs can perform the actual setting operation or the actual reset operation on the RRAM memory cell 40 to change the resistance state of the RRAM memory cell 40 according to the related data write request. To achieve the function of memorizing digital signals such as "0" or "1".

In different embodiments, the embodiments of the present invention may be based on an increasing first threshold value (T1), a second threshold value (hereinafter referred to as T2), a third threshold value (hereinafter referred to as T3), and a fourth threshold value. (Hereinafter referred to as T4) (ie, T4> T3> T2> T1) defines several intervals, and then depending on which interval the current value (I) of the memory cell current is located to determine the test operation that should be performed on the RRAM memory cell Content.

Please refer to FIG. 5. In this embodiment, steps S420 and S430 in FIG. 4A can be refined into steps S51a, S51b, S52, S53a, S53b, S54, and S55 in FIG. 5. The details are as follows.

First, when the current value (I) of the memory cell current is between the first threshold value (T1) and the second threshold value (T2), it means that the resistance of the RRAM memory cell may be high, so it can be In step S51a, the RRAM memory cell is set to try to reduce the resistance of the RRAM memory cell. After that, it can be determined in step S51b whether the current value (I) of the memory cell current is correspondingly changed to be higher than the third threshold value (T3). If not (that is, I <T3), it means that the resistance state of the RRAM memory cell has not been switched to a sufficiently low state in response to the setting operation, so the resistance state of the RRAM memory cell can be determined in step S54. The switching is not performed accordingly, and step S440 is performed to perform a recovery operation on the RRAM memory cell.

On the other hand, if I> T3, it means that the resistance state of the RRAM memory cell may have been switched to a sufficiently low state due to the setting operation, so step S52 may be continued to further test the RRAM memory cell.

In step S52, a plurality of reset operations may be performed on the RRAM memory cell, and it is determined whether the current value (I) is switched to be lower than the first threshold value (T1) accordingly after undergoing one of the foregoing reset operations. In an embodiment, the RRAM memory cell can be reset n times (n is a positive integer not greater than 8), and it is determined whether the current value (I) is lower than the first value after each reset operation. A threshold value (T1), that is, determining whether the RRAM memory cell has been switched to HRS due to the reset operation.

If after the kth reset operation (k is a positive integer not greater than n), the current value (I) is measured below the first threshold value (T1), it means that the RRAM memory cell has been switched to HRS, Therefore, it can be determined in step S55 that the resistance state of the RRAM memory cell has been switched accordingly, and step S450 is performed to determine that the RRAM memory cell is in a healthy state. In this case, the RRAM memory cell can be used normally to memorize digital signals such as "0" or "1", thereby providing a memory function.

In addition, the current value (I) measured after the n-th reset operation is not lower than the first threshold value (T1), which means that the RRAM memory cell cannot be switched to HRS, so it can be continued in step S54. It is determined that the resistance state of the RRAM memory cell is not switched accordingly, and step S440 is performed to perform a recovery operation on the RRAM memory cell.

In addition, as shown in FIG. 5, when the current value (I) of the memory cell current is between the second threshold value (T2) and the third threshold value (T3), it means that the resistance state of the RRAM memory cell is not High and not low, so the RRAM memory cell can be further tested by executing step S52.

In addition, when the current value (I) of the memory cell current is greater than the fourth threshold value (T4), it means that the resistance state of the RRAM memory cell may be in the LRS. At this time, the RRAM memory cell can be further tested by executing step S52. For details of step S52, reference may be made to the teaching of the foregoing embodiment, and details are not described herein again.

As taught in the previous embodiment, if the determination result of step S52 is YES, then it can be determined in step S55 that the resistance state of the RRAM memory cell has been switched accordingly, and step S450 is performed to determine that the RRAM memory cell is in a healthy state. . Conversely, if the determination result of step S52 is NO, then it can be determined in step S54 that the resistance state of the RRAM memory cell has not been switched accordingly, and step S440 is performed to perform a recovery operation on the RRAM memory cell.

In Figure 5, when the current value (I) of the memory cell current is between the third threshold value (T3) and the fourth threshold value (T4), it means that the resistance state of the RRAM memory cell may be quite close to the LRS. Therefore, step S53a can be executed accordingly to perform a first type of reset operation on the RRAM memory cell, so as to check whether the RRAM memory cell is in an under reset state. In this embodiment, the aforementioned first type of reset operation may be referred to as a gentle reset operation, which may be slightly lower than a general reset operation (or may be referred to as a second type of reset operation to distinguish (The first type of reset operation) resets the RRAM memory cell.

Next, in step S53b, it can be determined whether the current value (I) of the memory cell current is higher than the second threshold value (T2). If so, the current value (I) representing the memory cell current does not decrease significantly, that is, the resistance value of the RRAM memory cell does not increase significantly. Therefore, it can be determined in step S54 that the resistance state of the RRAM memory cell is not switched accordingly, and step S440 is performed to perform a recovery operation on the RRAM memory cell.

In addition, if it is determined in step S53b that the current value (I) of the memory cell current is less than the second threshold value (T2), the current value (I) representing the memory cell current is significantly reduced. In other words, the resistance value of the RRAM memory cell has been significantly increased in response to the above-mentioned gentle reset operation, so step S52 can be continued to further test the RRAM memory cell. For details of step S52, reference may be made to the teaching of the foregoing embodiment, and details are not described herein again.

As taught in the previous embodiment, if the determination result of step S52 is YES, then it can be determined in step S55 that the resistance state of the RRAM memory cell has been switched accordingly, and step S450 is performed to determine that the RRAM memory cell is in a healthy state. . Conversely, if the determination result of step S52 is NO, then it can be determined in step S54 that the resistance state of the RRAM memory cell has not been switched accordingly, and step S440 is performed to perform a recovery operation on the RRAM memory cell.

It can be known from the above that the method proposed in the embodiment of the present invention can perform corresponding test operations on the RRAM memory cell according to the current value (I) of the memory cell current, so as to confirm whether the resistance state of the RRAM memory cell can normally respond. It is surely switched during the reset operation and / or the setting operation. If not, the RRAM memory cell can be restored to restore the conductive wire therein. In this way, the RRAM memory cell that is about to be stuck in the LRS can be found early, so that the RRAM memory cell can't lose the ability to memorize data due to being stuck in the LRS.

In other embodiments, those with ordinary knowledge in the art may also use more or less thresholds to define more or fewer intervals based on the above teachings, and may also depend on the interval where the current value (I) is located. To perform steps S51a, S52 or S53a on the RRAM memory cell and the subsequent steps.

Please refer to FIG. 6, which is a flowchart of another RRAM detection method according to FIG. 5. In this embodiment, the incremented first threshold value (T1), second threshold value (T2), third threshold value (T3), and fourth threshold value (T4) are respectively substituted into specific values ( For example, 3 μA, 10 μA, 13 μA, and 17 μA) are used for more specific descriptions, but they are not intended to limit possible implementations of the present invention.

In summary, the method shown in FIG. 6 can determine which zone the current value (I) is in by steps S61b, S61c, S61d, and S61e, and decide which test operation should be performed on the RRAM memory cell accordingly.

As shown in FIG. 6, after performing step S410 to obtain the memory cell current of the RRAM memory cell, step S61a may be continued to set the number of reset operations (ie, the value of n taught in the foregoing embodiment). In different embodiments, the designer can determine the value of n (for example, 8) according to requirements. It should be noted that the value of n cannot be too large, otherwise the RRAM memory cell may be permanently damaged after repeated test reset operations on the RRAM memory cell.

After determining the value of n, it can be determined in step S61b whether the current value (I) of the memory cell current is less than T1 (ie, 3 μA). If so, it means that the RRAM memory cell is already in HRS, so steps S55 and S450 can be continued. For details, please refer to the teachings of the foregoing embodiments, and details are not described herein again.

If the current value (I) is not less than T1, step S61c may be continued to determine whether the current value (I) is greater than T4 (ie, 17 μA). If it is, it means that the resistance state of the RRAM memory cell may be in the LRS. At this time, the RRAM memory cell can be further tested by performing steps S63a, S63b, S63c, S63d, and S63e.

In step S63a, the RRAM memory cell can be reset once, and the value of n is decremented in step S63b. In step S63c, if the value of n has been decremented to 0 (that is, the RRAM memory cell has been continuously reset n times), then steps S55 and S450 can be continued. Conversely, if the value of n has not been decremented to 0, it can be judged in step S63d whether the current value (I) is less than T1 (that is, 3 μA). If it is, it means that the RRAM memory cell is already in HRS. S450.

Conversely, if it is determined in step S63d that the current value (I) is not less than T1 (ie, 3 μA), then it can be determined in step S63e whether the current value (I) is greater than T3 (ie, 13 μA). If it is, it means that the resistance of the RRAM memory cell has hardly increased due to the reset operation in step S63a (that is, it may be stuck in the LRS), so steps S54 and S440 can be continued for the recovery operation. For details, please refer to the foregoing. Examples of teaching.

On the other hand, if it is determined in step S63e that the current value (I) is not greater than T3 (ie, 13 μA), the resistance value of the RRAM memory cell may have been slightly increased, so it may return to step S63a to perform the RRAM memory cell again. One reset operation, and it can be judged again through steps S63b to S63e whether the resistance value of the RRAM memory cell has been significantly increased in response to the reset operation in step S63a.

In step S61c, if it is determined that the current value (I) is not greater than T4 (ie, 17 μA), step S61d may be continued to determine whether the current value (I) is greater than T2 (ie, 10 μA). If not, it means that the resistance of the RRAM memory cell may be too high. Therefore, in step S51a, a setting operation may be performed on the RRAM memory cell to try to reduce the resistance of the RRAM memory cell. After that, it can be judged in step S62 whether the current value (I) is correspondingly changed to be higher than T3 (ie, 13 μA). If not (that is, I <T3), it means that the resistance state of the RRAM memory cell has not been switched to a sufficiently low state in response to the setting operation, and therefore steps S54 and S440 can be performed to perform the restoration operation.

On the other hand, if it is determined in step S62 that the current value (I) is higher than T3 (ie, 13 μA), steps S63a to S63e can be continued to further test the RRAM memory cell, and details thereof will not be repeated here.

In step S61d, if it is determined that the current value (I) is higher than T2 (that is, 10 μA), step S61e may be continued to determine whether the current value (I) is higher than T3 (that is, 13 μA). If not, the resistance state of the RRAM memory cell is not high or low, so steps S63a to S63e can be continued to further test the RRAM memory cell, and details thereof will not be repeated here. If so, it means that the resistance state of the RRAM memory cell may be quite close to the LRS, so step S53a may be performed accordingly to perform the first type of reset operation (ie, a mild reset operation) on the RRAM memory cell. After that, it can be determined whether the current value (I) is higher than T2 (ie, 10 μA) in step S61f. If so, the current value (I) representing the memory cell current does not decrease significantly, that is, the resistance value of the RRAM memory cell does not increase significantly. Therefore, steps S54 and S440 can be performed successively to perform a recovery operation on the RRAM memory cell.

On the other hand, if it is determined in step S61f that the current value (I) is lower than T2 (that is, 10 μA), the current value (I) representing the memory cell current is significantly reduced. In other words, the resistance value of the RRAM memory cell has increased significantly in response to the above-mentioned gentle reset operation. Therefore, steps S63a to S63e can be performed to further test the RRAM memory cell, and details thereof will not be repeated here.

Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

31, 32, 33, 40‧‧‧RRAM memory cells

31a, 32a, 33a, 40a, 40b, 40c‧‧‧ conductive wire

S410 ~ S450, S51a, S51b, S52, S53a, S53b, S54, S55, S61a, S61b, S61c, S61d, S61e, S61f, S62, S63a, S63b, S63c, S63d, S63e ...

T1‧‧‧first threshold

T2‧‧‧Second threshold

T3‧‧‧three threshold

T4‧‧‧ Fourth threshold

FIG. 1 is a schematic diagram of an RRAM memory cell current that is not stuck in an LRS according to an embodiment of the present invention. FIG. 2 is a schematic diagram of an RRAM memory cell current stuck in an LRS according to an embodiment of the present invention. FIG. 3 is a schematic diagram of three RRAM memory cells after undergoing a reset operation. FIG. 4A is a flowchart of an RRAM detection method according to an embodiment of the present invention. FIG. 4B is a schematic diagram of a restoration operation according to an embodiment of the present invention. FIG. 5 is a flowchart of an RRAM detection method according to FIG. 4A. FIG. 6 is a flowchart of another RRAM detection method according to FIG. 5.

Claims (10)

A method for detecting a resistive random access memory cell includes: obtaining a resistive random access memory cell and measuring a current of the resistive random access memory cell; when a current value of the memory cell current is greater than At a first threshold value, performing at least one of multiple reset operations and a setting operation on the resistive random access memory cell; judging whether a resistance value state of the resistive random access memory cell is within After the reset operation and at least one of the setting operations are switched accordingly, if not, a reset operation is performed on the resistive random access memory cell to restore the resistive random access memory cell; and if it is , Determine that the resistive random access memory cell is in a healthy state. The method for detecting a resistive random access memory cell according to item 1 of the scope of patent application, wherein after determining that the resistive random access memory cell is in the healthy state, the method further includes: The resistive random access memory cell performs an actual setting operation or an actual reset operation. The method for detecting a resistive random access memory cell according to item 1 of the scope of the patent application, wherein at least one of the reset operation and the setting operation is performed on the resistive random access memory cell, and the judgment is performed. The step of whether the resistance state of the resistive random access memory cell switches accordingly after undergoing at least one of the reset operation and the setting operation includes: when the current value of the memory cell current is between When the first threshold value is between a second threshold value, perform the setting operation on the resistance random access memory cell, and determine whether the current value of the current of the memory cell is correspondingly changed to be higher than a first Three thresholds, where the third threshold is greater than the second threshold and the second threshold is greater than the first threshold; if not, determine the resistance of the resistive random access memory cell The value status is not switched accordingly. The method for detecting a resistive random access memory cell according to item 3 of the scope of patent application, wherein if the current value of the memory cell current has been changed to be higher than the third threshold value after the setting operation is performed, , Performing the reset operations on the resistive random access memory cell, and determining whether the current value of the current of the memory cell is switched to be lower than the first threshold correspondingly after undergoing one of the reset operations If yes, determine that the resistance state of the resistance random access memory cell has been switched accordingly; and if not, determine that the resistance state of the resistance random access memory cell has not been switched accordingly. The method for detecting a resistive random access memory cell according to item 1 of the scope of the patent application, wherein at least one of the reset operation and the setting operation is performed on the resistive random access memory cell, and the judgment is performed. The step of whether the resistance state of the resistive random access memory cell switches accordingly after undergoing at least one of the reset operation and the setting operation includes: when the current value of the memory cell current is between Between a second threshold value and a third threshold value, or greater than a fourth threshold value, performing the reset operations on the resistive random access memory cell, and determining the current of the memory cell Whether the current value is switched to be lower than the first threshold value correspondingly after undergoing one of the reset operations, wherein the fourth threshold value is greater than the third threshold value, and the third threshold value is greater than the second threshold value A threshold value, and the second threshold value is greater than the first threshold value; if it is, it is determined that the resistance state of the resistance random access memory cell has been switched accordingly; and if not, it is determined that the resistance random storage Take this resistance state of the memory cell Not switched accordingly. The method for detecting a resistive random access memory cell according to item 1 of the scope of patent application, wherein the reset operations include a first type reset operation and a plurality of second type reset operations, and the resistance type The random access memory cell performs at least one of the reset operation and the setting operation, and determines whether the resistance state of the resistive random access memory cell is undergoing the reset operation and the setting operation. A step of correspondingly switching at least one of the following includes: when the current value of the memory cell current is between a third threshold value and a fourth threshold value, performing the resistance random access memory cell The first type of reset operation, wherein the reset voltage of the first type of reset operation is lower than the reset voltages of the second type of reset operation; determining whether the current value of the memory cell current is undergoing the first type After a similar reset operation, it is higher than a second threshold, where the fourth threshold is greater than the third threshold, the third threshold is greater than the second threshold, and the second threshold is greater than The first threshold value; if yes, determine the resistance The resistance state of the random access memory cell is not switched accordingly. The method for detecting a resistive random access memory cell according to item 6 of the scope of patent application, wherein if the current value of the memory cell current does not exceed the second threshold value after undergoing the first type of reset operation , Performing the second type of reset operations on the resistive random access memory cell, and determining whether the current value of the current of the memory cell is switched to lower than correspondingly after undergoing one of the second type of reset operations. The first threshold value; if it is, it is determined that the resistance state of the resistance random access memory cell has been switched accordingly; and if not, it is determined that the resistance state of the resistance random access memory cell has not been switched accordingly. . The method for detecting a resistive random access memory cell according to item 1 of the scope of patent application, wherein the step of performing the restoration operation on the resistive random access memory cell to restore the resistive random access memory cell includes: Performing a specific reset operation on the resistive random access memory cell, wherein a reset voltage of the first specific reset operation is higher than a reset voltage of the reset operations; A forming operation; and performing another reset operation on the resistive random access memory cell, wherein a reset voltage of the other reset operation is lower than a reset voltage of the specific reset operation. The method for detecting a resistive random access memory cell according to item 1 of the scope of patent application, wherein a number of the reset operations is less than 8 times. The method for detecting a resistive random access memory cell according to item 1 of the scope of patent application, wherein when the current value of the memory cell current is greater than the first threshold value, it is determined that the resistive random access memory cell is in the health status.