TWI659511B - Substrate for package, method of manufacturing the same, and package - Google Patents

Abstract

A substrate for a package includes a carrier board, a first patterned conductor layer, a second patterned conductor layer, and a three-dimensional printed wire. The carrier board has a first surface, a second surface, and a third surface. The first surface is opposite to the second surface, and the third surface is connected between the first surface and the second surface. The first patterned conductor layer is disposed on the first surface. The second patterned conductor layer is disposed on the second surface. The three-dimensional printing wire is disposed on the third surface and is connected between the first patterned conductor layer and the second patterned conductor layer.

Description

Package substrate, manufacturing method thereof, and package

The present invention relates to a substrate for a package, a method for manufacturing the same, and a package, and more particularly, to a substrate for a package manufactured by using a three-dimensional printing technology, a method for manufacturing the same, and a package.

In the packaging process of semiconductor components, the leadframe package of the conventional technology is often limited by the single-layer structure and manufacturing requirements of the leadframe, and the circuit design of the leadframe cannot be freely performed.

In addition, for semiconductor packaging using a wire-wound design substrate, a via must be designed on the substrate to connect the lines between different layers. Vias are generally processed on the substrate using CNC machinery or lasers, which require multiple processes such as thinning, drilling, brushing, deposition, plating, and plugging to achieve wire interconnection. In addition to the manufacturing method being too complicated, the above-mentioned manufacturing method also causes disadvantages such as the consumption of materials and the impact on the environment.

The invention provides a substrate for a package, comprising a carrier board, a first patterned conductor layer, a second patterned conductor layer, and a three-dimensional printed wire. The carrier board has a first surface, a second surface, and a third surface. The first surface is opposite to the second surface, and the third surface is connected between the first surface and the second surface. The first patterned conductor layer is disposed on the first surface. The second patterned conductor layer is disposed on the second surface. The three-dimensional printing wire is disposed on the third surface and is connected between the first patterned conductor layer and the second patterned conductor layer.

The invention provides a method for manufacturing a substrate for a package, which includes the following steps. Carrier board provided. The carrier board has a first surface, a second surface, and a third surface. The first surface is opposite to the second surface, and the third surface is connected between the first surface and the second surface. A first patterned conductor layer is formed on the first surface. A second patterned conductor layer is formed on the second surface. A three-dimensional printing method is used to form a three-dimensional printing wire on the third surface. The three-dimensional printing wire is connected between the first patterned conductor layer and the second patterned conductor layer.

The present invention provides a package including a substrate for the package and a first electronic component. The substrate for a package includes a carrier board, a first patterned conductor layer, a second patterned conductor layer, and a three-dimensional printed wire. The carrier board has a first surface, a second surface, and a third surface. The first surface is opposite to the second surface, and the third surface is connected between the first surface and the second surface. The first patterned conductor layer is disposed on the first surface. The second patterned conductor layer is disposed on the second surface. The three-dimensional printing wire is disposed on the third surface and is connected between the first patterned conductor layer and the second patterned conductor layer. The first electronic component is disposed on the first surface and is electrically connected to the first patterned conductor layer.

Based on the above, in the package substrate and the manufacturing method thereof proposed by the present invention, the three-dimensional printing technology can print on a three-dimensional surface, so the three-dimensional printing method can be used to arrange the third surface of the carrier board. Print out three-dimensional printed wires, so there is no need to use the via process, you can complete the interconnection between the first patterned conductor layer and the second patterned conductor layer circuit in a simple way, and according to the characteristics of the packaged product Requirements, design the substrate shape for packaging. In addition, the method for manufacturing a substrate for a package can effectively reduce production complexity and required consumables, and therefore can effectively reduce the manufacturing time and cost of the substrate for a package. In addition, in the package proposed by the present invention, since the above-mentioned substrate for a package is used, it can have better design flexibility.

In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.

1A, 2A and 3A are top views of a manufacturing process of a package substrate according to an embodiment of the present invention. 1B, 2B, and 3B are right side views of FIGS. 1A, 2A, and 3A, respectively. 1C, 2C, and 3C are bottom views of FIGS. 1A, 2B, and 3A, respectively. Fig. 2D is a cross-sectional view of the interface between the three-dimensional printed wire and the carrier board along the I-I 'section line in Fig. 2A. FIG. 3D is a cross-sectional view of the interface between the three-dimensional printed wire and the carrier board along the II-II 'section line in FIG. 3A. For clear description, the components on the first surface and the second surface of the carrier board are omitted in FIGS. 1B, 2B, and 3B, and only the three-dimensional printed wire and the conductors are shown in FIGS. 2D and 3D. Carrier board.

Referring to FIGS. 1A to 1C, a carrier board 100 is provided. The material of the carrier board 100 may depend on the packaging requirements of the package. For example, the material of the carrier board 100 can be plastic, ceramic, or glass to provide a variety of package shapes and can be used for various semiconductor device packages. The carrier board 100 has a first surface 102a, a second surface 102b, and a third surface 102c. The first surface 102a is opposite to the second surface 102b, and the third surface 102c is connected between the first surface 102a and the second surface 102b.

In addition, the carrier board 100 may optionally have an opening 104 located in the carrier board 100 or at least one notch 106 located at an edge of the carrier board 100. The method for forming the opening 104 and the notch 106 is, for example, mechanical drilling, laser drilling, or direct formation by injection molding. The number of the gaps 106 in FIG. 1A and FIG. 1C is merely an example, and the present invention is not limited thereto.

The third surface 102c may be the surface of the opening 104 in the carrier board 100, the side surface of the edge of the carrier board 100, or the surface of the notch 106 on the edge of the carrier board 100, but the invention is not limited thereto. As long as the third surface 102c is a surface connected between the first surface 102a and the second surface 102b, it belongs to the scope of the present invention. In this embodiment, the third surface 102c is described by taking the surface of the opening 104 in the carrier board 100 and the surface of the notch 106 on the edge of the carrier board 100 as an example.

Referring to FIGS. 2A to 2D, a patterned conductive layer 108 is formed on the first surface 102 a. The patterned conductor layer 108 may include a contact 108 a and a wire 108 b, wherein the contact 108 a is connected to the wire 108 b. The material of the patterned conductor layer 108 may be a conductive material such as copper, silver, gold, or a conductive polymer, and the formation method thereof is, for example, a three-dimensional printing method, a screen printing method, an inkjet printing method, a gravure printing method, or elasticity. The printing method or the lithographic printing method prints conductive materials such as copper paste, silver paste, gold paste, or conductive polymer on the first surface 102a. The method for forming the patterned conductor layer 108 further includes performing a baking process on the conductive material printed on the first surface 102a, wherein the temperature of the baking process is, for example, 80 ° C to 260 ° C.

A patterned conductor layer 110 is formed on the second surface 102b. The patterned conductor layer 110 may include a contact point 110a and a conductive line 110b, wherein the contact point 110a is connected to the conductive line 110b. The material of the patterned conductor layer 110 may be a conductive material such as copper, silver, gold, or a conductive polymer, and the formation method thereof is, for example, a three-dimensional printing method, a screen printing method, an inkjet printing method, a gravure printing method, or elasticity. The printing method or the lithographic printing method prints a conductive material such as copper paste, silver paste, gold paste, or conductive polymer on the second surface 102b. The method for forming the patterned conductor layer 110 further includes performing a baking process on the conductive material printed on the second surface 102 b, wherein the temperature of the baking process is, for example, 80 ° C. to 260 ° C.

A three-dimensional printing wire 112 is formed on the third surface 102c using a three-dimensional printing method. In this embodiment, the three-dimensional printing wire 112 may be formed on the surface of the opening 104 and the surface of the notch 106. Three-dimensional printing wire The three-dimensional printing wire 112 is connected between the patterned conductor layer 108 and the patterned conductor layer 110. Specifically, the patterned conductive layer 108 may be electrically connected to the patterned conductive layer 110 through the conductive line 108b, the three-dimensional printing conductive line 112, and the conductive line 110b. The material of the three-dimensional printing wire 112 may be a conductive material such as copper, silver, gold, or a conductive polymer, and the formation method thereof is, for example, a conductive material such as copper paste, silver paste, gold paste, or conductive polymer by a three-dimensional printing method. Printed on the third surface 102c. The method for forming the three-dimensional printing wire 112 further includes performing a baking process on the conductive material printed on the third surface 102c. The temperature of the baking process is, for example, 80 ° C to 260 ° C.

In this embodiment, the three-dimensional printing wire 112 protrudes from the first surface 102a and the second surface 102b, so that the three-dimensional printing wire 112 is connected between the patterned conductor layer 108 and the patterned conductor layer 110. The invention is not limited to this. In another embodiment, the conductive wire 108b of the patterned conductive layer 108 protrudes from the first surface 102a and the conductive wire 110b of the patterned conductive layer 110 protrudes from the second surface 102b, so that the three-dimensional printed conductive wire 112 is connected to Between the patterned conductor layer 108 and the patterned conductor layer 110. Those skilled in the art can adjust the manner in which the three-dimensional printing wire 112 is connected between the patterned conductive layer 108 and the patterned conductive layer 110 according to the process requirements.

In addition, the patterned conductor layer 108, the patterned conductor layer 110, and the three-dimensional printing wire 112 may be formed separately or simultaneously. That is, the formation order of the patterned conductive layer 108, the patterned conductive layer 110, and the three-dimensional printed conductive line 112 may be determined according to process requirements.

Referring to FIGS. 3A to 3D, a solder resist layer 114 may be selectively formed on the first surface 102 a to protect the patterned conductor layer 108 on the first surface 102 a. The solder mask layer 114 covers the patterned conductor layer 108 and exposes a portion of the patterned conductor layer 108. For example, the solder mask 114 may expose the contacts 108 a of the patterned conductor layer 108. In addition, the solder resist layer 114 can further cover the upper surface of the three-dimensional printing wire 112. The material of the solder resist layer 114 is, for example, an insulating material, and the formation method thereof is, for example, a three-dimensional printing method, a screen printing method, an inkjet printing method, a gravure printing method, an elastic printing method, a lithographic printing method, or irradiation with a photosensitive insulating material. UV light is used for patterning.

In addition, a solder resist layer 116 may be selectively formed on the second surface 102b to protect the patterned conductor layer 110 on the second surface 102b. The solder mask layer 116 covers the patterned conductor layer 110 and exposes a portion of the patterned conductor layer 110. For example, the solder mask layer 116 may expose the contacts 110 a of the patterned conductor layer 110. In addition, the solder mask layer 116 can further cover the lower surface of the three-dimensional printing wire 112. The material of the solder resist layer 116 is, for example, an insulating material, and a formation method thereof is, for example, a three-dimensional printing method, a screen printing method, an inkjet printing method, a gravure printing method, an elastic printing method, a lithographic printing method, or irradiation with a photosensitive insulating material. UV light is used for patterning. In addition, the solder resist layer 114 and the solder resist layer 116 may be formed separately or simultaneously. That is, the formation order of the solder resist layer 114 and the solder resist layer 116 can be determined according to the process requirements.

In this embodiment, since the three-dimensional printing wire 112 is formed in the opening 104 and the notch 106, the three-dimensional printing wire 112 is not easy even if a solder resist layer covering the three-dimensional printing wire 112 is not formed on the third surface 102c. Damage due to external force. In addition, not forming a solder resist layer on the surface of the notch 106 to cover the three-dimensional printing wire 112 may be beneficial for performing electrical tests in subsequent processes. In another embodiment, a solder resist layer covering the three-dimensional printing wire 112 may be formed on the third surface 102c.

Hereinafter, the package substrate according to this embodiment will be described with reference to FIGS. 3A to 3D. In addition, although the manufacturing method of the package substrate according to this embodiment is described by taking the above-mentioned manufacturing method as an example, the manufacturing method of the package substrate of the present invention is not limited thereto. Referring to FIGS. 3A to 3D, the package substrate 10 includes a carrier board 100, a patterned conductor layer 108, a patterned conductor layer 110, and a three-dimensional printed wire 112. The carrier board 100 has a first surface 102a, a second surface 102b, and a third surface 102c. The first surface 102a is opposite to the second surface 102b, and the third surface 102c is connected between the first surface 102a and the second surface 102b. The patterned conductor layer 108 is disposed on the first surface 102a. The patterned conductor layer 110 is disposed on the second surface 102b. The three-dimensional printing wire 112 is disposed on the third surface 102 c and is connected between the patterned conductor layer 108 and the patterned conductor layer 110. In addition, the package substrate 10 may further include a solder resist layer 114 and a solder resist layer 116. The solder mask layer 114 covers the patterned conductor layer 108 and exposes a portion of the patterned conductor layer 108. The solder mask layer 116 covers the patterned conductor layer 110 and exposes a portion of the patterned conductor layer 110. In addition, the materials, installation methods, formation methods, and functions of the components of the substrate 10 for a package have been described in detail in the manufacturing method of FIGS. 1A to 3D described above, and will not be repeated here.

Based on the above-mentioned embodiments, it can be known that, in the substrate 10 for a package and the method for manufacturing the same, since the 3D printing technology can print on a three-dimensional surface, the three-dimensional printing method can be used on the third surface of the carrier board 100. 102c prints the three-dimensional printing wire 112, so the interconnection between the patterned conductor layer 108 and the patterned conductor layer 110 circuit can be completed in a simple manner without using a via process, and can also be based on packaged products Characteristic requirements, design the substrate shape for packaging. In addition, the method for manufacturing the substrate 10 for a package can effectively reduce production complexity and consumables, and therefore can effectively reduce the manufacturing time and cost of the substrate 10 for a package.

4A is a top view of a package substrate according to another embodiment of the present invention. Fig. 4B is a right side view of Fig. 4A. For clear description, the components on the first surface and the second surface of the carrier board are not shown in FIG. 4B. FIG. 4C is a bottom view of FIG. 4A. Please refer to FIGS. 3A to 3D and FIGS. 4A to 4C together. The differences between the package substrate 20 and the package substrate 10 are as follows. The package substrate 20 has only the surface of the cutout 106 as the third surface 102c. That is, since the carrier board 100 of the package substrate 20 does not have the opening 104, it does not have the three-dimensional printed wiring 112 on the surface of the opening 104. In the package substrate 20, the patterned conductive layer 108 and the patterned conductive layer 110 are connected by a three-dimensional printing wire 112 located on the surface of the cutout 106. In addition, the same components of the package substrate 20 and the package substrate 10 are denoted by the same symbols, and description thereof will not be repeated here.

5A is a top view of a package substrate according to another embodiment of the present invention. Fig. 5B is a right side view of Fig. 5A. For clear description, the components on the first surface and the second surface of the carrier board are not shown in FIG. 5B. Fig. 5C is a bottom view of Fig. 5A. Please refer to FIGS. 4A to 5C at the same time. Differences between the package substrate 30 and the package substrate 20 are as follows. The carrier board 100 of the package substrate 30 does not have the cutout 106. The package substrate 30 has a side surface of an edge of the carrier board 100 as the third surface 102c. That is, the three-dimensional printing wire 112 is located on a side surface of the edge of the carrier board 100. In the package substrate 30, the patterned conductor layer 108 and the patterned conductor layer 110 are connected by a three-dimensional printing wire 112 located on a side surface of the edge of the carrier board 100. In addition, a solder resist layer 118 covering the three-dimensional printing wire 112 can be selectively formed on the third surface 102c, so as to protect the three-dimensional printing wire 112 on the third surface 102c. In addition, the same members of the package substrate 30 and the package substrate 20 are denoted by the same symbols, and description thereof will not be repeated here.

6A is a top view of a package substrate according to another embodiment of the present invention. Fig. 6B is a right side view of Fig. 6A. Fig. 6C is a bottom view of Fig. 6A. FIG. 6D is a cross-sectional view of the interface between the three-dimensional printed wire and the carrier board along the III-III 'section line in FIG. 6A. For clear description, the components on the first surface and the second surface of the carrier board are not shown in FIG. 6B, and only the three-dimensional printing wire and the carrier board are shown in FIG. 6D.

Please refer to FIGS. 3A to 3D and FIGS. 6A to 6D at the same time. The differences between the package substrate 40 and the package substrate 10 are as follows. The package substrate 40 has only the surface of the opening 104 as the third surface 102c. That is, the carrier board 100 of the package substrate 40 does not have the cutouts 106, and therefore does not have the three-dimensional printing wires 112 located on the surface of the cutouts 106. In the package substrate 40, the patterned conductor layer 108 and the patterned conductor layer 110 are connected by a three-dimensional printing wire 112 located on the surface of the opening 104. In addition, the same components of the package substrate 40 and the package substrate 10 are denoted by the same symbols, and description thereof will not be repeated here.

The substrates 10, 20, 30, and 40 for a package according to the above embodiments can be applied to a packaging process performed by a die-bonding or flip-chip method. In addition, the package substrates 10, 20, 30, and 40 of the above embodiments can also be applied to a single-chip package, a dual-chip package, or a package on package (PoP).

Next, the package of the present invention is exemplified by the following examples.

FIG. 7 is a cross-sectional view of a package according to an embodiment of the present invention. Referring to FIGS. 4A to 4C and FIG. 7, the package 50 includes a package substrate 20 and a first electronic component 200. The structure of the substrate 20 for a package has been described in detail in the above-mentioned embodiment, and therefore the description will not be repeated here. In this embodiment, the description is made by using the package substrate 20 shown in FIGS. 4A to 4C to make the package 50 as an example, but the present invention is not limited thereto. In another embodiment, the package body 50 can also be fabricated using the package substrate 30 shown in FIGS. 5A to 5C.

The first electronic component 200 is disposed on the first surface 102 a of the package substrate 20 and is electrically connected to the patterned conductor layer 108 of the package substrate 20 (FIG. 4A). The first electronic component 200 is, for example, a wafer, but the invention is not limited thereto. The first electronic component 200 may be attached to the first surface 102 a of the package substrate 20 by an adhesive 202. The first electronic component 200 may be electrically connected to the patterned conductor layer 108 of the package substrate 20 through a bonding wire 204.

In addition, the package 50 may further include a solder ball 206. The solder ball 206 is disposed on the second surface 102 b of the package substrate 20 and is electrically connected to the patterned conductor layer 110 of the package substrate 20 (FIG. 4C). The first electronic component 200 may be electrically connected to the solder ball 206 through the patterned conductive layer 108, the three-dimensional printing wire 112, and the patterned conductive layer 100 (FIGS. 4A to 4C) of the package substrate 20.

In addition, the encapsulation body 50 may further include an encapsulation 208. The sealant 208 covers the first electronic component 200 and can be used to protect the first electronic component 200. The material of the sealant 208 is, for example, a dielectric polymer material.

FIG. 8 is a cross-sectional view of a package according to another embodiment of the present invention. Referring to FIGS. 3A to 3D and FIG. 8, the package body 60 includes a package substrate 10 and first electronic components 300 a and 300 b. The structure of the substrate 10 for a package has been described in detail in the above-mentioned embodiments, and therefore the description will not be repeated here. In this embodiment, the package 60 is described by using the package substrate 10 shown in FIGS. 3A to 4D as an example, but the present invention is not limited thereto. In another embodiment, the package body 60 can also be fabricated by using the package substrate 40 of FIGS. 6A to 6D.

The first electronic components 300 a and 300 b are disposed on the first surface 102 a of the package substrate 10 and are electrically connected to the patterned conductor layers 108 (FIG. 3A) of the package substrate 10. The first electronic component 300a is, for example, a driver IC, and the first electronic component 300b is, for example, a passive component, but the present invention is not limited thereto. The first electronic component 300 a can be electrically connected to the patterned conductor layer 108 of the package substrate 10 through a bump 302. The first electronic component 300 b can be mounted on the first surface 102 a of the package substrate 10 by a surface mount technology (SMT). The first electronic component 300 b may be electrically connected to the patterned conductor layer 108 of the package substrate 10 through a conductive paste 304.

In addition, the package 60 may further include at least one of the second electronic component 306 and the solder ball 308. The second electronic component 306 and the solder ball 308 are disposed on the second surface 102 b of the package substrate 10, and are electrically connected to the patterned conductor layer 110 of the package substrate 10 (FIG. 3C). The opening 104 of the package substrate 10 exposes the second electronic component 306 provided on the second surface 102b. The second electronic component 306 is, for example, an image sensor, but the invention is not limited thereto. The second electronic component 306 can be electrically connected to the patterned conductor layer 110 of the package substrate 10 through the bump 310, and the bump 310 can be protected by the primer 312. The first electronic components 300a and 300b can be electrically connected to the second electronic component 306 through the patterned conductive layer 108, the three-dimensional printed wire 112, and the patterned conductive layer 100 (FIGS. 3A to 3D) of the package substrate 10, respectively. / Or solder ball 308.

In addition, the package body 60 may further include a light transmitting plate 314, and light may pass through the light transmitting plate 314 and reach the second electronic component 306. The light transmitting plate 314 is disposed on the first surface 102 a of the package substrate 10 and covers the opening 104. The material of the light-transmitting plate 314 is, for example, glass. The light-transmitting plate 314 can be attached to the first surface 102 a of the package substrate 10 by an adhesive 316.

Based on the above embodiments, it can be known that by using the substrates 10, 20, 30, and 40 for the packages to make the packages 50 and 60, the packages 50 and 60 can have better design flexibility.

In summary, the package substrate and the manufacturing method of the above embodiments do not need to use a via process, and can complete the interconnection between the patterned conductor layer and the patterned conductor layer circuit in a simple manner. According to the requirements of packaging product characteristics, the shape of the substrate is designed for packaging. In addition, the method for manufacturing a substrate for a package can effectively reduce the manufacturing time and cost of the substrate for a package. In addition, in the package of the above embodiment, since the above-mentioned substrate for a package is used, it is possible to have better design flexibility.

Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

10, 20, 30, 40‧‧‧ substrates for packages

50, 60‧‧‧ package

100‧‧‧ Carrier Board

102a‧‧‧first surface

102b‧‧‧Second surface

102c‧‧‧ Third surface

104‧‧‧ opening

106‧‧‧ gap

108, 110‧‧‧ patterned conductor layer

108a, 110a‧‧‧ contact

108b, 110b‧‧‧ lead

112‧‧‧3D printing wire

114, 116, 118‧‧‧ solder mask

200, 300a, 300b ‧‧‧ the first electronic component

202, 316‧‧‧ Adhesive

204‧‧‧Welding wire

206, 308‧‧‧ solder balls

208‧‧‧Sealant

302, 310‧‧‧ bump

304‧‧‧Conductive Adhesive

306‧‧‧Second electronic component

312‧‧‧primer

314‧‧‧Translucent plate

1A, 2A and 3A are top views of a manufacturing process of a package substrate according to an embodiment of the present invention. 1B, 2B, and 3B are right side views of FIGS. 1A, 2A, and 3A, respectively. 1C, 2C, and 3C are bottom views of FIGS. 1A, 2B, and 3A, respectively. Fig. 2D is a cross-sectional view of the interface between the three-dimensional printed wire and the carrier board along the I-I 'section line in Fig. 2A. FIG. 3D is a cross-sectional view of the interface between the three-dimensional printed wire and the carrier board along the II-II 'section line in FIG. 3A. 4A is a top view of a package substrate according to another embodiment of the present invention. Fig. 4B is a right side view of Fig. 4A. FIG. 4C is a bottom view of FIG. 4A. 5A is a top view of a package substrate according to another embodiment of the present invention. Fig. 5B is a right side view of Fig. 5A. Fig. 5C is a bottom view of Fig. 5A. 6A is a top view of a package substrate according to another embodiment of the present invention. Fig. 6B is a right side view of Fig. 6A. Fig. 6C is a bottom view of Fig. 6A. FIG. 6D is a cross-sectional view of the interface between the three-dimensional printed wire and the carrier board along the III-III 'section line in FIG. 6A. FIG. 7 is a cross-sectional view of a package according to an embodiment of the present invention. FIG. 8 is a cross-sectional view of a package according to another embodiment of the present invention.

Claims (5)

A package includes: a substrate for a package, including: a carrier board having a first surface, a second surface, and a third surface, wherein the first surface is opposite to the second surface, and the third A surface is connected between the first surface and the second surface; a first patterned conductor layer is disposed on the first surface; a second patterned conductor layer is disposed on the second surface; and a three-dimensional A printing wire is disposed on the third surface and is connected between the first patterned conductor layer and the second patterned conductor layer. A first electronic component is disposed on the first surface and is electrically conductive. Connected to the first patterned conductor layer; and a second electronic component disposed on the second surface and electrically connected to the second patterned conductor layer, wherein the carrier board has an opening and the opening is exposed The second electronic component is disposed on the second surface. The package according to item 1 of the patent application scope, wherein the third surface includes a surface of the opening in the carrier board, a side surface of an edge of the carrier board, or a surface of at least one notch of the carrier board edge. The package according to item 1 of the patent application scope further includes a light-transmitting plate disposed on the first surface and covering the opening. A substrate for a package includes a carrier board having a first surface, a second surface, and a third surface, wherein the first surface is opposite to the second surface, and the third surface is connected to the first surface. Between the surface and the second surface, wherein the third surface is a side without a gap on the edge of the carrier board; a first patterned conductor layer is disposed on the first surface; a second patterned conductor layer is disposed on On the second surface; and a three-dimensional printing wire disposed on the third surface and connected between the first patterned conductor layer and the second patterned conductor layer. A method for manufacturing a substrate for a package includes: providing a carrier board having a first surface, a second surface, and a third surface, wherein the first surface is opposite to the second surface and the third surface is connected Between the first surface and the second surface, wherein the third surface is a side without a notch on the edge of the carrier board; a first patterned conductor layer is formed on the first surface; and the second surface is formed on the second surface A second patterned conductor layer; and forming a three-dimensional printing wire on the third surface using a three-dimensional printing method, wherein the three-dimensional printing wire is connected to the first patterned conductor layer and the second patterned conductor layer between.