TWI656601B - Asymmetric stair structure and method for fabricating the same - Google Patents

Abstract

An asymmetric step structure comprising: a stacked multi-level cell layer and m (m32) regions, wherein each of the cell layers having different portions in each region has a portion not covered by the upper adjacent cell layer, and the different portion The unit layers are separated by m layer unit layers, and a step having a step of m layer unit layers is formed, and unit layers of two different portions in any two regions are not repeated.

Description

Asymmetrical step structure and manufacturing method thereof

The present invention relates to a structure suitable for an integrated circuit and a method of fabricating the same, and more particularly to an asymmetric step structure and a method of fabricating the same.

Multi-layer component structures, such as wires of various layers of three-dimensional (3D) component arrays (for example, 3D memory), need to be electrically connected, so that each layer of the conductive layer in the contact region needs to be exposed to be electrically connected to form a stepped contact. Pad structure.

In the prior art, the step structure is formed by successively forming and gradually reducing a plurality of photoresist layers, and a plurality of etching steps and at least one photoresist reduction step alternately performed therebetween. FIG. 1 illustrates an example in which four patterned photoresist layers are sequentially formed by using four masks, and each photoresist layer is formed by alternately etching a layer of the unit layer 102 four times and three times of photoresist reduction steps, wherein The portion of the /2/3/4 photoresist layer that was etched away from the mask was 112/114/116/118, and finally formed 16 steps.

However, the symmetric step structure thus defined is wide, in which each unit layer has two portions which are respectively exposed to the two halves of the step structure, and one of the two portions, that is, half of the area is not used, so This will result in wasted wafer area.

The present invention provides an asymmetric step structure that reduces the width of the step structure by at least half, while avoiding wasted wafer area.

The present invention also provides a method of fabricating an asymmetric stepped structure that can be used to fabricate the asymmetric stepped structure of the present invention.

The asymmetric step structure of the present invention comprises: a stacked multi-layer unit layer and m (m32) regions, wherein each of the regions has a different portion of the unit layers, each of which has a portion not covered by the upper adjacent unit layer, and the difference A part of the unit layers are spaced apart by two m-unit layers, and a step having a step of m-layer unit layers is formed, and unit layers of two different portions in any two regions are not repeated. For example, when m=2, one of the regions exposes an odd-level layer unit layer, and the other region exposes an even-numbered layer unit layer.

In an embodiment, the total number of layers of the unit layer is N (N316), and when the unit layers are numbered from the bottom to the top of the first to Nth unit layers, in the i-th (i=1~m) region The unit layers of the different parts are numbered N-(i-1)-0 ́m, N-(i-1)-1 ́m ... N-(i-1)-k _i ́m, where k _i is Do not make N-(i-1)-k _i ́m the largest integer less than one.

In an embodiment, the stepwise arrangement of the m regions forms a peak shape. In another embodiment, the stepwise arrangement of the m regions forms a valley shape.

In an embodiment, the steps from the low to the high of the steps of at least two of the m regions are different or opposite. In another embodiment, the steps from at least two of the m regions are the same from low to high.

In one embodiment, each of the unit layers includes a first material layer and a second material layer, and the first material layers and the second material layers of the unit layers are alternately stacked. In a related embodiment, the unit layers are stacked on a substrate, wherein a second material layer is located on the first material layer in each unit layer, and a second material layer is between the lowest unit layer and the substrate. It covers the substrate or does not cover a portion of the substrate, wherein the portion of the substrate is located in at least one of the m regions.

In an embodiment, the total number of layers of the unit layer or the value of N is an integer multiple of the value of m.

The manufacturing method of the asymmetric step structure of the present invention comprises: forming a stacked structure including a plurality of unit layers on a substrate; a step generation program including lithography, mask reduction, and etching operation for each of m (m32) regions Generating a step shape in which the step is an m-layer unit layer; and a m-1 partial etching process for respectively performing the second to m-th regions, wherein the partial etching process for the i-th region (i=2 to m) is removed The i-1 layer unit layer in the i region. The order of the m steps of the step generation step and the m-1 partial etch process is arbitrary.

In one embodiment, at least one of the second to mth regions that have undergone the local etch process exposes a portion of the substrate after the step of step generation and the corresponding partial etch process.

In the asymmetric step structure of the present invention, since the two-part unit layers exposed in any two regions are not repeated, the area occupied by the step structure is at least half less than that of the prior art, and the larger the m value (m32), the more area saved. .

The above described features and advantages of the invention will be apparent from the following description.

The invention is further illustrated by the following examples, which are intended to be illustrative only and not to limit the scope of the invention.

For example, the total number of layers N of the unit layers may be an integral multiple of the number m of regions, but the invention is not limited thereto. When N/m is an integer, the aforementioned maximum integer k _{i which} does not make N-(i-1)-k _i ́m less than 1 is N/m-1, and the derivation process is as follows: N-(i-1) -k _i ́m31 ® k _i £N/mi/m; when i=m, N/mi/m is N/m-1, which is an integer, so k _i is N/m-1; when i<m When i/m<1, N/mi/m is greater than N/m-1 but less than N/m, so k _{i is} still N/m-1. When N/m is not an integer, k _i is an indefinite number.

2 is a cross-sectional view showing a valley-shaped asymmetric step structure of m=2 according to an embodiment of the present invention, and showing a portion removed by using a different photoresist layer as a mask in the process.

Referring to FIG. 2, the asymmetric step structure 20 has two regions (m=2), and the number of layers of the unit layer 102 is 16 (N=16). When the unit layers 102 are numbered from the bottom to the top of the first to sixteenth unit layers, the first region (i=1) is exposed to the 16th (=16-(1-1)-0 ́2), the 14th (= 16-(1-1)-1 ́2), 12th, 10th, 8th, 6th, 4th, and 2nd (=16-(1-1)-7 ́2) unit layers 102 (i= 1 time, the maximum integer k _i of N-(i-1)-k _i ́m less than 1 is not 7, which is equal to 16/2-1=N/m-1), that is, the unit layer 102 of the even layer, and Forming a step with a step difference of 2 (=m) layer unit layer 102; the second region (i=2) exposing the 15th (=16-(2-1)-0 ́2), the 13th (=16-(2) -1)-1 ́2), 11th, 9th, 7th, 5th, 3rd, and 1st (=16-(2-1)-7 ́2) cell layer 102 (i=2 does not make The largest integer k _{i of} N-(i-1)-k _i ́m less than 1 is also 7), that is, the unit layer 102 of the odd-numbered layer, and another layer layer 102 of the layer layer 102 having a step difference of 2 (=m) is formed. ladder. There is no overlap between the unit layer 102 of the even-numbered layer exposed in the first region and the unit layer 102 of the odd-numbered layer exposed in the second region, and the stepwise arrangement of the two regions forms a valley shape.

In addition, the numbers of the first and second regions herein are only intended to conform to the above rules, and have no particular meaning in terms of the order of arrangement. In the other embodiments in which m=2, the person who exposes the odd-numbered layer unit layer may be referred to as the first area, and the one that exposes the even-numbered layer unit layer may be referred to as the second area.

Each unit layer 102 includes, for example, a first material layer 104 and a second material layer 106 thereon, and the first material layers 104 and the second material layers 106 are alternately stacked. There may also be a second material layer 106 underneath the lowest unit layer 102, which may serve as an etch stop layer for the first material layer 104 of the lowest unit layer 102. The material combination of the first material layer 104 and the second material layer 106 is, for example, tantalum nitride and tantalum oxide, a complex germanium and tantalum oxide, tungsten and tantalum oxide, cobalt antimonide and antimony oxide, or nickel antimonide and antimony oxide.

The step structure 20 can be manufactured by using the above-described step generation program and a 1 (=m-1) partial partial etching process. The process is as shown in FIGS. 3A to 3F, and the step generation program sequentially forms two patterns using two masks. The photoresist layers 212 and 214, wherein each photoresist layer is formed by alternately etching the 2 (=m) layer unit layer 102 and 3 mask reduction steps to form symmetrically in 2 (=m) regions. Four steps are defined in each of them, and an eight-step step shape having a step of two layer unit layers 102 is generated in each of the two regions symmetrically by two rounds of lithography-etching-cutting cycles. Only a partial etching process of 1 (=m-1) times is performed, using the third mask to form another patterned photoresist layer 216 to cover one area, and removing 1 (=m-1) in the other area. Layer unit layer 102. The three portions removed by using the photoresist layers 212, 214, and 216 as the masks are also indicated by arrows and dashed lines in FIG. 2, and the three are separated by thick solid lines.

The above-described step generation program and partial etching procedure are further described below. The step generation program is shown in Figures 3A to 3E, and the local etching procedure is shown in Figures 3E to 3F.

Referring to FIG. 3A, a stacked structure of 16 layer unit layers 102 is formed on the substrate 100. The substrate 100 is, for example, a germanium substrate, and there may be a second material layer 106 between the substrate 100 and the lowest unit layer 102. A patterned photoresist layer 212 is then formed to expose a portion of the stack, the width of which is the valley bottom width of the finished product, which may be on the order of angstroms to micrometers. Next, an etching step 220 is performed to remove the exposed two-layer unit layer 102, and a first order having a height of two layer unit layers 102 is defined. Preferably, there is sufficient etch selectivity between the first and second materials such that any of the first material layers 104 can serve as an etch stop layer for the adjacent second material layer 106 thereon, and any second material layer 106 can serve as an etch stop layer for the first material layer 104 adjacent thereto. For example, it is possible that the first material is tantalum nitride and the second material is tantalum oxide.

Referring to FIG. 3B, a mask reduction step is then performed to reduce the width of the photoresist layer 212 by w. The w value is the width of one step, and the thickness of the photoresist layer 212 is also reduced. Then, using the reduced photoresist layer 212a as a mask, an etching step 222 is performed to remove the exposed two-layer unit layer 102, and the left-right symmetrically defines another step of the height of the two-layer unit layer 102, while making the previously defined That 1st order lowers the height of the 2 layer unit layer 102.

Then, the mask reduction step is alternately performed twice and the etching step of removing the exposed two-layer unit layer 102 is performed twice, and the second order is symmetrically defined by the left and right sides, together with the previously defined second order, a total of four steps, each height is Two layer unit layers 102, as shown in Figure 3C, where 224 is the fourth etch. At this time, the photoresist layer 212b is too thin due to the previous reduction and etching, and cannot be cut again, so it must be removed.

Referring to FIG. 3D, a patterned photoresist layer 214 is formed, the boundary of which is wider than the width of one step, that is, the width of one step, and then the step of etching the two-layer unit layer 102 and the third-time mask are alternately performed four times. The curtain reduction step, and the left and right symmetry define the next 4 steps, together with the previously defined 4th order, a total of 8 orders, each step height is 2 layers of the unit layer 102, as shown in FIG. 3E. At this time, the bottommost second material layer 106 is exposed.

Next, a partial etching process is performed, that is, the patterned photoresist layer 216 is formed to cover the left side region, as shown in FIG. 3E, and the 1 layer unit layer 102 in the right region is removed, as shown in FIG. 3F. In this embodiment, the boundary of the photoresist layer 216 is aligned with the boundary of the nextmost layer of the right region, so that the bottommost second material layer 106 is not etched.

However, it is not easy to completely align the boundary of the photoresist layer with the boundary of the next-most region of the right region, so the boundary of the photoresist layer is usually preset at the boundary of the next-order boundary of the left region and the boundary of the next-order region of the right region. Between, as shown in the photoresist layer 216' of FIG. 4A, in order to avoid reducing the width of the last step of the leftmost region of the finished product or the next step of the right region. In this case, the bottommost second material layer 106 is partially removed due to the local etching process, and a portion of the lower substrate 100 in the right region is exposed, as shown in Fig. 4B, thereby forming an asymmetric stepped structure 20'.

In addition, in an embodiment in which the first material layer 104 and the second material layer 106 are respectively a tantalum nitride layer and a tantalum oxide layer, after the asymmetric step structure is formed, a known method may be used to replace tantalum nitride. A conductor material such as a germanium, tungsten, cobalt telluride or nickel telluride is obtained, and an asymmetric step structure in which a layer of a tantalum oxide layer and a layer of a conductor material are stacked is obtained.

Although the asymmetric stepped structure 20 or 20' of the above embodiment is in the form of a valley, the present invention is not limited thereto, and the asymmetric stepped structure may also be a peak shape as shown in FIG. The width of the peak top of the asymmetric stepped structure 22, i.e., the width of the highest unit layer 102, may be on the order of angstroms to micrometers. The main difference between the process of the peak-shaped asymmetric step structure 22 and the valley-shaped asymmetric step structure 20 or 20' is that the boundary of the patterned photoresist layer in the step generation process is tapered from the sides of the step structure formation region toward the middle. .

In addition, although the step generation program in the above embodiment is performed before the partial etching process, the present invention is not limited thereto, and in other embodiments, the step generation program may be performed after performing the partial etching process.

Referring to FIG. 6, in an embodiment, the peak-shaped asymmetric step structure 22 is formed in the memory array region 600, and the valley-shaped asymmetric step structure 20/20' is formed in the peripheral region 602, wherein the hatching 610 corresponds to Sections 3F/4B and 5.

On the other hand, although the valley-shaped asymmetric stepped structure 20 or 20' and the peak-shaped asymmetric stepped structure 22 of the above embodiment are the reverse of the steps of the two regions from the low to the high, the present invention is not limited thereto, and two The step of the region may be the same from low to high, such as the asymmetric step structure 30 shown in FIG. The two regions of the valley-shaped asymmetric stepped structure 30 are asymmetrical to one of the vertical planes parallel to the stepped direction, and are symmetrical with respect to the other vertical plane that is cut through the center of the valley and perpendicular to the aforementioned vertical plane.

Further, the main difference between the process of the valley-shaped asymmetric step structure 30 and the valley-shaped asymmetric step structure 20 or 20' is that the boundary surface of the photoresist layer formed by the partial etching process is parallel to the stepwise direction. Another feature of the asymmetric step structure 30 thus formed is that the bottommost second material layer 106 is necessarily partially removed by a partial etching process to expose a portion of the underlying substrate 100.

Although the asymmetric step structure of the above embodiment has the number of regions m being two, the present invention is not limited thereto, and the number of regions m may be other integers greater than 2, but is usually an integer fraction of the total order N. . When N=16, the integer m greater than 2 is, for example, 4, and the manufacturing process of such an asymmetric step structure is, for example, the following embodiment.

Referring to FIG. 8, this embodiment forms a valley-shaped asymmetric step structure of N=16 and m=4, wherein each etching step in the step generation process removes 4 layer unit layers 102, so 4 times. The etching step etches to the lowest cell layer. Therefore, the mask reduction step is also required only three times, so that the step generation program is sufficient to form the patterned photoresist layer once. The area that is etched when the patterned photoresist layer is used as the mask in this step is the region 802, wherein the number of layers removed in each step is indicated by a small number. The local etching process is performed 3 (=m-1) times, respectively, for each of the regions 804, 806, and 808 overlapping with different portions of the region 802, and one, two, and three polymer layers are removed, respectively. The number of layers removed in each step is indicated by small numbers 1, 2, and 3. For any step region that has undergone a local etch process, the total number of layers removed in the step generation process and the number of layers removed from the local etch process subjected to the step region are summed. For all the stages, the total number of layers minus the total number of removed layers is the number of the exposed unit layers in the order (in the case of numbering starting from the lowest unit level).

It can also be seen from the number of layers removed as shown in Fig. 8. The above steps of the step generation program and the 3 (=m-1) partial etching process can be performed in any order, and the total number of layers removed in each step region does not change. .

9 illustrates different cross-sections of the asymmetric stepped structure 40 obtained above, wherein the portions removed by the etching of the regions 802, 804, 806, 808, and the number of the exposed unit layers 102 in each of the terrace regions are indicated ( In the case of numbering by the lowest unit layer 102). If the ith (i=1~m) region is applied, the N-(i-1)-0 ́m, N-(i-1)-1 ́m...N-(i-1)- For the rule of k _i ́m unit layer, the first region (i=1) reveals the 16th (=16-(1-1)-0 ́4), the 12th (=16-(1-1)-1 ́) 4), 8th and 4th (=16-(1-1)-3 ́4) unit layers, the second area (i=2) is exposed to the 15th (=16-(2-1)-0 ́4) , 11th (=16-(2-1)-1 ́4), 7th and 3rd (=16-(2-1)-3 ́4) cell layers, the third region (i=3) is exposed 14 (=16-(3-1)-0 ́4), 10th (=16-(3-1)-1 ́4), 6th and 2nd (=16-(3-1)-3 ́ 4) Unit layer, and the 4th area (i=4) is exposed to the 13th (=16-(4-1)-0 ́4), 9th (=16-(4-1)-1 ́4), 5 and the 1st (=16-(4-1)-3 ́4) unit layer, where i=1~4 does not make the maximum integer k _{i of} N-(i-1)-k _i ́m less than 1 Is 3, equal to 16/4-1=N/m-1.

Although the above embodiment forms a valley-shaped asymmetric stepped structure of m=4, the asymmetric stepped structure of m=4 may also be peak-shaped, for example, a peak-shaped asymmetrical step of m=4 as shown in FIG. Structure 50, the different sections of which are depicted in the figures. The difference between the process of the peak-shaped asymmetric step structure 50 and the process of the valley-shaped asymmetric step structure 40 is mainly that the boundary of the patterned photoresist layer in the step generation process is tapered from the periphery of the step-shaped structure region toward the middle.

In addition, although the number m of the regions in the above embodiment is 2 or 4, the number m of the regions in the present invention may be other integers greater than 1, as long as the respective step regions defined by the order m-1 shape generating program are overlapped. A total of m-1 areas subjected to the local etching process are sufficient. Further, although the total number of unit layers N in the above embodiment is an integral multiple of the number m of the regions, the N/m is not an integer in the present invention. For example, when N=17 and m=3, it may be that the first region subjected to the step generation program exposes the 17th, 14th, 11th, 8th, 5th, and 2th unit layers (i=1 when k _i is 5), the second region subjected to the partial etching process of removing the one-layer unit layer exposes the 16th, 13th, 10th, 7th, 4th, and 1st unit layers (ki _i is 5 when i=2), and is subjected to removal of the 2-layer unit layer The third region of the partial etching process exposes the 15th, 12th, 9th, 6th, and 3th unit layers (w _i is 4 when i=3). Similarly, the numbers of the first, second, and third regions herein are only for the purpose of conforming to the above rules, and have no particular meaning in terms of the order, as in the previous example of m=2.

In the asymmetric step structure of the present invention, since the two-part unit layers exposed in any two regions are not repeated, the area occupied by the step structure is at least half less than that of the prior art, and the larger the m value (m32), the more area saved. .

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

20, 20', 22, 30, 40, 50‧‧‧ asymmetric ladder structure

100‧‧‧Base

102‧‧‧Unit layer

104‧‧‧First material layer

106‧‧‧Second material layer

112, 114, 116, 118‧‧‧ Parts removed with different photoresist layers as masks

212, 212a, 212b, 214, 216, 216'‧‧‧ photoresist layer

220, 222, 224 ‧ ‧ etching

600‧‧‧Array area

602‧‧‧ surrounding area

610‧‧‧ hatching

802, 804, 806, 808‧‧‧ parts etched with different photoresist layers as masks

w‧‧‧Width

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross-sectional view of a prior art symmetric stepped structure and showing portions of the process in which the different patterned photoresist layers are used as a mask. 2 is a cross-sectional view showing a valley-shaped asymmetric step structure of m=2 according to an embodiment of the present invention, and showing a portion removed during the process of using a different patterned photoresist layer as a mask. 3A-3F are cross-sectional views showing a method of fabricating a valley-shaped asymmetric step structure of m=2 as shown in FIG. 2 according to an embodiment of the present invention. 4A-4B are cross-sectional views showing a partial etching process in a method for fabricating a valley-shaped asymmetric step structure of m=2 according to another embodiment of the present invention, and the step generation program of the other embodiment can be compared with FIG. 3A. The same is shown in 3D. FIG. 5 is a cross-sectional view showing a peak-shaped asymmetric step structure of m=2 according to an embodiment of the present invention. FIG. 6 illustrates a position where a valley-shaped asymmetric stepped structure and a peak-shaped asymmetric stepped structure are respectively located in an embodiment of the present invention. FIG. 7 is a diagram showing a valley-shaped asymmetric step structure in which the steps of the two regions of the present invention are the same m=2 from the low to the high. FIG. 8 is a diagram showing the number of unit layers removed in each of the m regions in the process of the valley-shaped asymmetric step structure of m=4 according to an embodiment of the present invention. 9 is a cross-sectional view showing different cross sections of a valley-shaped asymmetric step structure of m=4 according to an embodiment of the present invention, and showing a portion removed during the process of using a different patterned photoresist layer as a mask. 10 is a cross-sectional view showing a peak-shaped asymmetric step structure of m=4 according to an embodiment of the present invention.

Claims (10)

An asymmetric step structure comprising: a stacked multi-layer cell layer and m (m32) regions, wherein each of the cell layers having different portions in each region has a portion thereof not covered by the upper adjacent cell layer, and the different portion The unit layers are separated by m layer unit layers, and a step having a step of m layer unit layers is formed, and unit layers of two different portions in any two regions are not repeated. The asymmetric step structure according to claim 1, wherein the total number of layers of the unit layers is N (N316), and when the unit layers are numbered from the bottom to the top of the first to Nth unit layers, The number of the unit layers of the different part in the i-th (i=1~m) region is N-(i-1)-0 ́m, N-(i-1)-1 ́m ... N-(i- 1) - k _i ́m, where k _i is the largest integer that does not cause N-(i-1)-k _i ́m to be less than one. The asymmetric step structure according to claim 1 or 2, wherein the stepwise arrangement of the m regions forms a peak shape or a valley shape. The asymmetric step structure according to claim 1 or 2, wherein the steps from at least two of the m regions are different or opposite from the low to the high. The asymmetric step structure according to claim 1 or 2, wherein the steps of at least two of the m regions are the same from the low to the high. The asymmetric step structure of claim 1 or 2, wherein each unit layer comprises a first material layer and a second material layer, and the first material layers of the unit layers and the second The layers of material are stacked alternately. The asymmetric step structure according to claim 6, wherein the unit layers are stacked on a substrate, wherein the second material layer of each unit layer is located on the first material layer, and the lowest unit layer and the substrate There is also a second layer of material covering the substrate or not covering a portion of the substrate, wherein the portion of the substrate is in at least one of the m regions. The asymmetric step structure according to claim 1 or 2, wherein the total number of layers or the N value of the unit layers is an integer multiple of the m value. A method for fabricating an asymmetric step structure, comprising: forming a stacked structure including a plurality of unit layers on a substrate; a step generation program including lithography, mask reduction, and multiple etching steps of etching the m layer unit layer each time, For each of the m (m32) regions, a step shape having a step of the m layer unit layer is generated; and m-1 partial etching processes are performed for the second to mth regions, respectively, wherein the i-th region (i=2) The partial etching process performed by ~m) removes the i-1 layer unit layer in the i-th region, wherein the order of the step generation step and the m-1 partial etching process is arbitrary. The method for manufacturing an asymmetric step structure according to claim 9, wherein at least one of the second to mth regions subjected to the partial etching process passes through the step generation step and corresponding A portion of the substrate is exposed after the partial etching process.