TWI650841B - Molded intelligent power module - Google Patents

Abstract

An intelligent power module (IPM) having first, second, third, and fourth wafer pads, first, second, third, fourth, fifth, and sixth metal-oxide-semiconductor fields Effect transistor (MOSFET), tie rod, integrated circuit IC, multiple leads, and a molded package. The first MOSFET is connected to the first die pad. The second MOSFET is connected to the second die pad. The third MOSFET is connected to the third die pad. The fourth, fifth and sixth MOSFETs are connected to the fourth die pad. The IC is connected to the tie rod. Molded packages package the first, second, third, and fourth wafer pads, the first, second, third, fourth, fifth, and sixth MOSFETs, tie rods, and ICs. The smart power module has a small outline package. Reduce system design time and improve reliability. The IC includes a boost diode. Reduced the package size of the smart power module.

Description

Moulded Intelligent Power Module

The invention mainly relates to a molded intelligent power module (IPM) for driving a motor. More precisely, the invention relates to a molded IPM having a compact size.

A conventional IPM for driving a motor has three driving integrated circuits (ICs). In the patent application of 15 / 294,766, the IPM has a low voltage IC and a high voltage IC. In this specification, the IPM has a separate IC that is directly connected to the tie rod. In the 15 / 294,766 patent application, the IPM has a dual in-line package. In this specification, the IPM is a small form factor package.

The small form factor package reduces system design time and improves reliability. The separate IC includes a boost diode. This reduces the package size.

The present invention provides an IPM with first, second, third, and fourth wafer pads, first, second, third, fourth, fifth, and sixth metal-oxide-semiconductor field effects. A transistor (MOSFET), a tie rod, an IC, multiple leads, and a molded package. The first MOSFET is connected to the first die pad. The second MOSFET is connected to the second die pad. The third MOSFET is connected to the third die pad. The fourth, fifth and sixth MOSFETs are connected to the fourth die pad. The IC is connected to the tie rod. Molded packages package the first, second, third, and fourth wafer pads, the first, second, third, fourth, fifth, and sixth MOSFETs, tie rods, and ICs.

The power lead is between the ground lead and the insulated lead. One end of the insulated lead terminates in a molded package. The insulated lead is between the power lead and other leads. With insulated leads, the distance between the power leads and other leads is increased. For high-voltage applications, the creepage distance is increased.

In order to achieve the above object, the present invention provides an intelligent power module, which includes: first, second, third, and fourth wafer pads; a first transistor is connected to the first wafer solder On the disk; the second transistor is connected to the second wafer pad; the third transistor is connected to the third wafer pad; the fourth, fifth and sixth transistors are connected to the fourth wafer On the pad; an integrated circuit is located near the second and third wafer pads; the integrated circuit is electrically connected to the first, second, third, fourth, fifth and sixth transistors; A plurality of leads; and a molded package that packages the first, second, third, and fourth wafer pads, the first, second, third, fourth, fifth, and sixth transistors and the integrated body Circuit; where a plurality of lead portions are embedded in a molded package.

Preferably, the smart power module further includes a tie rod having a first end, a second end, and a middle extension, wherein the middle extension of the tie rod is mechanically and electrically connected to the ground lead.

Preferably, the first end surface of the first end and the second end surface of the second end of the tie rod are both exposed from the edge surface of the molded package.

Preferably, the power lead is between the ground lead and the insulated lead.

Preferably, at least a portion of the top edges of the first wafer pad, the top edges of the second and third wafer pads, and at least a portion of the top edges of the fourth wafer pad are coplanar; The middle portion of the bottom edge of the tie rod is parallel to the top edges of the second and third wafer pads.

Preferably, the integrated circuit is electrically connected to the first, second, third, fourth, fifth and sixth transistors through a plurality of gold bonding wires, wherein the plurality of copper bonding wires connect the first, The second, third, fourth, fifth and sixth transistors are electrically and mechanically connected to a portion of the plurality of leads.

Preferably, the first connection element connects the first wafer pad to the first lead of the plurality of leads; the second connection element connects the second wafer pad to the second lead of the plurality of leads A third connection element connects the third wafer pad to the third lead of the plurality of leads; and a fourth connection element connects the fourth wafer pad to the fourth lead of the plurality of leads on-line.

Preferably, the first insulated lead is between the first low-voltage lead and the first lead; the second insulated lead is between the first lead and the second lead; and the third insulated lead is between the first Between the second and third leads.

Preferably, the fourth insulated lead is between the first selected high-voltage lead and the second selected high-voltage lead.

Preferably, the first lead is connected to the second selected high-voltage lead through the printed circuit board, and the second lead is connected to the first selected high-voltage lead through the printed circuit board.

Preferably, the fifth, sixth and seventh leads of the plurality of leads are directly connected to the fourth connection element.

Preferably, the first transistor is the first metal-oxide-semiconductor field effect transistor MOSFET; the second transistor is the second MOSFET; the third transistor is the third MOSFET; the fourth Each transistor is a fourth MOSFET; the fifth transistor is a fifth MOSFET; and the sixth transistor is a sixth MOSFET.

Preferably, the first bonding wire connects the source of the first MOSFET to the low-voltage wiring; the second bonding wire connects the source of the first MOSFET to the source of the second MOSFET; and the third A bond wire connects the source of the second MSOFET to the source of the third MOSFET.

Preferably, the plurality of first bonding wires connect the integrated circuit to the plurality of leads, or the integrated circuit is connected to the first, second, third, fourth, fifth, and sixth transistors. Above; wherein the plurality of second bonding leads connect the sources of the first, second, third, fourth, fifth, and sixth transistors to a portion of the plurality of leads; wherein the plurality of first bonding leads The leads are gold bond leads; and wherein the plurality of second bond leads are copper bond leads.

Preferably, the smart power module further includes a fifth wafer pad, wherein the fourth wafer pad has an inverted letter “L” shape, and wherein the fourth wafer pad has a cutout to accommodate the fifth A part of the chip pads to facilitate the compactness of the intelligent power module.

Preferably, wherein the fourth wafer pad is an inverted letter "L" shape; wherein the fourth wafer pad has a cutout to accommodate the wire bonding area of the third wafer pad; and wherein the bonding wire will be The source of the sixth transistor is connected to the wire bond area of the third wafer pad.

Compared with the conventional technology, the present invention has the following beneficial effects: the intelligent power module of the present invention has a small outline package; the system design time is reduced, and the reliability is improved; the integrated circuit IC includes a boost diode, which reduces the Package size of smart power module.

Figure 1 shows a perspective view of an IPM 100 in an embodiment of the invention. The IPM 100 has a plurality of leads 180. The plurality of leads 180 are partially embedded in the molded package 198.

Figure 2 shows a top view of an IPM 200 in an embodiment of the invention. The IPM 200 has a first wafer pad 202A, a second wafer pad 202B, a third wafer pad 202C, a fourth wafer pad 202D, a first transistor 242, a second transistor 244, a first Three transistors 246, a fourth transistor 252, a fifth transistor 254, a sixth transistor 256, a tie rod 210, an IC 220, a plurality of leads, and a molded package 298.

The first wafer pad 202A, the second wafer pad 202B, the third wafer pad 202C, and the fourth wafer pad 202D are separated from each other, and are arranged one after another in a certain order. In an embodiment of the present invention, a portion of the top edge of the first wafer pad 202A, the top edge of the second wafer pad 202B, the top edge of the third wafer pad 202C, and the fourth wafer pad 202D Part of the top edge is coplanar. In one embodiment, the middle portion of the bottom edge of the tie bar 210 is in the X-direction and is parallel to the top edges of the second wafer pad 202B and the third wafer pad 202C. In another embodiment, the middle portion of the bottom edge of the tie rod 210 is parallel to a portion of the top edge of the first wafer pad 202A. In another embodiment, the middle portion of the bottom edge of the tie rod 210 is parallel to a portion of the top edge of the fourth wafer pad 202D. The first transistor 242 is connected to the first wafer pad 202A. The second transistor 244 is connected to the second wafer pad 202B. A third transistor is connected to the third wafer pad 202C. The fourth transistor 252, the fifth transistor 254, and the sixth transistor 256 are connected to the fourth wafer pad 202D.

In an embodiment of the present invention, the tie rod 210 extends along the top edges of the wafer pads 202A, 202B, 202C, and 202D. The first end 212 of the tie rod 210 extends above the outer edge of the first wafer pad 202A. The second end 214 of the tie rod 210 extends above the outer edge of the fourth wafer pad 202D. In the embodiment of the present invention, the tie rod 210 further includes an intermediate extension 216 between the first end 212 and the second end 214. The intermediate extension of the tie rod 210 is mechanically and electrically connected to the ground lead 216A. The intermediate extension 216 extends in a horizontal direction (Y-direction) perpendicular to the top edge of the third wafer pad 202C. In the embodiment of the present invention, the power supply lead 217 is between the ground lead 216A and the insulated lead 219. One end of the insulated lead 219 terminates in the molded package 298. The insulated lead 219 is between the power lead 217 and the lead 221. With the insulated lead 219, the distance between the power lead 217 and the lead 221 is increased, and the current performance is improved. The IC 220 is connected to an extension area of the tie rod 210 between the first end 212 and the second end 214. In the embodiment of the present invention, the IC is electrically connected to the first transistor 242, the second transistor 244, the third transistor 246, the fourth transistor 252, and the fifth transistor by bonding wires. 254 and the sixth transistor 256. In the embodiment of the present invention, the bonding wire is preferably a gold bonding wire.

In the embodiment of the present invention, the mold package 298 packs the first wafer pad 202A, the second wafer pad 202B, the third wafer pad 202C, the fourth wafer pad 202D, and the first electrical pad. The crystal 242, the second transistor 244, the third transistor 246, the fourth transistor 252, the fifth transistor 254, the sixth transistor 256, the tie rod 210, and the IC 220. In the embodiment of the present invention, a plurality of lead portions are embedded in the molded package 298. In the embodiment of the present invention, the end surface of the first end 212 and the second end 214 of the tie rod 210 are both exposed from the edge surface of the molded package 298.

In an embodiment of the present invention, the IPM200 has leads 290, 292A, 282A, 292B, 284A, 292C, 286, 292D, 284B, 292E, 282B, 292F, 288A, and 288B. In the embodiment of the present invention, the leads 282A, 284A, 286, 288A, and 288B are all high-voltage leads. The first connection element 281A connects the first wafer pad 202A to the first lead 282A. The second connection element 283A connects the second wafer pad 202B to the second lead 284A. The third connection element 285A connects the third wafer pad 202C to the third lead 286. The fourth connection element 287A connects the fourth wafer pad 202D to the fourth lead 288A.

In the embodiment of the present invention, the lead 290 is a low-voltage lead. The leads 282A, 282B, 284A, 284B, 286, 288A, and 288B are high-voltage leads. In the embodiment of the present invention, both the high-voltage leads 282A and 282B can be shortened. Both high-voltage leads 284A and 284B can be shortened.

In the embodiment of the present invention, the first insulated lead 292A is between the first low-voltage lead 290 and the first lead 282A. The second insulated lead 292B is between the first lead 282A and the second lead 284A. The third insulated lead 292C is between the second lead 284A and the third lead 286. The fourth insulated lead 292E is between the first selected high-voltage lead 284B and the second selected high-voltage lead 282B. The fifth insulated lead 292F is between the second selected high-voltage lead 282B and the fourth lead 288A. The first lead 282A is connected to the second selected high-voltage lead 282B through the printed circuit board 101 (shown in dotted lines in the figure) shown in FIG. The circuit board 101 is connected to the first selected high-voltage lead 284B. By connecting the printed circuit board, more space is provided for the IC220, thereby reducing the size of the IC220.

In the embodiment of the present invention, the IC 220 is directly connected to the tie rod 210. In the embodiment of the present invention, the IPM 200 does not have another IC and is directly connected to the tie rod 210 (only the IC 220 is directly connected to the tie rod 210). The first, second, third, fourth, fifth and sixth transistors are metal-oxide-semiconductor field effect transistors (MOSFETs). The first bonding wire 291A connects the source 242S of the first transistor 242 to the first low-voltage wire 290. The second bonding wire 291B connects the source 242S of the first transistor 242 to the source 244S of the second transistor 244. The third bonding wire 291C connects the source 244S of the second transistor 244 to the source 246S of the third transistor 246. In an embodiment of the present invention, the first, second, and third bonding wires are copper bonding wires.

FIG. 3 is a plan view of an IPM 300 according to an embodiment of the present invention. The IPM 300 has a first wafer pad 302A, a second wafer pad 302B, a third wafer pad 302C, a fourth wafer pad 302D, a first transistor 342, a second transistor 344, a first Three transistors 346, a fourth transistor 352, a fifth transistor 354, a sixth transistor 356, a tie rod 310, an IC 320, a plurality of leads, and a molded package 398.

The first wafer pad 302A, the second wafer pad 302B, the third wafer pad 302C, and the fourth wafer pad 302D are separated from each other, and are arranged one after another in a certain order. In an embodiment of the present invention, a portion of the top edge of the first wafer pad 302A, the top edge of the second wafer pad 302B, the top edge of the third wafer pad 302C, and the fourth wafer pad A portion of the top edge of 302D is coplanar. In one embodiment, the middle portion of the bottom edge of the tie rod 310 is along the X-direction, parallel to the top edges of the second wafer pad 302B and the third wafer pad 302C. In another embodiment, the middle portion of the bottom edge of the tie rod 310 is parallel to a portion of the top edge of the first wafer pad 302A. In another embodiment, the middle portion of the bottom edge of the tie rod 310 is parallel to a portion of the top edge of the fourth wafer pad 302D. The first transistor 342 is connected to the first wafer pad 302A. A second transistor 344 is connected to the second wafer pad 302B. The third transistor 346 is connected to the third wafer pad 302C. A fourth transistor 352, a fifth transistor 354, and a sixth transistor 356 are connected to the fourth wafer pad 302D.

In an embodiment of the present invention, the tie rod 310 extends along the top edges of the wafer pads 302A, 302B, 302C, and 302D. The first end 312 of the tie rod 310 extends above the outer edge of the first wafer pad 302A. The second end 314 of the tie rod 310 extends above the outer edge of the fourth wafer pad 302D. In the embodiment of the present invention, the tie rod 310 further includes an intermediate extension 316 between the first end 312 and the second end 314. The intermediate extension 316 extends perpendicular to the horizontal direction (Y-direction) of the third wafer pad 302C. The IC 320 is connected to an extension area of the tie rod 310 between the first end 312 and the second end 314. In the embodiment of the present invention, the IC 320 is electrically connected to the first transistor 342, the second transistor 344, the third transistor 346, the fourth transistor 352, and the fifth transistor 354 by bonding wires. And the sixth transistor 356. In the embodiment of the present invention, a gold bonding wire is preferably used as the bonding wire.

In the embodiment of the present invention, the mold package 398 packs the first wafer pad 302A, the second wafer pad 302B, the third wafer pad 302C, the fourth wafer pad 302D, and the first electrical pad. The crystal 342, the second transistor 344, the third transistor 346, the fourth transistor 352, the fifth transistor 354, the sixth transistor 356, the tie rod 310, and the IC 320. In the embodiment of the present invention, a plurality of lead portions are embedded in the molded package 398.

In an embodiment of the invention, the IPM 300 has leads 390, 382A, 382B, 384A, 384B, 386A, 386B, 392A, 392B, 392C, 388A, 388B, 388C and 388D. The first connection element 381A connects the first wafer pad 302A to the first lead 382A. The second connection element 383A connects the second wafer pad 302B to the second lead 384A. The third connection element 385A connects the third wafer pad 302C to the third lead 386A. The fourth connection element 387A connects the fourth wafer pad 302D to the fourth lead 388A. The fifth lead 388B, the sixth lead 388C, and the seventh lead 388D are directly connected to the fourth connection element 387A.

FIG. 4 is a plan view of the IPM 400 in the embodiment of the present invention. The IPM 400 has a first wafer pad 402A, a second wafer pad 402B, a third wafer pad 402C, a fourth wafer pad 402D, a fifth wafer pad 410, a first transistor 442, The second transistor 444, the third transistor 446, the fourth transistor 452, the fifth transistor 454, the sixth transistor 456, the IC 420, a plurality of leads, and a molded package 498. The first transistor 442 is connected to the first wafer pad 402A. A second transistor 444 is connected to the second wafer pad 402B. A third transistor 446 is connected to the third wafer pad 402C. A fourth transistor 452, a fifth transistor 454, and a sixth transistor 456 are connected to the fourth wafer pad 402D. The IC 420 is connected to the fifth wafer pad 410.

In an embodiment of the present invention, the fifth wafer pad 410 has a first end 412, which extends above the outer edge of the first wafer pad 402A in the X-direction of the eye to provide a tie rod connection, and the second end 414 is along the Y-direction extension. The first end 412 is narrower than other areas of the fifth wafer pad 410. The second end 414 of the fifth wafer pad 410 is mechanically and electrically connected to the ground lead 416A. The first wafer pad 402A, the second wafer pad 402B, the third wafer pad 402C, and the fourth wafer pad 402D are located near at least two adjacent edges of the fifth wafer pad 410. The IC 420 is mounted on a wider area of the fifth wafer pad 410. The wider area is wider than the other areas of the fifth wafer pad 410. The wider area is near the second wafer pad 402B, the third wafer pad 402C, and the fourth wafer pad 402D.

In an embodiment of the present invention, the fourth wafer pad 402D is an inverted letter "L" shape. The fourth wafer pad 402D has a cutout 403 to accommodate a part of the fifth wafer pad 410 to facilitate the compactness of the IPM 400.

In the embodiment of the present invention, the plurality of first bonding leads 481 connect the IC 420 to the plurality of leads, or the IC 420 is connected to the first transistor 442, the second transistor 444, and the third transistor. Crystal 446, fourth transistor 452, fifth transistor 454, and sixth transistor 456. In the embodiment of the present invention, the plurality of second bonding leads 491 connect the sources 442S, 444S, 446S, 452S, 454S, and 456S to the plurality of leads. In the embodiment of the present invention, the plurality of first bonding wires 481 are gold bonding wires, which are used for a better wire scribing process. The plurality of second bonding wires 491 are copper bonding wires in order to reduce costs.

In the embodiment of the present invention, the mold package 498 packs the first wafer pad 402A, the second wafer pad 402B, the third wafer pad 402C, the fourth wafer pad 402D, and the first electrical pad. The crystal 442, the second transistor 444, the third transistor 446, the fourth transistor 452, the fifth transistor 454, the sixth transistor 456, the fifth wafer pad 410, and the IC 420. In the embodiment of the present invention, a plurality of lead portions are embedded in the molded package 498.

FIG. 5 is a plan view of the IPM 500 in the embodiment of the present invention. The IPM 500 has a first wafer pad 502A, a second wafer pad 502B, a third wafer pad 502C, a fourth wafer pad 502D, a fifth wafer pad 510, a first transistor 542, A second transistor 544, a third transistor 546, a fourth transistor 552, a fifth transistor 554, a sixth transistor 556, an IC 520, a plurality of leads, and a molded package 598. The first transistor 542 is connected to the first wafer pad 502A. A second transistor 544 is connected to the second wafer pad 502B. A third transistor 546 is connected to the third wafer pad 502C. A fourth transistor 552, a fifth transistor 554, and a sixth transistor 556 are connected to the fourth wafer pad 502D. The IC 520 is connected to the fifth wafer pad 510.

In the embodiment of the present invention, the fifth wafer pad 510 is mechanically and electrically connected to the first ground lead 516A, the second ground lead 516B, and the third ground lead 516C.

In an embodiment of the present invention, the first, second, third, fourth, fifth, and sixth transistors 542, 544, 546, 552, 554, and 556 are metal-oxide-semiconductor field effect transistors (MOSFET). The source electrodes 542S, 544S, 546S, 552S, 554S, and 556S are on the first, second, third, fourth, fifth, and sixth transistors 542, 544, 546, 552, 554, and 556, respectively. In the embodiment of the present invention, the plurality of first bonding leads 581 connect the IC 520 to the plurality of leads, or the IC 520 is connected to the first transistor 542, the second transistor 544, and the third transistor. Crystal 546, fourth transistor 552, fifth transistor 554, and sixth transistor 556. In the embodiment of the present invention, the plurality of second bonding wires 591 connect the sources 542S, 544S, 546S, 552S, 554S, and 556S to the plurality of leads. In the embodiment of the present invention, the plurality of first bonding wires 581 are gold bonding wires for a better wire scribing process. The plurality of second bonding wires 591 are copper bonding wires in order to reduce costs.

In an embodiment of the present invention, the fourth wafer pad 502D is an inverted letter "L" shape. The fourth wafer pad 502D has a cutout 503 to accommodate the wire bonding area 571 of the third wafer pad 502C. The bonding wire connects the source 556S of the sixth transistor 556 to the wire bonding region 571 of the third wafer pad 502C.

In the embodiment of the present invention, the mold package 598 packages the first wafer pad 502A, the second wafer pad 502B, the third wafer pad 502C, the fourth wafer pad 502D, and the first transistor. 542, a second transistor 544, a third transistor 546, a fourth transistor 552, a fifth transistor 554, a sixth transistor 556, a fifth wafer pad 510, and an IC 520. In an embodiment of the present invention, a plurality of lead portions are embedded in the molded package 598.

Those skilled in the art should be aware that there may be modifications to various embodiments. For example, the positions of the plurality of insulated leads and insulated leads may vary. Within the scope of the present invention, those with ordinary knowledge in the technical field may further have various modifications and changes, and the present invention is defined by the scope of the attached application patent.

100, 200, 300, 400, 500: Intelligent power module 101: Printed circuit board 180: Multiple leads 198, 298, 398, 498, 598: Molded package 202A, 302A, 402A, 502A: First die bonding Disks 202B, 302B, 402B, 502B: second wafer pads 202C, 302C, 402C, 502C: third wafer pads 202D, 302D, 402D, 502D: fourth wafer pads 210, 310: tie rods 212, 312, 412: first end 214, 314, 414: second end 216, 316: intermediate extension 216A, 416A: ground lead 217: power lead 219: insulated lead 220, 320, 420: integrated circuit 221, 292D, 288B: leads 242, 342, 442, 542: the first transistor 242S, 244S, 246S, 252S, 254S, 256S, 342S, 344S, 346S, 352S, 354S, 356S, 442S, 444S, 446S, 452S, 454S, 456S, 542S, 544S, 546S, 552S, 554S, 556S: source 244, 344, 444, 544: second transistor 246, 346, 446, 546: third transistor 252, 352, 452, 552: Fourth transistor 254, 354, 454, 554: fifth transistor 256, 356, 456, 556: sixth transistor 281A , 381A: the first connection element 282A, 382A: the first lead 282B: the second selected high-voltage lead 283A, 383A: the second connection element 284A, 384A: the second lead 284B: the first selected High-voltage leads 285A, 385A: third connection element 286, 386A: third lead 287A, 387A: fourth connection element 288A: fourth lead 290: first low-voltage lead 291A: first bonding lead 291B: Second bonding lead 291C: third bonding lead 292A: first insulated lead 292B: second insulated lead 292C: third insulated lead 292E: fourth insulated lead 292F: fifth insulated lead 382B, 384B , 386B, 390, 392A, 392B, 392C: lead 388A: fourth lead 388B: fifth lead 388C: sixth lead 388D: seventh lead 403, 503: cutout 410, 510: fifth wafer bonding Disks 481, 581: a plurality of first bonding leads 491, 591: a plurality of second bonding leads 516A: a first ground lead 516B: a second ground lead 516C: a third ground lead 571: a wire bonding area

FIG. 1 shows a perspective view of an intelligent power module (IPM) in an embodiment of the present invention.

FIG. 2 shows a top view of an IPM (with a molded package outline) in an embodiment of the present invention.

FIG. 3 shows a top view of another IPM (with a molded package outline) in an embodiment of the present invention.

FIG. 4 shows a top view of another IPM (with a molded package outline) in an embodiment of the present invention.

FIG. 5 shows a top view of another IPM (with a molded package outline) in an embodiment of the present invention.

Claims (16)

An intelligent power module for driving a motor includes: first, second, third, and fourth wafer pads; a first transistor is connected to the first wafer pad; a second transistor Connected to the second wafer pad; third transistor is connected to the third wafer pad; fourth, fifth and sixth transistors are connected to the fourth wafer pad; an integrated circuit Located near the second and third wafer pads; the integrated circuit is electrically connected to the first, second, third, fourth, fifth, and sixth transistors; a plurality of leads; and a molding Packaging, packaging first, second, third, and fourth wafer pads, first, second, third, fourth, fifth, and sixth transistors and integrated circuits; wherein a plurality of lead portions are embedded In a molded package. The smart power module according to item 1 of the patent application scope, further comprising a tie rod having a first end, a second end, and an intermediate extension, wherein the intermediate extension of the tie rod is mechanically and electrically connected to the ground lead. According to the smart power module described in the second item of the patent application scope, the first end surface of the first end of the tie rod and the second end surface of the second end are exposed from the edge surface of the molded package. The intelligent power module according to item 2 of the patent application scope, wherein the power lead is between the ground lead and the insulated lead. The smart power module according to item 2 of the patent application scope, wherein at least a part of the top edge of the first wafer pad, the top edges of the second and third wafer pads, and the top of the fourth wafer pad At least a portion of the edges are coplanar; wherein the middle portion of the bottom edge of the tie rod is parallel to the top edges of the second and third wafer pads. The intelligent power module according to item 1 of the scope of patent application, wherein the integrated circuit is electrically connected to the first, second, third, fourth, fifth, and sixth transistors through a plurality of gold bonding wires, The plurality of copper bonding wires electrically and mechanically connect the first, second, third, fourth, fifth, and sixth transistors to a part of the plurality of leads. The intelligent power module according to item 1 of the scope of patent application, wherein the first connection element connects the first chip pad to the first lead of the plurality of leads; the second connection element connects the second chip The pad is connected to the second lead of the plurality of leads; the third connection element connects the third wafer pad to the third lead of the plurality of leads; and the fourth connection element bonds the fourth die The disk is connected to a first four-lead of the plurality of leads. The smart power module according to item 7 of the scope of patent application, wherein the first insulated lead is between the first low-voltage lead and the first lead; the second insulated lead is between the first lead and the second lead Between; and a third insulated lead between the second and third leads. The intelligent power module according to item 8 of the patent application scope, wherein the fourth insulated lead is between the first selected high-voltage lead and the second selected high-voltage lead. The smart power module described in item 9 of the scope of patent application, wherein the first lead is connected to the second selected high-voltage lead through a printed circuit board, and the second lead is connected to the first high-voltage lead through the printed circuit board. On a selected high voltage lead. The smart power module according to item 7 of the scope of patent application, wherein the fifth, sixth and seventh leads of the plurality of leads are directly connected to the fourth connection element. The intelligent power module according to item 1 of the scope of patent application, wherein the first transistor is the first metal-oxide-semiconductor field effect transistor (MOSFET); the second transistor is the second MOSFET; The third transistor is a third MOSFET; the fourth transistor is a fourth MOSFET; the fifth transistor is a fifth MOSFET; and the sixth transistor is a sixth MOSFET. The intelligent power module according to item 12 of the patent application scope, wherein the first bonding wire connects the source of the first MOSFET to the low-voltage wiring; the second bonding wire connects the source of the first MOSFET to The source of the second MOSFET; and a third bond wire connecting the source of the second MSOFET to the source of the third MOSFET. The intelligent power module according to item 1 of the scope of patent application, wherein the plurality of first bonding wires connect the integrated circuit to the plurality of leads, or the integrated circuit is connected to the first, second, third, Fourth, fifth, and sixth transistors; wherein a plurality of second bonding leads connect the sources of the first, second, third, fourth, fifth, and sixth transistors to the plurality of leads Where the plurality of first bonding wires are gold bonding wires; and wherein the plurality of second bonding wires are copper bonding wires. The smart power module according to item 1 of the patent application scope, further comprising a fifth wafer pad, wherein the fourth wafer pad is an inverted letter "L" shape, and wherein the fourth wafer pad is It has a cutout to accommodate a part of the fifth die pad, which is good for the compactness of the smart power module. The intelligent power module described in the first patent application scope, wherein the fourth wafer pad is an inverted letter "L" shape; wherein the fourth wafer pad has a cutout to accommodate the third wafer pad And a bonding wire connecting the source of the sixth transistor to the bonding wire of the third wafer pad.