TWI527199B - Semiconductor device and method of making the same - Google Patents

Description

Semiconductor device and method of fabricating the same

The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a semiconductor device having a semiconductor layer to change a well depth and a method of fabricating the same.

Electrically Erasable Programmable Read Only Memory (hereinafter referred to as EEPROM) is a non-volatile memory that has the advantage of retaining memory contents after being powered off, and can be repeatedly read. The function of entering data. In order to meet the requirements of low power consumption, high writing efficiency, low cost, and high density, as the line width of semiconductor processes shrinks and the degree of integration increases, common electronic products need to have many different functional components at the same time, for example, The EEPROM has components such as MOS transistors and Xiaoji diodes, and each component has its own electrical performance and process requirements.

For example, MOS transistors and other components are constantly moving toward miniaturization. However, when the line width of semiconductor processes has developed to the bottleneck, how to increase the carrier mobility to increase the speed of MOS transistors has become the current field of semiconductor technology. One of the big topics.

The Xiaoji diode element is a diode element composed of a metal and a semiconductor junction, and has a unidirectional conduction characteristic. Since the Schottky diode is a unipolar movement, its starting voltage is lower than that of the PN diode component. For example, when a standard 矽 diode has a forward voltage drop (forward voltage drop) At about 0.6 volts, the Schottky diode has a forward bias of 0.15 to 0.45 volts. Moreover, when the forward bias is switched, the Xiaoji diode component has a faster reaction speed, so it is particularly suitable for reducing the power consumption and increasing the switching speed.

Therefore, how to integrate processes of different semiconductor components such as MOS transistor components and diode components to reduce process time and cost is a problem that the related art desires to improve.

It is an object of the present invention to provide a semiconductor device and a method of fabricating the same that integrates processes of different semiconductor components to reduce process time and save fabrication costs, with a semiconductor layer for adjusting the depth of subsequently formed wells.

A preferred embodiment of the present invention provides a semiconductor device including a semiconductor substrate, a first well having a first conductivity type and disposed in a semiconductor substrate. A first electrode and a second electrode are disposed on the first well, and a heavily doped region having a first conductivity type is disposed in the first well below the second electrode. a semiconductor layer is disposed on the first well and located between the first electrode and the second electrode, and a second well having a second conductivity type is disposed in the first well below the semiconductor layer, the second well is completely The semiconductor layer is covered.

A preferred embodiment of the present invention provides a method of fabricating a semiconductor device, the steps of which are as follows. Providing a semiconductor substrate, wherein the semiconductor substrate has a first region, a The second area and a third area. Next, a first well having a first conductivity type is formed in the semiconductor substrate of the first region and the semiconductor substrate of the second region, respectively. Then, a first well partially covering the second region is formed. Thereafter, a second well having a second conductivity type is formed in the semiconductor substrate of the third region and the first well of the second region, wherein the second well of the second region is located below the semiconductor layer.

The invention provides a semiconductor layer disposed on a semiconductor device and a manufacturing method thereof, and the semiconductor layer can be used as a mask in the ion implantation process to adjust the depth of the subsequently formed well to achieve better insulation effect, and further reduce the edge of the well The effect and the increase of the resistance value due to the increased signal transmission path of the well setting are beneficial to prevent the penetration current caused by the high voltage signal from damaging the semiconductor device to improve the electrical reliability of the semiconductor device. In addition, the present invention also proposes a method of manufacturing a process for integrating different semiconductor elements such as a transistor element and a diode element to reduce process time and save manufacturing costs.

The present invention will be further understood by those of ordinary skill in the art to which the present invention pertains. .

Please refer to Figure 1 and Figure 2. 1 is a schematic view of a semiconductor device in accordance with a preferred embodiment of the present invention. Fig. 2 is a cross-sectional view showing a semiconductor device according to a preferred embodiment of the present invention taken along line A-A' of Fig. 1. As shown in FIGS. 1 and 2 , the semiconductor device 10 is a Schottky diode including a semiconductor substrate 12 , a first well 14 , a first electrode 16 , and a second electrode 18 . a heavily doped region 20, a shallow trench isolation (STI) 21, a semiconductor layer 22, and a second well 24. The semiconductor substrate 12 is, for example, a substrate made of gallium arsenide, a silicon on insulator (SOI) layer, an epitaxial layer, a germanium layer or other semiconductor substrate material. The first well 14 has a first conductivity type and is disposed in the semiconductor substrate 12, and can be formed by performing an ion implantation process with the first conductivity type dopant. The first conductivity type is N-type or P-type. In the present embodiment, the semiconductor substrate 12 is preferably a P-type semiconductor substrate 12, and the first well 14 is preferably an N-type first well 14, but not limit.

The first electrode 16 is disposed on the first well 14 and further includes a Schottky contact 26 disposed between the first electrode 16 and the first well 14. The heavily doped region 20 is disposed in the first well 14 and has a first conductivity type, which can be formed by performing an ion implantation process with the first conductivity type dopant. Wherein, the first well 14 and the heavily doped region 20 have the same conductivity type, but one of the heavily doped regions 20 has a doping concentration substantially greater than a doping concentration of the first well 14. In this embodiment, the heavily doped region 20 is preferably an N-type heavily doped region 20, but is not limited thereto. The second electrode 18 is disposed on the first well 14 , and the heavily doped region 20 is disposed in the first well 14 below the second electrode 18 , and further includes an ohmic contact 28 disposed on the second electrode 18 . Between the heavily doped regions 20. The semiconductor layer 22 can be a polysilicon layer, but not limited thereto, disposed on the first well 14 and between the first electrode 16 and the second electrode 18. The semiconductor layer 22 may also include a sidewall 25, and the material of the sidewall 25 may be selected from high temperature oxide (HTO), tantalum nitride, hafnium oxide or hexachlorodisilane (Si ₂ Cl _{6 ).} ) formed tantalum nitride (HCD-SiN). The second well 24 has a second conductivity type and is disposed in the first well 14 directly below the semiconductor layer 22, and can be formed by performing an ion implantation process with the second conductivity type dopant. The second conductivity type is a P-type or an N-type. In the present embodiment, the second well 24 is preferably a P-type second well 24, but is not limited thereto.

It should be noted that when the semiconductor device 10 further includes a metal telluride layer 23 disposed between the first well 14 and the first electrode 16 / the second electrode 18, the semiconductor layer 22 can be provided during the metal telluride layer process. The effect of self-alignment self-alignment, that is, the germanium substrate of the first well 14 not covered by the semiconductor layer 22 can react with the metal to form the metal telluride layer 23, and thus, the semiconductor layer 22 It can be used to distinguish a region in which the first electrode 16 and the second electrode 18 are predetermined. In short, the semiconductor layer 22 can abut and define the region where the Schottky junction 26 is located and the region where the ohmic junction 28 is located. In addition, in the present embodiment, the semiconductor layer 22 covers the second well 24 in a comprehensive manner as a mask for forming the ion implantation process of the second well 24, and is used to define the area where the second well 24 is located, so that the semiconductor layer The second well 24 below 22 is located between the area where the Xiaoji junction 26 is located and the area where the ohmic junction 28 is located, as shown in Fig. 1, surrounding the Xiaoji junction 26, but not in contact with the Xiaoji junction 26, and The depth d2 of one of the second wells 24 can be adjusted to be smaller than the depth d1 of the first well 14, so that the second well 24 achieves a better insulation effect.

When a forward bias is provided to the semiconductor device 10, the signal will pass from the heavily doped region 20, through the first well 14, to the Schottky junction 26, so that the second well 24 can be set up. The depletion effect formed by the conductivity type different from the first well 14 and the increase of the signal transmission path increase the resistance value, which is advantageous for preventing the punch through current caused by the high voltage signal from being applied to the semiconductor device 10. Damage is caused, and the reverse voltage value of the semiconductor device 10 is further increased and the electrical reliability of the semiconductor device 10 is improved.

Please refer to Figure 3. 3 is a schematic view of a semiconductor device in accordance with another preferred embodiment of the present invention. As shown in FIG. 3, the semiconductor device further includes an insulating layer 30 disposed in the second well 24 as compared with the foregoing embodiment. The material of the insulating layer 30 comprises yttria or a material having a low dielectric constant, for example including at least one shallow trench isolation (STI). Furthermore, one of the depths d3 of the insulating layer 30 is substantially smaller than the depth d2 of the second well. The insulating layer 30 is disposed to further enhance the insulating effect of the second well 24, preferably disposed below the semiconductor layer 22, in contact with the semiconductor layer 22 and surrounded by the second well 24. The depth d3 of the insulating layer 30 is substantially greater than the weight One of the doping regions 20 has a depth d4, but is not limited thereto.

Please refer to Figures 4 to 7. 4 to 7 are schematic views showing a semiconductor process of a preferred embodiment of the present invention. As shown in FIG. 4, first, a semiconductor substrate 40 is provided, and the semiconductor substrate 40 has a first region 41, a second region 42, and a third region 43. The semiconductor substrate 40 is, for example, a substrate composed of a gallium arsenide, a germanium-on-insulator (SOI) layer, an epitaxial layer, a germanium layer, or other semiconductor substrate material. The semiconductor substrate 40 further includes at least one shallow trench isolation 45 between the first region 41, the second region 42, and the third region 43 for separating the regions. The shallow trench isolation 45 typically comprises an insulating material, such as tantalum oxide, and the method of forming shallow trench isolation is well known to those skilled in the art and will not be described herein. The first region 41 and the third region 43 may form two or more semiconductor devices simultaneously or sequentially, such as a P-type MOS transistor, an N-type MOS transistor, or a strain 矽. The structure of the strained-silicon MOS or the like is not limited thereto, and the second region 42 is intended to form the semiconductor device of the present invention, for example, the aforementioned embodiments of the second and third embodiments A semiconductor device process, such as a logic transistor process or a high voltage transistor process, is integrated into the first region 41 and the third region 43 by a schottky diode.

Next, as shown in FIG. 5, an ion implantation process is performed to respectively form a semiconductor substrate 40 having a first well 46 of a first conductivity type in the semiconductor substrate 40 of the first region 41 and a second region 42. in. The first conductivity type is N-type or P-type. In the embodiment, the semiconductor substrate 40 is preferably a P-type semiconductor substrate, and the first well 46 is preferably an N-type first well 46, but is not limited thereto. .

Thereafter, as shown in FIG. 6, a first well 46 in which the semiconductor layer 48 partially covers the second region 42 is formed. The semiconductor layer 48 can be a polysilicon layer, but not limited thereto. The method for forming the semiconductor layer 48 can utilize a lithography process, including the following steps: First, sequentially forming a semiconductor layer (not shown) And a mask layer (not shown) on the semiconductor substrate 40, and then patterning the mask layer, and using an etching process to remove the semiconductor layer not covered by the mask layer to obtain a patterned semiconductor The layer 48, wherein the etching process comprises a dry etching process or a wet etching process, and removes the remaining mask layer, but not limited thereto, may also include other methods of patterning the semiconductor layer.

Next, an ion implantation process is performed to respectively form a second well 50 having a second conductivity type in the semiconductor substrate 40 of the third region 43 and the first well 46 of the second region 42, wherein the second The second well 50 of the region 42 is located below the semiconductor layer 48. It should be noted that the preferred embodiment utilizes the arrangement of the semiconductor layer 48 to change the depth of the ion implantation. Therefore, even if the ion implantation process having the same concentration of the same energy operating conditions is simultaneously performed, the second region 42 is formed. The depth d5 of one of the second wells 50 will be substantially less than the depth d6 of one of the second wells 50 formed simultaneously at the third region 43. The second conductivity type is a P-type or an N-type. In the present embodiment, the second well 50 is preferably a P-type second well 50, but is not limited thereto. The step of patterning the semiconductor layer and the step of forming the second well may also adjust the order of implementation due to process requirements.

As shown in FIG. 7, in the second region 42, the first well 46 not covered by the semiconductor layer 48 defines a Schottky junction region 42a and an ohmic junction region 42b, that is, the semiconductor layer 48 can be The Schottky junction area 42a and the ohmic junction area 42b are adjacent and positioned. A sidewall 49 can be formed on the sidewall of the semiconductor layer 48 and can be formed along with the sidewall process in the first region 41 or the third region 43. The method of forming the sidewall spacer 49 is a conventional technique and will not be described herein. The material of the sidewall 49 may be selected from high temperature oxide (HTO), tantalum nitride, hafnium oxide or tantalum nitride (HCD-SiN) formed using hexachlorodisilane (Si ₂ Cl ₆ ). . Then, a heavily doped region 52 having a first conductivity type is formed in the first well 46 of the ohmic junction region 42b, wherein the doped concentration of one of the heavily doped regions 52 is greater than the first well 46 of the second region 42. One of the doping concentrations, and the heavily doped region 52 can be formed with a semiconductor process within the first region 41 or the third region 43, such as a source/drain. Thereafter, a second electrode 54 is formed on the heavily doped region 52 to form an ohmic junction 56, and a first electrode 58 is formed on the first well 46 of the Schottky junction region 42a to form a Xiaoji. Junction 60. Before forming the first electrode 58 and the second electrode 54, a second metal halide layer 53 may be formed in the second region 42 on the first well 46 not covered by the semiconductor layer 48, in other words, in the metal The semiconductor layer 48 can provide self-aligned alignment when the telluride layer is processed. By the arrangement of the semiconductor layer 48, the second well 50 can be located between the Schottky junction 60 and the ohmic junction 56, surrounding the Xiaoji junction 60, but not in contact with the Xiaoji junction 60, and the second well 50 The depth is less than the depth of the first well 46. To this end, the Schottky diode structure 62 of a semiconductor device is completed in the second region 42. In addition, at least one high voltage transistor 61 of the first region 41 and at least one low voltage transistor 63 of the third region 43 may be disposed in the semiconductor substrate 40 through other conventional processing steps to perform metal telluride. Prior to the layer process, various semiconductor elements such as gates, source/drain electrodes, etc. in the first region 41 or the third region 43 may be formed first.

Please refer to Figure 8. FIG. 8 is a schematic view showing a semiconductor process of another preferred embodiment of the present invention. As shown in FIG. 8, in the present embodiment, before forming the semiconductor layer 48, a region in which an insulating layer 66 is formed in the second region 42 of the semiconductor substrate 40 to form the semiconductor layer 48 may be further included. One of the insulating layers 66 may have a depth that is less than a depth of the second well 50 that is subsequently formed by the second region 42. The material of the insulating layer 66 comprises yttria or a material having a low dielectric constant, for example including at least one shallow trench isolation (STI), and is formed together with shallow trench isolations 45 for separating the regions. The insulating layer 66 is disposed to further enhance the insulating effect of the second well 50, preferably disposed below the semiconductor layer 48, in contact with the semiconductor layer 48 and surrounded by the second well 50. The depth of the insulating layer 66 is substantially greater than the re-doping. One of the zones 52 is deep, but not limited thereto.

Please refer to Figure 9 and Figure 10. 9 and 10 are schematic views showing a semiconductor process of another preferred embodiment of the present invention. As shown in FIG. 9, the difference from the previous embodiment is that the present embodiment further includes defining a fourth region 44 on the semiconductor substrate 40. Next, an ion implantation process is performed to form the first well 46 having the first conductivity type in the semiconductor substrate 40 of the first region 41, the second region 42, and the fourth region 44, respectively. Then, a first well 46 in which the semiconductor layer 48 partially covers the first well 46 and the fourth region 44 of the second region 42 is formed. An ion implantation process is further performed to respectively form the second well 50 having the second conductivity type in the first well 46 of the semiconductor substrate 40 of the third region 43, the second region 42 and the fourth region 44, wherein The second well 50 of the second region 42 and the fourth region 44 is located directly below the semiconductor layer 48, that is, the implanted ions can be directly applied to the semiconductor substrate as compared to the third region 43 having no semiconductor layer 48. 40. In the second region 42 and the fourth region 44, the implanted ions need to pass through the semiconductor layer 48 to reach the first well 46. Therefore, the second region 42 and the second well 50 of the fourth region 44 have a depth d5. /d7 will be substantially smaller than the depth d6 of the second well 50 of the third region 43.

Thereafter, as shown in FIG. 10, as described in the previous embodiment, the high voltage transistor 61 on the first region 41, the Schottky diode structure 62 on the second region 42, and the third region 43 are completed. The low piezoelectric crystal 63, and further includes forming another semiconductor device, such as a bipolar junction transistor (BJT), on the fourth region 44. The method of forming a semiconductor device of the fourth region 44 includes removing the semiconductor layer 48 at the fourth region 44, forming a first doped region 68 in the first well 46 of the fourth region 44, and forming a second blend, respectively. The impurity region 70 and a third doping region 72 are in the second well 50 of the fourth region 44, and then a first electrode 74 is formed on the first doping region 68 to form a collector to form a second The electrode 76 is formed on the second doping region 70 to form a base, and a third electrode 78 is formed on the third doping region 72 to form an emitter, but is not limited thereto. To this end, a bipolar junction transistor (BJT) structure 64 of a semiconductor device is completed.

In summary, the present invention provides a semiconductor layer disposed on a semiconductor device and a method of fabricating the same, and the semiconductor layer can be used as a mask in an ion implantation process to adjust the depth of the subsequently formed well to achieve better insulation effect, and further The effect of increasing the resistance value due to the depletion effect at the edge of the well and the signal transmission path increased by the arrangement of the well is beneficial to prevent the penetration current caused by the high voltage signal from causing damage to the semiconductor device, thereby improving the electrical reliability of the semiconductor device. In addition, the present invention also proposes a method of manufacturing a process for integrating different semiconductor elements such as a transistor element and a diode element, for example, integrating the Schottky diode of the foregoing embodiment and a bipolar junction transistor into an electron simultaneously. Erasable rewritable read-only memory (EEPROM) to reduce process time and save production costs.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10. . . Semiconductor device

12. . . Semiconductor substrate

14. . . First well

16. . . First electrode

18. . . Second electrode

20. . . Heavily doped region

twenty two. . . Semiconductor layer

twenty three. . . Metal telluride layer

twenty four. . . Second well

25. . . Side wall

26. . . Xiao Ji junction

28. . . Ohmic junction

30. . . Insulation

40. . . Semiconductor substrate

41. . . First area

42. . . Second area

42a. . . Xiaoji junction area

42b. . . Ohmic junction area

43. . . Third area

44. . . Fourth area

45. . . Shallow trench isolation

46. . . First well

48. . . Semiconductor layer

49. . . Side wall

50. . . Second well

52. . . Heavily doped region

53. . . Metal telluride layer

54. . . Second electrode

56. . . Ohmic junction

58. . . First electrode

60. . . Xiao Ji junction

61. . . High voltage crystal

62. . . Xiaoji diode structure

63. . . Low voltage crystal

64. . . Bipolar junction crystal structure

66. . . Insulation

68. . . First doped region

70. . . Second doped region

72. . . Third doped region

74. . . First electrode

76. . . Second electrode

78. . . Third electrode

D1, d2, d3, d4, d5, d6, d7. . . depth

1 is a schematic view of a semiconductor device in accordance with a preferred embodiment of the present invention.

Fig. 2 is a cross-sectional view showing a semiconductor device according to a preferred embodiment of the present invention taken along line A-A' of Fig. 1.

3 is a schematic view of a semiconductor device in accordance with another preferred embodiment of the present invention.

4 to 7 are schematic views showing a semiconductor process of a preferred embodiment of the present invention.

FIG. 8 is a schematic view showing a semiconductor process of another preferred embodiment of the present invention.

9 to 10 are schematic views showing a semiconductor process of another preferred embodiment of the present invention.

40. . . Semiconductor substrate

41. . . First area

42. . . Second area

42a. . . Xiaoji junction area

42b. . . Ohmic junction area

43. . . Third area

45. . . Shallow trench isolation

46. . . First well

48. . . Semiconductor layer

49. . . Side wall

50. . . Second well

52. . . Heavily doped region

53. . . Metal telluride layer

54. . . Second electrode

56. . . Ohmic junction

58. . . First electrode

60. . . Xiao Ji junction

61. . . High voltage crystal

62. . . Xiaoji diode structure

63. . . Low voltage crystal

Claims (20)

A semiconductor device comprising: a semiconductor substrate; a first well having a first conductivity type disposed in the semiconductor substrate; a first electrode disposed on the first well; and a second electrode disposed on the a first well; a semiconductor layer disposed on the first well between the first electrode and the second electrode; a second well having a second conductivity type disposed under the semiconductor layer In the first well, the second well is completely covered by the semiconductor layer; and a heavily doped region having the first conductivity type and disposed in the first well below the second electrode. The semiconductor device of claim 1, wherein the first conductivity type is N-type or P-type, the second conductivity type is P-type or N-type, and the first conductivity type is different from the second conductivity type . The semiconductor device of claim 1, further comprising a Schottky contact disposed between the first electrode and the first well. The semiconductor device of claim 1, further comprising an ohmic contact disposed between the second electrode and the heavily doped region. The semiconductor device of claim 1, wherein the semiconductor layer comprises a polysilicon layer. The semiconductor device of claim 1, wherein an insulating layer is further disposed in the second well. The semiconductor device of claim 6, wherein the material of the insulating layer comprises yttria or a material having a low dielectric constant. The semiconductor device of claim 6, wherein the insulating layer comprises at least one shallow trench isolation (STI). A method of fabricating a semiconductor device, comprising: providing a semiconductor substrate, wherein the semiconductor substrate has a first region, a second region, and a third region; performing a first ion implantation process to form a first a first well of a conductivity type in the semiconductor substrate of the first region and the semiconductor substrate of the second region; forming a first layer of a semiconductor layer partially covering the second region; and performing a second ion cloth Forming a second well having a second conductivity type in the semiconductor substrate of the third region and in the first well of the second region, wherein the second well of the second region is located in the semiconductor Below the layer. The method of fabricating a semiconductor device according to claim 9, wherein the first conductivity type is N-type or P-type, the second conductivity type is P-type or N-type, and the first conductivity type and the second conductivity type Different conductivity types. The method of fabricating a semiconductor device according to claim 9, wherein the semiconductor layer comprises a polysilicon layer. The method of fabricating a semiconductor device according to claim 9, further comprising: defining a Schottky junction region and an ohmic junction region in the second region; forming a heavily doped region having the first conductivity type In the semiconductor substrate of the ohmic junction region; forming a second electrode on the heavily doped region to form an ohmic junction; and forming a first electrode on the first well of the Schottky junction region, To form a Xiaoji junction. The method of fabricating a semiconductor device according to claim 12, wherein a doping concentration of one of the heavily doped regions in the second region is greater than a doping concentration of the first well in the second region. The method of fabricating a semiconductor device according to claim 12, wherein before forming the first electrode and the second electrode, further comprising forming a metal telluride layer in the second region without being covered by the semiconductor layer On a semiconductor substrate. The method of fabricating a semiconductor device according to claim 9, further comprising forming an insulating layer disposed in the second well of the second region. The method of fabricating a semiconductor device according to claim 15, wherein the material of the insulating layer comprises yttria or a material having a low dielectric constant. The method of fabricating a semiconductor device according to claim 16, wherein the insulating layer comprises at least one shallow trench isolation (STI). The method of fabricating a semiconductor device according to claim 9, wherein the first region comprises at least one high voltage transistor and the third region comprises at least one low voltage transistor disposed in the semiconductor substrate. The method of fabricating a semiconductor device according to claim 9, further comprising: defining a fourth region on the semiconductor substrate; performing the first ion implantation process while forming a first well having the first conductivity type In the semiconductor substrate of the fourth region; forming the first well partially covering the fourth region; performing the second ion implantation process, and simultaneously forming a second well having the second conductivity type In the first well of the fourth region, wherein the second well of the fourth region is located below the semiconductor layer; removing the semiconductor layer located in the fourth region; Forming a first doped region in the first well of the fourth region; and forming a second doped region and a third doped region in the second well of the fourth region. The method of fabricating a semiconductor device according to claim 19, further comprising: forming a first electrode on the first doped region to form a collector; forming a second electrode on the second doped region Forming a base; and forming a third electrode on the third doped region to form an emitter.