TWI507777B - Display panel and method of manufacturing same - Google Patents

Description

Display panel and method of manufacturing same

The present invention relates to a display panel and a method of fabricating the same, and more particularly to a display panel and a method of fabricating the same that solves the problem of the sealant curing of a high-resolution ultra-thin bezel product.

With the advancement of display technology, people can make life more convenient by the aid of the display. In order to make the display light and thin, the flat panel display (FPD) has become the mainstream. Among many flat panel displays, liquid crystal displays (LCDs) have superior characteristics such as high space utilization efficiency, low power consumption, no radiation, and low electromagnetic interference. Therefore, liquid crystal displays are popular among consumers.

The liquid crystal display panel is mainly composed of two substrates and a liquid crystal layer, and usually the two substrates are adhered together by a seal and the liquid crystal is prevented from flowing out. In recent years, in order to reduce the area of the peripheral lines, the liquid crystal display panel has a tendency to gradually design toward an ultra-slim border (USD). However, the narrower the frame area, the more the layout space of the sealant coating is compressed, so the above design is produced at the time of production. One of the bottlenecks encountered is the sealant coating process. Since the frame coating can be made smaller and smaller, the easier it is to overlap the metal wires below. If the sealant overlaps with the metal wire underneath, the metal wire will shield the ultraviolet light in the subsequent illumination process, so that the sealant at the overlap is not sufficiently irradiated with ultraviolet light. As a result, the sealant will be incompletely cured, causing some of the sealant solvent to enter the display area, resulting in a mura defect in the display area.

The invention provides a display panel and a manufacturing method thereof, which can solve the problem of the sealant curing of the high-pixel ultra-thin frame product.

The invention provides a display panel and a manufacturing method thereof, which can increase the light transmission gap of the auxiliary circuit, so that the sealant above it is completely cured.

The invention provides a display panel comprising an array substrate and a sealant. The array substrate has a display area and a non-display area. The non-display area has a sealant area. The sealant is located in the sealant area. The array substrate includes: a pixel array and an auxiliary circuit. The pixel array is located in the display area. The auxiliary circuit is located in the non-display area. The auxiliary circuit at least partially overlaps the sealant. The auxiliary circuit includes a plurality of component groups. Each of the component groups includes a first source line, a second source line, a drain line, a plurality of gates, a plurality of source groups, and a plurality of drain electrodes. The first source line and the second source line are electrically connected to the pixel array. The plurality of gates are electrically connected to a gate voltage in common. Having sufficient light-transmissive gaps between adjacent gates allows the sealant material on the auxiliary circuit to fully cure. Each source group is overlapped with one of the gates. Each source group includes a first source and a second source. The first source in the source group is electrically connected to the first source line. The second source in the source group is electrically connected to the second source line. One of the light-transmissive spaces is located between two adjacent source groups. Multiple drains are electrically connected to the drain line. Each of the drains is disposed between the first source and the second source of one of the source groups.

The present invention provides a method of manufacturing a display panel, the steps of which are as follows. Step (a) provides an array substrate having a display area and a non-display area. The non-display area has a sealant area. The array substrate includes: a pixel array and an auxiliary circuit. The pixel array is located in the display area. The auxiliary circuit is located in the non-display area. The auxiliary circuit includes a plurality of component groups. Each of the component groups includes a first source line, a second source line, a drain line, a plurality of gates, a plurality of source groups, and a plurality of drain electrodes. The first source line and the second source line are electrically connected to the pixel array. The plurality of gates are electrically connected to a gate voltage in common. There are light-transmissive gaps between adjacent gates. Each source group is overlapped with one of the gates. Each source group includes a first source and a second source. The first source in the source group is electrically connected to the first source line. The second source in the source group is electrically connected to the second source line. One of the light-transmissive spaces is located between two adjacent source groups. Multiple drains are electrically connected to the drain line. Each of the drains is disposed between the first source and the second source of one of the source groups. Step (b) provides a sealant material on the array substrate. The frame glue material corresponds to the sealant area, wherein the auxiliary circuit and the frame glue material at least partially overlap. Step (c) is a step of illuminating the above-mentioned sealant material. The light of the illuminating step passes through the light-transmissive gap between the gates of each component group of the auxiliary circuit to cure the sealant material.

Based on the above, the present invention provides an array substrate that can increase auxiliary power A light-transmissive gap between the gates of each component group of the road. When the illumination step is performed, the light-transmissive void overlaps with the sealant material, and the sealant material can be sufficiently irradiated with light (for example, ultraviolet light) via the light-transmissive void. Since the sealant material is sufficiently irradiated with light to meet the Seal Curing Rule, the sealant material is completely cured. In this way, it is possible to reduce the problem that the part of the sealant solvent enters the display area due to incomplete curing of the sealant, thereby causing moiré defects.

The above described features and advantages of the invention will be apparent from the following description.

10‧‧‧ display panel

100‧‧‧Array substrate

100a‧‧‧ opposite substrate

101‧‧‧ Display media

102‧‧‧ display area

104‧‧‧Non-display area

106‧‧‧Blocking area

108‧‧‧ pixel array

110‧‧‧Box glue

110’‧‧‧Frame material

112‧‧‧Auxiliary circuit

114, 115‧‧‧ components

116, 117, 118, 119‧‧‧ source line

120, 121‧‧‧汲polar line

122, 124‧‧ ‧ gate

126a, 126b, 128a, 128b‧‧‧ source

130a, 130b, 132a, 132b‧‧‧ bungee

134a, 134b, 136a, 136b‧‧‧ channel layer

150‧‧‧Photomask

160‧‧‧Lighting steps

200‧‧‧Source Drive Module

202‧‧‧Scan Control Module

C‧‧‧ Section

D1, D2‧‧‧ distance

DL1-DL5‧‧‧ data line

G1, G2‧‧‧ light transmission gap

P‧‧‧ pixel structure

PE‧‧‧ pixel electrode

S1-S4‧‧‧Switching elements

S502-S510‧‧‧Manufacturing Process

SL1-SL5‧‧‧ scan line

T‧‧‧ active components

Vcom‧‧‧ common electrode

Vg‧‧‧ control signal, gate voltage

W1-W4‧‧‧ gate wire

Wg‧‧‧Width

1A is a cross-sectional view of a display panel in accordance with an embodiment of the present invention.

FIG. 1B is a top view of the array substrate of FIG. 1A.

2 is an enlarged schematic view showing a portion C of the auxiliary circuit of FIG. 1B.

3A-3B are schematic cross-sectional views showing a method of fabricating a display panel in accordance with an embodiment of the present invention.

4A-4B are top plan views of the array substrate in accordance with FIGS. 3A-3B, respectively.

FIG. 5 is a flow chart showing a method of manufacturing a display panel according to an embodiment of the invention.

1A is a cross-sectional view of a display panel in accordance with an embodiment of the present invention. FIG. 1B is a top view of the array substrate of FIG. 1A. Referring to FIG. 1A and FIG. 1B simultaneously, the display panel 10 of the embodiment of the present invention includes an array substrate 100, a sealant 110, a display medium 101, and a counter substrate 100a.

The array substrate 100 has a display area 102 and a non-display area 104 (as shown in FIG. 1B). The non-display area 104 is located around the display area 102 and substantially surrounds the display area 102. The non-display area 104 has a sealant area 106. Therefore, the sealant area 106 is also located around the display area 102 and does not overlap the display area 102. In other words, the sealant region 106 surrounds the display area 102 and is spaced a distance from the display area 102.

Referring to FIG. 1B , the array substrate 100 includes a pixel array 108 , an auxiliary circuit 112 , a source driving module 200 , and a scan control module 202 . The source driving module 200 is disposed on the lower side of the array substrate 100. Those of ordinary skill in the art will appreciate that the so-called lower side is used merely to express relative positional relationships. Therefore, in practical applications, regardless of whether the source driving module 200 is located on either side of the array substrate 100, the main spirit of the present invention is not affected. The scan control module 202 is disposed on one side of the array substrate 100. However, the present invention is not limited thereto. According to other embodiments, the scan control module 202 may also be disposed on both sides of the array substrate 100. The detailed design of the source drive module 200 and the scan control module 202 is well known to those of ordinary skill in the art and will not be repeated here. The pixel array 108 is located in the display area 102. The pixel array 108 includes a plurality of scan lines SL1-SL5, a plurality of data lines DL1-DL5, and a plurality of pixel structures electrically connected to the scan lines SL1-SL5 and the data lines DL1-DL5. P. For convenience of description, FIG. 1B shows only five scan lines SL1-SL5 and five data lines DL1-DL5, but it should be understood by those of ordinary skill in the art that the scan lines and data lines are actually composed of multiple scan lines. And a number of data lines. The scan lines SL1-SL5 and the data lines DL1-DL5 are alternately arranged with each other. In other words, the extending direction of the scanning lines SL1-SL5 is different from the extending direction of the data lines DL1-DL5. In an embodiment, the extending direction of the scan lines SL1-SL5 is substantially perpendicular to the extending direction of the data lines DL1-DL5. Based on the conductivity considerations, the scan lines SL1-SL5 and the data lines DL1-DL5 are generally made of a metal material. However, the present invention is not limited thereto, and according to other embodiments, other conductive materials may be used for the scan lines SL1-SL5 and the data lines DL1-DL5. For example: alloys, nitrides of metallic materials, oxides of metallic materials, oxynitrides of metallic materials, or other suitable materials, or stacked layers of metallic materials and other electrically conductive materials.

In addition, the pixel structure P includes an active element T and a pixel electrode PE. The active device T can be a bottom gate type thin film transistor or a top gate type thin film transistor including a gate, a channel, a source, and a drain. The active device T is electrically connected to a corresponding one of the scan lines (for example, one of the scan lines SL1 to SL5) and a corresponding one of the data lines (for example, one of the data lines DL1 - DL5). In addition, the active device T is electrically connected to the pixel electrode PE. In an embodiment, the pixel electrode PE may be, for example, a transmissive pixel electrode, a reflective pixel electrode, or a transflective pixel electrode. The material of the transmissive pixel electrode comprises a metal oxide such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium antimony zinc oxide, or other suitable oxide, or a stacked layer of at least two of the above. Reflective pixel electrode The material includes a metal material having high reflectivity.

The sealant 110 is located in the sealant region 106. In an embodiment, the material of the sealant 110 may comprise a photocurable material. The photocurable material may be, for example, a UV curable adhesive or a visible light curable adhesive.

Referring to FIG. 1A, the opposite substrate 100a is placed on the array substrate 100. The opposite substrate 100a is disposed on the opposite side of the array substrate 100 such that the sealant 110 is located between the array substrate 100 and the opposite substrate 100a. In addition, the display medium 101 is located between the array substrate 100 and the opposite substrate 100a and is located in the display area 102. In an embodiment, the display medium 101 may include liquid crystal molecules, an electrophoretic display medium, or other applicable medium, but the invention is not limited thereto.

The auxiliary circuit 112 is located in the non-display area 104. The auxiliary circuit 112 at least partially overlaps the sealant 110. In an embodiment, the auxiliary circuit 112 is located on the upper side of the array substrate 100. However, the present invention is not limited thereto, and according to other embodiments, the auxiliary circuit 112 may be located on either side of the array substrate 100. 2 is an enlarged schematic view of a portion C of the auxiliary circuit 112 of FIG. 1B. Referring to FIG. 2, the auxiliary circuit 112 includes a plurality of component groups 114, 115. The component group 114 includes a first source line 116, a second source line 118, a drain line 120, a plurality of gates 122, 124, a plurality of source groups 126, 128, a plurality of drain groups 130, 132, and The channel layer groups 134, 136, the source line, the drain line, the gate, the source group and the drain group in the component group are exemplified by a metal, an alloy, a nitride of a metal material, an oxide of a metal material, Nitrogen oxides of metallic materials, or other suitable materials, or a stacked layer of metallic materials and other electrically conductive materials. For convenience of description, FIG. 2 only shows two component groups 114, 115, but the corresponding It should be understood by those of ordinary skill in the art that the auxiliary circuit 112 is actually an array of a plurality of component groups.

Referring to FIG. 1B and FIG. 2 , the first source line 116 and the second source line 118 are electrically connected to the pixel array 108 . Specifically, the first source line 116 of the component group 114 is electrically connected to the data line DL1, and the second source line 118 is electrically connected to the data line DL2. Similarly, the first source line 117 of the component group 115 is electrically connected to the data line DL3, and the second source line 119 is electrically connected to the data line DL4. On the other hand, the other end of the data lines DL1-DL5 is electrically connected to the source driving module 200 (as shown in FIG. 1B). The drain line 120 of the element group 114 is disposed between the first source line 116 and the second source line 118, and the drain line 121 of the element group 115 is disposed on the first source line 117 and the second source line 119. between. The auxiliary circuit 112 in this embodiment is exemplified by a discharge circuit, but the invention is not limited thereto, and a detailed description about the discharge circuit is as follows. The drain lines 120 and 121 are electrically connected to a common voltage source (not shown) to sequentially transmit the pixel voltage in the display area 102 through the data lines DL1 - DL5 and the auxiliary circuit 112 to release the display. The residual pinch pressure between the pixel electrode PE or/and the common electrode (not shown) in the region 102. The gates 122 and 124 of the component group 114 are electrically connected to the gate voltage source (not shown) through the gate wires W1 and W2, respectively, to transmit the gate voltage Vg, and the gate wires W1, W2, W3, and W4. Each is electrically connected to a gate voltage source.

In the present embodiment, the component groups 114, 115 of the auxiliary circuit 112 are composed of a plurality of switching elements S1-S4, but the present invention is not limited thereto. According to other embodiments, the auxiliary circuit may further include other components or more switches. element. For example, the switch The element S1 is electrically connected to the first source line 116, the drain line 120, and the gate line W4. Similarly, the switching element S2 is electrically connected to the first source line 118, the drain line 120, and the gate line W4. Other switching elements are similar configurations and will not be described again here. In the present embodiment, the above-described switching elements S1-S4 can be realized by a bottom gate type thin film transistor. Of course, in other embodiments, the above-described switching elements S1-S4 can also be implemented by a top gate type thin film transistor, and the present invention is not limited thereto.

When the array substrate 100 is normally turned on and the power is turned on, the gate voltage Vg is at a first level, for example, a low potential. At this time, the switching elements S1 - S4 in the auxiliary circuit 112 are not turned on. In contrast, in this embodiment, if it is detected that the array substrate 100 is turned off by the power source, the potential of the gate voltage Vg is switched to the second level, for example, a high potential. At this time, all of the switching elements S1-S4 in the auxiliary circuit 112 are turned on, so that the data lines DL1-DL4 are all coupled to a preset voltage, for example, the common voltage Vcom. At this time, the residual charge in each pixel can be released through the corresponding data line and the auxiliary circuit 112. In this way, the charge remaining in each pixel can be effectively removed in the state of being turned off to avoid flickering of the display panel.

With continued reference to FIG. 2, the gate 122 in the component group 114 overlaps a portion of the first source line 116 and a portion of the second source line 118. The adjacent gate 122 and the gate 124 have a light-transmissive gap G1, and the sealant 110 overlaps with the light-transmissive gap G1 (as shown in FIG. 1B). In detail, the gate 122 in the component group 114 of the auxiliary circuit 112 has a first shortest distance D1 between the gate 124 and the gate 124. The component group 114 and the adjacent component group 115 have a second shortest distance D2, wherein the first shortest distance D1 is greater than the first The shortest distance D2. For example, the first shortest distance D1 may be greater than the width Wg of the Y-direction of one of the gates 122 such that the ratio of the plurality of light-shielding regions Wg to the plurality of light-transmissive voids G1 is at least 1:1. In an embodiment, the first shortest distance D1 is, for example, greater than 23 micrometers (μm). On the other hand, the second shortest distance D2 depends on the distance between adjacent element groups 114, 115 and adjacent source lines 117, 118, which is affected by the resolution of the associated display panel. In the present embodiment (for example, 403 ppi), the distance between the adjacent source lines 117, 118 corresponding to the adjacent element groups 114, 115 is 21 μm, and after subtracting the width of the other members, the second shortest distance D2 is about 6 μm. Therefore, the second shortest distance D2 is, for example, less than 6 μm. However, the present invention is not limited thereto. On a higher resolution display panel, the distance between adjacent source lines 117, 118 of adjacent component groups 114, 115 may be smaller, and even the second shortest distance D2 is, for example, 0 μm, however, the size of the second shortest distance D2 does not substantially affect the curing result of the sealant. The adjacent gate 122 and the gate 124 have a light-transmissive gap G1, and the light-transmissive gap G1 is divided into two by the drain line 120. The component group 114 and the adjacent component group 115 have a light-transmissive gap G2, and the light-transmitting gap G2 is separated by the gate wires W1-W4. When the illumination step is performed, since the sufficient light-transmissive gaps G1, G2 overlap with the sealant material, the sealant material covering the auxiliary circuit 112 can be sufficiently irradiated to the light via the light-transmissive gaps G1, G2 (for example, UV light) and fully cured. In this way, the problem of incomplete curing of the sealant due to the shielding of the light by the metal wires can be solved in the prior art.

The source group 126 is disposed to overlap the gate 122. In particular, source set 126 includes a first source 126a and a second source 126b. The first source 126a and the second source 126b partially cover the gate 122. The first source 126a is electrically connected to the first source line 116 Sexual connection. The second source 126b is electrically connected to the second source line 118. The drain electrodes 130a, 130b are electrically connected to the drain line 120. The drain electrodes 130a and 130b are disposed between the first source 126a and the second source 126b of the source group 126.

The channel layer group 134 includes a first channel layer 134a and a second channel layer 134b that are separated from each other. The first channel layer 134a is located between the gate 122 and the first source 126a and the drain 130a, and the second channel layer 134b is located between the gate 122 and the second source 126b and the drain 130b. In other words, the first channel layer 134a overlaps the first source 126a, the drain 130a, and the partial gate 122. Therefore, the first channel layer 134a is electrically connected to the first source 126a and the drain 130a. Similarly, the second channel layer 134b overlaps the second source 126b, the drain 130b, and the portion of the gate 122, and the second channel layer 134b is electrically connected to the second source 126b and the drain 130b. However, the first channel layer 134a and the second channel layer 134b do not overlap with the drain line 120 as an example. In an embodiment, the material of the first channel layer 134a, 134b may be, for example, a semiconductor material. The semiconductor material may be a single layer or a multilayer structure including amorphous germanium, polycrystalline germanium, microcrystalline germanium, single crystal germanium, organic semiconductor material, oxide semiconductor material (eg, indium zinc oxide, indium antimony zinc oxide, or Other suitable materials, or combinations thereof, or other suitable materials, or dopants (Dopant) in the above materials, or combinations thereof.

It is to be noted that the first source 126a and the second source 126b of the source group 126 can be, for example, a curved pattern, and the first source 126a and the second source 126b are opposite to the drain line 120. Mirror symmetry. However, the present invention is not limited thereto. According to other embodiments, the channel length of the first channel layer 134a between the first source 126a and the drain 130a and the second channel layer 134b between the second source 126b and the drain 130b. Pass The track length can be adjusted according to design requirements. The pattern of the first source 126a and the second source 126b of the present invention can be, for example, any pattern. In one embodiment, the ratio of the sum of the channel lengths of the channel layer groups between the first source or the second source and the corresponding drain to its width is a suitable ratio of the discharge elements. Specifically, the sum of the channel lengths refers to the channel length of the first channel layer 134a between the first source 126a of the component group 114 and the corresponding drain 130a plus the first source 128a of the component group 114. The channel length of the channel layer 136a between the corresponding drain electrodes 132a. Similarly, the sum of the channel lengths of the channel layer groups 134b, 136b between the second source electrodes 126b, 128b and the corresponding drain electrodes 130b, 132b can also be obtained by the above calculation. For convenience of description, FIG. 2 only shows eight source groups, drain electrodes, and channel layer groups. However, those of ordinary skill in the art should understand that the source group, the bungee, and the channel layer group are actually composed of multiple The source group, the plurality of drain electrodes, and the plurality of channel layer groups are formed depending on their needs, but the present invention is not limited thereto.

The embodiment of the invention utilizes a plurality of light-transmissive gaps between adjacent gates in the auxiliary circuit, which completely cures the sealant overlapping the auxiliary circuit, thereby solving the problem of moiré defects in the display area. In addition, although the plurality of light-transmissive voids of the embodiment of the present invention increase the length of the auxiliary circuit in the Y direction, the light-transmissive voids may cause the sealant material overlapping the auxiliary circuit to sufficiently illuminate the light to conform to the sealant curing rule. . Therefore, even if an alignment error occurs in the curing process of the sealant region, and the opaque region of the subsequent mask 150 (FIG. 3B) and the metal line in the auxiliary circuit 112 overlaps, the frame material can be cured. Completely to reduce the problem of moiré defects in the display area.

3A-3B are schematic cross-sectional views showing a method of fabricating a display panel in accordance with an embodiment of the present invention. 4A-4B are top plan views of the array substrate in accordance with FIGS. 3A-3B, respectively. FIG. 5 is a flow chart showing a method of manufacturing a display panel according to an embodiment of the invention.

Referring to FIG. 3A, FIG. 3B, FIG. 4A, FIG. 4B and FIG. 5, an embodiment of the present invention provides a method for manufacturing a display panel, the steps of which are as follows. First, the array substrate 100 is provided. The structure and material of the array substrate 100 are as shown in FIG. 1B (step S502), and thus will not be described again.

Next, in step S504, a sealant material 110' is formed in the sealant region 106 of the non-display area 104. The sealant material 110' corresponds to the sealant region 106, and the auxiliary circuit 112 at least partially overlaps the sealant material 110' (as shown in Figures 3A and 4A). In an embodiment, the sealant material 110' can comprise a photocurable material. The photocurable material may be, for example, a UV curable adhesive or a visible light curable adhesive. The method of forming the sealant material 110' may be, for example, screen printing, dispensing, gravure printing, ink jet printing, offset printing, embossing, or other coating methods.

Then, in step S506, the opposite substrate 100a is provided on the array substrate 100. The display medium 101 is provided between the array substrate 100 and the opposite substrate 100a. In an embodiment, the display medium 101 may include liquid crystal molecules, an electrophoretic display medium, or other applicable medium, but the invention is not limited thereto. The opposite substrate 100a is disposed on the opposite side of the array substrate 100 such that the sealant material 110' is located between the array substrate 100 and the opposite substrate 100a. As a result, as shown in FIG. 3A, the display medium 101 is sealed to the array substrate 100, the sealant material 110', and the opposite substrate. Between 100a.

Thereafter, step S508 is performed. As shown in FIG. 3B and FIG. 4B, the reticle 150 is disposed on the array substrate 100 and the counter substrate 100a. Specifically, the array substrate 100 is located between the counter substrate 100 and the reticle 150. The mask 150 shields the display area 102 and may even shield a portion of the non-display area 104 to expose the seal area 106 (as shown in FIG. 4B). In this embodiment, the reticle 150 covers the partial scanning control module 202, but the present invention is not limited thereto. According to other embodiments, the reticle 150 may partially cover or not cover the source driving module 200 and the scanning control module. 202. The material of the photomask 150 may be, for example, a metal, a carbon, a photoresist type material, or an oxynitride or the like, which may be formed by a vacuum sputtering method or a chemical vapor deposition method.

Next, in step S510, the masking material 110' is irradiated to the masking material 110' by the photomask 150 (as shown in Fig. 3B). The light from step illuminating step 160 passes through the light transmissive gap between the gates of each of the component groups of auxiliary circuit 112 to cure the sealant material 110'. Since there is sufficient light-transmissive gap between adjacent gates, the sealant material 110' overlying the auxiliary circuit 112 can be fully cured.

In summary, the present invention forms a plurality of light-transmissive gaps between adjacent gates of the auxiliary circuit. When the illumination step is performed, the light-transmissive voids may cause the sealant material overlapping the auxiliary circuit to sufficiently illuminate the light (which may be, for example, ultraviolet light). Since the sealant material is sufficiently irradiated to the light, the sealant material is completely cured, so that the curing of the sealant material is incomplete, so that the solvent of the part of the sealant material enters the display area, thereby causing the problem of moiré defects. In addition, the sum of the channel lengths of the channel layer groups between the plurality of source groups and the corresponding drains of each component group of the embodiment of the present invention The ratio to its width is not changed by being separated by a plurality of light-transmissive voids. Therefore, although the plurality of light-transmissive voids increase the length of the auxiliary circuit, the above-mentioned light-transmissive voids allow the sealant material overlapping the auxiliary circuit to sufficiently illuminate the light to conform to the sealant curing rule. Therefore, even if an alignment error occurs in the curing process of the sealant region, and the opaque region overlapping the metal line in the reticle and the auxiliary circuit is enlarged, the frame material can be completely cured to reduce the moiré of the display area. The problem of defects.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧Array substrate

102‧‧‧ display area

104‧‧‧Non-display area

106‧‧‧Blocking area

108‧‧‧ pixel array

110‧‧‧Box glue

112‧‧‧Auxiliary circuit

200‧‧‧Source Drive Module

202‧‧‧Scan Control Module

C‧‧‧ Section

DL1-DL5‧‧‧ data line

P‧‧‧ pixel structure

PE‧‧‧ pixel electrode

SL1-SL5‧‧‧ scan line

T‧‧‧ active components

Claims (10)

A display panel includes an array substrate and a sealant. The array substrate includes a display area and a non-display area. The non-display area has a sealant area. The sealant is located in the sealant area, wherein the array substrate comprises a pixel array located in the display area; and an auxiliary circuit located in the non-display area, and the auxiliary circuit at least partially overlapping the sealant, wherein the auxiliary circuit includes a plurality of component groups, each component group including a first source line, a second source line, and a drain line, the first source line and the second source line are electrically connected to the pixel array; and the plurality of gates are electrically connected Connected to a gate voltage, wherein adjacent gates have a light-transmissive gap, the sealant overlaps the light-transmissive gap; a plurality of source groups, each source group overlapping one of the gates The first source and the second source are electrically connected, and the first source in the source group is electrically connected to the first source line, and the first of the source groups The two sources are electrically connected to the second source line, wherein the light is empty One portion is located between two adjacent source groups; and a plurality of drains are electrically connected to the drain line, and each of the drains corresponds to the first source disposed in one of the source groups and the Between the second source. The display panel of claim 1, wherein the first source and the second source in each source group of each component group of the auxiliary circuit are in an arc pattern. The display panel of claim 2, wherein each of the source groups The first source and the second source are mirror symmetrical. The display panel of claim 1, wherein the pixel array comprises a plurality of scan lines, a plurality of data lines, and a plurality of pixel structures electrically connected to the scan lines and the data lines, each The first source line and the second source line of the auxiliary circuit are electrically connected to two adjacent data lines, respectively. The display panel of claim 1, wherein the drain line of each component group of the auxiliary circuit is electrically connected to a common voltage source. The display panel of claim 1, wherein each of the gates overlaps with the first source lines and the second source lines of the component groups, wherein each of the component groups further comprises The channel layer groups respectively overlap the corresponding source group and the drain. The display panel of claim 6, wherein the channel layer group in each of the component groups comprises a first channel layer and a second channel layer separated from each other, the first channel layer and the first layer The source is electrically connected to the drain, and the second channel is electrically connected to the second source and the drain, wherein a portion of the transparent gap is located between two adjacent channel layers. The display panel of claim 1, wherein each of the gates in each component group of the auxiliary circuit has a first shortest distance between each component group and an adjacent component group. a second shortest distance, wherein the first shortest distance is greater than the second shortest distance. A method for manufacturing a display panel, comprising: (a) providing an array substrate having a display area and a non-display area, the non-display The area has a masking area, the array substrate comprises: a pixel array, located in the display area; and an auxiliary circuit located in the non-display area, wherein the auxiliary circuit comprises a plurality of component groups, each component group comprising: a first source line, a second source line, and a drain line, the first source line and the second source line are electrically connected to the pixel array; and the plurality of gates are electrically connected a gate voltage, wherein adjacent gates have a light-transmissive gap; a plurality of source groups, each source group and one of the gates are overlapped and include a first source and a first a second source, wherein the first source in the source group is electrically connected to the first source line, and the second source and the second source in the source group are electrically connected And a plurality of drains electrically connected to the drain line, and each of the drains is disposed between the first source and the second source of one of the source groups; (b) providing a masking material is disposed on the array substrate, and the sealant material corresponds to the sealant region, wherein the auxiliary circuit and the sealant material And (c) performing a light-illuminating step on the sealant material, wherein the light of the illumination step passes through a light-transmissive gap between the gates of each component group of the auxiliary circuit to cure the sealant material. The method for manufacturing a display panel according to claim 9, further comprising: (d) providing a pair of substrates; (e) providing a display medium between the opposite substrate and the array substrate; and (f) disposing a photomask on the array substrate and the opposite substrate, the mask shielding the display area and exposing the sealant Wherein: step (b) includes providing the sealant material between the array substrate and the opposite substrate, wherein the sealant material is located in the sealant region, and step (b) is prior to step (c); Step (c) includes performing the illuminating step on the sealant material by using the reticle, wherein the illuminating step light passes through the transparent gap between the gates of each component group of the auxiliary circuit to cure the frame Glue material.