TWI505464B - Power mosfet and method of forming the same - Google Patents

Description

Power MOS semiconductor field effect transistor and manufacturing method thereof

The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a power metal-oxide-semiconductor field effect transistor (power MOSFET) and a method of fabricating the same.

Power MOSFETs are widely used in power switch components such as power supplies, rectifiers or low voltage motor controllers and the like. In general, power MOS field effect transistors are designed with vertical structures to increase component density. It uses the back side of the wafer as a drain, and the source and gate of a plurality of transistors are fabricated on the front side of the wafer. Since the drains of multiple transistors are connected in parallel, the current they can withstand can be quite large.

In general, a power MOS field effect transistor includes a cell area, a gate metal area, and a metal field plate area. The gate metal region is a signal for transmitting the gate, and the metal field region is used to increase the electric field of the entire component, and the two regions are generally collectively referred to as a terminator. As the integration of power MOS field effect transistors increases, the size of power MOS field effect transistors also shrinks. Therefore, how to effectively integrate the cell region, the gate metal region and the metal field plate region of the power MOS field effect transistor to reduce its size has become a One of the topics of importance.

In view of the above, the present invention provides a power MOS field effect transistor, which can effectively integrate the cell region, the gate metal region and the metal field plate region of the power MOS field effect transistor.

The invention further provides a method for manufacturing a power MOS field effect transistor, which can reduce the alignment deviation of the contact hole of the power MOS field effect transistor to the trench by using the process and the self-aligned process, thereby reducing the crystal Cell pitch improves the accumulation of components.

The invention provides a power MOS field effect transistor, comprising a substrate having a first conductivity type, an epitaxial layer having a first conductivity type, a body layer having a second conductivity type, an isolation structure, a first conductor layer, a dielectric layer, at least one source region having a first conductivity type, a second conductor layer, and a third conductor layer. The epitaxial layer is disposed on the substrate. The main body layer is disposed in the epitaxial layer, wherein the ditch is disposed in the main body layer and a part of the epitaxial layer. The isolation structure is disposed on the substrate on one side of the trench. The first oxide layer is disposed on the surface of the trench. The first conductor layer fills the trench and extends to a portion of the isolation structure. The dielectric layer is disposed on the first conductor layer and the isolation structure and has an opening exposing a portion of the first conductor layer. The source region is disposed in the body layer on the other side of the trench. The second conductor layer is disposed on the dielectric layer and electrically connected to the source region, but is electrically isolated from the first conductor layer by the dielectric layer. The third conductor layer is disposed on the dielectric layer and electrically connected to the first conductor layer via the opening of the dielectric layer, wherein the second conductor layer is separated from the third conductor layer.

In an embodiment of the invention, the first conductor layer includes a first portion filling the trench and a second portion extending from the first portion to the partial isolation structure, and the dielectric layer covers a portion of the first portion. The surface of the first portion of the first conductor layer is not higher than the surface of the body layer.

In an embodiment of the invention, the first conductor layer includes a first portion filling the trench and a second portion extending from the first portion to the partial isolation structure, and the dielectric layer does not cover the first portion. The surface of the first portion of the first conductor layer is not higher than the surface of the body layer.

In an embodiment of the invention, the body layer and the isolation structure are partially overlapped or separated from each other.

In an embodiment of the invention, the power MOS field effect transistor further includes a second oxide layer disposed at least at the bottom of the trench. The material of the second oxide layer includes an oxide having a dielectric constant of less than 4. Furthermore, the second oxide layer is further disposed between the upper surface of the isolation structure and the first conductor layer.

In an embodiment of the invention, the power MOS field effect transistor further includes: disposed between the second oxide layer and the first oxide layer and between the second oxide layer and the upper surface of the isolation structure Cover layer. The material of the mask layer includes tantalum nitride.

In an embodiment of the invention, the power MOS field effect transistor further includes a mask pattern overlying the isolation structure, and the mask pattern is between the mask layer and the isolation structure. The material of the mask pattern includes tantalum nitride.

In an embodiment of the invention, the power MOS field effect transistor further includes a mask pattern overlying the isolation structure. Cover pattern material The material includes tantalum nitride.

In an embodiment of the invention, the power MOS field effect transistor further includes at least one doped region having a second conductivity type disposed between the second conductor layer and the body layer.

In an embodiment of the invention, the power MOS field effect transistor further includes a pad oxide layer disposed between the body layer and the first conductor layer.

In an embodiment of the invention, the isolation structure comprises a field oxide structure or a shallow trench isolation structure.

In an embodiment of the invention, the material of the first conductor layer comprises doped polysilicon.

In an embodiment of the invention, the material of the second conductor layer and the third conductor layer comprises aluminum.

In an embodiment of the invention, the first conductivity type is an N type, the second conductivity type is a P type; or the first conductivity type is a P type, and the second conductivity type is an N type.

The invention further provides a method for manufacturing a power MOS field effect transistor. First, an epitaxial layer having a first conductivity type is formed on a substrate having a first conductivity type. Then, an isolation structure is formed on the substrate. Next, a body layer having a second conductivity type is formed in the epitaxial layer on one side of the isolation structure. Thereafter, a mask layer is formed on the substrate, the mask layer having at least one first mask pattern on the body layer, a second mask pattern covering the isolation structure, and a first mask pattern and a second mask pattern The first opening between the two. Then, with the mask layer as the mask, the corresponding layer is formed in the main layer and the epitaxial layer. An open trench. Next, a first oxide layer is formed on the surface of the trench. Then, the trench is filled with the first conductor layer, and the first conductor layer extends to the portion of the isolation structure. Next, the first mask pattern is subjected to a reduction process to reduce the line width of the first mask pattern. Thereafter, at least one source region having a first conductivity type is formed in the body layer on one side of the trench with the reduced first mask pattern as a mask. Then, a dielectric material layer is formed on the substrate to cover the reduced first mask pattern and the first conductor layer. Next, a portion of the dielectric material layer is removed to form a dielectric layer, wherein the dielectric layer exposes a surface of the first mask pattern and has a second opening exposing a portion of the first conductor layer. Then, the cut first mask pattern is removed. And forming a second conductor layer and a third conductor layer separated from each other, wherein the first conductor layer is electrically connected to the source region, and the third conductor layer passes through the second opening of the dielectric layer and the first conductor layer Electrical connection.

In an embodiment of the invention, the first conductor layer includes a first portion filling the trench and a second portion extending from the first portion to the partial isolation structure, and the dielectric layer covers a portion of the first portion. The surface of the first portion of the first conductor layer is not higher than the surface of the body layer.

In an embodiment of the invention, the first conductor layer includes a first portion filling the trench and a second portion extending from the first portion to the partial isolation structure, and the dielectric layer does not cover the first portion. The surface of the first portion of the first conductor layer is not higher than the surface of the body layer.

In an embodiment of the invention, the body layer and the isolation structure are partially overlapped or separated from each other.

In an embodiment of the invention, the step of forming the first oxide layer After the step of forming the first conductor layer, the method further includes forming a second oxide layer between the bottom of the trench and the second mask pattern and the first conductor layer. The material of the second oxide layer includes an oxide having a dielectric constant of less than 4.

In an embodiment of the invention, the step of forming the second oxide layer described above is described below. First, a mask layer and an oxide material layer are sequentially formed on the substrate. Then, with the mask layer as a barrier layer, the oxide material layer on the sidewalls of the trench, the first mask pattern and the second mask pattern is removed. Next, the mask layer not covered by the second oxide layer is removed. The material of the mask layer includes tantalum nitride.

In an embodiment of the invention, after the step of forming the trench and before the step of forming the first oxide layer, the method further comprises removing the second mask pattern covering the isolation structure.

In an embodiment of the invention, the step of forming the first conductor layer described above is described below. First, a layer of conductive material is formed on the substrate to fill the trench and cover the mask layer. A patterned photoresist layer is then formed over the layer of conductive material. Next, using the patterned photoresist layer as a mask, an etching process is performed to remove a portion of the conductor material layer.

In an embodiment of the invention, after the step of removing the reduced first mask pattern and before the step of forming the second and third conductor layers, the method further comprises using a dielectric layer as a mask for the main body At least one doped region having a second conductivity type is formed in the layer, and the second conductor layer is electrically connected to the doped region.

In one embodiment of the invention, the reduction process includes a wet etch process.

In an embodiment of the invention, after the step of forming the epitaxial layer and before the step of forming the bulk layer, the method further comprises forming a layer of pad oxide material on the substrate.

In an embodiment of the invention, the isolation structure comprises a field oxide structure or a shallow trench isolation structure.

In an embodiment of the invention, the material of the first conductor layer comprises doped polysilicon.

In an embodiment of the invention, the material of the second conductor layer and the third conductor layer comprises aluminum.

In an embodiment of the invention, the first conductivity type is an N type, the second conductivity type is a P type; or the first conductivity type is a P type, and the second conductivity type is an N type.

Based on the above, in the power MOS field effect transistor of the present invention, a conductor layer filling the trench and extending to a portion of the isolation structure is disposed in the trench located in the cell region and the termination region simultaneously to extend the cell region and The terminal areas are effectively integrated to achieve the purpose of reducing the size of the components.

In addition, the method of the present invention utilizes a reduction process and a self-aligned process to form a contact window of a power MOS field effect transistor, so that alignment misalignment does not occur between the contact window and the trench. Therefore, the pitch between the cells can be greatly reduced, and the degree of accumulation of components can be improved. In addition, the method of the invention is relatively simple, and the fabrication of the source region, the doping region and the contact window can be completed by using a self-aligned process without adding an additional mask, which greatly saves cost and enhances competitiveness. Further, since the gate oxide layer (i.e., the first oxide layer) of the present invention is formed at one time via the thermal oxidation method, there is no known situation in which the gate oxide layer has a discontinuous junction and reduces the device performance. Furthermore, the material of the bottom oxide layer (ie, the second oxide layer) formed at the bottom of the trench of the present invention is an oxide having a dielectric constant of less than 4, thereby reducing the capacitance C _{gd of the} gate to the drain, effective Reduce the switching loss.

The above described features and advantages of the present invention will be more apparent from the following description.

1 is a cross-sectional view showing a method of fabricating a power MOS field effect transistor according to an embodiment of the invention.

Referring to FIG. 1, the power MOS field effect transistor 100a of the present invention comprises a substrate 102 having a first conductivity type, an epitaxial layer 104 having a first conductivity type, a body layer 106 having a second conductivity type, and an isolation structure. 103, a pad oxide layer 105a, an oxide layer 115, a conductor layer 124, a conductor layer 126, a dielectric layer 129a, at least one source region 128 having a first conductivity type, and at least one doping region having a second conductivity type 130, conductor layer 132 and conductor layer 134.

Substrate 102 is, for example, a germanium substrate having an N-type heavily doped. This N-type heavily doped (N+) germanium substrate serves as the drain of the power MOS field effect transistor 100a. The epitaxial layer 104 is disposed on the substrate 102. The epitaxial layer 104 is, for example, an epitaxial layer having an N-type lightly doped (N-) layer. N+ represents a higher concentration of N-type impurities; N- represents a lower concentration of N-type impurities. The body layer 106 is disposed in the epitaxial layer 104. The body layer 106 is, for example, a P-type body layer. In addition, the trench 112 and the trench 114 are disposed in the main body layer 106 and the partial epitaxial layer 104. The width W2 of the trench 114 is the ditch 112 The width W1 is about 1 to 2 times.

The isolation structure 103 is disposed on the substrate 102 on one side of the trench 114. The isolation structure 103 is, for example, a field oxide (FOX) structure or a shallow trench isolation (STI) structure. The isolation structure 103 and the body layer 106 may partially overlap or be separated from each other. In this embodiment, the isolation structure 103 and the main body layer 106 are partially overlapped, but the invention is not limited thereto. The oxide layer 115 is disposed on the surface of the trench 112 and the trench 114. The material of the oxide layer 115 includes ruthenium oxide. The thickness of the oxide layer 115 is, for example, about 100 to 1000 angstroms. In an embodiment, the thickness of the oxide layer 115 is, for example, about 500 angstroms.

Conductor layer 124 fills trenches 112. Conductor layer 126 fills trench 114 and extends over portion of isolation structure 103. The material of the conductor layer 124 and the conductor layer 126 is, for example, an N-type heavily doped doped polysilicon. Further, the pad oxide layer 105 may be selectively disposed between the body layer 106 and the conductor layer 126. The material of the pad oxide layer 105 includes ruthenium oxide. The dielectric layer 129a is disposed on the conductor layers 124, 126 and the isolation structure 103 and has an opening 133 exposing a portion of the conductor layer 126. The material of the dielectric layer 129a is, for example, yttrium oxide, borophosphoquinone glass (BPSG), phosphoric bismuth glass (PSG), fluorocarbon glass (FSG) or undoped bismuth glass (USG).

In particular, the conductor layer 126 includes a first portion 125 that fills the trench 114 and a second portion 127 that extends from the first portion 125 to the partial isolation structure 103, and the dielectric layer 129a covers a portion of the first portion 125, as shown in FIG. Shown. However, the invention is not limited thereto. In another embodiment, the junction of the first portion 125 of the conductor layer 126 and the second portion 127 is heavier The stack, that is, the dielectric layer 129a does not cover the first portion 125, as shown in FIG. Moreover, the surface of the first portion 125 of the conductor layer 124 and the conductor layer 126 is not higher than the surface of the body layer 106. In other words, the surface of the first portion 125 of the conductor layer 124 and the conductor layer 126 is substantially equal to or lower than the surface of the body layer 106. .

The source region 128 is disposed in the body layer 106 on the other side of the trench 114. In this embodiment, the four source regions 128 are taken as an example for illustration. However, the present invention does not limit the number of source regions 128. One or more source regions may be disposed in the trenches 114 according to process requirements. In the body layer 106 on the other side. In this embodiment, except that one source region 128 is located in the body layer 106 adjacent to the trench 114, the remaining source regions 128 are in the body layer 106 on either side of each trench 112. The source region 128 is, for example, a doped region having an N-type heavily doped. The N-type impurity is, for example, phosphorus or arsenic. In addition, the doping region 130 may be selectively disposed between the conductor layer 132 and the body layer 106 to reduce the electrical resistance between the conductor layer 132 and the body layer 106. The doped region 130 is, for example, a doped region having a P-type heavily doped. The P-type impurity is, for example, boron. In this embodiment, two doped regions are taken as an example, but the present invention does not limit the number of doped regions 130. In other words, the number of doped regions 130 may be one or two or more.

The conductor layer 132 is disposed on the dielectric layer 129a and electrically connected to the source region 128 and the doped region 130, but is electrically isolated from the conductor layer 126 by the dielectric layer 129a. The conductor layer 134 is disposed on the dielectric layer 129a and electrically connected to the conductor layer 126 via the opening 133 of the dielectric layer 129a. Further, the conductor layer 132 and the conductor layer 134 are separated from each other. Conductor layer 132 and conductor layer 134 The material is, for example, aluminum.

In the power MOS field effect transistor 100a of the present invention, the cell region 101a is located on the left side of FIG. 1, and the termination region 101b is located on the right side of FIG. 1, and the trench 114 is simultaneously located in the cell region 101a and the termination region 101b. in. In the cell region 101a, the conductor layer 132 serves as a source metal layer, the substrate 102 serves as a drain, the conductor layers 124, 126 serve as gates, and the oxide layer 115 serves as a gate oxide layer. In the termination region 101b, the conductor layer 134 serves as a gate metal layer and a metal field plate layer, and the conductor layer 134 is electrically connected to the cell region 101a via the conductor layer 126.

Based on the above, in the power MOS field effect transistor 100a of the present invention, since the trench 114 is simultaneously located in the cell region 101a and the termination region 101b, and the conductor layer 126 fills the trench 114 and extends to the partial isolation structure 103, Therefore, the cell region 101a and the terminal region 101b including the gate metal region and the metal field plate region can be effectively integrated to achieve the purpose of reducing the size of the device. Compared with the conventional power MOS field effect transistor, the power MOS field effect transistor of the present invention can reduce the size of the termination region by about 10 to 20 micrometers (um), and greatly enhance the integration of components.

In addition, in order to make the cell region 101a and the termination region 101b process compatible, in addition to the components of the power MOS field effect transistor 100a, the mask pattern 109 may be selectively overlaid on the isolation structure 103, as shown in FIG. The power MOSFET field effect transistor 100c is shown. The material of the mask pattern 109 includes tantalum nitride and has a thickness of, for example, about 5,000 to 6,000 angstroms.

In addition, in order to reduce the gate-to-drain capacitance C _gd to effectively reduce the switching loss, the oxide layer 120 may be selectively disposed on the trench 112 and the bottom of the trench 114, such as the power MOS field effect of FIG. The crystal 100d is shown. The material of the oxide layer 120 includes an oxide having a dielectric constant of less than 4. The oxide layer 120 is, for example, a ruthenium oxide layer having a thickness of about 2000 angstroms. Further, the oxide layer 120 is disposed between the upper surface of the isolation structure 103 and the conductor layer 126. Further, a mask layer 116 may be selectively disposed between the oxide layer 120 and the oxide layer 115 and between the oxide layer 120 and the upper surface of the isolation structure 103. The mask layer 116 is, for example, a tantalum nitride layer having a thickness of about 200 angstroms.

Of course, the components of FIGS. 3 and 4 can also be integrated, wherein the mask pattern 109 is located between the mask layer 116 and the isolation structure 103, as shown in the power MOS field effect transistor 100e of FIG.

In the above embodiments, the first conductivity type is N-type and the second conductivity type is P-type as an example, but the invention is not limited thereto. Those skilled in the art will appreciate that the first conductivity type may also be P-type and the second conductivity type may be N-type.

Hereinafter, a method of manufacturing the power MOS field effect transistor of the present invention will be described. The manufacturing method of the most complicated structure described above (such as the power MOS field effect transistor 100e of Fig. 5) will be explained, and the manufacturing method of the remaining structure can be completed by omitting part of the steps, which will be described in detail below.

6A-6H are schematic cross-sectional views showing a method of fabricating a power MOS field effect transistor according to an embodiment of the invention.

First, referring to FIG. 6A, an epitaxial layer 104 having a first conductivity type is formed on a substrate 102 having a first conductivity type as a drain. Substrate 102 is, for example, a germanium substrate having an N-type heavily doped. The epitaxial layer 104 has, for example, An N-type lightly doped epitaxial layer, and a method for forming the same includes performing a selective epitaxy growth (SEG) process. Next, an isolation structure 103 is formed on the substrate 102. The isolation structure 103 is, for example, a field oxide structure or a shallow trench isolation structure.

Then, a body layer 106 having a second conductivity type is formed in the epitaxial layer 104 on one side of the isolation structure 103. The body layer 106 is, for example, a P-type body layer, and the method of forming the same includes performing an ion implantation process and a subsequent drive-in process. Further, the isolation structure 103 and the body layer 106 may partially overlap or be separated from each other. In an embodiment, the pad oxide material layer 105 may also be selectively formed on the substrate 102 after the step of forming the isolation structure 103 and before the step of forming the body layer 106. The pad oxide material layer 105 can avoid the tunneling effect caused when the ion implantation process is performed to form the body layer 106. The material of the pad oxide material layer 105 is, for example, ruthenium oxide, and the formation method thereof is, for example, a thermal oxidation process.

Thereafter, the mask material layer 108 and the patterned photoresist layer 110 are sequentially formed on the substrate 102. The material of the mask material layer 108 includes tantalum nitride, and the method of forming the same includes performing a chemical vapor deposition (CVD) process. In one embodiment, the mask material layer 108 is, for example, a single tantalum nitride layer having a thickness of about 5000 to 6000 angstroms, as shown in FIG. In another embodiment (not shown), the mask material layer 108 may also be a multi-layer structure, such as a two-layer structure including a bottom tantalum nitride layer and a top tantalum oxide layer, as required by the process.

Then, referring to FIG. 6B, the mask material layer 108 and the pad oxide material layer 105 are patterned by using the patterned photoresist layer 110 as a mask. A pad oxide layer 105a and a mask layer 108a are formed on the substrate 102. The mask layer 108a has a mask pattern 107 on the body layer 106, a mask pattern 109 covering the isolation structure 103, an opening 111 between the mask patterns 107, and an opening between the mask pattern 107 and the mask pattern 109. 113. In this embodiment, the two mask patterns 107 are taken as an example, but the present invention does not limit the number of the mask patterns 107. In other words, the number of the mask patterns 107 may be one or two or more. . Next, the patterned photoresist layer 110 is removed.

Then, the mask layer 108a is used as a mask to perform a dry etching process, and a trench 112 corresponding to the opening 111 and a trench 114 corresponding to the opening 113 are formed in the main body layer 106 and the partial epitaxial layer 104. The width W2 of the trench 114 is about 1 to 2 times the width W1 of the trench 112. In an embodiment, after the step of forming the trench 112 and the trench 114, the surface of the trench 112 and the trench 114 may be selectively subjected to an isotropic etching process to remove surface damage of the trench 112 and the trench 114. Then, a sacrificial oxide layer (not shown) may be selectively formed on the substrate 102 and then removed to repair the surface lattice damage of the trench 112 and the trench 114. It is particularly noted that when the mask material layer 108 is a two-layer structure including a bottom tantalum nitride layer and a top tantalum oxide layer, the top oxide layer is also removed in the step of removing the sacrificial oxide layer. Remove it together.

Next, referring to FIG. 6C, an oxide layer 115 is formed on the surface of the trench 112 and the trench 114. The material of the oxide layer 115 is, for example, ruthenium oxide, and the formation method thereof is, for example, a thermal oxidation process. The thickness of the oxide layer 115 is, for example, about 100 to 1000 angstroms. In an embodiment, the oxide layer 115 The thickness is, for example, about 500 angstroms.

Then, a mask layer 116 and an oxide material layer 118 are sequentially formed on the substrate 102. The method of forming the mask layer 116 and the oxide material layer 118 includes performing a chemical vapor deposition process. The mask layer 116 is, for example, a tantalum nitride layer having a thickness of about 200 angstroms. The material of the oxide material layer 118 includes an oxide having a dielectric constant of less than 4. The oxide material layer 118 is, for example, a ruthenium oxide layer having a thickness of about 4000 angstroms. However, due to the limitation of the chemical vapor deposition process, the thickness of the oxide material layer 118 on the top of the mask pattern 107, the mask pattern 109, and the bottom of the trench 112 and the trench 114 is generally larger than the oxide material layer 118 in the trench 112 and the trench. 114. The thickness of the side wall of the mask pattern 107 and the mask pattern 109. In one embodiment, the thickness of the oxide material layer 118 on the top of the mask pattern 107, the mask pattern 109, and the bottom of the trench 112 and the trench 114 is about 4000 angstroms, but in the trench 112, the trench 114, and the mask pattern. 107. The sidewall of the mask pattern 109 has a thickness of about 2000 angstroms.

Thereafter, referring to FIG. 6D, the mask layer 116 is used as a stop layer, and a blanket etching process is performed to remove the sidewalls of the trench 112, the trench 114, the mask pattern 107, and the mask pattern 109. The oxide material layer 118 is disposed, and the oxide layer 120 is disposed on the top of the mask pattern 107, the mask pattern 109, and the trench 112 and the bottom of the trench 114. In one embodiment, the oxide layer 120 has a thickness of about 2000 angstroms. The full etching process is, for example, a wet etching process, and the etching liquid used is, for example, a buffer oxide etchant (BOE) or diluted hydrofluoric acid (DHF).

Next, the mask layer 116 that is not covered by the oxide layer 120 is removed. The method of removing the mask layer 116 not covered by the oxide layer 120 is, for example, a wet etching process using an etching solution such as phosphoric acid (H ₃ PO ₄ ). In particular, the purpose of forming the oxide layer 120 at the bottom of the trench 112 and the trench 114 is to reduce the gate-to-drain capacitance C _gd to effectively reduce switching losses.

Then, referring to FIG. 6E, a conductor layer 124 is formed in the trench 112 and a conductor layer 126 is formed in the trench 114, and the conductor layer 126 extends onto the partial isolation structure 103. The step of forming the conductor layer 124 and the conductor layer 126 includes forming a conductive material layer 121 and a patterned photoresist layer 123 (as shown in FIG. 6D) on the substrate 102 to fill the trench 112 and the trench 114. The material of the conductor material layer 121 is, for example, an N-type heavily doped doped polysilicon. Next, using the patterned photoresist layer 123 as a mask, a dry etching process is performed to remove a portion of the conductive material layer 121. In this embodiment, the conductor layer 126 includes a first portion 125 that fills the trench 114 and a second portion 127 that extends from the first portion 125 to the portion of the isolation structure 103, and a subsequently formed dielectric layer 129a (shown in FIG. 6G). The first portion 125 will be covered.

In an embodiment, after the step of forming the conductor layer 124 and the conductor layer 126, the conductor layer 124 and the conductor layer 126 may be selectively subjected to a thermal oxidation process to increase the withstand voltage of the conductor layer 124 and the conductor layer 126. . Moreover, the surface of the first portion 125 of the conductor layer 124 and the conductor layer 126 is not higher than the surface of the body layer 106, that is, the surface of the first portion 125 of the conductor layer 124 and the conductor layer 126 is substantially equal to or lower than the body layer 106. s surface. Thereafter, the oxide layer 120 on the mask pattern 107 and the oxide layer 120 not covered by the conductor layer 126 are removed.

Next, referring to FIG. 6F, the mask pattern 107 is subjected to a reduction process to reduce the line width of each mask pattern 107. The line width of the mask pattern 107 is reduced to W4 by W3 (as shown in Fig. 6E) (as shown in Fig. 6F). The reduction process is, for example, a wet etching process, and the etching liquid used is, for example, phosphoric acid. In an embodiment, since the material of the mask pattern 107 and the mask layer 116 are both tantalum nitride, in the step of reducing the mask pattern 107, the mask layer on the mask pattern 107 is also removed at the same time. 116. In addition, the above-described reduction process is substantially a full etching process, and thus the mask layer 116 on the mask pattern 109 not covered by the conductor layer 126 is also removed.

Then, at least one source region 128 having a first conductivity type is formed in the body layer 106 on one side of the trench 114 by using the reduced mask pattern 107 as a mask. In this embodiment, except that one source region 128 is located in the body layer 106 adjacent to the trench 114, the remaining source regions 128 are in the body layer 106 on either side of each trench 112. The source region 128 is, for example, a doped region having an N-type heavily doped. The N-type impurity is, for example, phosphorus or arsenic. The step of forming the source region 128 includes performing an ion implantation process and a subsequent drive-in process, such that a portion of the source region 128 formed extends below the mask pattern 107. The ion implantation process that forms the source region 128 is a mask with a reduced mask pattern 107 and is therefore a self-aligned process.

Next, a dielectric material layer 129 is formed on the substrate 102 to cover the reduced mask pattern 107, the conductor layer 124, and the conductor layer 126. The material of the dielectric material layer 129 is, for example, yttrium oxide, borophosphoquinone glass (BPSG), phosphoric bismuth glass (PSG), fluorocarbon glass (FSG) or undoped bismuth glass (USG). And the method of forming the same includes performing a chemical vapor deposition process. Then, a patterned photoresist layer 131 is formed on the dielectric material layer 129.

Thereafter, referring to FIG. 6G, a portion of the dielectric material layer 129 is removed by patterning the photoresist layer 131 as a mask to form a dielectric layer 129a. The dielectric layer 129a exposes the surface of the reduced mask pattern 107 and the opening 133 having the exposed portion of the conductor layer 126 exposed. The method of forming dielectric layer 129a includes performing a dry etch process.

Thereafter, referring to FIG. 6H, the reduced mask pattern 107 is removed. Next, the pad oxide layer 105a under the reduced mask pattern 107 is removed. The method of removing the pad oxide layer 105a is, for example, a wet etching process using an etching liquid such as an etching oxidation buffer (BOE) or diluted hydrofluoric acid (DHF). In an embodiment, in the step of removing the pad oxide layer 105a, a portion of the dielectric layer 129a is also removed at the same time. Next, at least one doping region 130 having a second conductivity type is formed in the body layer 106 with the dielectric layer 129a as a mask. The purpose of forming the doping region 130 is to reduce the electrical resistance between the subsequently formed contact window and the body layer 106. The doped region 130 is, for example, a doped region having a P-type heavily doped. The P-type impurity is, for example, boron. The ion implantation process for forming the doping region 130 is based on the dielectric layer 129a and is therefore a self-aligned process. In addition, in this step, a portion of the P-type impurity forming the doping region 130 is also doped into the conductor layer 126 via the opening 133 of the dielectric layer 129a. However, since the conductor layer 126 is an N-type heavily doped doped polysilicon layer and its doping concentration is much higher than the doping concentration of the P-type doping region 130, the performance of the conductor layer 126 is not affected.

Next, conductor layers 132 and leads separated from each other are formed on the substrate 102. The body layer 134 is electrically connected to the source region 128 and the doped region 130, and the conductor layer 134 is electrically connected to the conductor layer 126 via the opening 133 of the dielectric layer 129a. The method of forming the conductor layer 132 and the conductor layer 134 includes sequentially forming a conductive material layer (not shown) and a patterned photoresist layer (not shown) on the substrate 102. The material of the conductor material layer is, for example, aluminum, and the method of forming the same includes performing a chemical vapor deposition process. Then, using a patterned photoresist layer as a mask, a dry etching process is performed to remove a portion of the conductor material layer to form it. Thus far, the manufacture of the power MOS field effect transistor 100e of the present invention has been completed.

In the above method of fabricating the power MOS field effect transistor 100e, the mask pattern 109 covering the isolation structure 103 is removed after the step of forming the trench 112 and the trench 114 and before the step of forming the oxide layer 115. The method of removing the mask pattern 109 covering the isolation structure 103 includes performing a lithography process and an etching process. Further, the following steps are omitted: a step of forming the mask layer 116 and the oxide material layer 118, a step of removing a portion of the oxide material layer 118 to form the oxide layer 120, and removing a mask not covered by the oxide layer 120. The fabrication of the power MOS field effect transistor 100a is accomplished by the step of layer 116.

In the method of fabricating the power MOS field effect transistor 100a, in the step of forming the conductor layer 124 and the conductor layer 126, the pattern position of the patterned photoresist layer 123 is changed such that the first portion 125 of the conductor layer 126 is The junction of the two portions overlaps, that is, the dielectric layer 129a does not cover the first portion 125, and the fabrication of the power MOS field effect transistor 100b can be completed.

In the above method of fabricating the power MOS field effect transistor 100e, the following steps are omitted: the step of forming the mask layer 116 and the oxide material layer 118, and the step of removing a portion of the oxide material layer 118 to form the oxide layer 120. The fabrication of the power MOS field effect transistor 100c can be accomplished by the step of removing the mask layer 116 that is not covered by the oxide layer 120.

In the manufacturing method of the power MOS field effect transistor 100e, after the step of forming the trench 112 and the trench 114 and before the step of forming the oxide layer 115, the mask pattern 109 covering the isolation structure 103 is removed. The fabrication of the power MOS field effect transistor 100d is completed.

In summary, in the power MOS field effect transistor of the present invention, the trenches 114 simultaneously located in the cell region 101a and the termination region 101b are disposed in the trenches 114 which fill the trench 114 and extend to the portion of the isolation structure 103. In order to effectively integrate the cell region 101a and the termination region 101b including the gate metal region and the metal field plate region, the purpose of reducing the size of the component is achieved. Compared with the conventional power MOS field effect transistor, the power MOS field effect transistor of the present invention can reduce the size of the termination region by about 10 to 20 micrometers, and greatly enhance the integration of components.

In addition, the method of the present invention forms a contact window of the power MOS field effect transistor by reducing the process and the self-aligned process, so that no alignment deviation occurs between the contact window and the trench. Therefore, the spacing between the cells can be minimized. In other words, the distance from the ditch to the ditch can be reduced to the limit of the lithography machine (ie, the lithography resolution), and then the reduction process and the self-aligned process are used to form the contact window, thereby greatly reducing the spacing between the cells and improving The degree of accumulation of components.

In addition, the manufacturing method of the present invention is relatively simple, and the fabrication of the source region 128, the doping region 130, and the contact window can be completed by using a self-aligned process without a need for an additional photomask, thereby greatly saving cost and improving competitiveness.

Furthermore, the gate oxide layer (i.e., oxide layer 115) of the present invention is formed once by a thermal oxidation process, so that there is no known situation in which the gate oxide layer has discontinuous junctions to reduce component performance.

Moreover, the material of the bottom oxide layer (ie, the oxide layer 120) formed at the bottom of the trench 112 and the trench 114 is an oxide having a dielectric constant lower than 4, thereby reducing the capacitance of the gate to the drain C _gd , effectively reducing switching losses.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100a~100d‧‧‧Power MOS field effect transistor

101a‧‧‧cell area

101b‧‧‧ terminal area

102‧‧‧Base

103‧‧‧Isolation structure

104‧‧‧ epitaxial layer

105‧‧‧Material layer of oxide material

105a‧‧‧Mat oxide layer

106‧‧‧ body layer

108‧‧‧ Cover material layer

107, 109‧‧‧ mask pattern

108a‧‧‧ Cover layer

111, 113, 133‧‧

110, 123, 131‧‧‧ patterned photoresist layer

112, 114‧‧‧ Ditch

115, 120‧‧‧ oxide layer

116‧‧‧ Cover layer

118‧‧‧Oxide material layer

121‧‧‧layer of conductor material

124, 126, 132, 134‧‧‧ conductor layers

125‧‧‧Part 1

127‧‧‧Part II

128‧‧‧ source area

129‧‧‧ dielectric material layer

129a‧‧‧ dielectric layer

130‧‧‧Doped area

W1, W2‧‧‧ width

W3, W4‧‧‧ line width

FIG. 1 is a cross-sectional view of a power MOS field effect transistor according to an embodiment of the invention.

2 is a cross-sectional view of a power MOS field effect transistor according to another embodiment of the invention.

3 is a cross-sectional view of a power MOS field effect transistor according to another embodiment of the invention.

4 is a cross-sectional view of a power MOS field effect transistor according to still another embodiment of the present invention.

FIG. 5 is a cross-sectional view of a power MOS field effect transistor according to another embodiment of the invention.

6A-6H are schematic cross-sectional views showing a method of fabricating a power MOS field effect transistor according to an embodiment of the invention.

100a‧‧‧Power MOS field effect transistor

101a‧‧‧cell area

101b‧‧‧ terminal area

102‧‧‧Base

103‧‧‧Isolation structure

104‧‧‧ epitaxial layer

105a‧‧‧Mat oxide layer

106‧‧‧ body layer

133‧‧‧ openings

112, 114‧‧‧ Ditch

115‧‧‧Oxide layer

124, 126, 132, 134‧‧‧ conductor layers

125‧‧‧Part 1

127‧‧‧Part II

128‧‧‧ source area

129a‧‧‧ dielectric layer

130‧‧‧Doped area

W1, W2‧‧‧ width

Claims (36)

A power MOS field effect transistor comprising: a substrate having a first conductivity type, having a cell region and a termination region; and an epitaxial layer having the first conductivity type disposed on the substrate; a body layer having a second conductivity type disposed in the epitaxial layer, wherein a trench is disposed in the body layer and a portion of the epitaxial layer, and the trench is simultaneously located in the cell region and the termination region; An isolation structure disposed on the substrate of the terminal region on one side of the trench; a first oxide layer disposed on a surface of the trench; a first conductor layer filling the trench and extending to the portion of the isolation Structurally, a dielectric layer disposed on the first conductor layer and the isolation structure and having an exposed portion of the first conductor layer; a source region having the first conductivity type disposed adjacent to the a second conductor layer disposed on the dielectric layer and electrically connected to the source region, but the first conductor layer is used by the main conductor layer of the cell region on the other side of the trench Dielectric layer and electrically isolated; and a third conductor layer, configured The dielectric layer is electrically connected to the first conductor layer via the opening of the dielectric layer, wherein the second conductor layer is separated from the third conductor layer, wherein the first conductor layer comprises filling the trench The first part of And extending from the first portion to a second portion of the isolation structure, and the dielectric layer covers a portion of the first portion, and a surface of the first portion of the first conductor layer is not higher than a surface of the body layer. The power MOS field effect transistor of claim 1, wherein the body layer is partially overlapped or separated from the isolation structure. The power MOS field effect transistor of claim 1, further comprising a second oxide layer disposed at least at the bottom of the trench. The power MOS field effect transistor of claim 3, wherein the material of the second oxide layer comprises an oxide having a dielectric constant of less than 4. The power MOS field effect transistor of claim 3, wherein the second oxide layer is disposed between the upper surface of the isolation structure and the first conductor layer. The power MOS field effect transistor of claim 5, further comprising: disposed between the second oxide layer and the first oxide layer, and between the second oxide layer and the isolation structure a mask layer between the upper surfaces. The power MOS field effect transistor of claim 6, wherein the material of the mask layer comprises tantalum nitride. The power MOS field effect transistor of claim 6, further comprising a mask pattern covering the isolation structure, and the mask pattern is located between the mask layer and the isolation structure. The power MOS field effect transistor of claim 8, wherein the material of the mask pattern comprises tantalum nitride. The power MOS field effect transistor of claim 1, further comprising a mask pattern covering the isolation structure. The power MOS field effect transistor of claim 10, wherein the material of the mask pattern comprises tantalum nitride. The power MOS field effect transistor of claim 1, further comprising at least one doped region having the second conductivity type disposed between the second conductor layer and the body layer. The power MOS field effect transistor of claim 1, further comprising a pad oxide layer disposed between the body layer and the first conductor layer. The power MOS field effect transistor of claim 1, wherein the isolation structure comprises a field oxide structure or a shallow trench isolation structure. The power MOS field effect transistor of claim 1, wherein the material of the first conductor layer comprises doped polysilicon. The power MOS field effect transistor of claim 1, wherein the material of the second conductor layer and the third conductor layer comprises aluminum. The power MOS field effect transistor of claim 1, wherein the first conductivity type is N type, the second conductivity type is P type; or the first conductivity type is P type, the first The two conductivity type is N type. Method for manufacturing power MOS semiconductor field effect transistor, package Forming: forming an epitaxial layer having the first conductivity type on a substrate having a first conductivity type; forming an isolation structure on the substrate; forming an epitaxial layer on one side of the isolation structure a body layer of the second conductivity type; forming a mask layer on the substrate, the mask layer having at least a first mask pattern on the body layer, a second mask pattern covering the isolation structure, And a first opening between the first mask pattern and the second mask pattern; the mask layer is used as a mask, and a corresponding one of the first openings is formed in the body layer and a portion of the epitaxial layer a trench; a first oxide layer is formed on the surface of the trench; a first conductor layer is filled in the trench, and the first conductor layer extends to a portion of the isolation structure; and the first mask pattern is performed Cutting the process to reduce the line width of the first mask pattern; forming the first mask pattern as a mask, and forming at least one of the first conductivity type in the body layer on one side of the trench a source region; a dielectric material layer is formed on the substrate to cover Cutting the first mask pattern and the first conductor layer; removing a portion of the dielectric material layer to form a dielectric layer, wherein the dielectric layer exposes a surface of the first mask pattern and has an exposure a second opening of the portion of the first conductor layer; Removing the reduced first mask pattern; and forming a second conductor layer and a third conductor layer separated from each other on the substrate, wherein the first conductor layer is electrically connected to the source region, and the The third conductor layer is electrically connected to the first conductor layer via the second opening of the dielectric layer. The method of fabricating a power MOS field effect transistor according to claim 18, wherein the first conductor layer comprises filling a first portion of the trench and extending from the first portion to a portion of the isolation structure. a second portion, and the dielectric layer covers a portion of the first portion. The method of manufacturing a power MOS field effect transistor according to claim 19, wherein a surface of the first portion of the first conductor layer is not higher than a surface of the body layer. The method of fabricating a power MOS field effect transistor according to claim 18, wherein the first conductor layer comprises filling a first portion of the trench and extending from the first portion to a portion of the isolation structure. a second portion, and the dielectric layer does not cover the first portion. The method of manufacturing a power MOS field effect transistor according to claim 21, wherein a surface of the first portion of the first conductor layer is not higher than a surface of the body layer. The method of fabricating a power MOS field effect transistor according to claim 18, wherein the body layer and the isolation structure are partially overlapped or separated from each other. A method of manufacturing a power MOS field effect transistor according to claim 18, in the step of forming the first oxide layer After the step of forming the first conductor layer, a second oxide layer is further formed between the bottom of the trench and the second mask pattern and the first conductor layer. The method of manufacturing a power MOS field effect transistor according to claim 24, wherein the material of the second oxide layer comprises an oxide having a dielectric constant of less than 4. The method for manufacturing a power MOS field effect transistor according to claim 24, wherein the step of forming the second oxide layer comprises: sequentially forming a mask material layer and an oxide on the substrate a layer of material; removing the layer of oxide material on the sidewalls of the trench, the first mask pattern, and the second mask pattern with the mask material layer as a barrier layer; and removing the second layer The layer of masking material covered by the oxide layer. The method of manufacturing a power MOS field effect transistor according to claim 26, wherein the material of the mask material layer comprises tantalum nitride. The method for manufacturing a power MOS field effect transistor according to claim 18, after the step of forming the trench and before the step of forming the first oxide layer, further comprising removing the covering structure of the isolation structure The second mask pattern. The method for manufacturing a power MOS field effect transistor according to claim 18, wherein the step of forming the first conductor layer is Forming a layer of a conductive material on the substrate to fill the trench and covering the mask layer; forming a patterned photoresist layer on the conductive material layer; and using the patterned photoresist layer as a mask, An etching process is performed to remove a portion of the layer of conductive material. The method of manufacturing a power MOS field effect transistor according to claim 18, after the step of removing the reduced first mask pattern and before the step of forming the second and third conductor layers The method further includes forming, by the dielectric layer, at least one doped region having the second conductivity type in the body layer, and the second conductor layer is electrically connected to the doped region. The method of manufacturing a power MOS field effect transistor according to claim 18, wherein the reduction process comprises a wet etching process. The method for fabricating a power MOS field effect transistor according to claim 18, after the step of forming the epitaxial layer and before the step of forming the bulk layer, further comprising forming a pad oxide on the substrate Material layer. The method of fabricating a power MOS field effect transistor according to claim 18, wherein the isolation structure comprises a field oxide structure or a shallow trench isolation structure. The method of fabricating a power MOS field effect transistor according to claim 18, wherein the material of the first conductor layer comprises doped polysilicon. The method of manufacturing a power MOS field effect transistor according to claim 18, wherein the material of the second conductor layer and the third conductor layer comprises aluminum. The power MOS field effect transistor of claim 18, wherein the first conductivity type is N type, the second conductivity type is P type; or the first conductivity type is P type, the first The two conductivity type is N type.