TWI597829B - High density patterned material on integrated circuits - Google Patents

Description

High-density patterned material for integrated circuits

The present invention relates to a patterned strip material and contact region for an integrated circuit and a method of fabricating the same, including forming a bulk circuit by forming a strip material to facilitate the use of multiple patterning methods.

Integrated circuits are commonly used to fabricate various electronic devices, such as memory chips. Reducing the size of the integrated circuit is a strong requirement to increase the density of individual components and to enhance the functionality of the integrated circuit. The minimum pitch on the integrated circuit (the adjacent structure of two identical types, such as the minimum distance between the same points of two adjacent gate conductors) is typically used as a representative measure of circuit density.

Increasing the circuit density is typically limited by the resolution of the available photolithographic equipment. The minimum size of the pattern and spacing that can be produced by a particular lithographic apparatus is related to its resolution capacity.

The sum of the minimum pattern width and the minimum spacing width that can be produced by a particular lithographic apparatus is the minimum spacing that can be produced by the lithographic apparatus. The minimum pattern width is typically approximately equal to the minimum spacing width, so the minimum spacing that a particular lithographic apparatus can produce is approximately equal to twice the minimum pattern width.

One way to reduce the spacing between integrated circuits at a lower pitch than the lithographic apparatus produced is through the use of double or quadruple patterning, sometimes referred to herein as multiple patterning. In this way, a single reticle is typically used to make a series of parallel strips of material on the substrate. Each of the parallel strips can then be converted into multiple parallel strips in a different manner. Various methods are typically achieved using a series of deposition and etching steps. Different ways can be found in Xie, Peng and Smith, Bruce W., " Analysis of Higher-Order Pitch Division for Sub-32 nm Lithography", Optical Microlithography XXII, Proc. of SPIE Vol. 7274, 72741Y, © 2009 SPIE.

A layer of strip material can be connected to another layer through an interlayer connector, and the in-layer connector landed on a landing area. The in-layer connectors are formed using different patterning steps that have a greater spacing than the patterning steps for the denser strips. When the parallel strips are reduced by a multiple patterning process for higher density, the spacing of the landing zones required to connect the connectors in the layers of parallel strips of material becomes greater than the spacing of the strips of material.

It is therefore desirable to provide a technique for making landing zones with a pitch greater than that of parallel strips of material without the need to relax the spacing of the parallel strips of material as a minimum spacing that can be produced by a particular lithographic apparatus.

In accordance with the present invention, an integrated circuit is proposed that includes a plurality of strips of material and a plurality of landing zones. The strip material is on a substrate, the strip material comprises a plurality of strips S(i), and each S(i) of i from 3 to n has a first section and a second section, and the second section passes through a The gap is separate from the first section. In the opposite direction of the gap, the first section of strip S(i) is aligned with the second section such that the first section is in line with the second section. The landing zone includes a plurality of landing zones A(i), i each landing zone A(i) from 3 to n-2 connects one of the first sections of the plurality of strips of material S(i) to a plurality of strips of material A second segment of one of the strips S(i+2) and disposed in a gap between the first segment and the second segment in the strip S(i+1). The strip S(i) has a first pitch in a direction orthogonal to the plurality of strips of material, and the landing zone A(i) has a second pitch in a direction orthogonal to the plurality of strips of material, the second pitch being Double the distance. The strip S(i) may comprise a conductive material and is disposed, for example, within the layer of the metal layer 2.

The gap in the strip S(i) has a length in a direction parallel to the plurality of strips of material, and the landing zone A(i) has a width in a direction parallel to the plurality of strips of material, and the width is smaller than the strip S(i+1) The length of the gap between the first section and the second section. Adjacent landing zones A(i) and A(i+1) in the landing zone have an offset in the direction parallel to the plurality of strips of material. The offset may be at least the length of the gap between the first segment and the second segment of the strip S(i+1). The adjacent landing zones A(i) and A(i+1) in the landing zone have a spacing in a direction parallel to the plurality of strips of material, the spacing and the first section and the second of the strip S(i+1) The lengths of the gaps between the segments are equal. Adjacent landing zones A(i) and A(i+1) in the landing zone have an offset through a first spacing in a direction orthogonal to the plurality of strips of material.

In the plurality of strips S(i) of the integrated circuit, each S(i) of i from 3 to n has a third section, and the third section is separated from the second section by a gap. In the opposite direction of the gap, the second section of strip S(i) is aligned with the third section such that the second section is in line with the third section. The integrated circuit can include a plurality of second landing zones. The plurality of second landing zones include a plurality of landing zones A2(i), i each of the landing zones A2(i) from 3 to n connecting one of the plurality of strips of material S(i) to a plurality of strips A second section of one of the strips S(i+2) in the material, and disposed in a gap between the second section and the third section in the strip S(i+1). The second landing zone A2(i) has a second pitch in a direction orthogonal to the plurality of strips of material, the second pitch being twice the first pitch. The landing zone A(i) and the second landing zone A2(i) are mirror images in a direction parallel to the plurality of strips of material.

The plurality of strip materials and the plurality of landing zones described herein can be used for any closely spaced strip material in the integrated circuit, such as integrated circuit memory, central processing units (CPU), field programmable Field programmable gate arrays (FPGA), etc. The closely spaced plurality of strips of material may include global word lines, global bit lines, local word lines, local bit lines, bus bars, and the like.

According to the present invention, a method of fabricating a memory device as described herein is presented.

In order to provide a better understanding of the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings

Embodiments of the embodiments of the present invention will be described below with reference to the accompanying drawings. It is understood that the invention is not limited to the specific structural embodiment or method embodiments, and the invention may be practiced with other features, elements, methods and embodiments. The examples are intended to describe the invention and are not intended to limit the scope defined by the scope of the claims. Those skilled in the art will recognize various equivalent variations described below. Similar elements in the various embodiments will be designated by like reference numerals.

Figure 1 is a top plan view of a plurality of strips of material on a substrate and a plurality of landing zones connecting the sections of the strip of material in the X-Y plane. As shown in Fig. 1, the integrated circuit 100 includes a plurality of strips of material (e.g., strips 1-9). The plurality of strips of material comprise strips S(i), each strip of S(i) from 3 to n having a first section and a second section, the second section being separated from the first section by a gap. On the opposite side of the gap, the first section of strip S(i) (eg, S(5)) is aligned with the second section (eg, 151, 152) such that the first section and the second section are set to A straight line (for example, 105). Although the example of FIG. 1 is illustrated to n=9, n may be greater than 9, such as 32, 64, 128, and the like.

The integrated circuit includes a plurality of landing zones (e.g., 110a, 120a, 130a, 140a, 150a, 160a, and 170a). The plurality of landing zones include a plurality of landing zones A(i), i each landing zone A(i) from 3 to n-2 connecting one of the first segments of the plurality of strips of material S(i) to a plurality of strips A second section of one of the strips S(i+2) in the material, and the landing zone A(i) is disposed in a gap between the first section and the second section of the strip S(i+1).

For example, when i=3, the landing zone A(3) (eg, 130a) connects one of the first segment of the plurality of strips of material S(3) (eg, 131) to the strip of the plurality of strips of material S (5) one of the second sections (eg, 152), and the landing zone A(3) (eg, 130a) is disposed in the first section and the second section (eg, 141 and 142) of the strip S(4) The gap between them. For example, when i=6, the landing zone A(6) (eg, 160a) connects one of the first segments (eg, 161) of the strips S(6) in the plurality of strips of material to the strips S of the plurality of strips of material. (8) one of the second sections (eg, 182), and the landing zone A (6) (eg, 160a) is disposed in the first section and the second section (eg, 171 and 172) of the strip S (7) The gap between them.

In the present invention, i from 1 to n, (n-2) landing zones in the plurality of landing zones A(i) are connected to n of the plurality of S(i). For example, as shown in Figure 1, when n = 9, seven landing zones (e.g., 110a, 120a, 130a, 140a, 150a, 160a, and 170a) in the plurality of landing zones are connected to nine of the plurality of bars.

The strip S(i) has a first pitch (e.g., P1) in a direction orthogonal to the plurality of strips of material (e.g., the X direction), and the landing zone A(i) has a direction orthogonal to the plurality of strips of material A second pitch (eg, P2), the second pitch being twice the first pitch. The first pitch can be defined by a self-aligned double patterning process. For example, the first spacing can be less than 40 nm (nano).

The gap in the strip S(i) has a length (e.g., 101) in a direction parallel to the plurality of strips of material (e.g., the Y direction), and the landing zone A(i) has a width in a direction parallel to the plurality of strips of material ( For example, 102). The width of the landing zone A(i) is less than the length of the gap (e.g., 101) between the first section and the second section of the strip S(i+1). For example, when i=6, the width (eg, 102) of the landing zone A(6) (eg, 160a) is less than the gap (eg, 101) between the first section and the second section of the strip S(7). length.

Adjacent landing zones A(i) and A(i+1) in the landing zone have an offset in the direction parallel to the plurality of strips of material. For example, adjacent landing zones A (6) and A (7) (e.g., 160a and 170a) in the landing zone have an offset in a direction parallel to the plurality of strips of material.

In a direction parallel to the plurality of strips of material, the offset between adjacent landing zones A(i) and A(i+1) is at least the first segment and the second of strips S(i+1) The length of the gap between the segments. For example, when i=6, the offset between adjacent landing zones A(6) and A(7) (eg, 160a and 170a) is at least strip S in a direction parallel to the plurality of strips of material. (7) The length of the gap between the first section and the second section (e.g., 171 and 172).

The adjacent landing zones A(i) and A(i+1) in the landing zone may have a spacing in a direction parallel to the plurality of strips of material, the spacing and the first section of the strip S(i+1) The length of the gap between the second segments is equal. For example, when i=6, adjacent landing zones A(6) and A(7) (eg, 160a and 170a) in the landing zone may have a spacing in a direction parallel to the plurality of strips of material, the spacing The length of the gap (e.g., 101) between the first segment and the second segment (e.g., 171 and 172) of the strip S(7) is equal.

Adjacent landing zones A(i) and A(i+1) in the landing zone have an offset in the direction of the transmission orthogonal to the plurality of strips of material. For example, when i=3, adjacent landing zones A(3) and A(4) (eg, 130a and 140a) in the landing zone have a transmission pitch (P1) in a direction orthogonal to the plurality of strips of material. An offset.

Figure 2 is a plan view of the plurality of strips of material, the plurality of landing zones connecting the strips of material as described in Figure 1, and the plurality of second landing zones mirrored to the landing zone, in the X-Y plane. Similar elements in Fig. 2 will be given similar reference numerals as in Fig. 1.

In the example shown in FIG. 2, in the plurality of S(i), each S(i) of i from 3 to n may have a third segment, and the third segment is separated from the second segment by a gap. . For example, when i=5, strip S(5) may have a third segment (eg, 153) that is separated from the second segment (eg, 152) by a gap (eg, 240a). On the opposite side of the gap, the second section of strip S(i) (eg, S(5)) is aligned with the third section (eg, 152, 153) such that the second section and the third section are aligned (eg 105).

In addition to the plurality of landing zones (eg, 110a, 120a, 130a, 140a, 150a, 160a, and 170a) shown in FIG. 1, the integrated circuit can include a plurality of second landing zones (eg, 210a, 220a, 230a, 240a, 250a, 260a) And 270a). The plural second landing zone includes a plurality of landing zones A2(i), i from 3 to n. Each landing zone A2(i) connects a third section of one of the plurality of strips S(i) to a second section of one of the plurality of strips S(i+2), and a landing zone A2(i) is disposed in a gap between the second section and the third section in the strip S(i+1). For example, when i=3, the landing zone A2(3) (eg 230a) connects one of the plurality of strips S(3) in the third section (eg 133) to the strips in the plurality of strips of material S (5) one of the second sections (eg, 152), and the landing zone A2(3) (eg, 230a) is disposed in the second section and the third section (eg, 142 and 143) of the strip S(4) The gap between them.

The strip S(i) has a first pitch (e.g., P1) in a direction orthogonal to the plurality of strips of material (e.g., the X direction), and the landing zone A2(i) has a direction orthogonal to the plurality of strips of material A second pitch (eg, P2), the second pitch being twice the first pitch.

The landing zone A(i) and the plurality of second landing zones (eg, 210a, 220a, 230a, 240a, 250a, 260a, and 270a) in the plurality of landing zones (eg, 110a, 120a, 130a, 140a, 150a, 160a, and 170a) The landing zone A2(i) is mirrored in a direction parallel to the plurality of strips of material (eg, the Y direction).

In a plurality of strips of certain embodiments, the two left strips may not have a second section and the two right side strips may not have a first section. For example, the two left side strips S(1) and S(2) may have no second sections 112 and 122, and the second sections 112 and 122 are respectively located in the first section 111 and the landing zone of the strip S(1). Under 110a. For example, when n=9, the two right side strips S(n-1) and S(n) may not have the first section, and the first section is located in the landing zone 170a and the second zone of the strip S(9), respectively. Above segment 192 (not shown). Therefore, when i<3, the strip S(i) may not have a second segment; when i=3, the strips S(i-1) and S(i-2) may not have a second segment; when i= 4. The strip S(i-2) may not have a second segment.

In a plurality of strips of other embodiments, the two left strips can have a second section (eg, 112 and 122) and/or the two right side strips can have a first section. In these embodiments, the landing zone in the plurality of landing zones is not connected to the second section of the two left side bars, nor is the first section of the two right side bars connected. The second section of the two left side strips and the first section of the two right side strips can serve as dummy segments.

Although in the present embodiment, the plurality of strip materials and the plurality of landing areas are marked (i) from left to right, the plurality of strips may be landed as the sign (i) increases from right to left. The area is reduced from left to right. For example, if the sign (i) is increased from right to left, in the plurality of strip materials, the two right strips S(1) and S(2) may not have the first segment, and the two left strips S (n-1) and S(n) may not have the second segment. For example, if the sign (i) is increased from right to left, i in each of the landing zones A(i) from 3 to (n-2) in the plurality of landing zones is connected to the strips S of the plurality of strips of material. a first section of one of (i+2) to a strip S(i) of the plurality of strips of material, and disposed in the first section and the second section of the strip S(i+1) The gap between them.

FIG. 3 is a schematic view of a reticle 300 including a plurality of mask lines and a plurality of mask areas connected by a plurality of reticle segments separated by a gap, in an X-Y plane. The reticle can be a lithographic mask for defining a pattern of the integrated circuitry described herein. The pattern includes an opaque reticle strip and reticle region, and an open area between the reticle strips that allow light to pass through. The reticle is used in a self-aligned double patterning process to produce a plurality of strips of material and a plurality of landing zones as shown in FIG. The photomask can be formed on a substrate of an integrated circuit. Although the substrate can be mixed with a variety of suitable materials, in this embodiment, the material layer of the substrate may include a dielectric antireflective coating (DARC), a sacrificial layer, a semiconductor material layer, and an insulating layer 540 from top to bottom. And an etch stop layer. The sacrificial layer is, for example, an Advanced Patterning Film (APF), the semiconductor material layer is, for example, amorphous silicon, and the insulating layer 540 may include an intermetal dielectric (IMD) oxide, an etch stop layer. Silicon nitride (SiN) may be included. The intermetal dielectric layer oxide may include, for example, PEOX, HDP OX, PETEOS OX, FSG, and PSG. The layers of material may be formed on an array area of an integrated circuit memory, and the integrated circuit memory includes a memory cell array.

The reticle includes a plurality of reticle strips (eg, reticle strips 1-4). The plurality of reticle strips includes a plurality of reticle strips ML(j), each of the reticle strips ML(j) from 2 to m having a first segment (eg, 321 and 331) and a second segment (eg, 322) And 332), the second section is separated from the first section by a reticle gap (eg, 321 g, 331 g). For example, when j=2, the mask strip ML(2) has a first section 321 and a second section 322, and the second section 322 is separated from the first section 321 by a mask gap 321g.

The reticle 300 includes a plurality of reticle regions (e.g., 310a, 320a, 330a). The plurality of mask regions include a plurality of mask regions MA(j), and each of the mask regions MA(j) from 2 to m-1 connects one of the mask strips ML(j) in the plurality of mask strips. A second segment of the reticle ML(j+1) in the segment to the plurality of reticle strips, and disposed between the reticle ML(j) and the reticle ML(j+1).

For example, when j=2, the mask area MA(2) (for example, 320a) connects the first section 321 of one of the mask strips ML(2) in the plurality of mask strips to the mask in the plurality of mask strips. The second section 332 of one of the strips ML (3) is disposed between the mask strip ML (2) and the mask strip ML (3). For example, when m=4, j=m-1=3, the mask area MA(3) (for example 330a) connects the first section 331 of one of the mask strips ML(3) in the plurality of mask strips to A second section 342 of one of the reticle strips ML (4) in the reticle strip is disposed between the reticle strip ML (3) and the reticle strip ML (4).

The reticle gap (eg, 321 g) in the reticle has a length (eg, 301) in a direction parallel to the plurality of reticle strips (eg, the Y direction), and the reticle region (eg, 320a) is parallel to the plurality of reticle strips There is a width in the direction (for example 302). The width of the mask region (e.g., 302) and the length of the mask gap (e.g., 301) may be equal. A mask area MA(j) between the mask strip ML(j) and the mask strip ML(j+1) and an adjacent mask gap in the mask strip ML(j+1) are parallel to the plural The strip of reticle has an offset in the direction. For example, when j=2, the reticle area MA(2) (for example, 320a) between the reticle ML(2) and the reticle ML(3) is in phase with the reticle ML(3). The adjacent reticle gap (e.g., 331 g) has an offset in a direction parallel to the plurality of reticle strips. This offset is at least the length of the reticle gap (e.g., 301) or the width of the reticle region (e.g., 302).

The spacing between adjacent mask regions MA(j) and MA(j+1) in the plurality of mask regions in a direction orthogonal to the plurality of mask strips (eg, the X direction) through a plurality of mask strips (eg, P2) Has an offset. For example, when j=2, adjacent mask regions MA(2) and MA(3) (eg, 320a and 330a) in the plurality of mask regions pass through the plurality of masks in a direction orthogonal to the plurality of mask strips. A pitch P2 of the strip has an offset. The distance P2 between the reticle strips in the direction orthogonal to the plurality of reticle strips in Fig. 3 is the first pitch P1 of the strip material in the direction orthogonal to the plurality of strips of material as described in Fig. 1 double.

4 is a reticle including a plurality of reticle strips, a plurality of reticle regions, and a plurality of second reticle regions connected to the second and third segments of the reticle, as shown in FIG. schematic diagram. The second and third sections of the reticle are separated by a gap. The reticle region MA(j) in the plurality of reticle regions and the reticle region MA2(j) in the plurality of second mask regions are mirror images in a direction parallel to the plurality of reticle strips (e.g., the Y direction). The reticle is used in a self-aligned double patterning process to produce a plurality of strips of material and a plurality of landing zones as described in FIG. Similar elements in Fig. 4 are numbered similarly in Fig. 3.

In the embodiment shown in Fig. 4, each of the mask strips ML(j) of j from 2 to m may have a third section, the third section being separated from the second section by a mask gap . For example, when j=2, the reticle ML(2) may have a third segment (eg, 323) separated from the second segment (eg, 322) by a reticle gap.

In addition to the plurality of reticle regions (e.g., 310a, 320a, 330a) shown in FIG. 3, the reticle can include a plurality of second reticle regions (e.g., 410a, 420a, 430a). The plurality of second mask regions include a plurality of mask regions MA2(j), j from 2 to m-1. Each reticle region MA2(j) connects one of the third segment of the reticle ML(j) in the plurality of reticle strips to one of the second regions of the reticle ML(j+1) in the plurality of reticle strips The segment is disposed between the mask strip ML(j) and the mask strip ML(j+1). For example, when j=2, the mask area MA2(2) (eg, 420a) connects one of the third sections (eg, 323) of the mask strip ML(2) in the plurality of mask strips to the plurality of mask strips. A second section (for example, 332) of one of the reticle strips ML (3) is disposed between the reticle strip ML (2) and the reticle strip ML (3).

The reticle gap in the mask strip ML(j) has a length in a direction parallel to the plurality of reticle strips, and the reticle region MA2(j) in the plurality of second mask regions is parallel to the direction of the plurality of reticle strips There is a width on it. The width (e.g., 302) of the reticle region MA2(j) in the plurality of second mask regions may be equal to the length of the reticle gap (e.g., 301). In the plurality of second mask regions, one of the mask regions MA2(j) between the mask strip ML(j) and the mask strip ML(j+1) and the mask strip ML(j+1) The adjacent reticle gap has an offset in a direction parallel to the plurality of reticle strips. For example, in the plurality of second mask regions, when j=2, the mask region MA2(2) (for example, 420a) and the light between the mask strip ML(2) and the mask strip ML(3) An adjacent mask gap (e.g., 332g) in the cover strip ML(3) has an offset in a direction parallel to the plurality of mask strips. This offset is at least the length of the reticle gap (e.g., 301) or the width of the reticle region (e.g., 302).

The adjacent mask regions MA2(j) and MA2(j+1) of the plurality of second mask regions pass through a distance of the plurality of mask strips in a direction orthogonal to the plurality of mask strips (eg, the X direction) (eg, P2) has an offset. For example, when j=2, the mask regions MA2(2) and MA2(3) in the plurality of second mask regions have a pitch P2 through the plurality of mask strips in a direction orthogonal to the plurality of mask strips. An offset. The distance P2 between the reticle strips in the direction orthogonal to the plurality of reticle strips in Fig. 4 is the first pitch P1 of the strip material in the direction orthogonal to the plurality of strips of material as described in Fig. 1 double.

In a plurality of strips of reticle material, a leftmost reticle strip (eg, ML(1)) can have a second section (eg, 312) and/or a rightmost reticle strip (eg, ML(4)) There is a first section (for example, located on the reticle gap 341g, not shown). The reticle region MA(j) in the plurality of reticle regions and the reticle region MA2(j) in the plurality of second reticle regions are not connected to the second segment of the leftmost reticle (for example, 312), nor Connect the first section of the rightmost reticle. In the embodiment illustrated in Figure 4, the second section of the leftmost reticle strip (e.g., 312) and the first section of the rightmost reticle strip can serve as a dummy line. In an embodiment, the dummy strips may be mirror images, depending on the wiring and circuit design.

In a self-aligned double patterning process, such as the process described in Figures 5-20, the second section of the leftmost mask strip in the mask and the first section of the rightmost mask strip are available. As a dummy strip for manufacturing the second section of the two left side strips (for example, 112, 122 of FIG. 2) and the first section of the two right side strips as shown in FIG.

5 to 20 illustrate that a self-aligned double patterning process is performed on the substrate using a reticle as described in FIG. 3 to fabricate a plurality of strip materials and a plurality of strip materials as described in FIG. The rehearsal landing zone of the section.

Figures 5 through 12 and 13 through 20 illustrate the fabrication steps for using the same reticle (e.g., 300 of Figure 3) in a self-aligned double patterning process. The difference is that the figures 5 to 12 show the section cut by the AA line of a mask area between the two mask strips as shown in FIG. 3, and the figures 13 to 20 are as shown in FIG. A section cut through the BB line of a reticle gap in a reticle is shown. The cross-sections shown in Figures 5 through 20 are located in the X-Z plane, wherein the Z-direction is orthogonal to the X-Y plane as shown in Figures 1-4. Here, the self-aligned double patterning process using the photomask causes the strip S(i) to have a first pitch in a direction orthogonal to the strip material, and the landing area A(i) is orthogonal to the strip The material has a second spacing in the direction and the second spacing is twice the first spacing.

FIG. 5 is a cross-sectional view of the photomask formed on the substrate of an integrated circuit (for example, 300 in FIG. 3) in the XZ plane, which is through two reticle strips as shown in FIG. A cross-sectional view taken along line AA of a reticle region (e.g., 330a) between (e.g., 331 and 342). The substrate of the present embodiment has a plurality of layers of material, and may include a dielectric anti-reflective coating (DARC) 570, a sacrificial layer 560, a semiconductor material layer 550, an insulating layer 540, and an etch stop layer 530 from top to bottom. The sacrificial layer 560 is, for example, an advanced pattern film (APF), the semiconductor material layer 550 is, for example, an amorphous germanium, the insulating layer 540 may include an inter-metal dielectric (IMD) oxide, and the etch stop layer 530 may include tantalum nitride (SiN). . These layers of material may be formed on an array region 520 of an integrated circuit comprising a memory cell array.

Figure 5 is a cross-section (e.g., 581) of a reticle (e.g., 311 of Figure 3), a cross-section (e.g., 582) of an adjacent reticle (e.g., 321 of Figure 3), and a mask area MA. (3) (for example, 330a of Fig. 3) (e.g., 583), the mask area MA(3) is connected to the first section of the mask strip ML(3) (for example, 331 of Fig. 3) to the mask strip The second segment of ML(4) (e.g., 342 of Figure 3). The mask area MA (3) (for example, 330a of Fig. 3) is disposed between the mask strip ML (3) and the mask strip ML (4).

FIG. 6 illustrates the result of etching the sacrificial layer (sacrificial material) 560, stopping at the semiconductor material layer 550, and removing the photomask 300 using the photomask 300 (FIG. 3). The etching step uses a photomask (for example, 300 in FIG. 3), and generates a plurality of sacrificial strips (eg, 661 and 662) and a plurality of sacrificial regions (eg, 663), and the plurality of sacrificial strips and the plurality of sacrificial regions correspond to the plural number shown in FIG. A reticle (eg, 581, 582) and a plurality of reticle regions (eg, 583).

Figure 7 illustrates the deposition of a spacer material (e.g., 790) on a portion of a plurality of sacrificial strips (e.g., 661 and 662) and a plurality of sacrificial regions (e.g., 663) that are fabricated on an integrated circuit, such as a low temperature. Oxide.

Figure 8 illustrates the etch spacer material (e.g., 790 of Figure 7) to form a plurality of sidewall spacers on the plurality of sacrificial layers and the sacrificial regions. For example, sidewall spacers 891a and 891b are formed on sacrificial strips 661, sidewall spacers 892a and 892b are formed on sacrificial strips 662, and sidewall spacers 893a and 893b are formed on sacrificial regions 663.

FIG. 9 illustrates the result of removing the plurality of sacrificial layers and the sacrificial regions after forming the plurality of sidewall spacers in the plurality of sacrificial layers and the sacrificial regions. The sidewall spacers (e.g., 891a, 891b, 892a, 892b, 893a, 893b) remain on the layer of semiconductor material 550 after the plurality of sacrificial layers and sacrificial regions are removed.

Figure 10 illustrates the result of etching the layer of semiconductor material 550 using sidewall spacers as an etch mask.

FIG. 11 illustrates the result of etching the insulating layer 540 under the semiconductor material layer 550 to form a plurality of trenches (eg, 1111~1116, 1119) in the insulating layer. Since the sidewall spacers and the insulating layer (eg, 540) include an oxidized material, the sidewall spacers (eg, 891a, 891b, 892a, 892b, 893a, 893b) are removed during the etching process to form a plurality of trenches (eg, 1111~) 1116, 1119).

Figure 12 illustrates the results of depositing a layer of material in a trench (e.g., 1111~1116) to form a plurality of strips of material and a plurality of landing zones. The layer of material may comprise a conductive material such as copper. The cross section shown in Fig. 12 corresponds to the cross section cut by the CC line of the landing zone shown in Fig. 1. For example, the bars 1291, 1292, 1293, 1294, 1295, and 1299 shown in FIG. 12 may correspond to the first segment and the strip 9 of the strips 1, 2, 3, 4, and 5 shown in FIG. The second section. The zone 1296 shown in Fig. 12 may correspond to the landing zone 160a of the first section (e.g., 161) of the connecting strip S(6) of Fig. 1 to the second section (e.g., 182) of the strip S(8). Wherein the landing zone 160a is disposed between the first section and the second section (eg, 171 and 172) of the strip S(7). After depositing the layer of material in the trench, the plurality of strips of material and the plurality of landing zones are planarized. The plurality of strips of material and the plurality of landing zones may be disposed on a metal layer, such as gold layer 2.

13 to 20 are cross-sectional views showing the manufacturing steps cut by the BB line by the reticle gap of a reticle as shown in Fig. 3. Figure 13 is a cross-sectional view showing a reticle (e.g., 300 of Fig. 3) formed on a substrate of an integrated circuit, the cross-sectional view being through a reticle gap of a reticle as shown in Fig. 3. Cutaway view of the BB line. The substrate may have a multilayer material as described in Figure 5.

Figure 13 is a cross-sectional view of a first segment of a mask strip ML (1) (e.g., 311 of Figure 3) in the XZ plane (e.g., 1381), an adjacent mask strip ML (2) (e.g., the third A cross section of the first section of the graph 321) in the XZ plane (eg, 1382) and a second section of a reticle ML (4) (eg, 342 of FIG. 3) in the XZ plane (eg, 583). Figure 13 also shows that the reticle gap 1383 is disposed between the sections 1382 and 1384. The mask gap 1383 shown in FIG. 13 corresponds to the mask gap 331g shown in FIG. 3, and is disposed on the mask strip ML(3) (for example, 331, 332) in a direction parallel to the plurality of mask strips. Between a segment and a second segment, and disposed in a direction orthogonal to the plurality of reticle strips in a first segment of the reticle ML(2) and the reticle ML(4) (eg, Figure 3) Between the second sections of 321 and 342).

FIG. 14 illustrates the result of etching the sacrificial layer (sacrificial material) 560, stopping at the semiconductor material layer 550, and removing the photomask 300 using the photomask 300 (FIG. 3). The etching step uses a reticle (eg, 300 of FIG. 3) and produces a plurality of sacrificial strips (eg, 1461, 1462, 1464) corresponding to the plurality of reticle strips shown in FIG. 13 (eg, 1381, 1382, 1384) ). The etching step forms a gap (eg, 1463) between the sacrificial strips (eg, 1462 and 1464) in the sacrificial layer (sacrificial material) 560 and corresponds to the reticle gap 1383 shown in FIG.

Figure 15 illustrates the deposition of a spacer material (e.g., 790) on a portion of a complex circuit comprising a plurality of sacrificial strips (e.g., 1461, 1462, 1464) and a gap (e.g., 1463). The gap (e.g., 1463) is interposed. Between the sacrificial strips (eg, 1462 and 1464) in the sacrificial layer (sacrificial material) 560, the spacer material is, for example, a low temperature oxide.

Figure 16 illustrates the etch spacer material (e.g., 790 of Figure 7) to form a plurality of sidewall spacers on the plurality of sacrificial layers and the sacrificial regions. For example, sidewall spacers 1691a and 1691b are formed on sacrificial strips 1461, sidewall spacers 1692a and 1692b are formed on sacrificial strips 1462, and sidewall spacers 1694a and 1694b are formed on sacrificial regions 1464.

Figure 17 illustrates the result of removing a plurality of sacrificial strips (e.g., 1461, 1462, 1464) after forming a plurality of sidewall spacers at the plurality of sacrificial layers. After removing the plurality of sacrificial layers, sidewall spacers (eg, 1691a, 1691b, 1692a, 1692b, 1694a, 1694b) remain on the layer of semiconductor material 550.

Figure 18 illustrates the result of etching the layer of semiconductor material 550 using sidewall spacers as an etch mask.

FIG. 19 illustrates the use of sidewall spacers as an etch mask to etch the insulating layer 540 under the semiconductor material layer 550 to form a plurality of trenches (eg, 1911-1915, 1918, 1919) in the insulating layer.

Figure 20 illustrates the deposition of a layer of material in a trench (e.g., 1911-1915, 1918, 1919) to form a plurality of strips of material and a plurality of landing zones. The layer of material may comprise a conductive material such as copper. The section shown in Fig. 20 may correspond to the section cut by the DD line of the landing zone shown in Fig. 1. For example, the strips 2091, 2092, 2093, 2094, 2098, and 2099 shown in FIG. 20 may correspond to the first section and the strips 8, 9 of the strips 1, 2, 3, and 4 shown in FIG. The second section. The zone 2095 shown in Fig. 20 may correspond to the landing zone 150a of the first section (e.g., 151) of the connecting strip S(5) of Fig. 1 to the second section (e.g., 172) of the strip S(7). Wherein the landing zone 150a is disposed between the first section and the second section (eg, 161 and 162) of the strip S(6). After depositing the layer of material in the trench, the plurality of strips of material and the plurality of landing zones are planarized. The plurality of strips of material and the plurality of landing zones may be disposed on a metal layer, such as gold layer 2.

Figure 21A is a cross-sectional view of a landing zone and adjacent strips of material in the X-Z plane. The landing zone (e.g., 2103) depicted in Figure 21A and the adjacent strip of material (e.g., 2102, 2104) may correspond to the landing zone (e.g., 1296) depicted in Figure 12 and the adjacent strip of material (e.g., For example, 1295, 1299), or a landing zone (eg, 2095) corresponding to that depicted in FIG. 20 and an adjacent strip of material (eg, 2094, 2098). For the sake of simplicity, the insulating material between the landing zone and the adjacent strip material is omitted in the 21A and 21B drawings.

A layer of internal connectors (e.g., 2101) can be formed on the landing zone, for example, using different patterning steps in the landing zone with adjacent strips of material. The strip material has a first pitch in a direction orthogonal to the strip material (for example, the X direction), and the landing region has a second pitch in a direction orthogonal to the strip material, the second pitch being the first Double the spacing. The first spacing (e.g., P1) and the second spacing (e.g., P2) are shown in Figure 1. In an embodiment of the invention, the width of the in-layer connector is less than the second spacing.

Figure 21B is a cross-sectional view of a capping area and an adjacent strip of material in the X-Z plane, as compared to the landing zone of Figure 21A. Figure 21B illustrates a landing zone (e.g., 2103) at a higher level and an adjacent strip of material (e.g., 2112 and 2114) and a landing zone (e.g., 2103) and a phase at a lower level as depicted in Figure 21A. The adjacent strips of material (e.g., 2102 and 2104) are aligned and have a tight spacing from the landing zone of the lower layer (e.g., 2103) and the adjacent strip of material (e.g., 2102 and 2104). The strip material and landing zone at the lower and upper layers may comprise a high density patterned strip of material and landing zone as described in Figures 1 and 2. An in-layer connector (e.g., 2101) can be connected to a landing zone (e.g., 2103) at a lower level to a cover area (e.g., 2114) at a higher level.

Fig. 22A is a view showing a second mask other than the mask including the mask strip ML(j), as described in Figs. The second mask 2200 includes mask regions 2201 and 2202 shown in the X-Y plane for cutting the end points of the plurality of strips of material S(i) as shown in Figs. The second reticle may also include other patterns (e.g., reticle regions and open regions) to fabricate the components of the area surrounding the integrated circuit. Elements of the surrounding area may include, for example, a controller, a voltage generator, an address generator, a general purpose decoder, a gate, a patterned metal layer, and the like. Figure 22B shows the end point after the strip material S(i) is cut using the second mask. Figures 22A and 22B are all shown in the X-Y plane.

Figure 23 is a circuit diagram showing an embodiment of a NAND string of XY planes in a memory cell block, the memory cell block being connected to a local and global word line driver in a 3D memory, wherein A strip of material in a plurality of strips of material as described in Figures 1 and 2.

The NAND string corresponds to four pages of the memory cell: page 0, page 1, page 2, and page 3. NAND strings share even and odd ground select lines (GSL) on even and odd pages, and have separate string select lines (SSL), even and odd bits at opposite ends of the block. The meta-line contact structure is coupled to the global bit line BL-N and coupled to the even and odd common source (CS) lines 2320 and 2321. The serial connection is connected to the corresponding global bit lines BL-0 to BL-3 by respective first serial selection switches (eg, 2330, 2331, 2332, and 2333), and the first serial selection switch may also be referred to as serial selection. Line switch (SSL switch). The series is connected to the even and odd common source lines of the plane by respective second series selection switches (eg, 2340, 2341), which may also be referred to as a ground select switch. The plurality of NAND strings in the memory cell block have a channel line between the first string select switch and the second string select switch, and the NAND string share is located between the first string select switch and the second string select switch A set of word lines between (eg, WL0-WL1, ..., WL(in-2), WL(in-1), WL(in), ..., WL(i), ..., WL(i+n) , WL(i+n+1), WL(i+n+2), ..., WL62-WL63). The memory can include a set of local word line drivers (e.g., 2360~2370), abbreviated as LWLD, to drive individual word lines in a set of word lines in the selected block of memory cells.

The memory can include a set of global word lines (e.g., 2311g) connected to a set of local word line drivers (e.g., 2360~2370) within the memory block. The memory includes a global word line driver (e.g., 2311) that can drive a global word line (e.g., 2311g). In this embodiment, there are N parallel global word lines that can be connected through a local word line decoder. (For example, 2380) The memory cell block selected in the memory, and the local word line driver connected. Although only one of the even or odd pages is depicted in this embodiment, the global word line can be connected to a number of block local word line drivers in the memory. In the embodiment of the present invention, for example, the high-density patterned strip material and landing zone described in FIGS. 1 and 2 may be implemented in a global word line (eg, 2311 g) connected to a global word line driver (eg, 2311) to Local word line driver (for example, 2360~2370).

A global word line decoder (e.g., 2390), abbreviated GWL, is coupled to the global word line driver using a conductor (e.g., 2395) in a patterned conductive layer. The conductor can pass one or more output signals to the global word line driver. A local word line decoder (eg, 2380), abbreviated as LWL, is connected to a local word line driver (eg, 2360~2370) using a conductor in a patterned conductive layer to connect the switching signal, the bias signal, Address signal and/or other control signals to the local word line driver. The connection from the local word line decoder 2380 can include a control signal line 2385 that transmits control signals to each of the local word line drivers in the first subset of the local word line driver groups of the block. And passing control signals to each of the local word line drivers in the second subset of the local word line driver groups of the block.

A local word line driver (eg, 2366) can include an N-type metal oxide semiconductor (NMOS) transistor having an input, an output, and a control gate, the input being coupled to the global word A global word line (eg, 2311g) in the set of meta-wires, the output is connected to a word line in the set of word lines (eg, WL(i+n)), and the control gate is connected from a local word line driver ( For example, a control signal of 2390). The global word line driver (e.g., 2311) can include a layer of shifters that shift the output voltage level in response to one or more output signals from a global word line decoder (e.g., 2390). For example, the layer shifter can change the output voltage level according to the requirements of the page erase operation and the requirements of the read, write, and block erase operations.

The high-density patterned strip material and landing zone as described in Figures 1 and 2 can be used in other integrated circuit applications. For example, an integrated circuit including a memory array can include a page buffer coupled to a memory array, a data path, an ECC circuit, and the like. The page buffer can include a sense amplifier and a program buffer. The sense amplifier and the stylized buffer in the page buffer can be coupled to the memory array by a data line. The data path can be coupled to an input/output system and alternately coupled to an external circuit of the integrated circuit. In the embodiment of the present invention, the high-density patterned strip material and the landing area as described in FIGS. 1 and 2 can be used as a data line to couple the page buffer and the memory array.

In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

S(1)~S(9), 131: strip 100: integrated circuit 101: length of the gap 102: width of the landing zone 105: straight lines 110a, 120a, 130a, 140a, 150a, 160a, 170a, 210a, 220a, 230a, 240a, 250a, 260a, 270a, 2103: landing zones 141, 151, 161, 171, 1291, 1292, 1293, 1294, 1295, 1296, 2091, 2092, 2093, 2094: first sections 112, 122, 142, 152, 162, 172, 182, 192, 1299, 2095, 2098, 2099: second section 133, 143, 153: third section 1295, 1299, 2094, 2098, 2112, 2114: strip material 300 : Photomask 301: length of mask gap 302: width of mask area ML (1) ~ ML (4), 311, 331, 342, 581, 582, 1381, 1382, 1384: mask strips 310a, 320a, 330a, 420a, 583, 2201, 2202: reticle regions 321, 331: first segments 321g, 331g, 1383: reticle gaps 312, 322, 332, 342: second segment 530: etch stop layer 540: insulation Layer 550: semiconductor material layer 560: sacrificial layer 570: dielectric anti-reflective coating 661, 662, 1461, 1462, 1464: sacrificial strip 1463: gap 663: sacrificial region 790: spacer material 891a 891b, 892a, 892b, 893a, 893b, 1691a, 1691b, 1692a, 1692b, 1694a, 1694b: sidewall spacers 1111~1116, 1119, 1911~1915, 1918, 1919: Trench 2010: In-layer connector 2114: cover Areas 2320, 2321: Common Source Lines 2330, 2331, 2332, 2333: First Tandem Select Switch 2340, 2341: Second Tandem Select Switch 2360~2370: Local Word Line Driver 2311: Global Character Driver 2311g: Global character line 2366: local word line driver 2380: local word decoder 2385: control signal line 2390: global character decoder 2395: conductor P1: first pitch P2: second pitch X, Y, Z: coordinate axis

Figure 1 is a top plan view of a plurality of strips of material on a substrate and a plurality of landing zones connecting the sections of the strip of material. Figure 2 is a plan view of a plurality of strips of material, a plurality of landing zones joined to the sections of the strip of material as described in Figure 1, and a plurality of second landing zones mirrored to the landing zone. Figure 3 is a schematic illustration of a reticle comprising a plurality of reticle strips and a plurality of reticle regions connecting the plurality of reticle segments separated by the gap. 4 is a schematic diagram of a reticle including a plurality of reticle strips, a plurality of reticle regions, and a plurality of second reticle regions connected to the second and third segments of the reticle. Figures 5 through 12 illustrate the manufacturing steps of the cross-section cut through the line AA of a reticle region between the two reticle strips as shown in Figure 3. Figures 13 through 20 illustrate the manufacturing steps of the cross section cut through the BB line of a reticle gap in a reticle as shown in Fig. 3. Figure 21A is a cross-sectional view of a landing zone and adjacent strips of material in the X-Z plane. Figure 21B is a cross-sectional view of a cover area and adjacent strips of material, as compared to the higher level of the landing zone shown in Figure 21A. Fig. 22A is a view showing a second mask other than the mask including the mask strip ML(j), as described in Figs. Figure 23 is a circuit diagram showing an embodiment of a NAND string of XY planes in a memory cell block, the memory cell block being connected to a local and global word line driver in a 3D memory, wherein A strip of material in a plurality of strips of material as described in Figures 1 and 2.

S(1)~S(9), 131: Bar 100: Integrated circuit 101: Length of the gap 102: Width of the landing zone 105: Straight lines 110a, 120a, 130a, 140a, 150a, 160a, 170a: Landing area 141 , 151, 161, 171: first section 142, 152, 162, 172, 182, 192: second section P1: first pitch P2: second pitch X, Y: coordinate axis

Claims (10)

An integrated circuit comprising: a plurality of strips of material on a substrate, the plurality of strips of material comprising a plurality of strips S(i), each strip of S(i) from 3 to n having a first segment and a second section, the second section being separated from the first section by a gap; and a plurality of landing zones including a plurality of landing zones A(i), i from each of 3 to n-2 The landing zone A(i) is connected to the first section of one of the strips S(i) of the plurality of strips of material to the second section of one of the strips S(i+2) of the plurality of strips of material, and is disposed at a gap between the first segment and the second segment in the strip S(i+1); wherein the strips S(i) have a first pitch in a direction orthogonal to the plurality of strips of material, The landing zones A(i) have a second spacing in the direction orthogonal to the plurality of strips of material, the second spacing being twice the first spacing. The integrated circuit of claim 1, wherein the gaps in the strips S(i) have a length in a direction parallel to the plurality of strips of material, the landing areas A(i) being parallel to The plurality of strips of material have a width in the direction that is less than a length of a gap between the first section and the second section of the strip S(i+1), and adjacent landing zones in the landing zones A(i) and A(i+1) have an offset in this direction parallel to the plurality of strips of material. The integrated circuit of claim 1, wherein adjacent landing zones A(i) and A(i+1) of the landing zones have a direction parallel to the plurality of strips of material. The pitch is equal to the length of the gap between the first segment and the second segment of the strip S(i+1). The integrated circuit of claim 1, wherein adjacent landing zones A(i) and A(i+1) of the landing zones are transmitted in a direction orthogonal to the plurality of strips of material A first spacing has an offset. The integrated circuit of claim 1, wherein in the plurality of strips S(i), each strip S(i) of i from 3 to n has a third section, the third section Separating from the second segment through a gap, and the integrated circuit further includes: a plurality of second landing zones including a plurality of landing zones A2(i), i from each of the landing zones of 3 to n A2(i) connects a third section of one of the strips S(i) of the plurality of strips of material to a second section of one of the strips S(i+2) of the plurality of strips of material, and is disposed on the strip S A gap between the second segment and the third segment in (i+1). The integrated circuit of claim 5, wherein the second landing areas A2(i) have the second spacing in a direction orthogonal to the plurality of strips of material, the second spacing being Double the first spacing. A method of manufacturing an integrated circuit, comprising: forming a reticle on a substrate, the reticle comprising: a plurality of reticle strips comprising a plurality of reticle strips ML(j), j from 2 to m Each of the mask strips ML(j) has a first section and a second section, the second section being separated from the first section by a mask gap; and a plurality of mask regions, the plurality of masks The area includes a plurality of reticle regions MA(j), each of the reticle regions MA(j) from 2 to m-1 is connected to the first segment of one of the reticle strips ML(j) in the plurality of reticle strips to a second section of the reticle strip ML(j+1) in the plurality of reticle strips, disposed between the reticle strip ML(j) and the reticle strip ML(j+1); and utilizing the light A self-aligned double patterning process is performed on the substrate. The manufacturing method of claim 7, wherein the gaps in the mask strips ML(j) have a length in a direction parallel to the plurality of mask strips, the mask regions MA(j) a mask area MA(j) and a mask strip ML having a width in a direction parallel to the plurality of mask strips and located between the mask strip ML(j) and the mask strip ML(j+1) An adjacent mask gap in (j+1) has an offset in the direction parallel to the plurality of mask strips. The manufacturing method of claim 7, wherein adjacent mask regions MA(j) and MA(j+1) of the mask regions are transmitted in a direction orthogonal to the plurality of mask strips. The spacing of the plurality of reticle strips has an offset. The manufacturing method according to claim 7, wherein in the plurality of mask strips ML(j), each of the mask strips ML(j) having j from 2 to m has a third section, the The three sections are separated from the second section by a mask gap, and the mask further comprises: a plurality of second mask regions, the plurality of mask regions including a plurality of mask regions MA2(j), j from 2 Each of the reticle regions MA2(j) to m-1 connects a third segment of the reticle ML(j) in the plurality of reticle strips to the reticle ML (j+) in the plurality of reticle strips 1) One of the second sections and disposed between the mask strip ML(j) and the mask strip ML(j+1).