TWI594378B - Non-volatile memory cell and manufacture method of the same - Google Patents

Description

Non-volatile memory unit and manufacturing method thereof

The invention provides a non-volatile memory and a manufacturing method thereof, wherein the non-volatile memory unit comprises a selection gate, an erase gate, a floating gate and a coupling gate.

In general, non-volatile memory uses a three-layer conductor structure to form a split gate structure. A selective gate is generally formed by a first conductor layer, a second gate layer forms a floating gate, and a third multi-conductor layer forms a coupling gate, wherein the coupled gate is also referred to as a control Coupling gate.

In a three-conductor layer structure, the floating gate and the top of the source junction are typically completely covered by the coupled gate. Therefore, when the erase operation is performed while charging the coupled gate and the source junction with a relatively high voltage, a high band-to-band leakage current is generated. In order to reduce the leakage current between the strips, the vertical electric field under the floating gate is usually reduced by adding a dielectric layer under the source junction engineering or under the floating gate.

Although the above method can reduce the leakage current between the bands, it also makes the size of the memory unit larger, and the performance of the memory unit, such as writing, reading or wiping In addition, it has an adverse effect.

It is an object of the present invention to provide a non-volatile memory cell comprising a select gate, a wipe gate, a floating gate, a coupled gate, and one or more dielectric layers. The erase gate is located between the coupled gate and the first doped region. When the erase operation is performed, electrons can tunnel from the floating gate to the erase gate to complete the erase operation, and the coupled gate and the second can be reduced. Inter-band leakage current between a doped region.

It is still another object of the present invention to provide a method of fabricating a non-volatile memory by separately depositing and patterning four conductor layers to form a select gate, an erase gate, a floating gate, and a coupled gate. Wherein the erase gate is located between the coupled gate and the first doped region, and when the erase operation is performed, electrons can tunnel from the floating gate to the erase gate to complete the erase operation, and the coupled gate can be lowered Inter-band leakage current between the first doped regions.

Another object of the present invention is to provide a method for fabricating a non-volatile memory. The memory cell fabricated by the method has a protruding structure on the sidewall of the floating gate adjacent to the erase gate. This protruding structure will facilitate the injection of electrons from the floating gate into the erase gate during the erase operation.

To achieve the above objective, the present invention provides a non-volatile memory cell, comprising: a substrate including a first doped region and at least a second doped region, wherein the first doped region and the second doped region are a gate electrode is disposed on the substrate between the first doped region and the second doped region; a wipe gate is located above the first doped region; and a floating gate is located at the select gate And between the erase gates; a coupled gate located at the erase gate, the floating gate and the portion Selecting a top of the projection of the gate; and one or more dielectric layers for the insulating layer, located adjacent to the selected gate, the erase gate, the floating gate, the coupled gate, or the first doped region between.

To achieve the above objective, the present invention provides a non-volatile memory cell, comprising: a substrate including a first doped region and at least a second doped region, wherein the first doped region and the second doped region are a gate electrode is disposed on the substrate between the first doped region and the second doped region; a wipe gate is located above the first doped region; and a floating gate is located at the select gate And between the erase gates; a coupled gate located above the projection of the floating gate; and one or more dielectric layers for the insulating layer, adjacent to the selected gate, the erase gate, Between the floating gate, the coupled gate or the first doped region.

In order to achieve the above object, the present invention provides a method for fabricating a non-volatile memory cell, the method comprising: providing a substrate; forming a selective gate on the substrate; forming a first substrate dielectric layer covering the selected gate And a substrate, and forming a first doped region in the substrate; forming a erase gate on the first substrate dielectric layer, wherein the erase gate is above the first doped region; forming a cladding erase gate a gate dielectric layer is formed by a gate; a floating gate is formed between the gate and the erase gate; and a coupled gate dielectric layer is formed to cover the exposed first substrate dielectric layer and the erase gate a pole dielectric layer and a floating gate; and a coupling gate formed on the coupled gate dielectric layer.

To achieve the above object, the present invention provides a method of fabricating a non-volatile memory cell, the method comprising: providing a substrate; forming a selective gate on the substrate; forming a first doped region, a first doping a dielectric layer, a gate removing gate, and a gate removing dielectric layer, wherein the first doping region is disposed in the substrate, and the first doped dielectric layer is disposed on the substrate and is located at the first doping In the region, the erase gate is disposed on the dielectric layer of the first doped region, and the gate is erased The cover dielectric layer is disposed on the erase gate; the portion of the first doped region dielectric layer and the partial erase gate cover the dielectric layer are removed, so that the first doped region dielectric layer and the erase gate cover dielectric The length or cross-sectional area of the layer is smaller than the erase gate; forming a tunneling dielectric layer to cover the exposed selected gate, the erase gate, the first doped dielectric layer, the erase gate cover dielectric layer, and a surface of a portion of the substrate; forming a floating gate between the select gate and the erase gate, wherein the floating gate has a protruding structure adjacent to the sidewall of the erase gate; forming a coupled gate dielectric layer Covering the exposed tunneling dielectric layer and the floating gate; and forming a coupled gate on the coupled gate dielectric layer.

In an embodiment of the non-volatile memory cell of the present invention, the substrate includes a surface dielectric layer between the substrate and the select gate, the floating gate, and the erase gate.

In an embodiment of the non-volatile memory cell of the present invention, the dielectric layer comprises: a first substrate dielectric layer covering the sidewalls and the upper surface of the gate, and having a thickness between 10 Å and 150 Å; a gate dielectric layer encapsulating the periphery of the gate and between the erase gate and the substrate, the floating gate and the coupling gate, and having a thickness between 100 Å and 600 Å; a coupled gate dielectric layer, Located between the coupled gate and the erase gate, the floating gate, and the select gate, the thickness is between 100 Å and 300 Å.

In an embodiment of the non-volatile memory cell of the present invention, the material of the first substrate dielectric layer, the erase gate dielectric layer, and the coupled gate dielectric layer is a yttria or high dielectric material composite.

In an embodiment of the non-volatile memory cell of the present invention, the dielectric layer includes: a first substrate dielectric layer between the floating gate and the selected gate and between the floating gate and the substrate, and the thickness is between Between 50 Å and 200 Å; and a wiper dielectric layer between the floating gate and the erase gate, between 50 Å and 200 Å thick.

In an embodiment of the non-volatile memory cell of the present invention, the material of the first substrate dielectric layer and the coupled gate dielectric layer is a yttria or high dielectric material composite.

In an embodiment of the non-volatile memory cell of the present invention, the dielectric layer includes a selective gate capping dielectric layer disposed on the upper surface of the select gate.

In an embodiment of the non-volatile memory cell of the present invention, wherein the gate thickness of the gate is between 200 Å and 2000 Å, the thickness of the erase gate is between 200 Å and 2000 Å, and the thickness of the floating gate is between 150 Å. Between 2000Å.

In an embodiment of the non-volatile memory cell of the present invention, the sidewall of the floating gate adjacent to the erase gate is planar or has a convex structure.

In an embodiment of the non-volatile memory cell of the present invention, the protruding structure of the floating gate is between the first doped region and the erase gate.

In an embodiment of the method of fabricating a non-volatile memory cell of the present invention, the coupling gate is located above the projection of the erase gate, the floating gate, and the portion of the select gate.

In an embodiment of the method of fabricating a non-volatile memory cell of the present invention, wherein the coupling gate is above the projection of the floating gate.

In an embodiment of the method for fabricating a non-volatile memory cell of the present invention, the method includes the steps of: forming a second doped region in the substrate, wherein the first doped region is adjacent to the second doped region.

In an embodiment of the method for fabricating a non-volatile memory cell of the present invention, the method includes the following steps: after forming the first substrate dielectric layer, forming at least one sacrificial spacer on the first substrate dielectric layer, wherein the sacrificial The spacer is adjacent to the select gate; and after forming the erase gate dielectric layer, the sacrificial spacer between the erase gate and the select gate is removed.

In an embodiment of the method for fabricating a non-volatile memory cell of the present invention, the method includes the steps of: forming a first substrate dielectric layer over the select gate and the substrate after forming the select gate; forming at least one sacrificial spacer a first substrate dielectric layer, wherein the sacrificial spacer is adjacent to the select gate; forming a second substrate dielectric layer overlying the exposed first substrate dielectric layer and the sacrificial spacer; forming an erase gate On the second substrate dielectric layer, wherein the erase gate is located above the first doped region and between the two adjacent sacrificial spacers; and after the erase gate is formed to cover the dielectric layer, the erase layer is removed a sacrificial spacer, a portion of the first substrate dielectric layer, and a portion of the second substrate dielectric layer, the first substrate dielectric layer between the erase gate and the first doped region, and the first a second dielectric layer, whereby the first doped dielectric layer is formed between the erase gate and the first doped region.

In an embodiment of the method for fabricating a non-volatile memory cell of the present invention, the method includes the steps of: forming a dielectric layer on the select gate and the substrate after forming the select gate; removing a portion of the dielectric layer, retaining the selection a dielectric layer on the upper surface of the gate and a portion of the substrate, whereby a selective gate capping dielectric layer is formed on the upper surface of the selective gate, and a first doped dielectric layer is formed on the upper surface of the portion of the substrate.

1‧‧‧Non-volatile memory array

1A‧‧‧Non-volatile memory unit

1B‧‧‧Non-volatile memory unit

10‧‧‧Substrate

11‧‧‧Selecting the gate

12‧‧‧ Wipe the gate

13‧‧‧Floating gate

131‧‧‧ Sacrificial spacers

132‧‧‧Opening

14‧‧‧coupled gate

15‧‧‧First doped area

16‧‧‧Second doped area

18‧‧‧ dielectric layer

181‧‧‧Selected gate covered dielectric layer

182‧‧‧First Substrate Dielectric Layer

183‧‧‧Second Substrate Dielectric Layer

184‧‧‧Erase the gate covered dielectric layer

185‧‧‧ Wipe the gate dielectric layer

186‧‧‧coupled gate dielectric layer

187‧‧‧Surface dielectric layer

191‧‧‧ character line

192‧‧‧ bit line

2A‧‧‧Non-volatile memory unit

2B‧‧‧Non-volatile memory unit

20‧‧‧Substrate

21‧‧‧Select gate

22‧‧‧ Wipe the gate

23a‧‧‧Floating gate

23b‧‧‧Floating gate

231‧‧‧ protruding structure

233‧‧‧Extended structure

24‧‧‧coupled gate

25‧‧‧First doped area

26‧‧‧Second doped area

28‧‧‧Dielectric layer

281‧‧‧Selected gate covering dielectric layer

283‧‧‧First doped dielectric layer

284‧‧‧ Wipe the gate covered dielectric layer

285‧‧‧Tunnel dielectric layer

286‧‧‧coupled gate dielectric layer

287‧‧‧Surface dielectric layer

3‧‧‧Non-volatile memory unit

30‧‧‧Substrate

31‧‧‧Selecting the gate

32‧‧‧ Wipe the gate

33‧‧‧Floating gate

34‧‧‧coupled gate

35‧‧‧First doped area

36‧‧‧Second doped area

38‧‧‧Dielectric layer

381‧‧‧Selected gate covered dielectric layer

387‧‧‧Surface dielectric layer

Figure 1 is a plan view of an embodiment of a non-volatile memory array of the present invention.

Figure 2 is a cross-sectional view showing a first embodiment of the non-volatile memory cell of the present invention.

3A to 3F are schematic views showing a manufacturing flow of the non-volatile memory unit according to the first embodiment of the present invention.

Figure 4 is a cross-sectional view showing a second embodiment of the non-volatile memory cell of the present invention.

5A to 5F are schematic views showing a manufacturing process of a non-volatile memory unit according to a second embodiment of the present invention.

Figure 6 is a cross-sectional view showing a third embodiment of the non-volatile memory cell of the present invention.

7A to 7D are schematic views showing a manufacturing flow of a non-volatile memory unit according to a third embodiment of the present invention.

Figure 8 is a cross-sectional view showing a fourth embodiment of the non-volatile memory cell of the present invention.

Figure 9 is a cross-sectional view showing a fifth embodiment of the non-volatile memory unit of the present invention.

While the specific embodiments of the present invention have been described in the drawings and are described in detail herein, the invention herein The schema content of this creation may be unequal proportions, and the detailed descriptions of the drawings and their detailed descriptions are only for the disclosure of specific types, and are not limited by the scope of the creation. On the contrary, according to the spirit and scope of the patent scope of the creation, Modifications, equal components and their replacements are covered by this creation.

1 to 2 are a plan view of a non-volatile memory array and a cross-sectional view of a first embodiment of a non-volatile memory unit, respectively. Figure 2 is a cross-sectional view along the AA' direction of the non-volatile memory array of Figure 1, and includes two along Non-volatile memory unit 1A adjacent in the X direction.

In order to make the following description more clear, please refer to the coordinates in FIG. 1 and FIG. 2, in the description of the present invention, the first direction X, the second direction Y and the third direction Z are defined, wherein the first direction X, The second direction Y and the third direction Z are perpendicular to each other, for example, the first direction X is a horizontal direction, the second direction Y is a vertical direction, and the arrow direction of the second direction Y is upward, and vice versa, and the third direction Z may be on the same level as the X direction in the first direction and perpendicular to the first direction X and the second direction Y, respectively.

The non-volatile memory array 1 of the present invention includes a plurality of non-volatile memory cells 1A, wherein each of the non-volatile memory cells 1A includes a substrate 10, a select gate (SG) 11, and a wipe. In addition to an erect gate (ES) 12, a floating gate (FG) 13, a coupling gate (CG) 14, and one or more dielectric layers 18.

The substrate 10 includes a first doped region 15 and a second doped region 16, and the first doped region 15 is adjacent to the second doped region 16, and the first doped region 15 and the second doped region 16 are located. In the substrate 10, and close to the upper surface of the substrate 10, there may be a space between the first doping region 15 and the second doping region 165. The gate 11 is disposed on the substrate 10 between the first doped region 15 and the projected or vertically extended position of the second doped region 16, for example, disposed in the first doped region 15 and the second doped region. Above the projection of the set space between the zones 165.

The erase gate 12 is located above the first doped region 15, and the floating gate 13 is located between the erase gate 12 and the select gate 11, such as the gate 11, the floating gate 13, and the erase gate. 12 is disposed on the substrate 10 along a first direction X, wherein the floating gate 13 is located between the projected or vertically extended positions of the first doped region 15 and the second doped region 16, eg, the floating gate 13 is adjacent to the erase gate The sidewall of the pole 12 is a planar structure as shown in FIG. The coupling gate 14 is located above the projection of the erase gate 12, the floating gate 13 and the partial selection gate 11, such that the floating gate 13 and the erase gate 12 are located between the coupling gate 14 and the substrate 10.

The dielectric layer 18 is located between the adjacent select gate 11, the erase gate 12, the floating gate 13, the coupling gate 14, or the first doped region 15. For example, the dielectric layer 18 is located between the adjacent selection gate 11 and the floating gate 13 , between the floating gate 13 and the erase gate 12 , between the selection gate 11 and the coupling gate 14 , and the gate is erased. 12 and between the coupling gates 14, between the floating gates 13 and the coupling gates 14 and between the erase gates 12 and the first doping regions 15, and covering the exposed selection gates 11 and the substrate 10 surface. The function of the dielectric layer 18 is to serve as an insulating layer between two adjacent gates, such that the adjacent selection gate 11, the erase gate 12, the floating gate 13, the coupling gate 14, or the first doping Zone 15 achieves the effect of mutual insulation.

In an embodiment of the invention, the thickness of the gate 11 is selected to be between 200 Å and 2000 Å, the thickness of the erase gate 12 is between 200 Å and 2000 Å, and/or the thickness of the floating gate 13 is between 150 Å. Between 2000Å. In the embodiment of the present invention, the thickness of the gate refers to the length of the gate along the second direction Y or the direction perpendicular to the surface of the substrate 10. For example, the thickness of the floating gate 13 is slightly greater than or equal to the thickness of the selective gate 11, and the thickness of the floating gate 13 and the selective gate 11 is slightly greater than or equal to the thickness of the erase gate 12.

In an embodiment of the invention, the first doped region 15 is used as a source and the second doped region 16 is used as a drain. Of course, in other embodiments, the first doping region 15 can also serve as a drain, and the second doping region 16 can also serve as a source.

The non-volatile memory array 1 is composed of a plurality of non-volatile memory cells 1A arranged in a first direction X and a second direction Z perpendicular to each other. A checkerboard shape, for example, a bit line 192 is formed along the first direction X, and a word line WL is formed along the third direction Z. The adjacent two non-volatile memory cells 1A arranged along the first direction X share the erase gate 12, the coupling gate 14 and the first doping region 15, as shown in FIGS. 1 and 2.

Please refer to FIG. 3A to FIG. 3F , which are schematic diagrams showing the manufacturing process of the non-volatile memory unit according to the first embodiment of the present invention. Through this manufacturing process, the non-volatile memory unit 1A as shown in Fig. 2 can be manufactured.

Referring to FIG. 3A, a substrate 10 is first provided, a first conductor polysilicon layer (conductor poly-Si) is formed on the substrate 10, and a first conductor polysilicon layer is patterned to form a selective gate 11 on the substrate 10. A first substrate dielectric layer 182 is then formed over the select gate 11 and the substrate 10 such that the first substrate dielectric layer 182 covers the selected gate 11 and the exposed regions of the substrate 10.

In another embodiment of the present invention, the surface of the substrate 10 is provided to include a surface dielectric layer 187 having a thickness between 10 Å and 150 Å as indicated by the dashed line in FIG. 3A. A first conductor polysilicon layer (conductor poly-Si) may be formed on the surface dielectric layer 187 on the substrate 10, and after the first conductor polysilicon layer is patterned, a selective gate 11 is formed on the surface dielectric layer 187. A first substrate dielectric layer 182 is then formed over the gate 11 and the surface dielectric layer 187 of the substrate 10 to cover the regions where the gate 11 and the surface dielectric layer 187 are exposed.

In an embodiment of the invention, the first substrate dielectric layer 182 can be formed by means of oxide chemical vapor deposition, but the oxidized chemical vapor deposition is only an embodiment of the invention, and To the extent that the scope of the invention is limited, the first substrate dielectric layer 182 can also be formed in different ways in different embodiments.

Referring to FIG. 3B, after the first substrate dielectric layer 182 is formed, a sacrificial spacer spacer 131 is formed on the first substrate dielectric layer 182, and the sacrificial spacer 131 is adjacent to the selection gate 11. . The material of the sacrificial spacer 131 may be tantalum nitride (SiN) or other suitable material. Two adjacent sacrificial spacers 131 are spaced apart by an opening 132. The ion implantation is performed on the opening 132, and a first doping region 15 is formed in the substrate 10. The first doping region 15 is located adjacent to the substrate 10. Upper surface. In other words, the position of the first doping region 15 in the first direction X is defined using the sacrificial spacer 131.

In an embodiment of the invention, the sacrificial spacers 131 are formed by first depositing a sacrificial layer on the first substrate dielectric layer 182, and then removing a portion of the sacrificial layer by etching or developing, leaving only and selecting A sacrificial layer adjacent to both sidewalls of the gate 11 forms a sacrificial spacer 131.

In an embodiment of the invention, an oxide layer may be formed on the upper surface of the first doping region 15 to increase the first doping region 15 and the erase gate 12 formed subsequently over the projection of the first doping region 15 Insulation between.

Referring to FIG. 3C, after the first doping region 15 is formed, a second substrate dielectric layer 183 is formed on the surface of the exposed sacrificial spacer 131 and the exposed first substrate dielectric layer 182. An erase gate 12 is then formed on the second substrate dielectric layer 183 with a second conductor polysilicon layer, wherein the erase gate 12 is located above the first doped region 15 and is located at two adjacent sacrificial spacers 131. between.

In an embodiment of the invention, the erase gate 12 is formed by first forming a second conductor polysilicon layer on the second substrate dielectric layer 183, and then removing it by using an etch back planarization method. A second conductor polysilicon layer outside the projected region above the doped region 15 forms a wiper gate 12 in the projected region above the first doped region 15.

Referring to FIG. 3D, after the erase gate 12 is formed, a portion of the second substrate dielectric layer 183 is removed, leaving only the second substrate dielectric layer 183 on the sidewalls and the lower surface of the erase gate 12, such as The second substrate dielectric layer 183 between the erase gate 12 and the sacrificial spacer 131 and the first substrate dielectric layer 182 is left.

A wipe-off dielectric layer 184 is then formed over the erase gate 12. To facilitate the subsequent description, in the embodiment of the present invention, the second substrate dielectric layer 183 and the erase gate capping dielectric layer 184 around the erase gate 12 are defined as the erase gate dielectric layer 185. The second substrate dielectric layer 183 and the erase gate capping dielectric layer 184 may be formed of the same or different materials.

Referring to FIG. 3E, after the erase gate dielectric layer 185 is formed, the sacrificial spacer 131 is removed, and the floating gate 13 is formed on the first substrate dielectric layer 182 as a third conductor polysilicon layer. The floating gate 13 is located between the selection gate 11 and the erase gate 12. In other words, the position of the floating gate 13 is defined by the sacrificial spacer 131 originally located between the selection gate 11 and the erase gate 12, and the spacer type floating gate 13 has The ability to erase the adjacent erase gate 12 and/or the first doped region 15 junction.

In an embodiment of the invention, the floating gate 13 is formed by depositing a third conductive polysilicon layer on the exposed first substrate dielectric layer 182 and the erase gate dielectric layer 185, and then etching back ( Etching back) and patterning the third conductor polysilicon layer to form a floating gate 13 between the select gate 11 and the erase gate 12.

Referring to FIG. 3F, after forming the floating gate 13, the coupled gate dielectric layer 186, the coupling gate 14 and the second doping region 16 are sequentially formed. The order of forming the coupled gate dielectric layer 186, the coupling gate 14 and the second doping region 16 can be adjusted. For example, the second doping region 16 can be formed first, and then the coupled gate dielectric layer 186 and the coupling gate can be formed. Pole 14, or form a coupling first The gate dielectric layer 186 is closed, followed by the formation of a second doped region 16, and finally a coupling gate 14 is formed.

The second doped region 16 is located in the substrate 10 and is adjacent to the first doped region 15. A coupled gate dielectric layer 186 overlies the exposed first substrate dielectric layer 182, floating gate 13 and erase gate dielectric layer 185. The coupling gate 14 is located on the coupled gate dielectric layer 186 and over the projections of the erase gate 12, the floating gate 13, and the partial erase gate 11.

In the embodiment of the present invention, the materials for selecting the gate 11, the erase gate 12, the floating gate 13, and the coupling gate 14 are all conductors, and a conductor polysilicon (Poly-Si) is used as the material of the gates, but This is not a limitation of the scope of the invention, and in various embodiments, the materials used for the gates may be other suitable conductor materials.

3F and 2 are cross-sectional views of the non-volatile memory cell 1A according to the first embodiment of the present invention, including two adjacent non-volatile memory cells 1A, two adjacent non- The volatile memory 1A shares the erase gate 12, the coupling gate 14, and the first doping region 15. The main difference is that in Figure 3F, each dielectric layer 18 is layered in accordance with the process steps, and in Figure 2, all of the dielectric layers 18 are considered as one.

In practical applications, when the materials of the first substrate dielectric layer 182, the erase gate dielectric layer 185, and the coupled gate dielectric layer 186 are the same, the profile of the non-volatile memory cell 1A will be difficult to distinguish. At the junction of the different dielectric layers 18, the profile will be close to the configuration of Figure 2. Conversely, when the materials of the first substrate dielectric layer 182, the erase gate dielectric layer 185, and the coupled gate dielectric layer 186 are different, the cross section of the non-volatile memory cell 1A will be easier to distinguish different dielectric layers. At the junction of 18, the profile will be close to the structure of Figure 3F.

In an embodiment of the present invention, if the substrate 10 provided in the step of FIG. 3A includes a surface dielectric layer 187, the non-volatile memory unit 1A completed in FIG. 3F, A surface dielectric layer 187 will also be included between the substrate 10 and the select gate 11, the floating gate 13 and the erase gate 12, as indicated by the dashed lines in the figure.

Referring to FIG. 3F, and referring to FIG. 2, in an embodiment of the invention, the dielectric layer 18 includes a first substrate dielectric layer 182 having a thickness between 10 Å and 150 Å, including yttrium oxide and / or high dielectric (high K) material composite. The first substrate dielectric layer 182 covers both sidewalls and the upper surface of the gate 11.

In an embodiment of the invention, the dielectric layer 18 includes a erase gate dielectric layer 185 surrounding the erase gate 12 and located between the erase gate 12 and the substrate 10, the floating gate 13 and the coupled gate. Between 14 and between 100 Å and 600 Å thick, including yttria and/or high K material composites.

In an embodiment of the invention, the dielectric layer 18 includes a coupled gate dielectric layer 186 between the coupled gate 14 and the erase gate 12, between the coupled gate 14 and the floating gate 13 and the coupled gate. Between the pole 14 and the selection gate 11, the thickness is between 100 Å and 300 Å, including yttria and/or high K material composites.

In another embodiment of the invention, dielectric layer 18 may also include more than one dielectric layer 18, and these dielectric layers 18 have the same thickness range. For example, the dielectric layer 18 can include a first substrate dielectric layer 182 and a erase gate dielectric layer 185. The first substrate dielectric layer 182 is located between the floating gate 13 and the select gate 11 and between the floating gate 13 and the substrate 10, and has a thickness between 50 Å and 200 Å, including yttrium oxide and or high dielectric (high) K) Material composites. The erase gate dielectric layer 185 is located between the floating gate 13 and the erase gate 12 and has a thickness between 50 Å and 200 Å, including yttria and/or a high-k material composite.

Please refer to FIG. 4, which is a second embodiment of the non-volatile memory unit of the present invention. Sectional view. Please refer to FIG. 1 together. FIG. 4 is a cross section taken along the AA' direction in FIG. 1 and includes two non-volatile memory cells 1B adjacent in the first direction X. The non-volatile memory unit 1B includes a substrate 10, a selection gate 11, an erase gate 12, a floating gate 13, a coupling gate 14, a selective gate capping dielectric layer 181, and one or more Dielectric layer 18. The non-volatile memory cell 1B is similar to the non-volatile memory cell 1A of the first embodiment. For example, the floating gate 13 of the above two embodiments is adjacent to the sidewall of the erase gate 12 and has a planar structure. The main difference is that the non-volatile memory cell 1B further includes a selective gate capping dielectric layer 181 on the upper surface of the select gate 11 such that the distance between the select gate 11 and the coupled gate 14 in the Y direction is shallower than that of the floating gate. The 13-pole erase gate 12 is long with the coupled gate 14. Other configurations of the non-volatile memory unit 1B have been described in the first embodiment and will not be described again.

Please refer to FIG. 5A to FIG. 5F , which are schematic diagrams showing the manufacturing process of the non-volatile memory unit according to the second embodiment of the present invention. The manufacturing flow of the non-volatile memory unit 1B is similar to that of the first embodiment, and the main difference is that in the step of FIG. 5A, after the selection gate 11 is formed on the substrate 10, a selection gate is subsequently formed on the selection gate 11. The dielectric layer 181 is covered, and then the first substrate dielectric layer 182 is formed on the exposed selection gate 11, the selective gate capping dielectric layer 181, and the surface of the substrate 10, as shown in FIG. 5A.

The subsequent manufacturing process of the non-volatile memory unit 1B according to the embodiment of the present invention, as shown in FIGS. 5B to 5F, is similar to the manufacturing method of the non-volatile memory unit 1A described in the first embodiment, such as the 3B. To 3F map. After the first substrate dielectric layer 182 is formed, the sacrificial spacers 131 and the first doping regions 15 are sequentially formed, as shown in FIG. 5B. Next, a second substrate dielectric layer 183 and an erase gate 12 are sequentially formed as shown in FIG. 5C. Forming an erase gate capping dielectric layer 184 on the exposed surface of the erase gate 12 and the second substrate dielectric layer 183, and The second substrate dielectric layer 183 and the erase gate capping dielectric layer 184 are defined as erase gate dielectric layers 185, as shown in FIG. 5D. The sacrificial spacer 131 is then removed and the floating gate 13 is formed as shown in FIG. 5E. Finally, the formation of the coupled gate dielectric layer 186, the coupling gate 14 and the second doped region 16 completes the non-volatile memory cell 1B as shown in FIG. 5F.

5F and 4 are cross-sectional views of the non-volatile memory unit 1B according to the second embodiment of the present invention, including two adjacent non-volatile memory cells 1B, two adjacent non- The volatile memory 1B shares the erase gate 12, the coupling gate 14, and the first doping region 15. The main difference is that Figure 5F shows each dielectric layer in a layered manner, and Figure 4 shows all dielectric layers 18 as one.

In practical applications, the non-volatile memory is selected when the materials of the gate-covering dielectric layer 181, the first substrate dielectric layer 182, the erase gate dielectric layer 185, and the coupled gate dielectric layer 186 are the same. The cross section of the bulk cell 1B will make it difficult to distinguish the junction of the different dielectric layers 18, and the cross section will be close to the configuration of Fig. 4. Conversely, when the materials of the gate cover dielectric layer 181, the first substrate dielectric layer 182, the erase gate dielectric layer 185, and the coupled gate dielectric layer 186 are different, the profile of the non-volatile memory cell 1B is different. It will be easier to distinguish the junction of the different dielectric layers 18, and the profile will be close to the configuration of Figure 5F.

In an embodiment of the invention, the substrate 10 of the non-volatile memory cell 1B may also include a surface dielectric layer 187 between the substrate 10 and the select gate 11, the floating gate 13 and the erase gate 12.

Please refer to FIG. 6, which is a cross-sectional view showing a third embodiment of the non-volatile memory unit of the present invention. Please refer to FIG. 1 together. FIG. 6 is a cross section taken along the AA' direction in FIG. 1 and includes two non-volatile memory cells 2A adjacent in the first direction X. This hair The non-volatile memory cell 2A includes a substrate 20, a select gate 21, a erase gate 22, a floating gate 23a, a coupled gate 24, and one or more dielectric layers 28.

Referring to FIG. 4, the non-volatile memory unit 2A of the embodiment of the present invention is similar to the non-volatile memory unit 1B of the second embodiment, and the main difference is that the floating gate 23a of the embodiment of the present invention is close to the erase gate. The sidewall of the pole 22 has a protruding structure 231, such as a convex pointed structure, wherein the protruding structure 231 extends from the floating gate 23a toward the erasing gate 22 such that part or all of the protruding structure 231 is located. The gate 22 is erased between the gate and the first doping region 25. The floating gate 13 in the second embodiment is a planar structure near the sidewall of the erase gate 12, as shown in FIG. The non-volatile memory cell 2A has a protruding structure that facilitates electron injection from the floating gate 23a into the erase gate 22 during the erase operation.

Another major difference is that the first doped region 25 of the embodiment of the present invention is located below the projection of the erase gate 22 and a portion of the floating gate 23a. For example, some or all of the protruding structures 231 of the floating gate 23a are located at the first doping. Above the projection of zone 25. The first doped region 15 in the second embodiment is located below the projection of the erase gate 12 and is not located below the projection of the portion of the floating gate 13.

In the embodiment of the present invention, the sidewall of the floating gate 23a adjacent to the selection gate 21 may also have an extension structure 233, wherein the extension structure 233 extends from the floating gate 23a toward the selection gate 21, so that part or all of the extension Structure 233 is located between select gate 22 and coupled gate 24.

Please refer to FIG. 7A to FIG. 7D , which are schematic diagrams showing the manufacturing process of the non-volatile memory unit according to the third embodiment of the present invention. Through this manufacturing process, the non-volatile memory unit 2A as shown in Fig. 6 can be manufactured.

Referring to FIG. 7A, a substrate 20 is first provided, and a substrate 20 is formed on the substrate 20. Selecting the gate 21 and a selective gate covering the dielectric layer 281 over the selection gate 21, and sequentially forming the first doping region 25, the first doping region dielectric layer 283, the erasing gate 22, and The gate is covered with a dielectric layer 284. As shown, the first doped region 25 is located in the substrate 20 near the upper surface of the substrate 20. The first doped dielectric layer 283 is located on the upper surface of the substrate 20. For example, the first doped dielectric layer 283 is located. Above the first doped region 25 in the substrate 20, the erase gate 22 is on the first doped dielectric layer 283, and the erase gate cover dielectric layer 284 is on the erase gate 22.

In an embodiment of the invention, the substrate 20 is provided to include a surface dielectric layer 287, as shown by the dashed line in FIG. 7A. When the substrate 20 includes the surface dielectric layer 287, the first doped region 25 will Located in the substrate 20 near the surface dielectric layer 287.

In an embodiment of the present invention, the cross-sectional structure of FIG. 7A may be manufactured after the steps of FIGS. 5A to 5D, and may be first performed on the substrate 11 according to the steps of FIGS. 5A to 5D. Forming the select gate 11, the select gate cap dielectric layer 181, the first substrate dielectric layer 182, the sacrificial spacer 131, the first doping region 15, the second substrate dielectric layer 183, and the erase gate 12 And erasing the gate covering dielectric layer 184. The sacrificial spacer 131, a portion of the first substrate dielectric layer 182, and a portion of the second substrate dielectric layer 183 may be removed after forming the configuration of the 5D figure, leaving only the erase gate above the erase gate 12/22 The gate covers the dielectric layer 184/284 and the first substrate dielectric layer 182 and the second substrate dielectric layer 183 between the erase gate 12/22 and the first doped region 15/25. In the embodiment of the present invention, the first substrate dielectric layer 182 and the second substrate dielectric layer 183 stacked between the erase gate 12/22 and the first doped region 15/25 are defined as in FIG. 7A. The first doped region dielectric layer 283. Through the above, the cross-sectional structure as shown in FIG. 7A can be formed after the 5D map.

After the above-mentioned process steps of FIGS. 5A to 5D, the following is continued The process steps described in FIG. 7A are only an embodiment of the present invention and are not intended to limit the scope of the invention. In another embodiment of the invention, the configuration described in FIG. 7A can also be formed through different process steps. For example, a selection gate 21 is formed on the substrate 20, a dielectric layer is formed on the selection gate 21 and the substrate 20, and the upper surface of the gate 21 and the dielectric layer on the portion of the substrate 20 are retained by etching. A selective gate capping dielectric layer 281 is formed on the upper surface of the selection gate 21, and a first doping region dielectric layer 283 is formed on the upper surface of the portion of the substrate 20. Then, a first doping region 25 is formed on the substrate 20 under the first doped dielectric layer 283, and an erase gate 22 is formed on the first doped dielectric layer 283, and the gate 22 is erased. An erase gate is formed over the dielectric layer 284.

Referring to FIG. 7B, after completing the configuration in FIG. 7A, a portion of the selected gate capping dielectric layer 281, the erase gate capping dielectric layer 284, and the first doped region dielectric layer 283 are removed. Selecting a length of the gate-covered dielectric layer 281 in the first direction X or a cross-sectional area in a plane formed by the first direction X and the third direction Z is smaller than a length or a cross-sectional area of the selection gate 21, and causing the erase gate The length of the pole-covered dielectric layer 284 and the first doped dielectric layer 283 in the first direction X or the cross-sectional area in the plane formed by the first direction X and the third direction Z is smaller than the length of the erase gate 22 Or cross-sectional area as shown. In other words, the upper surface of the partial selection gate 21 does not cover the selective gate dielectric layer 281, and the upper surface of the partial erase gate 22 does not cover the erase gate dielectric layer 284, and the partial erase gate 22 is partially There is no first doped dielectric layer 283 between the first doped regions 25 and/or the substrate 20.

In an embodiment of the invention, an over-etched portion is used to remove portions of the selected gate capping dielectric layer 281, the erase gate capping dielectric layer 284, and the first doped region dielectric. Layer 283.

Please refer to Figure 7C, in the bare selected gate 21, select gate coverage Dielectric layer 281, substrate 20, first doped dielectric layer 283, erase gate 22 and/or erase gate cover dielectric layer 284 surface form a tunneling dielectric layer 285 (tunneling dielectric), and A floating gate 23a is formed on the tunnel dielectric layer 285 between the selection gate 21 and the erase gate 22.

The floating gate 23a has a protruding structure 231 and an extending structure 233, wherein the protruding structure 231 extends from the floating gate 23a toward the erasing gate 22, so that part or all of the protruding structure 231 is located at the erasing gate. Between 22 and the first doped region 25, in other words, the first doped region 25 is located below the projection of the erase gate 22 and a portion of the floating gate 23a. The protrusion structure 231 is formed because in the step of FIG. 7B, the length of the first doped dielectric layer 283 in the first direction X or the cross-sectional area in the XZ direction is larger than the length of the erase gate 22 or The small area has an accommodating space between the erase gate 22 and the first doped region 25 and/or the substrate 20. Therefore, when the floating gate 23a is formed, the floating gate 23a is close to the sidewall of the erase gate 22. The truss structure 231 is formed by extending into the accommodating space.

The extension structure 233 extends from the floating gate 23a toward the selection gate 21. The extension structure 233 is formed because, in the step of FIG. 7B, the length of the selective gate capping dielectric layer 281 in the first direction X or the cross-sectional area in the XZ direction is smaller than the length or cross-sectional area of the selection gate 21, There is an accommodating space between the upper surface of the selection gate 22 and the sidewall of the selective gate-covering dielectric layer 281. Therefore, when the floating gate 23a is formed, the floating gate 23a extends to the side wall of the selection gate 21 to The accommodating space further forms an extension structure 233.

Referring to FIG. 7D, after forming the erase gate 23a, the coupled gate dielectric layer 286, the coupling gate 24, and the second doping region 26 are sequentially formed to complete the non-volatile embodiment of the present invention. Memory unit 2A. The order in which the coupled gate dielectric layer 286, the coupled gate 24, and the second doped region 26 are formed can be adjusted. For example, the second doping region 26 may be formed first, and then The coupled gate dielectric layer 286 and the erase gate 24 are formed, or the coupled gate dielectric layer 286 is formed first, followed by the second doped region 26, and finally the coupled gate 24 is formed.

In an embodiment of the invention, the substrate 20 of the non-volatile memory cell 2A may also include a surface dielectric layer 287 between the substrate 20 and the select gate 21, the floating gate 23a, and the erase gate 22.

The second doping region 26 is located in the substrate 20 adjacent to the first doping region 25, and an arrangement space may exist between the first doping region 25 and the second doping region 26. A coupled gate dielectric layer 286 overlies the exposed tunnel dielectric layer 285, the floating gate 23a, and the erase gate dielectric layer 285. The coupling gate 24 is located on the coupled gate dielectric layer 286 and over the projections of the erase gate 22, the floating gate 23a, and the partial erase gate 21.

7D and 6 are cross-sectional views of a non-volatile memory cell 2A according to a third embodiment of the present invention, including two adjacent non-volatile memory cells 2A, two adjacent non- The volatile memory 2A shares the erase gate 22, the coupling gate 24, and the first doping region 25. The main difference is that the 7D pattern shows each dielectric layer 28 in a layered manner according to the process requirements. Figure 6 shows all the dielectric layers 28 as one.

In practical applications, when the gate capping dielectric layer 281, the first doped dielectric layer 283, the erase gate capping dielectric layer 284, the tunneling dielectric layer 285, and the coupled gate dielectric layer 286 are selected. When the materials are the same, the profile of the non-volatile memory cell 2A will be difficult to distinguish the junction of the different dielectric layers 28, and the profile will be close to the configuration of FIG. Conversely, when the materials for selecting the gate capping dielectric layer 281, the first doped dielectric layer 283, the erase gate capping dielectric layer 284, the tunneling dielectric layer 285, and the coupled gate dielectric layer 286 are different, The cross-section of the non-volatile memory cell 2A will make it easier to distinguish the junction of the different dielectric layers 28, and the profile will be close to the configuration of Figure 7D.

Referring to FIG. 8, a cross-sectional view of a fourth embodiment of a non-volatile memory cell of the present invention includes two non-volatile memory cells 2B adjacent in a first direction X. As shown, the non-volatile memory cell 2B of the present invention includes a substrate 20, a select gate 21, an erase gate 22, a floating gate 23b, a coupled gate 24, and one or more Dielectric layer 28. Referring to FIG. 6 and FIG. 7D together, the non-volatile memory unit 2B is similar to the non-volatile memory unit 2A in the third embodiment, the main difference being that the non-volatile memory unit 2B is in production, and A selective gate capping dielectric layer 281 is not formed on the select gate 21, such that the sidewall of the floating gate 23b adjacent to the select gate 21 does not have the extension structure 233. Other configurations of the non-volatile memory unit 2B of the present invention have been described in the third embodiment and will not be described again.

Referring to FIG. 9, a cross-sectional view of a fifth embodiment of a non-volatile memory cell of the present invention includes two non-volatile memory cells 3 adjacent in a first direction X. The non-volatile memory unit 3 includes a substrate 30, a select gate 31, an erase gate 32, a floating gate 33, a coupled gate 34, and one or more dielectric layers 38.

Referring to FIG. 2, the structure of the non-volatile memory unit 3 of the present invention is similar to that of the non-volatile memory unit 1A of the first embodiment of the present invention, and the main difference is the floating gate 33 and the coupling gate 34. The cross-sectional area on the plane formed by the first direction X and the second direction Y is smaller than that of the first embodiment, and the position of the coupling gate 34 is closer to the substrate 30 in the second direction Y. Specifically, the floating gate 33 of the embodiment of the present invention has a height in the second direction Y that is smaller than the selection gate 31 such that a portion of the coupling gate 34 and the selection gate 31 and the erase gate 32 are in the second direction Y. Overlap, for example, a portion of the coupled gate 34 is located in the accommodating space between the select gate 31 and the erase gate 32. In addition, the coupling of the embodiment of the present invention is only disposed on the projection of the floating gate 33, and is not disposed in the The projection of the gate 31 and the erase gate 32 is selected.

Another major difference is that the two non-volatile memory cells 3 adjacent in the first direction X of the embodiment of the present invention share only the erase gate 32 and the first doped region 35, and do not share the coupled gate 34. Other configurations of the non-volatile memory unit 3 according to the embodiment of the present invention have been described in the first embodiment, and will not be described again.

In an embodiment of the invention, the substrate 30 includes a surface dielectric layer 387 between the substrate 30 and the select gate 31, the floating gate 33, and the erase gate 32. As shown by the dashed line in FIG. 9, when the substrate 30 includes the surface dielectric layer 387, the first doped region 35 and the second doped region 36 will be located in the substrate 30 near the surface dielectric layer 387.

In another embodiment of the present invention, the non-volatile memory cell 3 of the present invention includes a selective gate capping dielectric layer 381, wherein the selective gate capping dielectric layer 381 is located on the upper surface of the select gate 31.

In another embodiment of the present invention, the floating gate 33 may have a protruding structure 231 near the sidewall of the erase gate 22/32 as in the floating gate 23a of the third embodiment, as shown in FIG. Show.

The method for manufacturing the non-volatile memory unit 3 according to the embodiment of the present invention is similar to the non-volatile memory unit 1 of the first embodiment of the present invention, and can be manufactured through the process steps of the third to third embodiments. The main difference is that when the floating gate 33 is formed, the length of the floating gate 33 in the second direction Y is shorter than that of the selection gate 32. Another major difference is that when the coupling gate 34 is formed, the coupling gate 34 is only above the projection of the floating gate 33 in the second direction Y, and not above the projection of the selection gate 31 and the erase gate 32.

The words, perhaps, and changes described in the manual are not the creation of this work. limit. The technical terms used in the specification are mainly for the description of specific embodiments, and are not intended to be limiting. The single quantifiers (such as one and the one) used in the specification may also be plural, unless explicitly stated in the contents of the specification. For example, a device referred to in the specification may include a combination of two or more devices, and one of the materials mentioned in the specification may include a mixture of a plurality of substances.

The above is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, that is, the equivalent changes and modifications of the shapes, structures, features and spirits described in the scope of the patent application. , should be included in the scope of the patent application of this creation.

1A‧‧‧Non-volatile record unit

10‧‧‧Substrate

11‧‧‧Selecting the gate

12‧‧‧ Wipe the gate

13‧‧‧Floating gate

14‧‧‧coupled gate

15‧‧‧First doped area

16‧‧‧Second doped area

18‧‧‧ dielectric layer

Claims (18)

A non-volatile memory cell includes: a substrate including a first doped region and at least a second doped region, wherein the first doped region is adjacent to the second doped region; and a select gate And disposed on the substrate between the first doped region and the second doped region; a wipe gate is located above the first doped region; a floating gate is located at the select gate and Between the erase gates; a coupled gate over the projection of the erase gate, the floating gate and a portion of the select gate; and one or more dielectric layers for the insulating layer, Located adjacent to the select gate, the erase gate, the floating gate, the coupling gate, or the first doped region. The non-volatile memory unit of claim 1, wherein the substrate comprises a surface dielectric layer between the substrate and the select gate, the floating gate and the erase gate. The non-volatile memory unit of claim 1, wherein the dielectric layer comprises: a first substrate dielectric layer covering the sidewalls and the upper surface of the selective gate, and the thickness is between 10 Å and 150 Å. a wiper dielectric layer covering the erase gate and located between the erase gate and the substrate, the floating gate and the coupling gate, and having a thickness between 100 Å and 600 Å a coupled gate dielectric layer between the coupled gate and the erase gate, the floating gate, and the select gate, and having a thickness between 100 Å and 300 Å. The non-volatile memory cell of claim 3, wherein the first substrate dielectric layer, the erase gate dielectric layer, and the material of the coupled gate dielectric layer are yttrium oxide or high dielectric. Electrical material composite. The non-volatile memory cell of claim 1, wherein the dielectric layer comprises: a first substrate dielectric layer between the floating gate and the select gate and the floating gate The thickness between the substrates is between 50 Å and 200 Å; A wiper dielectric layer is located between the floating gate and the erase gate and has a thickness between 50 Å and 200 Å. The non-volatile memory cell of claim 5, wherein the first substrate dielectric layer and the erase gate dielectric layer are made of yttria or a high dielectric material composite. The non-volatile memory cell of claim 1, wherein the dielectric layer comprises a selective gate capping dielectric layer disposed on an upper surface of the select gate. The non-volatile memory unit according to claim 1, wherein the thickness of the selection gate is between 200 Å and 2000 Å, and the thickness of the erase gate is between 200 Å and 2000 Å. The thickness of the pole is between 150Å and 2000Å. The non-volatile memory unit of claim 1, wherein the floating gate is adjacent to the sidewall of the erase gate as a planar structure or has a convex structure. The non-volatile memory cell of claim 9, wherein the protruding structure of the floating gate is between the first doped region and the erase gate. A method for fabricating a non-volatile memory cell, the method comprising: providing a substrate; forming a selection gate on the substrate; forming a first substrate dielectric layer covering the selection gate and the substrate, and Forming a first doped region in the substrate; forming a erase gate on the first substrate dielectric layer, wherein the erase gate is above the first doped region; forming a wrap-around erase gate a gate dielectric layer is formed, a floating gate is formed between the select gate and the erase gate; and a coupled gate dielectric layer is formed to cover the exposed first substrate dielectric layer, The gate dielectric layer and the floating gate are erased; and a coupling gate is formed on the coupled gate dielectric layer. The method of fabricating the non-volatile memory unit of claim 11, wherein the coupling gate is located above the projection of the erase gate, the floating gate, and a portion of the select gate. The method of fabricating the non-volatile memory unit of claim 11, wherein the coupling gate is located above the projection of the floating gate. The method for fabricating a non-volatile memory cell according to claim 11, comprising the steps of: forming a second doped region in the substrate, wherein the first doped region and the second doped region Adjacent. The method for fabricating a non-volatile memory cell according to claim 11, comprising the steps of: forming at least one sacrificial spacer on the first substrate dielectric layer after forming the first substrate dielectric layer The sacrificial spacer is adjacent to the select gate; and after the erase gate dielectric layer is formed, the sacrificial spacer between the erase gate and the select gate is removed. A method for fabricating a non-volatile memory cell, the method comprising: providing a substrate; forming a selective gate on the substrate; forming a first doped region, a first doped dielectric layer, and an erase layer a gate electrode and a gate electrode covering the dielectric layer, wherein the first doped region is disposed in the substrate, the first doped region dielectric layer is disposed on the substrate, and is located on the first doped region The erase gate is disposed on the first doped dielectric layer, and the erase gate cover dielectric layer is disposed on the erase gate; removing part of the first doped dielectric layer, part of the Wiping the gate to cover the dielectric layer, such that the first doped region dielectric layer and the erase gate cover dielectric layer have a length or a cross-sectional area smaller than the erase gate; forming a tunneling dielectric layer to cover the bare The selection gate, the erase gate, the first doped dielectric layer, the erase gate cover dielectric layer and a portion of the surface of the substrate; forming a floating gate at the select gate And between the erase gates, wherein a side of the floating gate adjacent to the erase gate has a convex Structure; forming a gate dielectric coupled to cover the bare tunneling dielectric layer and the floating gate; And forming a coupling gate on the coupled gate dielectric layer. The method for fabricating a non-volatile memory cell according to claim 16 includes the following steps: after forming the selective gate, forming a first substrate dielectric layer covering the selective gate and the substrate; Forming at least one sacrificial spacer on the first substrate dielectric layer, wherein the sacrificial spacer is adjacent to the select gate; forming a second substrate dielectric layer overlying the exposed first substrate dielectric a layer and the sacrificial spacer; forming the erase gate on the second substrate dielectric layer, wherein the erase gate is above the first doped region and located between two adjacent sacrificial spacers And after forming the erase gate capping dielectric layer, removing the sacrificial spacer, a portion of the first substrate dielectric layer, and a portion of the second substrate dielectric layer, remaining at the erase gate The first substrate dielectric layer and the second substrate dielectric layer are disposed between the first doped region, thereby forming the first doping between the erase gate and the first doped region Miscellaneous dielectric layer. The method for fabricating a non-volatile memory unit according to claim 16, comprising the steps of: forming a dielectric layer on the selection gate and the substrate after forming the selection gate; removing the portion The dielectric layer retains the upper surface of the selective gate and a portion of the dielectric layer on the substrate, thereby forming a selective gate capping dielectric layer on the upper surface of the selective gate, and forming the portion on the upper surface of the substrate The first doped region dielectric layer.