TWI590151B - Binary half-adder and other logic circuits - Google Patents

Description

Binary half adder and other logic circuits

This invention relates to a binary half adder and other logic circuits.

The binary half adder is a logic circuit that adds two bit-two binary digits together. A binary half adder can be used to construct more complex logic circuits (such as full adders). The binary half adder is the main unit for constructing the arithmetic logic unit. The arithmetic logic unit is the main unit for constructing a computer processor. The binary half adder can, for example, be provided on a semiconductor wafer that is connected together such that it provides the logic required by the computer processor.

One object of the present invention is to provide a binary half adder formed in a manner not known in the art.

According to a first aspect of the present invention, a binary half adder is provided, comprising a first oscillator and a second oscillator, each oscillator being coupled to a first input and a second input, the second oscillator Connected to the first oscillator, wherein the first oscillator is configured to oscillate if the first input is high or the second input is high, the second oscillator being configured to be at the first input and The second input is oscillating, and wherein the connection between the second oscillator and the first oscillator is configured to disable the first oscillator if the second oscillator is oscillating oscillation.

Each oscillator can be configured to tend to a stable non-oscillating state in the absence of an external input, and can be configured to be present in a presence above one of the thresholds The input is oscillated with a limit cycle.

At least one of the oscillators can be configured to tend to a stable non-oscillating state if the external input exceeds an upper threshold.

The first oscillator and the second oscillator can be circuits.

The first oscillator and the second oscillator can include a plurality of FETs.

The first oscillator and the second oscillator may be a Fitzhugh-Nagumo oscillator, and a circuit may provide the connection between the second oscillator and the first oscillator, the connection being a suppression connection.

The first oscillator may be formed by a pair of Josephson junctions, the second oscillator being formed by a pair of Josephson junctions, and a circuit providing between the second oscillator and the first oscillator The connection is an inhibitory connection.

The connection between the second oscillator and the first oscillator can include a slave oscillator configured to oscillate non-in phase with the first oscillator and thereby cause the first oscillation The oscillator of the device stops vibrating.

The second oscillator can have a higher threshold than the first oscillator.

The first oscillator can receive a bias current or a bias voltage that is greater than the second oscillator.

The connection from the first input and the second input to the second oscillator may have an impedance higher than a connection from the first input and the second input to the first oscillator.

The first oscillator and the second oscillator can be a neuron, the connection can be a synapse, and the second neuron can be configured to produce an inhibitory neurotransmitter when it is oscillating.

A binary adder may include a first binary half adder according to a first aspect of the present invention and a second binary half adder according to the first aspect of the present invention, the binary half adder Combined with an additional oscillator.

According to a second aspect of the present invention, there is provided a binary adder comprising a binary half adder according to a first aspect of the present invention, and further comprising a third oscillator coupled to one of the second oscillators, The connection between the third oscillator and the second oscillator is configured to inhibit oscillation of the second oscillator if the third oscillator is oscillating, and wherein the first oscillator, the second The oscillator and the third oscillator are each coupled to a first input, a second input, and a third input, the first oscillator being configured to be in the first input, the second input, or the third input Oscillating when one is high, the second oscillator is configured to oscillate if any of the first input, the second input, or the third input is high, and the third oscillator is The configuration is oscillated with the first input, the second input, and the third input high.

According to a third aspect of the present invention, a binary half adder includes a first oscillator and a second oscillator, each oscillator being coupled to a first input and a second input, the second oscillator Connected to an output of the first oscillator, wherein the first oscillator is configured to oscillate if the first input is high or the second input is high, the second oscillator is configured to be at the Oscillation with an input and the second input being high, and wherein the first oscillator and the second oscillator are configured to oscillate at the same frequency, and the output of the second oscillator and the first oscillator The connection between the configurations is configured to The output from the second oscillator when the first oscillator and the second oscillator are oscillating will be combined with the output from the first oscillator in an inverted manner.

According to a fourth aspect of the present invention, a logic circuit is provided, comprising: a first oscillator coupled to a second oscillator, the connection between the second oscillator and the first oscillator being configured Suppressing oscillation of the first oscillator while the second oscillator is oscillating, wherein the first oscillator is coupled to a power supply such that the second oscillator is disabled unless the oscillation of the first oscillator is inhibited by the second oscillator An oscillator will oscillate.

Two inputs can be provided to the second oscillator, and a threshold of the second oscillator can cause the second oscillator to oscillate if the first input is high or the second input is high.

Two inputs can be provided to the second oscillator, and the threshold of the second oscillator can be such that the second oscillator will only be high if both the first input and the second input are high oscillation.

According to a fifth aspect of the present invention, a binary half adder includes a first oscillator and a second oscillator, each oscillator being coupled to a first input and a second input, the second oscillator Connected to the first oscillator via a connection, wherein the first oscillator is configured to oscillate if the first input is high or the second input is high, the second oscillator being configured to Oscillation if the first input and the second input are high, and wherein the first oscillator is configured such that it will not be received if it receives a signal indicating that the second oscillator is oscillating via the connection oscillation.

Two binary half adders in accordance with the fifth aspect of the present invention can be used to form a binary adder.

A computer can be constructed using a binary half adder in accordance with the present invention.

DETAILED DESCRIPTION OF THE INVENTION A specific embodiment of the present invention will now be described by way of example only with reference to the accompanying drawings.

Referring to Figure 1, a pair of oscillators 1, 2 are schematically illustrated that are configured to operate as a binary half adder in accordance with an embodiment of the present invention.

Each oscillator is configured to tend to a stable non-oscillating state in the absence of an external input and is configured to oscillate in a limit cycle in the presence of an external input above a predetermined threshold. Each oscillator can be, for example, a Fitzhugh-Nagumo oscillator. Each oscillator can be configured to traverse a predetermined upper threshold (eg, in the case of an oscillator with a Fitzhugh-Nagumo oscillator) tending to a stable non-oscillating state, but for some oscillations This may not be the case. The first input In1 is transmitted to the first oscillator 1 and the second oscillator 2 via the connections 11, 12. The first connection 11 has a low resistance and the second connection 12 has a high resistance. This is schematically illustrated in Figure 1 by indicating the first connection 11 as a thick line and the second connection as a thin line 12. The second input In2 is transmitted to the first oscillator 1 and the second oscillator 2 via the connections 21, 22. The first connection 21 has a low resistance and the second connection 22 has a high resistance (again indicated by thick lines and thin lines). Connection 30 extends between second oscillator 2 and first oscillator 1.

In operation, when the first input ln1 and the second input ln2 are low, none of the oscillators 1, 2 oscillate. This is because the signals received at the oscillators 1, 2 via connections 11, 12, 21 and 22 are not high enough to reach the threshold level required for oscillation.

When the first input In1 is high and the second input In2 is low, the first oscillator 1 will oscillate. Since the magnitude of the signal received at the first oscillator is sufficiently high to exceed a threshold level above which the first oscillator will oscillate, the first oscillator 1 oscillates. Since the first connection 11 has a low resistance and therefore does not significantly reduce the magnitude of the input signal, the magnitude of the signal is sufficiently high. The second oscillator 2 does not oscillate. This is because the magnitude of the signal received at the second oscillator is below the threshold level (above the threshold level, the second oscillator will oscillate) and the magnitude of the input signal has been connected by the second connection. The high resistance of 12 is reduced.

When the first input In1 is low and the second input In2 is high, the first oscillator 1 will oscillate. Since the magnitude of the signal received via the first connection 21 is sufficiently high to exceed a threshold level above which the first oscillator will oscillate, the first oscillator oscillates. This is because the first connection 21 has a low resistance and therefore does not significantly reduce the magnitude of the input signal. The second oscillator 2 does not oscillate. This is because the magnitude of the signal received at the second oscillator is below the threshold level (above the threshold level, the second oscillator will oscillate) and the magnitude of the input signal has been connected by the second connection. The high resistance of 22 is reduced.

When the first input In1 and the second input In2 are high, the second oscillator 2 oscillates. This is because the magnitudes of the first input signal (provided to the second oscillator 2 via the second connection 12) and the second input signal (provided to the second oscillator 2 via the second connection 22) are exceeded when added together The threshold required to cause oscillation to occur. Thus, even if the magnitude of the input signals has been reduced by the high resistance of the second connections 12, 22, the combined high input is still sufficient to exceed the threshold required to cause oscillation of the second oscillator 2.

When the second oscillator 2 is oscillating, the first oscillator 1 will not oscillate. This is because the connection 30 between the second oscillator 2 and the first oscillator 1 inhibits the oscillation of the first oscillator when the second oscillator is oscillating. The manner in which the prohibition of the oscillation of the first oscillator 1 is achieved is further explained below.

Table 1 is a truth table of the oscillator shown in Fig. 1. The truth table reflects the above description and confirms that the oscillators 1, 2 act as binary carry adders.

As further mentioned above, when the second oscillator 2 is oscillating, the connection 30 between the second oscillator 2 and the first oscillator 1 inhibits oscillation of the first oscillator 1. If the connection does not exist, both the first oscillator 1 and the second oscillator 2 will oscillate when both inputs In1 and In2 are high. The connection 30 between the second oscillator 2 and the first oscillator 1 thus changes the logic provided by the first oscillator from OR logic to "exclusive" (XOR) logic. It is the operation of the first oscillator 1 as an XOR oscillator that allows the use of these oscillators to construct a binary half adder. Connection 30 can be a one-way connection that carries a signal from second oscillator 2 to first oscillator 1. In electronic terms, connection 30 can include a diode.

In one embodiment, the simulated neural hyperpolarization is transmitted from the second oscillator 2 to the first oscillator 1 via connection 30, which inhibits oscillation of the first oscillator. One way to simulate neural hyperpolarization is by group The first oscillator 1 and the second oscillator 2 and the connection 30 cause the second oscillator 2 to affect the oscillation parameters of the first oscillator 1. For example, the second oscillator 2 can affect the oscillation parameters of the first oscillator 1 such that the input provided to the first oscillator 1 via the connection 11 and/or the connection 21 is insufficient to oscillate the first oscillator.

In an alternative embodiment, the second oscillator 2 is coupled to the first oscillator via a slave oscillator (indicated by dashed line 30a in FIG. 1) instead of the first oscillator 1 and the second oscillator 2 Connected by connection 30. The slave oscillator 30a is connected to the second oscillator 2 such that when the second oscillator 2 is oscillating, the slave oscillator 30a also oscillates. The oscillation of the driven oscillator 30a does not affect the oscillation of the second oscillator 2. However, the driven oscillator 30a is coupled to the first oscillator 1 and has an output that is not in phase with the first oscillator 1. The slave oscillator 30a is configured such that when both the first oscillator 1 and the slave oscillator 30a are oscillating, they are not in phase with the first oscillator 1 to be sufficient to cause the oscillator of the first oscillator 1 to stop vibrating ( Via the coupling between the first oscillator 1 and the driven oscillator 30a). The oscillator stall due to the coupling of the first oscillator 1 and the slave oscillator 30a also causes the slave oscillator 30a to stop oscillating. For this reason, in this embodiment, the first oscillator 1 is coupled to the slave oscillator 30a and not directly coupled to the second oscillator 2. If the first oscillator 1 and the second oscillator 2 are directly coupled to each other in this manner and have a connection allowing the oscillator to stop, the oscillation of the first oscillator 1 can inhibit the oscillation of the second oscillator 2. And therefore the truth table for these oscillators will not be the truth table for the binary half adder.

The oscillation frequencies of the first oscillator 1 and the slave oscillator 30a may be the same or different.

In still another alternative embodiment, the second oscillator has a second output (indicated by dashed line 30b in FIG. 1) coupled to the output Out1 of the first oscillator 1, rather than the first oscillator 1 and the second oscillator. The device 2 is connected by a connection 30. The output Out1 is thus the sum of the output of the first oscillator 1 and the second output 30b of the second oscillator 2. A timing circuit (not shown) linked to the first oscillator 1 and the second oscillator 2 ensures that its outputs have the same frequency and are in phase. Since the output of the first oscillator 1 and the second output 30b of the second oscillator 2 are in opposite phases, when both the first oscillator 1 and the second oscillator 2 are oscillating, the output Out1 has an amplitude when This amplitude is reduced when the output Out1 when only the first oscillator 1 is oscillating is compared. The amplitude of the decrease in the output Out1 when both the first oscillator 1 and the second oscillator 2 are oscillating may be zero (or substantially zero).

Figure 2 shows a logic gate configuration that operates in an equivalent manner to oscillators 1 and 2 (the logic gate is configured as a binary half adder). The logic gate 1a is an XOR gate equivalent to the oscillator 1. The logic gate 2a is an AND gate equivalent to the oscillator 2. Equivalent connections, inputs, and outputs have been given the numbers used in Figures 1 and 2.

Referring again to FIG. 1, in the above embodiment, the resistors of the connections 11, 12, 21, 22 are used to modify the input signals In1, In2 such that a single input signal will exceed the threshold of the first oscillator 1, but requires two inputs. The signal exceeds the threshold of the second oscillator 2. In an alternative embodiment, the connections 11, 12, 21, 22 do not significantly modify the input signal, but the threshold is different between the first oscillator and the second oscillator. For example, the threshold of the second oscillator 2 can be higher than the threshold of the first oscillator 1. Therefore, a single high input is sufficient The threshold of the first oscillator 1 is exceeded, but two high inputs are required to exceed the threshold of the second oscillator 2. This alternative embodiment provides the same logic as the embodiments described further above.

In still another alternative embodiment, there is no significant difference between the connections 11, 12, 21, 22, nor is there a significant difference between the first oscillator 1 and the second oscillator 2. The fact is that an additional input is connected to the first oscillator 1. This additional input provides a continuous signal that brings the first oscillator 1 closer to its threshold than the second oscillator 2. In the presence of this continuous signal, a single high input is sufficient to cause oscillator 1 to exceed its threshold. Two high inputs are required to cause the second oscillator to exceed its threshold because it does not receive a continuous signal. This still further alternative embodiment provides the same logic as the embodiments described further above.

The above is an example of a way in which the first oscillator can oscillate when there is a single high input and the second oscillator can oscillate only when there are two high inputs. Other ways of achieving this logic can be used.

As further mentioned above, the oscillators 1, 2 are limit cycle oscillators. The oscillators therefore switch from a stable fixed point (when the input is at a threshold) to a stable limit cycle oscillation (when the input is at the threshold). An example of one of the oscillators that can be used is the Fitzhugh-Nagumo oscillator (although other oscillators can be used as described further below). The Fitzhugh-Nagumo oscillator is an easy-to-excitation system that can be used to model the electrical activity of neurons. The easy excitation system is a system that has a ground state and can be excited from the ground state to an excited state by external input. A simulation of the half adder of Figure 1 has been constructed in which the first oscillator 1 and the second oscillator 2 are modeled as a Fitzhugh-Nagumo oscillator. Use the following equation to mimic each oscillator: Where c ₁ is the external input voltage, u is the voltage that is linked to the excitation of the oscillator and v is the recovery of the voltage. Neurons can be simulated by an input (eg, an external input voltage). After simulation by input, the neurons can be moved to the excited state. The excited state of a neuron is described by the voltage u in the Fitzhugh-Nagumo model, which represents the excitation of a neuron as a function of time. When a neuron is activated, the physiological process will urge the neuron to return to its unactivated state. In the Fitzhugh-Nagumo model, v is the voltage, which is a parameter for the restoration of the characterized neurons. Excitation of neurons caused by a stimulus by an external input c ₁ is characteristic of the model. The external input can be a constant voltage or can be an oscillating voltage. If the external input c ₁ exceeds a certain threshold and does not exceed a certain threshold, the solution of the above equation confirms the slow collection of external input voltage by the neuron and the rapid voltage of the neuron in the excited state. freed. The behavior of neurons in this way can be called "integration and stimulation." If the input is below the lower threshold, the neurons are not activated. If the input is above the upper threshold, the neurons are not fired. These thresholds are determined by values of 20, -1.2, and -0.3, and can be modified by modifying the values.

Figures 3a through 3c show the operation of a single Fitzhugh-Nagumo oscillator modeled using Equations 1 and 2. In Figure 3a, the input c ₁ applied to the oscillator does not exceed the lower threshold of the oscillator ( c ₁ 0.1). Therefore, the oscillator decays to a stable fixed point (which may also be referred to as a stable critical point). In Figure 3b, an input is applied to the oscillator that exceeds the lower threshold of the oscillator and does not exceed the upper threshold of the oscillator (0.1 < c ₁ 0.6). The oscillator thus quickly moves to a stable limit cycle oscillation and remains in its extreme cycle oscillation. In Figure 3c, the oscillator is applied to the input of the threshold value c (c _1> 0.6) over more than _one oscillator. Therefore, the oscillator decays to a stable fixed point (which may also be referred to as a stable critical point). When c ₁ The stable critical point at which the oscillator decays to 0.1 may be referred to as the first stable critical point, and the stable point at which the oscillator decays when c ₁ >0.6 may be referred to as the second stable critical point. The first stable critical point and the second stable critical point have different values of u and v . The oscillator thus provides an indication of whether the input c _{1 is} high or low. The oscillator can therefore be considered to be a threshold hysteresis oscillator.

A Fitzhugh-Nagumo oscillator exhibiting the above behavior (for example) can be used as the first oscillator 1 shown in FIG. The Fitzhugh-Nagumo oscillator can, for example, be configured such that it is in a stable limit cycle oscillation (as a result of input values at inputs In1 and In2), but then receives an additional input value at input 30, which pushes the total input high At the upper limit, the oscillator then stops oscillating and decays to a second stable critical point. Input 30 is thus used to disable oscillation of the oscillator.

In an embodiment, the inputs In1, In2, and 30 can be configured such that their combined value is always less than the upper threshold (eg, less than 0.6 in the above example). In the case of this condition, the oscillator will decay to the first stable critical point if the external input is below the threshold and will move to a stable limit cyclic oscillation if the external input is above the threshold. (Oscillator does not provide hysteresis). In an embodiment, the values used in the oscillator model can be modified to improve The upper limit. The connection 30 between the second oscillator 2 and the first oscillator 1 can provide a negative voltage. The negative voltage can be large enough to move the first oscillator 1 below the lower threshold regardless of the values at inputs In1, In2. This inhibits the oscillation of the first oscillator 1 when the second oscillator 2 is oscillating.

Figures 4a through 4d show simulation results for the half adder of Figure 1 based on the Fitzhugh-Nagumo oscillator. The simulation confirms that an oscillating input (eg, from the previous oscillator) will cause an oscillating output from the binary half adder according to the truth table shown in Table 1.

Referring first to Figure 4a, when both inputs In1, In2 are low, the outputs Out1, Out2 are also low.

Referring to FIG. 4b, when the first input In1 is high and the second input In2 is low, the first output Out1 is high and the second output Out2 is low. The high signal at the first input In1 is an oscillating signal rather than a continuous signal. This is intended to mean a signal that has been generated by a previous oscillator (which may, for example, form part of the previous binary half adder). As can be seen from Figure 4b, the second output Out2 is not zero, but the reality is an oscillating signal having a low amplitude and having a power below zero. Although the signal is not zero, it is small enough that it can be considered equivalent to zero. For example, it will not trigger the oscillation of the subsequent oscillator.

Referring to FIG. 4c, when the first input In1 is low and the second input In2 is high, the first output Out1 is high and the second output Out2 is low. As described above with respect to Figure 4b, the high output signal is an oscillating signal and the low output signal is non-zero but low enough that it can be considered equivalent to zero.

Referring to FIG. 4d, when the first input In1 is high and the second input In2 is high, the first output Out1 is low and the second output Out2 is high. Again, the high output signal is oscillating signal. The low output signal is non-zero and has a form that is slightly different from the form seen in Figures 4b and 4c. However, the low output signal is low enough that it can be considered equivalent to zero.

A nervous system that operates in the manner described above can be constructed. The nervous system can be constructed, for example, using two neurons that act as oscillators shown in Figure 1, which are connected together in an equivalent manner to that shown in Figure 1. Each neuron is a limit cycle oscillator. Neurons require very little power and operate at high speeds. The oscillation inhibition of the first oscillator 1 by the second oscillator 2 can be via hyper-polarization of the nerve (which is transmitted via the connection 30).

Neurons can be grown on a substrate (eg, a ruthenium substrate) using microcontact printing to provide a chemical guide. Microcontact printing can be used to deposit a pattern formed in two parts, each portion of the pattern providing a different guiding cues. The first portion of the pattern may include neuronal adhesion sites and interrupted dendrites to guide the pathway. The first portion of the pattern can be formed on the substrate, for example, using poly-L-isoamine. The second portion of the pattern can include a wider path that is uninterrupted for axonal development. A second portion of the pattern can be formed on the substrate, for example, using a mixture of poly-L-lysine and (laminin). This combination of different guiding cues for dendrites and axon growth provides controlled neuronal polarity.

Using microcontact printing techniques, a structured nervous system can be fabricated and single cell resolution (i.e., a single cell body adhered to a single site) can be achieved. Microcontact printing techniques can be used, for example, to construct the nervous system shown in FIG. Since the pattern printed using microcontact printing can be aligned with the previously provided pattern, the microcontact printing technique allows the printing of chemicals to the configuration junction. The surface of the wafer is structured. The configuration of the surface of the wafer helps to keep the neurons in their proper position over time. The movement of neurons can be suppressed by forming a wall of the conformational structure from Teflon (available from DuPont of Delaware, USA) or some other suitable material.

Within a nervous system, where the oscillator is a neuron, each connection between adjacent neurons can be in the form of a synapse that can diffuse across the synapse. A signal is sent from a neuron to a neighboring neuron as follows: a synapse is present between the first neuron and the second neuron. The first neuron is activated such that its membrane produces a neurotransmitter. The neurotransmitter produced by the first neuron spreads across the synapse and interacts with the membrane of the second neuron. The effect of the neurotransmitter produced by the first neuron on the second neuron depends on both the type of neurotransmitter produced by the first neuron and the membrane of the second neuron.

In some cases, the neurotransmitter produced by the first neuron will interact with the membrane of the second neuron such that the second neuron is excited and excited (this can be thought of as a oscillation of the neuron). In the embodiment of the invention illustrated in Figure 1, this situation is equivalent to connections 11, 12, 21 and 22 (and the output connections of each of the oscillators 1, 2). Examples of neurotransmitters that can excite adjacent neurons include glutamate (glutamic acid) and acetylcholine.

In some cases, the neurotransmitter produced by the first neuron will interact with the membrane of the second neuron such that the second neuron is inhibited (or inhibited) from firing. This can be considered to be an inhibition of the oscillation of the neurons. This situation is equivalent to the connection 30 in the embodiment shown in FIG. An example of a neurotransmitter that can inhibit adjacent neurons is gamma-aminobutyric acid (GABA).

It will be appreciated that a single neuron may be capable of producing a plurality of different neurotransmitters and/or interacting with such different neurotransmitters. The interaction of a neuron with different neurotransmitters can have different effects on the neuron. For example, if a neuron interacts with a first neurotransmitter, it can be excited and excited, and if the neuron interacts with a second neurotransmitter, the neuron can be inhibited from being inhibited.

Different neurotransmitters can spread across synapses at different rates. The neurotransmitter produced by the first neuron and diffusing across the synapse to the second neuron at a relatively fast rate may be in the second nerve compared to the concentration of the neurotransmitter diffusing across the synapse at a relatively slow rate The membrane of the element has a large concentration (once it has spread across the synapse). Neurons that can be used as part of the invention can be configured such that the concentration of a particular neurotransmitter at the membrane of a neuron must exceed a certain threshold in order to render the neurotransmitter effective.

In one embodiment, a neuron's threshold concentration for a particular neurotransmitter may be higher than the concentration of the neurotransmitter after it has spread across a synapse from a single neighboring neuron. The threshold concentration of neurons may be lower than the concentration of the neurotransmitter after it has spread across the synapse while simultaneously diffusing from two separate adjacent neurons. Thus, the threshold concentration of neurons is not exceeded in the case where an adjacent neuron is in an excited state (and adjacent neurons are producing neurotransmitters), but in the vicinity of two adjacent neurons in an excited state (and two adjacent The case where the neuron is producing a neurotransmitter at the same time is exceeded. The neurons therefore function in an equivalent manner to the AND logic gate. This type of neuron can be used as the oscillator 2 in the embodiment of the invention shown in FIG. In this situation, the neurotransmitter of interest may be a neurotransmitter that diffuses across the synapse at a relatively slow rate. The synapses (and neurotransmitters) that link adjacent neurons to the oscillator 2 are equivalent to the connections 12 and 22 in the embodiment shown in FIG. Acetylcholine is an example of a neurotransmitter that can diffuse across synaptic at a relatively slow rate (diffusion coefficient is approximately 1-5 x 10 ^-9 cm ² /sec = approximately 1-5 x 10 ^-13 m ² / Sec), and it can be used to provide a connection equivalent to connections 12 and 22 in FIG.

In one embodiment, the threshold concentration of another neuron for a particular neurotransmitter may be lower than the concentration of the neurotransmitter after it has spread across a synapse from a single adjacent neuron. Neurons can be connected to two adjacent neurons by synapses. Each adjacent neuron can produce a neurotransmitter with a concentration that is greater than the threshold concentration after the neurotransmitter has spread across the synapse. Since the threshold concentration of the neuron is such that it is exceeded in the case where either of the adjacent neurons is in an excited state (and any of the adjacent neurons is producing a neurotransmitter), the neuron can be Or "OR" logic gates work in an equivalent manner. This type of neuron can be used as the oscillator 1 in the embodiment of the invention shown in FIG. In this situation, the neurotransmitter of interest may be a neurotransmitter that diffuses across the synapse at a relatively fast rate. The synapses (and neurotransmitters) that link the oscillator 1 to two adjacent neurons are equivalent to the connections 11 and 21 in the embodiment shown in FIG. Glutamine is an example of a neurotransmitter that can diffuse across synapses at a relatively fast rate (diffusion coefficient is approximately 0.01-1 x μm ² /msec = approximately 0.01-1 x 10 ^-9 m ² /sec), and It can be used to form a connection equivalent to the connections 11 and 2a in FIG.

It will be appreciated that for the neuron described in the preceding paragraph to be used as the oscillator 1 in the embodiment shown in Figure 1, the neuron should be connected to The second neuron (in this case, can be used as the neuron of the oscillator 2 in the embodiment of the invention shown in Fig. 1) such that when the second neuron is being excited, the excitation of the neuron is suppressed (or prohibited). This can be achieved by connecting the first neuron and the second neuron via synapses and by enabling the second neuron to generate a neurotransmitter that diffuses across the synapse to the first neuron when it is being excited. The neurotransmitter produced by the second neuron can cause it to inhibit first neuronal firing when it interacts with the first neuron. The neurotransmitter can be a hyperpolarized neurotransmitter. An example of a hyperpolarized neurotransmitter is gamma-aminobutyric acid (GABA). The combination of synapses and neurotransmitters that link the second neuron to the first neuron is equivalent to the connection 30 between the first oscillator 1 and the second oscillator 2 of the embodiment shown in FIG. Since the first neuron is inhibited by the second neuron, it means that the first neuron can function in an equivalent manner to the XOR logic gate (as opposed to acting as an OR logic gate equivalent).

In one embodiment, a binary half adder can be used to form a programmable biocomputer using the neurons as described above.

In an alternative embodiment, the binary half adder is constructed as a circuit (e.g., an integrated circuit on a semiconductor wafer) rather than using neurons and synapses to construct the binary half adder of Figure 1. The circuit can, for example, comprise two Fitzhugh-Nagumo oscillators connected together.

Figure 5 is a circuit diagram showing the binary carry-half adder of Figure 1 constructed using two Fitzhugh-Nagumo oscillators. The first oscillator 1f constructed as the first Fitzhugh-Nagumo oscillator is connected to the second oscillator 2f constructed as the second Fitzhugh-Nagumo oscillator by the connection circuit 30f. More information about the Fitzhugh-Nagumo oscillator is available at S.Binczak et al. Found in Experimental Study of Electrical Fitzhugh-Nagumo Neurons with Modified Excitability (Neural Networks 19 684 (2006)).

The first Fitzhugh-Nagumo oscillator 1f includes a negative resistor 301 formed using an operational amplifier, which is connected in parallel with two resistive branches 302, 303. Each of the resistive branches 302, 303 is commutated by a diode (eg, a germanium diode). Negative resistor 301, together with resistive branches 302, 303, includes a non-linear resistor. The negative resistor 301 and the resistive branches 302, 303 are connected in parallel to the capacitor 304 and the two branches 305, 306. The branches 305, 306 comprise an inductor, a resistor and a voltage source, and are connected by a diode 307 (for example, 矽Diode) and reversing. The analog commutator 308 is controlled by a periodic signal and determines the state of the oscillator 1f.

The second Fitzhugh-Nagumo oscillator 2f has the same configuration as the first Fitzhugh-Nagumo oscillator 1f.

In operation, an input signal is provided to the first Fitzhugh-Nagumo oscillator 1f via the analog commutator 308. If the input signal exceeds a threshold, the first Fitzhugh-Nagumo oscillator 1f will oscillate during the stabilization limit cycle (with the constraint that the input signal does not exceed the upper threshold). If the input does not exceed the threshold, the first Fitzhugh-Nagumo oscillator 1f will not oscillate. The second Fitzhugh-Nagumo oscillator 2f behaves in the same manner. The threshold is determined by capacitor 304.

The connection circuit 30f provides unidirectional coupling from the second Fitzhugh-Nagumo oscillator 2f to the first Fitzhugh-Nagumo oscillator 1f. The connection circuit 30f includes: an adder-inverter 320 that receives an input from the second oscillator 2f a signal; an inverter 321 that receives an input signal from the adder-inverter; and a follower 322 that receives an input signal from the inverter. The output from the follower 322 is coupled to an analog commutator 308 that is coupled to an input to a first Fitzhugh-Nagumo oscillator 1f. Various resistors 323-328 are included in the connection circuit 30f. The three resistors 323-325 have a higher resistance than the other resistors (for example, 100 kΩ). The two resistors 326, 327 have a lower resistance (eg, 10 kΩ). Residual resistor 328 is located between the follower 322 and the analog commutator 308. This resistor 328 controls the coupling strength between the second Fitzhugh-Nagumo oscillator 2f and the first Fitzhugh-Nagumo oscillator 1f. The resistance of this resistor 328 can be selected based on the desired degree of coupling between the second Fitzhugh-Nagumo oscillator 2f and the first Fitzhugh-Nagumo oscillator 1f.

Although the above description has been referred to the use of the Fitzhugh-Nagumo oscillator, other types of oscillators can be used. The oscillator should have its property of tending to a stable non-oscillating state in the absence of an external input and oscillating in a limit cycle in the presence of an external input above a predetermined threshold. As further described above, neurons have this property. Examples of other types of oscillators that behave like neurons (and can be used to practice the invention) include Hodgkin-Huxley oscillators, Morris-Lecar oscillators, Hindmarsh-Rose oscillators, and Josephson junction oscillators.

Figure 6 is a circuit diagram showing two Josephson junction oscillators 1j, 2j connected by a one-way hyperpolarization (forbidden) link 30j. Each of the Josephson junction oscillators 1j, 2j is formed by one of the superconducting loops connected to the Josephson junctions 101, 102, 111, 112 (the Josephson junction is indicated as the intersection) Cross). Each Josephson junction contains two superconductors separated by an insulating barrier. The insulating barrier can be thin enough to allow current and/or voltage to pass between the superconductors. The insulating barrier may, for example, be 1 nm thick or may have some other suitable thickness. The electrons in each of the superconductors are represented by a coherent wave function with a definite phase. The phase difference from one side of the barrier to the other is called the Josephson phase and controls all electrical properties of the junction. More information on Josephson junctions can be found in Josephson Junction Simulation of Neurons (Phys Rev. E 82(1), 011914 (2010)) by P. Crotty et al.

As can be seen from FIG. 6, the second Josephson junction oscillator 2j includes a first Josephson junction 101 and a second Josephson junction 102. An inductor 103 is provided between the first Josephson junction 101 and the second Josephson junction 102. The bias current input _Ib provides a bias current to each of the Josephson junctions 101, 102. Receiving an input I _in an input signal, the input signal may be (e.g.) is generated by another oscillator. Input I _in is coupled to first Josephson junction 101 via first input inductor 104 and to second Josephson junction 102 via second inductor 105. The Josephson junctions 101, 102 and the inductors 103-105 together form a loop that establishes the Josephson junction oscillator 2j. An output is connected across the second Josephson junction 102, the output being a one-way link 30j.

In use, the bias current input I _b supplies current to the Josephson junctions 101, 102, which is insufficient to move the Josephson junctions to the swing state (the swing state is the excited state of the Josephson junction, as familiar This technology should be understood). When the input current I _in is high enough, current 102 of a second Josephson junction of the second Josephson junction into the turning state. A voltage across the second Josephson junction 102 occurs, thereby providing an output voltage to the one-way link 30j. The voltage across the second Josephson junction 102 produces a magnetic flux in the loop (i.e., Josephson junction oscillator 2j) that is similar to the membrane potential rise of the neuron. The magnetic flux induces a current in the loop, and this current causes the first Josephson junction 101 to move toward the swivel state. When the first Josephson junction 101 enters the swing state, the flux is discharged from the loop and the second Josephson junction 102 is thus relaxed from the revolution state. The first Josephson junction 101 is also relaxed from the swing state. This begins a cycle during which it is extremely difficult to initiate the rotation of the second Josephson junction 102. At the end of this period, if the input current I _in is kept high, the Josephson junction 102 will enter the second swing state again. When the input I _{in is} high, the process of the second Josephson junction 102 turning, stopping the rotation, turning again, etc. will continue indefinitely. This provides a limit cycle oscillation across the output voltage of the second Josephson junction 102. Thus, the first Josephson junction 101 and the second Josephson junction 102 together with the inductor form a Josephson junction oscillator 2j that acts as a limit cycle oscillator. When the input current I _in is cut off, once it has been through the first Josephson junction 101 stops rotation, it is no longer sufficient current is available for starting rotation of a second Josephson junction 102. The Josephson junction oscillator 2j therefore stops oscillating.

The first Josephson junction oscillator 1j has the same configuration as the second Josephson junction oscillator 2j.

The connection circuit 30j connects the second Josephson junction oscillator 2j to the first Josephson junction oscillator 1j. The connection circuit can act as a suppression connection circuit for preventing the first Josephson junction oscillator 1j in the second Joseph The Mori junction oscillator 2j oscillates while oscillating. The circuit 30j connecting the first Josephson junction oscillator 1j and the second Josephson junction oscillator is a resonance circuit formed by two resistors 121, 122, a capacitor 123 and an inductor 124. The capacitor 123 is connected across the second Josephson junction 102 of the second Josephson junction oscillator 2j and is connected between the resistors 121, 122. The inductor 124 is connected between the first resistor 121 and the second Josephson junction 102 of the second Josephson junction oscillator 2j. The output from the second resistor 122 is coupled to the input of the first Josephson junction oscillator 1j.

In operation, the effect of the connection circuit 30j depends on the sign of the bias current _Ib supplied to the second Josephson junction oscillator 2j. If the bias current is negative, the connection circuit 30j is inhibitory (providing a hyperpolarized connection) such that the first Josephson junction oscillator 1j will not oscillate if the second Josephson junction oscillator 2j is oscillating oscillation. This configuration can be used by embodiments of the present invention. If the bias current is positive, the oscillation of the second Josephson junction oscillator 2j will cause the first Josephson junction oscillator 1j to oscillate.

Other connection circuits can be used to provide an inhibitory connection between the second Josephson junction oscillator 2j and the first Josephson junction oscillator 1j.

Josephson junctions are available from HYPRES, Inc., New York, USA. HYPRES provides an integrated circuit with a large number of Josephson junctions (eg, 20,000 Josephson junctions) operating at 10 mW. A binary half adder comprising a Josephson junction as shown in Fig. 6 can thus be implemented in the integrated circuit. A large number of binary half adders can be implemented in the integrated circuit.

In other embodiments of the invention, other limit cycle oscillators (e.g., standard CMOS oscillators) may be used. In an embodiment, the group can be used State of operation with an oscillating amplifier. An example of this configuration is shown in Figure 7. More information on this form of oscillator can be found in C.M. Kim et al., Excitable Behaviour of an Operational Amplifier (Europhys. Lett. 71 723 (2005)).

In an embodiment, an oscillator formed by a Schmidt trigger can be used. Schmitt triggers are bistable multi-resonators that can be used to implement a relaxation oscillator. An example of a Schmitt trigger oscillator is shown in FIG.

Figure 9 shows a simulation of two oscillators (with an inhibitory (neural hyperpolarization) connection between the oscillators) that may form part of an embodiment of the invention. The simulations generated using Simulink software provide binary half adder operation.

Referring to Fig. 9, the first oscillator 1s and the second oscillator 2s are connected by an inhibitory connection 30s. The first oscillator 1s and the second oscillator 2s are Fitzhugh-Nagumo oscillators modeled using Equations 1 and 2 (see above). The two inputs I _n 1 _s and I _n 2 _s provide an input signal that is combined by adder A1. The first oscillator 1s is connected to the combined input by a low resistance connection R1 (here represented by an amplifier having a gain of 0.3). The second oscillator 2s is connected to the combined input via a high resistance connection R2 (here represented by an amplifier having a gain of 0.1).

Each input I _n 1 _s , I _n 2 _s has a value of 1 when the input is high and a value of 0 when the input is low. The resistance of the high resistance connection R2 is such that the threshold of the second oscillator 2s is reached only if both the first input I _n 1 _s and the second input I _n 2 _s are high. If only one input (eg, I _n 1 _s ) is high, the output from the high-resistance connection R2 is 0.1. This is not enough to oscillate the second oscillator 2s (requires an input exceeding 0.1). If the two inputs I _n 1 _s and I _n 2 _{s are} high, the output from the high-resistance connection R2 is 0.2. This exceeds the threshold of 0.1 and, as a result, the oscillator 2s oscillates.

The resistance of the low resistance connection R1 is such that the threshold of the first oscillator 1s is reached if the first input I _n 1 _s or the second input I _n 2 _{s is} high (output is 0.3, which exceeds the threshold value 0.1) . The first oscillator 1s has an upper threshold of 0.6 and will stop oscillating if this threshold is exceeded. If the two inputs I _n 1 _s and I _n 2 _{s are both} high, the output of the low-resistance connection R1 is 0.6. Since this does not exceed the threshold above the first oscillator 1s, the first oscillator will oscillate when both inputs I _n 1 _s , I _n 2 _{s are} high.

The connection 30s provides a one-way connection from the second oscillator 2s to the first oscillator 1s. The connection receives an output from the second oscillator 2s that is zero when the second oscillator is oscillating and one when the second oscillator is not oscillating. Connection 30s includes an operator configured to determine an input minus the absolute value of 1 (the input being the output received from the second oscillator 2s). Therefore, if the input to the connection 30s is 0, the output from the connection is 1. If the input to the connection 30s is 1, the output from the connection is 0. Therefore, if the second oscillator 2s is oscillating, the connection 30s provides an output 1. If the second oscillator is not oscillating, the operator OP provides an output of zero. The output of the connection 30s is indicated as C2. The output C2 connected to 30s is combined with the output from the low resistance connection R1 by the adder A2.

If the output from the connection 30s is high, the input to the first oscillator 1s will be 1 or greater (1.3 in the case where one of the inputs I _n 1 _s , I _n 2 _s is high, in two In the case where the input is high, it is 1.6). Since this exceeds the threshold 0.6, the first oscillator 1s will not oscillate. Therefore, if the second oscillator 2s is oscillating, the effect of the connection 30s is to suppress the oscillation of the first oscillator 1s. If the output from the connection 30s is low, the input to the first oscillator 1s will be completely determined by the inputs I _n 1 _s , I _n 2 _s . Therefore, when the second oscillator 2s is not oscillating, the high value at any of the inputs I _n 1 _s , I _n 2 _s causes the first oscillator 1s to oscillate. However, when the second oscillator 2s is oscillating, the first oscillator is prevented from oscillating regardless of the value at the first input C1. This provides the second oscillator 2s with the XOR functionality required by the binary half adder.

An advantage of a binary half adder in accordance with an embodiment of the present invention is that it may require relatively little energy to operate than a binary half adder formed using a transistor in a conventional manner. This is because the energy required to move the oscillator to the limit cycle state is relatively small.

An additional advantage of one of the binary half adders according to embodiments of the present invention is that its wiring can be made simpler than the wiring of a binary half adder formed in a conventional manner using a transistor.

An additional advantage of one of the binary half adders according to embodiments of the present invention is that it provides faster operation than conventional binary half adders. The operating speed of the binary half adder according to an embodiment of the present invention will depend on the cycle time of the oscillators 1, 2. The cycle time of the oscillator is often dependent on the power supplied to the oscillator. Therefore, the cycle time can be reduced by increasing the power. While increasing the power supplied to the oscillator will increase the power consumption of the binary half adder, the condition can be as follows: the power consumption remains less than the power consumption of an equivalent binary half adder formed by the transistor in a conventional manner. The power consumption of the oscillator can be reduced by reducing the size of the components used to form the oscillator.

An integrated digital circuit has been designed using a Simulation Program with Integrated Circuit Emphasis (SPICE), which provides binary half adder functionality in accordance with an embodiment of the present invention.

Figure 10 is a high-level representation of the integrated circuit designed using the SPICE simulator. The integrated circuit includes a first oscillator circuit 1 and a second oscillator circuit 2. The first oscillator circuit and the second oscillator circuit have an action corresponding to the behavior of the oscillator shown in FIG. 1. The first input A and the second input B are connected to the first oscillator 1 and the second oscillator 2 (these respectively correspond to the inputs In1 and In2 shown in FIG. 1). The output Vout from the second oscillator 2 is connected as the input C of the first oscillator 1 (this corresponds to the connection 30 shown in Figure 1). The output Out1 is obtained from the first oscillator 1 and the output Out2 is obtained from the second oscillator 2. The supply voltage Vdd of 1.2 V is supplied to the first oscillator 1 and the second oscillator 2 (other voltages can be used).

Figure 11 is a diagram showing the component order of the first oscillator circuit 1 shown in Figure 10. The first oscillator circuit 1 includes a large number of FETs (eg, MOSFETs) Q1-Q20. Some of the FETs Q1, Q3, Q5, Q7, Q9-10, Q13-14, Q17-18 are PFETs and are configured such that when their gate is connected to a low voltage (eg, connected to ground) it is turned "on". The other FETs Q2, Q4, Q6, Q8, Q11-12, Q15-16, Q19-20 are NFETs and are configured such that when their gate is connected to a high voltage (eg, connected to the supply voltage Vdd) it is turned "on". To facilitate a clear interpretation of the first oscillator circuit 1, the first oscillator circuit is divided into different sections by dashed lines.

The first portion of the first oscillator circuit 1 is an oscillator 1101. Oscillator 1101 includes six FETs Q1-Q6 that are configured as three inverters connected in series to each other. The first inverter 1102 includes a PFET Q1 connected in series with the NFET Q2 between the supply voltage Vdd and ground. The gates of FETs Q1, Q2 are coupled together and include the input of first inverter 1102. When the input is high, NFET Q2 is turned "on" and PFET Q1 is turned "off", and as a result, the output of the inverter is connected to ground. When the input is low, PFET Q1 is turned on and NFET Q2 is turned off, and as a result, the output of first inverter 1102 is connected to supply voltage Vdd. The FETs Q1, Q2 thus invert an input signal and thus act as an inverter.

The second inverter 1103 includes a pair of FETs Q3, Q4 provided in the same configuration as the first inverter 1102. The second inverter 1103 operates in the same manner as the first inverter 1102. The third inverter 1104 also includes a pair of FETs Q5, Q6 provided in the same configuration as the first inverter 1102. The third inverter 1104 operates in the same manner as the first inverter 1102. Since an odd number of inverters 1102-1104 are provided, the output from the third inverter 1104 is opposite to the input at the first inverter 1102.

Three inverters 1102-1104 are used instead of one inverter because the gain provided by the FETs is relatively low (the FETs are not designed to operate as amplifiers). The three inverters together provide a gain high enough to allow the oscillator 1101 to operate properly in the presence of noise. In an embodiment, the oscillator 1101 can include five inverters, seven inverters, or some other suitable odd number of inverters.

The output from the third inverter 1104 is coupled to the input of the first inverter 1102. The output from the third inverter 1104 to the input of the first inverter 1102 This connection causes the three inverters 1102-1104 to oscillate between the supply voltage Vdd and ground (i.e., act as an oscillator). The oscillation frequency is determined by the propagation delay through the inverter Vdd.

Although the oscillator 1101 will continuously oscillate regardless of the values at the inputs A, B, C of the first oscillator circuit 1, the signals seen at the output Out1 of the first oscillator circuit 1 are derived from the values at their inputs. Control, as explained below.

The input C of the first oscillator circuit 1 corresponds to the input 30 shown in Figure 1 and is an inhibitory input. Therefore, when the input C is high, the output Out1 of the first oscillator circuit 1 should be low. When the input C is low, in the case where the input A or the input B is high, the output Out1 of the first oscillator circuit 1 should oscillate between high and low. This functionality (excluding the effects of inputs A and B) is provided by six FETs Q7-Q12.

The second portion of the first oscillator circuit 1 is a pair of FETs Q7, Q8 connected in series to form an inverter 105. Inverter 105 provides "NOT" logic, i.e., provides an output signal that is opposite to the signal at input C.

The third portion of the first oscillator circuit 1 is four FETs Q9-Q12 that are connected such that they form a NAND circuit 106 that provides "NAND" logic. The input to NAND circuit 106 is the output from inverter 105 and the output from oscillator 1101. If the input received by NAND circuit 106 from inverter 105 is low (i.e., input C is high), the output from the NAND circuit is high. This applies regardless of whether the input received from oscillator 1101 is high or low. This is because the PFET Q9 is turned on and the output of the NAND circuit 106 is connected to the supply voltage Vdd regardless of the state of the input received from the oscillator 1101.

If the input received by the NAND circuit 106 from the inverter is high (i.e., input C is low), the output from the NAND circuit will depend on the signal received from the oscillator 1101. NFET Q11 is turned on, but this FET is not directly connected to ground, but is actually connected to ground via NFET Q12. The input to the NFET Q12 receives the output from the oscillator 1101. When the output from the oscillator 1101 is high, the NFET Q12 is turned on, thereby connecting the output of the NAND circuit 106 to ground via NQ11 and NQ12. When the output from the oscillator 1101 is low, the NFET Q12 is turned off, but the PFET Q10 is turned on, thereby connecting the output of the NAND circuit 106 to the supply voltage Vdd. Thus, when input C is low, NAND circuit 106 provides an oscillating output that is opposite in phase to the output of oscillator 1101.

The combined effect of oscillator 1101, inverter 105, and NAND circuit 106 is to provide a high output with input C high and an oscillating output with input C low. The remainder of the oscillator circuit 1 combines this logic with the logic caused by inputs A and B.

The fourth portion of the first oscillator circuit 1 includes four FETs Q13-16 that are configured to receive inputs A and B and provide a NOR circuit based on the output of the "reverse OR" (NOR) logic. A pair of PFETs Q13, Q14 are connected in series to the voltage supply Vdd. A pair of NFETs Q15, Q16 are connected in parallel to ground. When both inputs A and B are high, PFETs Q13 and Q14 are turned off and NFETs Q15 and Q16 are turned "on". The output from the NOR circuit 107 is thus connected to ground. When both inputs A and B are low, PFETs Q13 and Q14 are turned "on" and NFETs Q15 and Q16 are turned "off". The output from the NOR circuit 107 is thus connected to the voltage supply Vdd. If input A is high and input B is low, then FET Q13 and Q15 are turned on and FETs Q14 and Q16 are turned off. Since the PFET Q13 is connected in series with the PFET Q14 (which is turned off), the output from the NOR circuit 107 is not connected to the voltage supply Vdd. However, since the NFET Q15 is connected in parallel with the NFET Q16, the output from the NOR circuit 107 is connected to the ground even if the NFET Q16 is turned off. Therefore, when input A is high and input B is low, the output from NOR circuit 107 is low. Similarly, if input A is low and input B is high, FETs Q13 and Q15 are turned off and FETs Q14 and Q16 are turned "on". The output from the NOR circuit 107 is thus connected to ground via the NFET Q16. The logic provided by the NOR circuit 107 is therefore such that if both inputs A and B are low, the output is high, and if input A or input B is high, the output is low.

The last portion of the first oscillator circuit 1 contains four FETs Q17-20, which are also configured as NOR circuits 108. The NOR circuit 108 has the same configuration as the NOR circuit 107 described above. The NOR circuit 108 receives the output from the NAND circuit 106 and the output from the NOR circuit 107 as inputs. The logic provided by NOR circuit 108 is that if both inputs are low, the output is high, and if either input is high, the output is low.

As explained further above, if the input C is high, the output from NAND circuit 106 is high. In the event of this condition, NFET Q20 is turned "on", thereby connecting the output of NOR circuit 108 (and thus the output Out1 of oscillator circuit 1) to ground. This provides the oscillator circuit 1 with the inhibitory functionality further mentioned above. That is, if the input C is high, the oscillator circuit 1 cannot provide a high output.

As explained further above, if the input C is low, then from NAND The output of path 106 oscillates. In the case of this condition, the NOR circuit 108 oscillates between a first state (where PFET Q17 is turned on and NFET Q20 is turned off) and a second state (where PFET Q17 is turned off and NFET Q20 is turned on). . When the NOR circuit 108 is in the second state, its output is connected to ground. When the NOR circuit 108 is in the first state, its output can be connected to the voltage supply Vdd, but will only be connected if the PFET Q18 is turned "on". PFET Q18 is controlled by the output of NOR circuit 107 and is turned "on" with the output from NOR circuit 107 low. If you enter A or the input B is high, the situation will be the same. Thus, if input A or input B is high and input C is low, NOR circuit 108 will be in a first state (where its output Out1 is connected to supply voltage Vdd (via PFETs Q17 and Q18)) and a second state (where its output is Out1) Connected to ground (via NFET Q20)) to oscillate. The first oscillator circuit 1 thus provides an oscillating output Out1.

If either input A or input B is non-high, then NFET Q19 is turned "on" and the first oscillator circuit 1 thus provides a zero output. The first oscillator circuit 1 provides an oscillating output according to logic (A OR B) NOT C.

Figure 12 is a diagram showing the component order of the second oscillator circuit 2 shown in Figure 10. The second oscillator circuit 2 includes a plurality of FETs Q21-Q39, two resistors Res1, Res2, and a capacitor Cap1. Some of the FETs Q21, Q23, Q25, Q27, Q29-32, Q37, Q38 are PFETs and are configured such that when their gate is connected to a low voltage (eg, connected to ground) it is turned "on". The other FETs Q22, Q24, Q26, Q28, Q33-36, Q39 are NFETs and are configured such that when their gate is connected to a high voltage (eg, connected to the supply voltage Vdd) it is turned "on". To facilitate a clear explanation of the second oscillator circuit 2, The dashed line divides the second oscillator circuit into different sections.

The first portion of the second oscillator circuit 2 is an oscillator 201 constructed using six FETs Q21-Q26. FETs Q21-Q26 are configured as three inverters 202-204 connected in series. The configuration of the oscillator 201 is the same as the oscillator 1101 described above with respect to Figure 11, and the oscillator operates in the same manner.

The second portion of the second oscillator circuit 2 is an inverter 205 formed by two FETs Q27, Q28 connected in series. The inverter 205 has the same configuration as the inverter 105 described above with respect to FIG. 11 and operates in the same manner. Inverter 205 provides an output that is opposite of the input received at input C.

A portion of the second oscillator circuit 2 is a NAND circuit 206. The NAND circuit 206 includes four PFETs Q29-Q32 connected in parallel to the supply voltage Vdd and four NFETs Q33-Q36 connected in series to the ground. The four PFETs Q29-Q32 connected to the supply voltage Vdd have gates connected to the input B, the input A, the output from the oscillator 201, and the output from the inverter 205, respectively. The four NFETs Q33-36 connected in series to ground have gates connected to the output from inverter 205, input B, input A, and the output from oscillator 201, respectively. Due to the parallel connection of PFET Q29-Q32 to supply voltage Vdd, NAND circuit 206 will generate high if either input A, input B, output from inverter 205, or output from oscillator 201 is low. Output. Due to the series connection of NFETs Q33-Q36 to ground, if input A, input B, output from inverter 205, or output from oscillator 201 are both high, NAND circuit 206 will only produce a low output.

If input C is high, this will be converted by inverter 205 to a low output. Since NAND circuit 206 is receiving a low input, it will produce a high output. If lost If A or input B is low, then NAND circuit 206 will similarly produce a high output. However, if both input A and input B are high and input C is low, the output of NAND circuit 206 will be controlled by the output of oscillator 201. When the output of the oscillator is high, then NFET Q36 will be turned on and PFET Q 31 will be turned off. All four NFETs Q33-Q36 are thus turned "on" (and all four PFETs Q29-Q32 are turned off) and NAND circuit 206 produces a low output. When the output of the oscillator is low, then NFET Q36 will be turned off and PFET Q31 will be turned "on". Thus there is no longer a connection between the output of NAND circuit 206 and ground, but there is a connection between this output and supply voltage Vdd. The NAND circuit 206 thus produces a high output. Thus, when the NAND circuit is controlled by the oscillator 201, it produces an output that oscillates and is phase-opposited to the oscillator output.

The last portion of the second oscillator circuit 2 is an inverter 208 (the second portion 207 of the second oscillator circuit 2 is further described below). Inverter 208 includes two FETs Q38, Q39 connected in series. Inverter 208 inverts the input signal to provide an output Out2. Considering the other parts of the second oscillator circuit 2 described above, if either of the inputs A and B is low or if the input C is high, the output Out2 is low. If the inputs A and B are high and if the input C is low, the output Out2 oscillates. The second oscillator circuit 2 provides an oscillating output according to logic (A AND B) NOT C. This is the logic required by the second oscillator 2 shown in FIG.

The second portion of the second oscillator circuit 2 includes a conversion circuit 207 including a PFET Q37, a pair of resistors Res1, Res2, and a capacitor Cap1. Conversion circuit 207 converts the oscillating input to a constant (or substantially constant) high output and provides a low output when the input is low. The first resistor Res1 has a resistance of 100 kΩ and the second resistor Res2 has a 1 MΩ resistance. Capacitor Cap1 has a capacitance of 10 femtofarads. The resistors Res1, Res2 are arranged in series, the second resistor Res2 is connected to ground and the first resistor Res1 is connected to the collector of the PFET Q37. The emitter of PFET Q37 is connected to the supply voltage Vdd. The capacitor Cap1 is connected in parallel with the second resistor Res2. Capacitor Cap1 and resistors Res1, Res2 may have other suitable values.

When the output from the NAND circuit 206 is low, the PFET Q37 is turned on, thereby connecting the first resistor Res1 to the supply voltage Vdd. The current therefore flows through the resistors Res1, Res2. Since the resistance of the first resistor Res1 is one tenth of the resistance of the second resistor Res2, the voltage between the resistors is close to the supply voltage Vdd. In practice, due to the operation of NAND circuit 206, the input to detection circuit 207 will never be constantly low, and the reality is that it will be high or will oscillate between high and low. The capacitor Cap1 is used to smooth the oscillation between high and low such that the output connection Vout has a value that remains high when the input to the conversion circuit 207 is positively oscillating. When the input to the conversion circuit 207 is high, the PFET Q37 is turned off. The capacitor Cap1 is discharged via the resistor Res2 and the voltage at the output connection Vout is thus lowered to ground. If inputs A and B are high and input C is low, the output connection Vout is therefore high, and if either of inputs A and B is low or if input C is high, then output connection Vout is low. The output connection Vout is used as the input C of the first oscillator 1 (as shown in FIG. 10).

Referring to Figure 12 in conjunction with Figure 10, it can be seen that the input C of the second oscillator 2 is coupled to ground. Since the input C of the second oscillator 2 is always low, if both inputs A and B are high, the output Out2 of the second oscillator will oscillate.

Figure 13 is a set of graphs that have been produced using the SPICE simulated circuits shown in Figures 10-12. Shows input A and input B (the input A and The input B is connected to both the first oscillator circuit 1 and the second oscillator circuit 2), together with the respective outputs Out1 and Out2 of the first oscillator circuit and the second oscillator circuit. The inputs and the outputs are shown as being a function of the voltage as a function of time (the total time of 100 nanoseconds shown in Figure 13).

At zero time, both input A and input B are low and outputs Out1 and Out2 are also low. At about 10 nanoseconds, input A goes high and input B goes low. Output Out1 begins to oscillate and output Out2 remains low. This is as needed, because if one of the inputs A, B goes high, the output of the first oscillator circuit 1 should oscillate and the output of the second oscillator circuit 2 should remain low. The first oscillation of the output Out1 has an intermediate amplitude, but the subsequent oscillation of the output Out1 has a full amplitude (this is because the first oscillator circuit 1 has a limited start-up time).

At about 20 nanoseconds, input A goes low and input B goes high. This does not cause any change in the output. Output Out1 continues to oscillate and output Out2 remains low. This is as needed, because if one of the inputs A, B is high, the output of the first oscillator circuit 1 should continue to oscillate while the output of the second oscillator circuit 2 should remain low.

At about 30 nanoseconds, input A goes high and input B remains high. This causes the output Out2 to start oscillating and the output Out1 to go low. This is as needed: if both input A and input B are high, the output of the second oscillator circuit 2 should oscillate, and if both input A and input B are high, then the first oscillator circuit 1 The output strain is low. The two oscillations of the output Out1 of the first oscillator circuit 1 occur after the input A has gone high. This is primarily due to the limited time it takes for the conversion circuit 207 to produce a high output (once it has received the oscillating input). As can be seen from Figure 13, the oscillation frequency is about 5 nanoseconds. This frequency is passed through the inverter The propagation delays of 1102-1104 and 202-204 are determined. It can be modified by changing the number of inverters. Alternatively, it can be changed by adding a resistor and a capacitor. In a VLSI circuit, many inverters are preferably used to change the propagation instead of adding resistors and capacitors.

As can be seen from Figure 10, the input C of the second oscillator circuit 2 is not used by a binary half adder (which is connected to ground). However, input C can be used when constructing a more complex configuration of the oscillator (e.g., the full adder described below with respect to Figure 14).

The integrated circuit corresponding to the integrated circuit shown in Figs. 10 to 12 can be manufactured in a conventional manner. The integrated circuit can be fabricated, for example, using a lithography apparatus that provides a resolution (critical dimension) of about 90 nm. The integrated circuit can be fabricated, for example, at some other resolution.

Although the outputs Out1, Out2 of the first oscillator circuit 1 and the second oscillator circuit 2 are oscillating outputs, in an embodiment, the first oscillator and the second oscillator may be configured such that they provide a constant (or substantial Upper constant) output, not oscillating output. This can be done, for example, by using a conversion circuit (or other suitable conversion circuit) similar to the conversion circuit 207 shown in FIG. The advantage of providing a constant or substantially constant output is to avoid the need to consider the phase when connecting the oscillators together.

The first oscillator circuit 1 and the second oscillator circuit 2 shown in Figs. 11 and 12 are merely examples of oscillator circuits which can form part of an embodiment of the present invention and which can be implemented as an integrated circuit. Other oscillator circuits can be used and implemented as integrated circuits.

A large number of binary half adders according to the present invention can be used by known parties The half adders are combined to form a computer processor. Figure 14 is a graphical illustration of five oscillators 3-7 configured to operate as a binary adder, in accordance with an embodiment of the present invention. The oscillators can have any of the types previously discussed. The first input In3 is transmitted to the oscillator 7 and the oscillator 3 via the connections 37 and 33, respectively. Connection 33 has a low resistance and connection 37 has a high resistance. This is schematically illustrated in Figure 14 by indicating connection 33 as a thick line and connecting connection 37 as a thin line. The second input ln4 is passed to the oscillators 7 and 3 via connections 47 and 43, respectively. Connection 43 has a low resistance and connection 47 has a high resistance (represented again by thick lines and thin lines, respectively). Connection 70 extends between oscillator 7 and oscillator 3. The oscillators 7 and 3 thus form a first half adder. The third input In5 is transmitted to the oscillator 4 and the oscillator 5 via the connections 54 and 55, respectively. Connection 54 has a low resistance and connection 55 has a high resistance (represented by thick lines and thin lines, respectively). The output of the oscillator 3 is passed to the oscillators 4 and 5 via connections 34 and 35, respectively. Connection 34 has a low resistance and connection 35 has a high resistance (represented again by thick lines and thin lines, respectively). Connection 50 extends between oscillator 5 and oscillator 4. The oscillators 4 and 5 thus form a second half adder connected to one of the first half adders. The outputs of oscillators 5 and 7 are passed to further oscillator 6 via connections 56 and 76, respectively. Both connections 56 and 76 have low resistance (indicated by thick lines). Therefore, the oscillator 6 is connected to both the first half adder and the second half adder to form an adder.

In a manner similar to connection 30 of the embodiment shown in Figure 1, connection 50 ensures that the oscillation of oscillator 4 is disabled when oscillator 5 is oscillating. Similarly, connection 70 ensures that oscillation of oscillator 3 is banned when oscillator 7 is oscillating stop.

In the embodiment shown in FIG. 14, the nature of the connection between the input, the input and the oscillator, and the connection between the oscillator and the other oscillator determines whether the oscillator is similar to the embodiment shown in FIG. The mode oscillates.

Table 2 is a truth table of the oscillator shown in Fig. 14. The truth table reflects the above description and it is verified that the oscillator 3-7 acts as a binary adder.

Figure 15 shows a logic gate configuration operating in an equivalent manner to oscillator 3-7. The logic gate 3a is an XOR gate equivalent to the oscillator 3. The logic gate 4a is an XOR gate equivalent to the oscillator 4. The logic gate 5a is an AND gate equivalent to the oscillator 5. The logic gate 6a is an OR gate equivalent to the oscillator 6. The logic gate 7a is an AND gate equivalent to the oscillator 7. Equivalent connections, inputs, and outputs have been given the same numbers in Figures 5 and 6.

Figure 16 schematically illustrates a binary adder that can be constructed using three oscillators B1-3 in accordance with an embodiment of the present invention. The oscillator can have any of the types previously discussed. The binary adder has three inputs In3-5, each of which is connected to each oscillator B1-3. The first output Out3 is connected to the first oscillator B1. The second output Out4 is connected to the first Both the oscillator B2 and the third oscillator B3. The binary adder can be considered to include a binary half adder (formed by the first oscillator B1 and the second oscillator B2) and an additional oscillator B3.

Each of the oscillators B1-3 has a different threshold. The threshold of the first oscillator B1 is set such that the first oscillator B1 will oscillate if any of the three inputs In3-5 has a high value. The second oscillator B2 has a threshold that is set such that it will oscillate if either of the three inputs In3-5 has a high value. The threshold of the third oscillator B3 is set such that it will oscillate only if all three inputs In3-5 have a high value.

The unidirectional suppression connection 80 is coupled from the third oscillator B3 to the second oscillator B2. The unidirectional suppression connection 90 extends from the second oscillator B2 to the first oscillator B1. The effect of the suppression connections 80, 90 is such that the second oscillator B2 will not oscillate if the third oscillator B3 is oscillating, and so that the first oscillator B1 will oscillate while the second oscillator B2 is oscillating No oscillation.

In operation, if only one of the three inputs In3-5 is high, only the threshold of the first oscillator B1 will be exceeded. The first oscillator B1 will therefore oscillate and provide a high output at output 3. The second oscillator B2 and the third oscillator B3 will not oscillate and the output at output 4 will remain low.

If the first input In3 and the second input In4 are both high, the threshold of the first oscillator B1 and the second oscillator B2 will be exceeded, but will not exceed the threshold of the third oscillator B3. Therefore, the second oscillator B2 will oscillate. The oscillation of the second oscillator B2 will prevent the first oscillator B1 from oscillating via the suppression connection 90. Therefore, a low output will be provided at output 3 and a high input will be provided at output 4. Out. This same operation will occur regardless of which of the three inputs In3-5 is high, since each of the inputs is connected to each of the oscillators B1-3.

If all three inputs In3-5 are high, the thresholds for all three B1-3 oscillators will be exceeded. The oscillation of the third oscillator B3 will prevent the second oscillator B2 from oscillating (via the suppression connection 80). Since the second oscillator B2 does not oscillate, the suppression connection 90 between the second oscillator B2 and the first oscillator B1 has no effect. Therefore, the first oscillator B1 will also oscillate. Output 3 and output 4 are therefore high.

The above explanation confirms that the binary adder shown in Fig. 16 provides an operation according to the truth table further shown in Table 2 above.

The binary adder shown in Figure 16 does not rely solely on conventional logic gates having one or two inputs. Instead, three inputs are provided to each oscillator B1-3. Each oscillator behaves differently according to its threshold. In an alternative embodiment, an attribute other than the threshold of the oscillator can be used to provide a similar effect. For example, each oscillator B1-3 can have the same threshold, but can have different bias currents.

In the above embodiment, the coupled oscillator has been used to generate the binary half adder and the binary adder. To achieve this, the oscillators are coupled in the following manner: they form XOR, AND and OR logic gates. It will be appreciated that the use of coupled oscillators to form other types of logic gates is also within the scope of the present invention. 17 and 18 respectively show oscillators that form a NOR gate and a NAND gate.

The NOR gate shown in FIG. 17 includes a first oscillator 8, which is first oscillator 8. Connected to the first input In6 and the second input In7 via connections 68 and 78, respectively. These connections all have low resistance such that an input signal provided at In6 or In7 will cause oscillator 8 to oscillate. Connection 100 extends between first oscillator 8 and second oscillator 9. The second oscillator 9 is provided with a constant power input P such that the second oscillator 9 oscillates. However, when the first oscillator 8 is oscillating, the oscillation of the second oscillator 9 is inhibited via the connection 100.

Table 3 is a truth table of the oscillator shown in Fig. 17. This truth table reflects the above description and confirms that oscillators 8 and 9 act as NOR logic gates.

The NAND gate shown in FIG. 18 includes a first oscillator 801 that is coupled to a first input In8 and a second input In9 via connections 810 and 910, respectively. These connections all have a high resistance such that an input signal that needs to be provided at both In8 and In9 causes the oscillator 801 to oscillate. Connection 800 extends between first oscillator 801 and second oscillator 802. The second oscillator 802 is provided with a constant power input P such that the second oscillator 802 oscillates. However, when the first oscillator 801 is oscillating, the oscillation of the second oscillator 802 is disabled via the connection 800.

Table 4 is a truth table of the oscillator shown in Fig. 18. The truth table reflects the above description and confirms that the oscillators 801 and 802 act as NAND logic gates.

Any of the above logic gates (eg, NOR gates and NAND gates) can be used to form a memory. Memory of a known type that can use NOR and/or NAND logic gates is referred to as a flip-flop. Those skilled in the art will well understand the use of logic gates to generate flip-flops. The use of a memory of a NOR and/or NAND gate formed by an oscillator in accordance with the present invention would require continuous supply of power to some oscillators (as indicated by P in Figures 11 and 12). Since the memory will require a continuous supply of power, the memory is referred to as dynamic memory. The power required to maintain the oscillator at a stable limit cyclic oscillation can be relatively small (e.g., as compared to the power required by conventional memory).

It will be appreciated that the logic gate formed by the oscillator in accordance with the present invention can be used to form any suitable type of memory.

In applications other than computer processors and memories, a large number of binary half adders in accordance with the present invention can be used to replace half adders formed using conventional transistor configurations.

The present invention provides different methods for using neurons (or circuits similar to neurons) for calculations. Instead of trying to replicate a biological system (in this case, millions of connections are provided to each neuron), only two or three connections are provided, for example, to each neuron. The neurons are configured to provide a binary block adder, a building block for the binary logic circuit, rather than trying to make the god A network of complex interconnections is built over the network.

1‧‧‧Oscillator

1a‧‧‧Logic gate

1f‧‧‧first oscillator

1j‧‧‧Josephson junction oscillator

1s‧‧‧first oscillator

2‧‧‧Oscillator

2a‧‧‧Logic gate

2f‧‧‧second oscillator

2j‧‧ Josephson junction oscillator

2s‧‧‧second oscillator

3‧‧‧Oscillator

3a‧‧‧Logic gate

4‧‧‧Oscillator

4a‧‧‧Logic gate

5‧‧‧Oscillator

5a‧‧‧Logic gate

6‧‧‧Oscillator

6a‧‧‧Logic gate

7‧‧‧Oscillator

7a‧‧‧Logic gate

8‧‧‧First oscillator

9‧‧‧second oscillator

11‧‧‧Connect

12‧‧‧Connect

21‧‧‧Connect

22‧‧‧Connect

30‧‧‧Connect/Input

30a‧‧‧ driven oscillator

30b‧‧‧second output

30f‧‧‧Connected circuit

30j‧‧‧One-way hyperpolarized (prohibited) link/connection circuit

30s‧‧‧Connect

33‧‧‧Connect

34‧‧‧Connect

35‧‧‧Connect

37‧‧‧Connect

43‧‧‧Connect

47‧‧‧Connect

50‧‧‧Connect

54‧‧‧Connect

55‧‧‧Connect

56‧‧‧Connect

68‧‧‧Connect

70‧‧‧Connect

76‧‧‧Connect

78‧‧‧Connect

80‧‧‧ one-way restraint connection

90‧‧‧ one-way restraint connection

100‧‧‧Connect

101‧‧‧Josephson junction

102‧‧‧Josephson junction

103‧‧‧Inductors

104‧‧‧First Input Inductor

105‧‧‧Second inductor/inverter

106‧‧‧ "Reverse" (NAND) circuit

107‧‧‧"NOR" circuit

108‧‧‧NOR circuit

111‧‧‧Josephson junction

112‧‧‧Josephson junction

121‧‧‧Resistors

122‧‧‧Resistors

123‧‧‧ capacitor

124‧‧‧Inductors

201‧‧‧Oscillator

202‧‧‧Inverter

203‧‧‧Inverter

204‧‧‧Inverter

205‧‧‧Inverter

206‧‧‧NAND circuit

207‧‧‧End part/conversion circuit

208‧‧‧Inverter

301‧‧‧negative resistor

302‧‧‧Resistive branch

303‧‧‧Resistive branch

304‧‧‧ capacitor

305‧‧‧ branch

306‧‧‧ branch

307‧‧‧ diode

308‧‧‧ Analog commutator

320‧‧‧Adder-Inverter

321‧‧‧Inverter

322‧‧‧Follower

323‧‧‧Resistors

324‧‧‧Resistors

325‧‧‧Resistors

326‧‧‧Resistors

327‧‧‧Resistors

328‧‧‧Resistors

800‧‧‧Connect

801‧‧‧ first oscillator

802‧‧‧second oscillator

810‧‧‧Connect

910‧‧‧Connect

1101‧‧‧Oscillator

1102‧‧‧First Inverter

1103‧‧‧Second inverter

1104‧‧‧ Third Inverter

A‧‧‧ input

A1‧‧‧Adder

A2‧‧‧Adder

B‧‧‧ input

B1‧‧‧ first oscillator

B2‧‧‧second oscillator

B3‧‧‧ third oscillator

C‧‧‧ input

C1‧‧‧ first input

C2‧‧‧ output

I _b ‧‧‧bias current input

I _in ‧‧‧Input current

In1‧‧‧ first input

In2‧‧‧ second input

In3‧‧‧ first input

In4‧‧‧ second input

In5‧‧‧ third input

In6‧‧‧ first input

In7‧‧‧ second input

In8‧‧‧ first input

In9‧‧‧ second input

I _n 1 _s ‧‧‧ input

I _n 2 _s ‧‧‧Input

Out1‧‧‧ first output

Out2‧‧‧second output

Out3‧‧‧ first output

Out4‧‧‧second output

P‧‧‧ Constant power input

Q1-Q39‧‧‧FET

R1‧‧‧ low resistance connection

R2‧‧‧ high resistance connection

Res1‧‧‧First Resistor

Res2‧‧‧second resistor

Cap1‧‧‧ capacitor

Vdd‧‧‧Power supply voltage

Vout‧‧‧Output/Output Connection

1 is a schematic illustration of a binary half adder in accordance with an embodiment of the present invention; FIG. 2 is a logic gate diagram of a binary half adder equivalent to the embodiment shown in FIG. 1; FIG. 3a, FIG. 3b And Figure 3c shows the simulation results of the operation of the oscillator forming part of the binary half adder; Figures 4a to 4d show the simulation results of the operation of the binary half adder; Figure 5 is an illustration of the operation of the binary half adder according to an embodiment of the present invention Circuit diagram of a binary half adder formed by a Fitzhugh-Nagumo oscillator; FIG. 6 is a circuit diagram of a binary half adder formed by a Josephson junction oscillator according to an embodiment of the present invention; FIG. 7 is a circuit diagram capable of forming the present invention A circuit diagram of an oscillator of a portion of an embodiment; FIG. 8 is a circuit diagram of a Schmitt trigger oscillator that may form part of an embodiment of the present invention; and FIG. 9 schematically illustrates an embodiment of the invention in accordance with an embodiment of the present invention. Simulation of a binary half adder; FIG. 10 is a high-order representation of an integrated circuit in accordance with an embodiment of the present invention; FIG. 11 is a block diagram representation of the first portion of the integrated circuit shown in FIG. 10; Integrated circuit shown in 10 The component level representation of the second part; Figure 13 is a set of graphs showing the operation of the integrated circuit shown in Figures 10 to 12; Figure 14 is a graphical illustration of a binary adder according to an embodiment of the present invention; Figure 15 is the same as Figure 14 The illustrated embodiment is equivalent to a logical gate diagram of a binary adder; FIG. 16 is a graphical illustration of a binary adder in accordance with an embodiment of the present invention; and FIG. 17 is a NOR logic gate in accordance with an embodiment of the present invention. FIG. 18 is a graphical illustration of a NAND logic gate in accordance with an embodiment of the present invention.

1. . . Oscillator

2. . . Oscillator

11. . . connection

12. . . connection

twenty one. . . connection

twenty two. . . connection

30. . . Connection/input

30a. . . Slave oscillator

30b. . . Second output

In1. . . First input

In2. . . Second input

Out1. . . First output

Out2. . . Second output

Claims (17)

A binary half-adder includes a first oscillator and a second oscillator, each oscillator being coupled to a first input and a second input, the second oscillator being coupled to the a first oscillator, wherein the first oscillator is configured to oscillate if the first input is high or the second input is high, the second oscillator being configured to be at the first input and the The second input is oscillating, and wherein the connection between the second oscillator and the first oscillator is configured to suppress the second oscillator while the second oscillator is oscillating An oscillator oscillation. As in claim 1, the binary half adder, wherein each oscillator is configured to tend to a stable non-oscillating state in the absence of an external input, and is configured to be external to one of the thresholds The input oscillates with a limit cycle. The continuation half adder of claim 2, wherein at least one of the oscillators is configured to steer toward a stable non-oscillating state if the external input exceeds an upper threshold. The binary half adder of any one of claims 1 to 3, wherein the first oscillator and the second oscillator are circuits. The second half adder of claim 4, wherein the first oscillator and the second oscillator comprise a plurality of FETs. The second half adder of claim 4, wherein the first oscillator and the second oscillator are Fitzhugh-Nagumo oscillators, and a circuit provides the connection between the second oscillator and the first oscillator , the connection is one Inhibitory connection. The requesting device 4 bis carry a half adder, wherein the first oscillator is formed by a pair of Josephson junctions, the second oscillator is formed by a pair of Josephson junctions, and a circuit provides the second oscillator The connection between the first oscillators is a suppression connection. The binary half adder of any one of claims 1 to 3, wherein the connection between the second oscillator and the first oscillator comprises a slave oscillator configured to Oscillation is non-in-phase with the first oscillator and thereby causing the oscillator of the first oscillator to stop. The binary half adder of any one of claims 1 to 3, wherein the second oscillator has a higher threshold than the first oscillator. A binary half adder according to any one of claims 1 to 3, wherein the first oscillator receives a bias current or a bias voltage greater than the second oscillator. The binary half adder of any one of claims 1 to 3, wherein the connection from the first input and the second input to the second oscillator has a ratio from the first input and the second input to the The first oscillator is connected to a high impedance. The ninth carry-half adder of claim 1, wherein the first oscillator is a first neuron (neuron) and the second oscillator is a second neuron, the connection is a synapse, and The second neuron is configured to produce an inhibitory neurotransmitter as it is oscillating. A binary adder comprising two binary half adders, wherein Each of the binary half adders is a binary half adder as claimed in any one of claims 1 to 12, and the binary half adders are combined with an additional oscillator. A binary adder comprising a binary half adder according to any one of claims 1 to 12, and further comprising a third oscillator connected to the second oscillator, the third oscillator and the The connection between the second oscillators is configured to inhibit oscillation of the second oscillator while the third oscillator is oscillating, and wherein the first oscillator, the second oscillator, and the third oscillation The devices are each coupled to a first input, a second input, and a third input, the first oscillator being configured to be high if the first input, the second input, or the third input is high Oscillation, the second oscillator configured to oscillate if any of the first input, the second input, or the third input is high, and the third oscillator is configured to The first input, the second input, and the third input are both oscillating. A binary half adder comprising a first oscillator and a second oscillator, each oscillator being respectively connected to a first input and a second input, the second oscillator being connected to one of the first oscillators An output, wherein the first oscillator is configured to oscillate if the first input is high or the second input is high, the second oscillator being configured to be at the first input and the second input Oscillation when both are high, and wherein the first oscillator and the second oscillator are configured to oscillate at the same frequency, and the connection between the second oscillator and the output of the first oscillator Configuring to cause the second oscillator and the second oscillator to oscillate from the second The output of the oscillator will be combined anti-phase with the output from the first oscillator. A logic circuit device comprising a first oscillator coupled to a second oscillator, the connection between the second oscillator and the first oscillator being configured to oscillate while the second oscillator is oscillating In the case of oscillating the first oscillator, wherein the first oscillator is coupled to a power supply such that the first oscillator will oscillate unless the oscillation of the first oscillator is inhibited by the second oscillator, wherein a first input and a second input are provided to the second oscillator and the threshold of the second oscillator is such that the second oscillator is high when the first input is high or the second input is high It will oscillate. A logic circuit device comprising a first oscillator coupled to a second oscillator, the connection between the second oscillator and the first oscillator being configured to oscillate while the second oscillator is oscillating In the case of oscillating the first oscillator, wherein the first oscillator is coupled to a power supply such that the first oscillator will oscillate unless the oscillation of the first oscillator is inhibited by the second oscillator, wherein a first input and a second input are provided to the second oscillator and one of the second oscillators has a threshold such that the second oscillator will only be at both the first input and the second input Oscillate for high conditions.