TWI582769B - Static random access memory - Google Patents

Description

Static random access memory

The invention relates to a single port static random access memory (SRAM), in particular to an effective improvement of the standby performance of the 單埠SRAM, and can effectively improve the reading speed and effectively reduce Leakage current and can solve the problem that SRAM is difficult to write logic 1 with a single bit line.

As is shown in FIG. 1a, the static random access memory (SRAM) mainly includes a memory array, which is composed of a plurality of memory blocks (memory block, MB _1). , MB _{2 ,} etc., each memory block is composed of a plurality of columns of memory cells and a plurality of columns of memory cells. Each column of memory cells and each row of memory cells each include a plurality of memory cells; a plurality of word lines (word line, WL ₁ , WL _{2 ,} etc.), each word line corresponding to a plurality of columns of memory One of the body cells; and a plurality of bit line pairs (BL ₁ , BLB ₁ ... BL _m , BLB _{m ,} etc.), each bit line pair corresponding to a plurality of rows of memory cells One row, and each bit line pair is composed of one bit line (BL ₁ ... BL _m ) and one complementary bit line (BLB ₁ ... BLB _m ).

Figure 1b is a schematic diagram of a 6T單埠 SRAM cell, in which PMOS transistors (P11) and (P12) are called load transistors, NMOS transistors. (N11) and (N12) are called driving transistors, NMOS transistors (N13) and (N14) are called access transistors, WL is word line, and BL And BLB are a bit line and a complementary bit line, respectively, since the 單埠SRAM cell requires 6 transistors, and when reading logic 0, in order to avoid the initial moment of the read operation (initial instant) Another driving transistor is turned on, and the initial instantaneous voltage (V _AR ) of the node A must satisfy the equation (1): V _AR = V _DD × (R _N11 ) / (R _N11 + R _N13 ) < V _TN12 (1) to prevent half-selected cell disturbance when reading, wherein V _AR represents the initial instantaneous voltage of the reading of node A, and R _N11 and R _N13 respectively represent the NMOS transistor (N11) ) oN resistance of the NMOS transistor (N13), and V _DD and V _TN12 respectively represent the power supply voltage and the threshold voltage of the NMOS transistor (N12) of this The current drive capability ratio (ie, cell ratio) between the drive transistor and the access transistor is typically set between 2.2 and 3.5 (refer to US Pat. No. 2,760,060, filed on October 20, 1998. Lines 8-10).

The HSPICE transient analysis results of the 6T單埠 SRAM cell shown in Figure 1b during the write operation, as shown in Figure 2, are simulated using the TSMC 90 nm CMOS process parameters.

One way to reduce the number of transistors in a 6T static random access memory (SRAM) cell is disclosed in FIG. Figure 3 shows a circuit diagram of a 5T 單埠 SRAM cell with only a single bit line, compared to the 6T 單埠 SRAM cell of Figure 1b. The random access memory cell has one transistor and one less bit line than the 6T static random access memory cell, but the 5T單埠 SRAM cell does not change the PMOS transistor (P11). Write logic 1 with (P12) and channel width-to-length ratio of NMOS transistors (N11), (N12), and (N13) (that is, maintaining the same transistor channel width-to-length ratio as the 6T SRAM cell) Quite difficult problem. Considering that the node A on the left side of the memory cell originally stores a logic 0, since the charge of the node A is transmitted only from the bit line (BL) alone, the logic 0 previously written in the node A is overwritten with a logic 1 write. The initial instantaneous voltage (V _AW ) is equal to equation (2): V _AW = V _DD × (R _N11 ) / (R _N11 + R _N13 ) (2) where V _AW represents the initial instantaneous voltage of the write of node A, R _N11 And R _N13 respectively indicate the on-resistances of the NMOS transistor (N11) and the NMOS transistor (N13). Comparing equations (1) and (2), the initial transient voltage (V _AW ) is smaller than the NMOS transistor (N12). The threshold voltage (V _TN12 ) makes it impossible to complete the operation of writing logic 1. Figure 5 shows the results of the HSPICE transient analysis simulation of the 5T SRAM cell during the write operation. As shown in Figure 4, it is simulated using the TSMC 90 nm CMOS process parameters. The simulation results confirm that it is quite difficult to write logic 1 in a 5T SRAM cell with a single bit line.

The method for solving the above-mentioned 5T static random access memory cell writing logic 1 is as follows. The first method is to pull the voltage level supplied to the memory cell lower than the power supply voltage when writing. (VDD), so that when writing logic 1 (assuming node A originally stores logic 0, and now wants to write logic 1), by increasing the on-resistance of the driving transistor NMOS transistor (N11) during the write operation The driving transistor NMOS transistor (N12) can be turned on to complete the operation of writing the logic 1, for example, Patent Document 1 (US Pat. No. 7,706,202 B2, April 27, 1999) "Memory System" proposed in the "Memory System", Patent Document 2 (TWI426515 B, February 11, 103), "SRAM with reduced power supply voltage during write operation", Patent Document 3 (February 11, 103, pp. TWI426514 B) "Standard Static Random Access Memory with Reduced Power Supply Voltage During Write Operation", Patent Document 4 (TWI419162 B, December 11, 102) "Five Transistor SRAM Cell", etc., as disclosed in Patent Document 5 (US2014/0029333 A1, January 30, 103), which can effectively solve the writing. Logic 1 is difficult, but because these patents require dual power and/or discharge paths, the voltages supplied to the memory cell must be pulled low below the power supply voltage (VDD). And returning the voltage level supplied to the memory cell to the power supply voltage (VDD) after writing is completed, thus causing unnecessary power consumption, and none of these patents considers reducing standby power and 45 The reading speed caused by the nano operating voltage will drop to 1.1±30% Reduce the problem, so there is still room for improvement.

The second method is to redesign the channel width to length ratio of the PMOS transistors (P11) and (P12) and the NMOS transistors (N11), (N12) and (N13), for example, Non-Patent Document 6 (Satyan and Nalam et al., "5T SRAM with asymmetric sizing for improved read stability", IEEE Journal of Solid-State Circuits. , Vol . 46. No. 10, pp 2431-2442, Oct. 2011.), due to PMOS transistors (P11) and ( The channel width to length ratio of P12) is no longer the same and the channel width to length ratio of NMOS transistors (N11) and (N12) are no longer the same, thus reducing the static noise margin (SNM) and not reducing the standby power. And when the operating voltage of 45 nm is reduced to 1.1±30%, the reading speed is reduced, so there is still room for improvement.

The third method is to increase the word line (WL) voltage level of the access transistor (N13) gate supplied to the memory cell to a voltage higher than the power supply voltage (VDD) for writing. Logic 1 (assuming node A originally stores a logic 0, but now wants to write a logic 1), The operation of writing the logic 1 can be completed by lowering the on-resistance of the access transistor (N13) to enable the driving transistor NMOS transistor (N12) to be turned on at the initial write instant, for example, Patent Document 7 (No. TWI404065, August 1, 102) "Serial random access memory that raises the word line voltage level during write operation", but is supplied to the memory cell due to writing. Accessing the transistor (N13) gate word line (WL) voltage level higher than the power supply voltage (VDD) increases the half-selected cell disturbance during writing, and also The problem of reduced read speed caused by a 45 nm operating voltage drop of 1.1 ± 30% is not taken into account, so there is still room for improvement.

The fourth method is to raise the source voltage level of the driving transistor NMOS transistor (N11) above the ground voltage during writing so as to write logic 1 (assuming that node A originally stores logic 0, and now wants Write logic 1), by increasing the gate voltage level of the driving transistor NMOS transistor (N11), so that the driving transistor NMOS transistor (N12) can be turned on at the initial writing speed, and the writing logic 1 is completed. The operation is as follows, for example, "High-performance static random access memory" proposed in Patent Document 8 (TWI451414, September 1, 103), and Patent Document 9 (TWI 436359, May 1, 103) "5T 單埠SRAM", "5T static random access memory" proposed in Patent Document 10 (TWI433151, April 1, 103), and Patent Document 11 (TWI425510, February 1, 103) Proposed "Static Static Random Access Memory with Low Standby Current", but these patents do not take into account the problem of reduced read speed caused by a 45 nm operating voltage drop of 1.1 ± 30%. 12 (TWI478165, March 21, 104) "High-performance static random access memory Although the read speed is reduced due to the SRAM operating voltage drop of 1.1±30% below 45 nm, the source of the transistor NMOS transistor (N11) will be driven by the read operation. The voltage is pulled down from the original ground voltage to below the ground voltage to increase the reading speed, but the source voltage of the driving transistor NMOS transistor (N11) is reduced from the ground voltage to the ground voltage during the read operation. Mechanism There is a lack of unnecessary power consumption, so there is still room for improvement.

The fifth method is to increase the threshold voltage of the driving transistor NMOS transistor (N11) while reducing the threshold voltage of the access transistor (N13) by writing back gate bias technology. When writing logic 1 (assuming node A originally stores logic 0, but now wants to write logic 1), by increasing the gate voltage level of the driving transistor NMOS transistor (N11), the initial instant energy can be written. The drive transistor NMOS transistor (N12) is turned on to complete the operation of writing logic 1, but the method requires the use of a split well to increase process complexity and is therefore less used.

The sixth method is to redesign the connection relationship between the PMOS transistors (P11) and (P12) and the NMOS transistors (N11), (N12) and (N13), for example, Non-Patent Document 13 (Chua-Chin Wang et al) "A single-ended disturb-free 5T loadless SRAM with leakage sensor and read delay compensation using 40 nm process", 2014 International Symposium on Circuits and Systems, pp 1126-1129, June 2014.) and non-patent document 14 (Shyam Akashe et al., "High density and low leakage current based 5T SRAM cell using 45 nm technology", 2011 International Conference on Nanoscience, Engineering and Technology (ICONSET), pp 346-350, Nov. 2011.), but due to these The non-patent literature does not consider the problem of a reduction in reading speed caused by a 45 nm operating voltage drop of 1.1 ± 30%, so there is still room for improvement.

Next, it is proposed to reduce the standby voltage by increasing the source voltage of the NMOS transistors (N11) and (N12) in all the memory cells from the original ground voltage to a predetermined voltage higher than the ground voltage. A technique of power consumption, for example, "Static random access memory (SRAM) with clamped source potential in standby mode" proposed in Patent Document 15 (No. US Pat. No. 7,382,674 B2, June 3, 1997), Patent Document 16 (August 96) "Static random access memory device and method of reducing standby current", No. 77254085 B2, No. 7 (Tae-Hyoung Kim et al., "A Voltage Scalable 0.26 V, 64 kb 8T SRAM With Vmin Lowering Techniques and Deep Sleep Mode", IEEE Journal of Solid-State Circuits. , Vol . 64, pp 1785-1795, 2009.) 8T SRAM and Non-Patent Document 18 (Ding-Ming Kwai, "Modeling of SRAM Standby Current by Three-Parameter Lognormal Distribution " , Design, and Testing, 2009.MTDT '09 .IEEE International Workshop on Memory Technology, pp 77-82, Aug.31 2009-Sept.2009.) , etc. are the property of, such In the standby operation, the source voltage of the driving transistor (ie, the NMOS transistors N11 and N12 of FIG. 1b) in all the memory cells is increased from the original ground voltage. Up to a predetermined voltage higher than the ground voltage, in order to reduce the power consumption of the standby operation, but the predetermined voltage higher than the ground voltage of the patent documents or the non-patent literature is only caused by the leakage current of the transistor. The charging of parasitic capacitance occurs, and the rate at which the SRAM enters the standby mode is extremely slow, and thus the lack of standby performance is reduced: that is, the patent documents or the non-patent literature lack a standby start circuit to promote Static random access memory quickly enters standby mode, so there is still room for improvement.

In view of the above, the main object of the present invention is to provide a static random access memory capable of changing the source voltage of a driving transistor close to a bit line from an original ground voltage by a control circuit for reading an initial moment. In order to be lower than the grounding voltage, the driving transistor with a smaller channel width to length ratio can be configured to complete the reading operation, and the logic transistor 0 is not caused to instantaneously turn on the driving transistor away from the bit line. However, the reading operation is hindered, and the writing can also effectively avoid the problem that it is quite difficult to write the logic 1 in the SRAM with a single bit line.

A secondary object of the present invention is to provide a static random access memory that can be applied to a selected cell by a word line voltage level conversion circuit during a read operation. The transistor's word line voltage is pulled down below the power supply voltage to effectively reduce half-selected cell interference during reading.

A further object of the present invention is to provide a static random access memory capable of effectively improving the reading speed by the control circuit, and capable of improving the reading speed while avoiding the read speed by the two-stage read control. Unnecessary power consumption.

Still another object of the present invention is to provide a static random access memory capable of effectively reducing leakage current in a standby mode by a control circuit.

The invention provides a static random access memory, which mainly comprises a memory array, a plurality of control circuits (2), a plurality of precharge circuits (3), a standby start circuit (4), and a plurality of word line voltages. a level conversion circuit (5) and a plurality of high voltage level control circuits (6), the memory array is composed of a plurality of columns of memory cells and a plurality of rows of memory cells, each column of memory cells is provided with a cell a control circuit and a word line voltage level conversion circuit (5), and each memory cell (1) includes a first inverter (from a first PMOS transistor P11 and a first NMOS transistor) The N11 is composed of a second inverter (composed of a second PMOS transistor P12 and a second NMOS transistor N12) and an access transistor (composed of a third NMOS transistor N13). Each control unit (2) is connected to a source of the first NMOS transistor (N11) of each memory cell of the corresponding column memory cell and a source of the second NMOS transistor (N12) In order to control the source voltage of the first NMOS transistor (N11) and the source voltage of the second NMOS transistor (N12) in response to different operation modes. In the first stage of the read mode, the source of the first NMOS transistor (N11) close to the bit line (BL) is changed from the original ground voltage to be lower than the ground voltage, and the configuration is smaller. Channel width The read operation can be completed compared to the first NMOS transistor (N11) and the second NMOS transistor (N12), and the second bit away from the bit line (BL) is not caused when the logic 0 is read. The NMOS transistor (N12) blocks the read operation due to the transient conduction, and in the second stage of the read mode, the source of the first NMOS transistor (N11) is set back to ground from the ground voltage. Voltage to reduce unnecessary power consumption; in the write mode, the source of the first NMOS transistor (N11) near the bit line (BL) maintains the original ground voltage due to the configuration of a smaller channel width Compared with the first NMOS transistor (N11) and the second NMOS transistor (N12), it can effectively avoid the problem that it is quite difficult to write the logic 1 in the SRAM with a single bit line; in the standby mode The leakage current can be effectively reduced, while the original electrical characteristics can be maintained in the hold mode. Moreover, the design of the standby start circuit (4) is effective to prompt the 單埠SRAM to quickly enter the standby mode, and thus effectively improve the standby performance of the 單埠SRAM. In addition, the plurality of word line voltage level conversion circuits (5) and the plurality of high voltage level control circuits (6) are designed to increase the third NMOS transistor (N13) in the read mode. The on-resistance of the first NMOS transistor (N11) reduces the on-resistance of the first NMOS transistor (N11) to effectively reduce the half-selected cell interference during reading.

BLB ₁ ^... BLB _m ‧‧‧complementary bit line

BLB‧‧‧complementary bit line

MB ₁ ^... MB _k ‧‧‧ memory block

WL ₁ ^... WL _n ‧‧‧ character line

BL ₁ ^... BL _m ‧‧‧ bit line

I ₁ , I ₂ , I ₃ ‧‧‧ leakage current

1‧‧‧SRAM cell

2‧‧‧Control circuit

3‧‧‧Precharge circuit

4‧‧‧Standby start circuit

5‧‧‧Word line voltage level conversion Circuit

P11‧‧‧First PMOS transistor

P12‧‧‧Second PMOS transistor

N11‧‧‧First NMOS transistor

N12‧‧‧Second NMOS transistor

N13‧‧‧ Third NMOS transistor

A‧‧‧ storage node

B‧‧‧ Inverting storage node

BL‧‧‧ bit line

WLC‧‧‧ word line control signal

S‧‧‧Standby mode control signal

/S‧‧‧Inverted standby mode control signal

VL1‧‧‧ first low voltage node

VL2‧‧‧ second low voltage node

N21‧‧‧4th NMOS transistor

N22‧‧‧ fifth NMOS transistor

N23‧‧‧ sixth NMOS transistor

N24‧‧‧ seventh NMOS transistor

N25‧‧‧ eighth NMOS transistor

N26‧‧‧Ninth NMOS transistor

RC‧‧‧ read control signal

RGND‧‧‧Accelerated reading voltage

INV‧‧‧ third inverter

D1‧‧‧First delay circuit

P31‧‧‧ Third PMOS transistor

P‧‧‧Precharge signal

N41‧‧‧ tenth NMOS transistor

P41‧‧‧4th PMOS transistor

D2‧‧‧second delay circuit

V _DD ‧‧‧Power supply voltage

WL‧‧‧ character line

R‧‧‧Read signal

/W‧‧‧Inverted write signal

/RW‧‧‧Inverted read/write control signal

P51‧‧‧ Fifth PMOS transistor

N51‧‧11 eleventh NMOS transistor

N52‧‧‧12th NMOS transistor

6‧‧‧High voltage level control circuit

V _DD ‧‧‧Power supply voltage

HV _DD ‧‧‧High power supply voltage

P61‧‧‧6th PMOS transistor

P62‧‧‧ seventh PMOS transistor

I63‧‧‧fourth inverter

VH‧‧‧ high voltage node

Figure 1a shows a conventional static random access memory; Figure 1b shows a schematic circuit diagram of a conventional 6T static random access memory cell; and Fig. 2 shows a conventional 6T static random access memory cell. The write operation timing chart; the third figure shows the circuit diagram of the conventional 5T static random access memory unit cell; the fourth figure shows the write operation timing chart of the conventional 5T static random access memory unit cell; Figure 5 is a circuit diagram showing the preferred embodiment of the present invention; 6 is a simplified circuit diagram showing a preferred embodiment of the present invention in FIG. 5 during writing; FIG. 7 is a timing chart showing the writing operation of the preferred embodiment of the present invention in FIG. 5; FIG. 5 is a simplified circuit diagram of a preferred embodiment of the present invention during reading; and FIG. 9 is a simplified circuit diagram showing a preferred embodiment of the present invention in FIG. 5 during standby.

According to the above main object, the present invention provides a static random access memory, which mainly includes a memory array composed of a plurality of columns of memory cells and a plurality of rows of memory cells, each column of memory. The body cell and each row of memory cells include a plurality of memory cells (1); a plurality of control circuits (2), each column of memory cells is provided with a control circuit (2); and a plurality of precharge circuits ( 3), each row of memory cells is provided with a pre-charging circuit (3); a standby starting circuit (4); a plurality of word line voltage level conversion circuits (5) each column of memory cells is set to a word line voltage bit A quasi-conversion circuit (5); and a plurality of high-voltage level control circuits (6), each column of memory cells is provided with a high-voltage level control circuit (6).

For convenience of explanation, the static random access memory shown in FIG. 5 has only one memory cell (1), one word line (WL), one bit line (BL), and one control circuit (2). A precharge circuit (3), a standby start circuit (4), a word line voltage level conversion circuit (5), and a high voltage level control circuit (6) are described as an embodiment. The memory cell (1) includes a first inverter (composed of a first PMOS transistor P11 and a first NMOS transistor N11) and a second inverter (by a second PMOS) a first NMOS transistor (N13), wherein the first NMOS transistor and the second NMOS transistor are in an inter-coupled connection, that is, the first The output of the inverter (ie, node A) is connected to the input of the second inverter, and the output of the second inverter (ie, node B) is An input of the first inverter is connected, and an output of the first inverter (node A) is used to store data of the SRAM cell, and an output of the second inverter (node B) is used for storing Inversion data of SRAM cell. It should be noted here that the first NMOS transistor (N11) and the second NMOS transistor (N12) have the same channel width to length ratio, the first PMOS transistor (P11) and the second PMOS transistor. (P12) also has the same channel aspect ratio, and the ratio of the channel width to length ratio of the first NMOS transistor (N11) to the third NMOS transistor (N13) is designed to be smaller than the conventional 6T SRAM of FIG. 2.2 of the unit cell, for example, the ratio of the channel width to length ratio of the first NMOS transistor (N11) to the third NMOS transistor (N13) is designed to be between 1.2 and 1.8, preferably between 1.2 and 1.5.

Referring to FIG. 5 again, the control circuit (2) is composed of a fourth NMOS transistor (N21), a fifth NMOS transistor (N22), a sixth NMOS transistor (N23), and a seventh NMOS device. a crystal (N24), an eighth NMOS transistor (N25), a ninth NMOS transistor (N26), a read control signal (RC), a third inverter (INV), and a first delay circuit ( D1), an accelerated read voltage (RGND), a standby mode control signal (S), and an inverted standby mode control signal (/S). a source, a gate and a drain of the fourth NMOS transistor (N21) are respectively connected to a ground voltage, the inverted standby mode control signal (/S) and a second low voltage node (VL2); a source, a gate and a drain of the NMOS transistor (N22) are respectively connected to the second low voltage node (VL2), the standby mode control signal (S) and a first low voltage node (VL1); The source of the six NMOS transistor (N23) is connected to the ground voltage, and the gate is connected to the drain and connected to the first low voltage node (VL1); the source of the seventh NMOS transistor (N24) The gate and the drain are respectively connected to the drain of the eighth NMOS transistor (N25), the read control signal (RC) and the first low voltage node (VL1); The source, the gate and the drain of the eighth NMOS transistor (N25) are respectively connected to the accelerated read voltage (RGND), the output of the first delay circuit (D1), and the seventh NMOS transistor (N24) a source of the first delay circuit (D1) connected between the output of the third inverter (INV) and the gate of the eighth NMOS transistor (N25); the third inverter ( The input of INV) is for receiving the read control signal (RC), and the output is connected to the input of the first delay circuit (D1); the source, the gate and the drain of the ninth NMOS transistor (N26) The system is respectively connected to a ground voltage, the reverse standby mode control signal (/S) and the first low voltage node (VL1). It is worth noting here that the inverted standby mode control signal (/S) is obtained by the standby mode control signal (S) via an inverter.

The control circuit (2) is designed to control the voltage level of the first low voltage node (VL1) and the second low voltage node (VL2) according to different operation modes, and select the unit cell in the write mode. The source voltage of the driving transistor (ie, the first NMOS transistor N11) closer to the bit line (BL) (ie, the first low voltage node VL1) is set to a ground voltage, and another cell in the selected cell will be selected The source voltage of the driving transistor (ie, the second NMOS transistor N12) (ie, the second low voltage node VL2) is set to a ground voltage.

In the first phase of one of the read modes, the source voltage of the driving transistor (ie, the first NMOS transistor N11) closer to the bit line (BL) in the cell is selected (ie, the first low voltage node) VL1) is set to the accelerated read voltage (RGND) which is lower than the ground voltage, and the accelerated read voltage (RGND) which is lower than the ground voltage can effectively improve the read speed, and is one of the read modes. In the phase, the source voltage of the driving transistor (ie, the first NMOS transistor N11) of the selected cell closer to the bit line (BL) is set back to the ground voltage to reduce unnecessary power consumption, wherein the reading The time between the second phase of the pattern and the first phase is equal to The read control signal (RC) is converted from a logic low level to a logic high level, and until the gate voltage of the eighth NMOS transistor (N25) is sufficient to turn off the eighth NMOS transistor (N25), The value can be adjusted by the falling delay time of the third inverter (INV) and the delay time provided by the first delay circuit (D1).

In the standby mode, the source voltage of the driving transistor in all the memory cells is set to the predetermined voltage higher than the ground voltage to reduce the leakage current; and in the hold mode, the driving power in the memory cell is The source voltage of the crystal is set to the ground voltage to maintain the original retention characteristics. The detailed operating voltage levels are shown in Table 1.

The read control signal (RC) in Table 1 is the result of the AND operation of a read signal (R) and the word line (WL) signal. It is worth noting here that the read control signal (RC) during the non-read mode is set to the level of the accelerated read voltage (RGND) to prevent leakage of the seventh NMOS transistor (N24). Current.

Referring to FIG. 5, the precharge circuit (3) is composed of a third PMOS transistor (P31) and a precharge signal (P), and the source and gate of the third PMOS transistor (P31). And the drain system are respectively connected to a power supply voltage (V _DD ), the precharge signal (P) and the bit line (BL), so as to be pre-charged by a logic low level during pre-charging (P) ) to precharge the bit line (BL) to the level of the power supply voltage (V _DD ).

Referring to FIG. 5 again, the standby starting circuit (4) is a fourth PMOS transistor (P41), a tenth NMOS transistor (N41), a second delay circuit (D2), and the reverse standby mode. The control signal (/S) is composed of. a source, a gate and a drain of the fourth PMOS transistor (P41) are respectively connected to the power supply voltage (V _DD ), the reverse standby mode control signal (/S), and the tenth NMOS transistor ( a drain of N41); a source, a gate and a drain of the tenth NMOS transistor (N41) are respectively connected to the output of the first low voltage node (VL1), the second delay circuit (D2), and a drain of the fourth PMOS transistor (P41); an input of the second delay circuit (D2) is coupled to the inverted standby mode control signal (/S), and an output of the delay circuit (D2) is coupled to the The gate of a ten NMOS transistor (N41).

Referring to FIG. 5 again, the word line voltage level conversion circuit (5) is composed of a fifth PMOS transistor (P51), an eleventh NMOS transistor (N51), and a twelfth NMOS transistor ( N52), the read signal (R), an inverting write signal (/W), an inverting read/write control signal (/RW), and a word line control signal (WLC), wherein the reading The signal (R) and the inverted write signal (/W) may be from a read/write control pin of the SRAM, and the read operation is indicated when the read/write control pin is at a logic high level (ie, the read signal R is a logic high bit) The read/write control pin is a logic low-level on-time indicating write operation (ie, the inverted write signal /W is a logic low level), and the inverted signal of the read/write control pin is equivalent to the reverse phase Read and write control signals (/RW). a source, a gate and a drain of the fifth PMOS transistor (P51) are respectively connected to the word line (WL), the inverted write signal (/W) and the word line control signal (WLC) ; a source, a gate and a drain of the eleventh NMOS transistor (N51) are respectively connected to the word line control signal (WLC), the read signal (R) and the word line (WL); a source, a gate and a drain of the twelfth NMOS transistor (N52) are respectively connected to the word line control signal (WLC), the inverted read/write control signal (/RW), and the word line ( WL).

The detailed operating voltage level of the word line voltage level conversion circuit (5) is shown in Table 2.

Where V _TN51 represents the threshold voltage of the eleventh NMOS transistor (N51). It should be noted here that the present invention uses two-stage read control to improve the reading speed while avoiding unnecessary power consumption, and on the other hand, the word line voltage level conversion circuit ( 5), in order to effectively lower the word line voltage applied to the access transistor of the selected cell during the read operation to be lower than the power supply voltage (ie, V _DD -V _TN51 ) Selected cell interference.

Referring to FIG. 5 again, the high voltage level control circuit (6) is composed of a sixth PMOS transistor (P61), a seventh PMOS transistor (P62), and a fourth inverter (I63). The source, the gate and the drain of the sixth PMOS transistor (P61) are respectively connected to the power supply voltage (V _DD ), the read control signal (RC) and a high voltage node (VH), The source, the gate and the drain of the seventh PMOS transistor (P62) are respectively connected to a high power supply voltage (HV _DD ), the output of the fourth inverter (I63) and the high voltage node (VH) And the input of the fourth inverter (I63) is for receiving the read control signal (RC), and the output is connected to the drain of the seventh PMOS transistor (P62). It is worth noting here that the first inverter is connected between the power supply voltage (V _DD ) and the first low voltage node (VL1), and the second inverter is connected to the high voltage. Between the node (VH) and the second low voltage node (VL2).

The working principle of the preferred embodiment of the present invention in FIG. 5 is as follows:

(I) write mode

Before the start of the write operation, the standby control signal (S) is at a logic low level, and the inverted standby control signal (/S) is at a logic high level, such that the ninth NMOS transistor (N26) is turned "ON", and The first low voltage node (VL1) is brought to a ground voltage.

During the write operation period, the standby control signal (S) is at a logic low level, and the inverted standby control signal (/S) is at a logic high level, so that the ninth NMOS transistor (N26) is turned on (ON). And the first low voltage node (VL1) is still grounded, because the channel width to length ratio of the first NMOS transistor (N11) is designed to be larger than the driving transistor (N11) of the conventional 6T SRAM of FIG. The channel width-to-length ratio is also small, that is, node A originally stores logic 0 and now writes logic 1 to write the initial instantaneous voltage (V _AW ) to satisfy equation (3): V _AW = V _DD × (R _N11 ) /(R _N11 +R _N13 )>V _TN12 (3) wherein V _AW represents the initial transient voltage of the node A, and R _N11 and R _N13 represent the first NMOS transistor (N11) and the third NMOS, respectively. The on-resistance of the crystal (N13), and V _DD and V _TN12 respectively represent the threshold voltage of the power supply voltage and the second NMOS transistor (N12), so that the problem of difficulty in writing the logic 1 can be effectively avoided. Figure 6 is a simplified circuit diagram of the preferred embodiment of the invention of Figure 5 during writing.

Next, how the write operation of the preferred embodiment of the present invention in FIG. 6 is completed depends on the four write states of the SRAM.

(1) Node A originally stores a logic 0, but now wants to write a logic 0: before the write operation occurs (the word line control signal WLC is a ground voltage), the first NMOS transistor (N11) is turned on (ON) ). Since the first NMOS transistor (N11) is ON, the word line control signal (WLC) is turned from Low (ground voltage) to High (the power supply voltage V _DD ) when the write operation starts. When the voltage of the word line control signal (WLC) is greater than the threshold voltage of the third NMOS transistor (N13) (ie, the access transistor), the third NMOS transistor (N13) is turned from OFF (OFF) to Turn on (ON). At this time, because the bit line (BL) is the ground voltage, the node A will maintain the original ground voltage until the end of the write cycle.

(2) Node A originally stores a logic 0, and now wants to write a logic 1: before the write operation occurs (the word line control signal WLC is a ground voltage), the first NMOS transistor (N11) is turned on (ON) ). Since the first NMOS transistor (N11) is ON, when the write operation starts, the word line control signal (WLC) is turned from Low (ground voltage) to High (the power supply voltage V _DD ), the node A The voltage will rise following the voltage of the word line control signal (WLC).

When the voltage of the word line control signal (WLC) is greater than the threshold voltage of the third NMOS transistor (N13), the third NMOS transistor (N13) is turned from OFF to ON. Because the bit line (BL) is High (the power supply voltage V _DD ), and because the first NMOS transistor (N11) is still ON and the node B is still at a voltage level close to the power supply voltage ( The initial state of the voltage level of V _DD ), so the first PMOS transistor (P11) is still turned off (OFF), and the node A satisfies the equation (3), thereby enabling the second NMOS transistor ( N12) is turned on, so that the node B is discharged to a lower voltage level, and the lower voltage level of the node B causes the conduction equivalent resistance (R _N11 ) of the first NMOS transistor (N11) to be higher. The resistance value, the higher resistance value of the first NMOS transistor (N11) will obtain a higher voltage level at the node A, and the higher voltage level of the node A will pass through the second inverter ( The second PMOS transistor P12 and the second NMOS transistor N12 are formed, so that the node B exhibits a lower voltage level, and the lower voltage level of the node B passes through The first inverter (composed of the first PMOS transistor P11 and the first NMOS transistor N11) causes the node A to obtain a higher voltage level, and according to the cycle, the node A can be charged to the node The power supply voltage (V _DD ) completes the write operation of logic 1.

(3) Node A originally stores logic 1, and now wants to write logic 1: Before the write operation occurs (the word line control signal WLC is the ground voltage), the first PMOS transistor (P11) is turned on (ON) ). When the word line control signal (WLC) is turned from Low (ground voltage) to High (the power supply voltage V _DD ), and the voltage of the word line control signal (WLC) is greater than that of the third NMOS transistor (N13) At the threshold voltage, the third NMOS transistor (N13) is turned from OFF to ON; at this time, since the bit line (BL) is High (the power supply voltage V _DD ), and because of the A PMOS transistor (P11) is still ON, so the voltage at node A is maintained at the voltage level of the power supply voltage (V _DD ) until the end of the write cycle.

(4) Node A originally stores logic 1, and now wants to write logic 0: before the write operation occurs (the word line control signal WLC is the ground voltage), the first PMOS transistor (P11) is turned on (ON) ). When the word line control signal (WLC) is turned from Low (ground voltage) to High (the power supply voltage V _DD ), and the voltage of the word line control signal (WLC) is greater than that of the third NMOS transistor (N13) At the threshold voltage, the third NMOS transistor (N13) is turned from off (OFF) to on (ON). At this time, since the bit line (BL) is Low (ground voltage), the node A and the node are The first low voltage node (VL1) is discharged to complete the logic 0 write operation until the end of the write cycle.

The simplified circuit diagram of the preferred embodiment of the present invention shown in FIG. 6 shows the HSPICE transient analysis simulation result during the write operation, as shown in FIG. 7, which is simulated using the TSMC 90 nm CMOS process parameters. The simulation results prove that the static random access memory of the present invention can improve the voltage level of the node A during the writing by configuring the first NMOS transistor (N11) with a small channel aspect ratio to be effective. It is quite difficult to avoid the existence of a single bit line and the existence of a write logic 1 in a static random access memory cell.

(II) Read mode (read mode)

Before the reading operation starts, the read control signal (RC) and the standby mode control signal (S) are both logic low levels, so that the ninth NMOS transistor (N26) is turned on (ON), and The first low voltage node (VL1) is at a ground voltage. On the other hand, since the read control signal (RC) is at a logic low level, the seventh NMOS transistor (N24) is turned off (OFF), and the eighth NMOS transistor (N25) is turned "ON".

Figure 8 is a simplified circuit diagram of the preferred embodiment of the present invention during the reading period of Figure 5, which is controlled by two stages to improve the reading speed while avoiding unnecessary power consumption. In a first stage of the read operation, the read control signal (RC) is at a logic high level, such that the seventh NMOS transistor (N24) is turned on, since the eighth NMOS transistor (N25) is still turned on at this time, Then, the first low voltage node (VL1) is at the accelerated read voltage (RGND) which is lower than the ground voltage, and the accelerated read voltage (RGND) which is lower than the ground voltage can effectively improve the read speed.

In the second phase of the read operation, although the read control signal (RC) is still at a logic high level, the seventh NMOS transistor (N24) is still turned on, but since the eighth NMOS transistor is at this time (N25) is turned off, so that the first low voltage node (VL1) is grounded via the turned-on ninth NMOS transistor (N26), thereby effectively reducing unnecessary power consumption. It is worth noting here that the second phase of the read operation is separated from the first phase by a time equal to the read control signal (RC) transitioning from a logic low level to a logic high level, and to the The gate voltage of the eight NMOS transistor (N25) is sufficient to turn off the eighth NMOS transistor (N25), and the value thereof can be decreased by the delay time of the third inverter (INV) and the first delay circuit. (D1) The delay time provided is adjusted. Furthermore, regardless of the first phase of the read operation or the second phase, the ninth NMOS transistor (N26) is in an on state (since the gate of the ninth NMOS transistor (N26) is at a power supply voltage The level of V _DD ).

Next, the 8th figure of the static random access memory is explained. The preferred embodiment of the present invention sets the accelerated read voltage (RGND) and how to reduce the half-selected cell interference during reading.

(1) Read logic 1 (node A storage logic 1): before the read operation occurs, the first NMOS transistor (N11) is off (OFF) and the second NMOS transistor (N12) is on (ON) The node A and the node B are respectively the power supply voltage (V _DD ) and the ground voltage, and the bit line (BL) is equal to the power supply voltage (V _DD ) due to the precharge circuit (3) . During the reading, since the word line control signal (WLC) is that the power supply voltage is _{biased against} the threshold voltage of the eleventh NMOS transistor (N51) (ie, V _DD -V _TN51 ), the third NMOS is The crystal (N13) is turned off (OFF), whereby the bit line (BL) can be effectively maintained for the power supply voltage until the read cycle ends and the operation of reading the logic 1 is successfully completed. It is worth noting here that since the first low voltage node (VL1) is the accelerated read voltage (RGND) at this time, in order to effectively reduce the half-selected cell interference during reading and effectively reduce the leakage current, it is necessary to The accelerated read voltage (RGND) is set lower than the threshold voltage (V _TN11 ) of the first NMOS transistor (N11), that is, |RGND|<V _TN11 (4), where |RGND| and V _TN11 respectively indicate Accelerating the absolute value of the read voltage and the threshold voltage of the first NMOS transistor (N11).

(2) Reading logic 0 (node A stores logic 0): before the read operation occurs, the first NMOS transistor (N11) is turned on (ON) and the second NMOS transistor (N12) is turned off (OFF) The node A and the node B are respectively a ground voltage and the power supply voltage (V _DD ), and the bit line (BL) is equal to the power supply voltage (V _DD ) due to the precharge circuit (3) . Because the first NMOS transistor (N11) is ON, when the reading operation starts, the word line control signal (WLC) is turned from Low (ground voltage) to High (the power supply voltage is applied to the eleventh NMOS). The threshold voltage of the transistor (N51) is V _DD -V _TN51 ). When the voltage of the word line control signal (WLC) is greater than the threshold voltage of the third NMOS transistor (N13), the third NMOS transistor (N13) is turned from OFF to ON. The initial instantaneous voltage (V _AR ) of the reading of node A must satisfy equation (5): V _AR = V _DD × (R _N11 + (R _N24 + R _N25 ) ∥ R _N26 ) / (R _N13 + R _N11 + ( R _N24 +R _N25 )∥R _M26 )+RGND×(R _N11 +R _N13 )∥R _N26 /(R _N24 +R _N25 +(R _N11 +R _N13 )∥R _N26 )×R _N13 /(R _N11 + R _N13 )<V _TN12 (5)

Wherein, V _AR represents the initial instantaneous voltage when node A reads logic 0, and R _M11 , R _{M13 ,} R _{M24 ,} R _M25 and R _M26 respectively represent the first NMOS transistor (M11) and the third NMOS transistor ( M13), an on-resistance of the seventh NMOS transistor (M24), the eighth NMOS transistor (M25) and the ninth NMOS transistor (M26), and V _DD , RGND and V _TM12 respectively represent the power supply voltage (V _DD ), the accelerated read voltage (RGND) and the threshold voltage of the second NMOS transistor (M12). It is worth noting here that the accelerated read voltage (RGND) is designed to be lower than the ground voltage and the absolute value of the accelerated read voltage is designed to be smaller than the threshold voltage of the first NMOS transistor (N11). Furthermore, in order to effectively reduce the half-selected cell interference during reading and to easily satisfy equation (5), the present invention sets the word line control signal (WLC) during reading to the power supply voltage to the tenth a threshold voltage (V _DD -V _TN51 ) of an NMOS transistor (N51) to increase the on-resistance (R _N13 ) of the third NMOS transistor ( _N13 ), and above the power source when logic 0 is read the high voltage power supply (HV _DD) supply voltage (V _DD) applied to the first of the NMOS transistor (N11) of the gate, in order to reduce the first NMOS transistor (N11) of the on-resistance (R _N11). It is worth noting here that the high power supply voltage (HV _DD ) is set higher than the power supply voltage (V _DD ) but lower than the power supply voltage (V _DD ) and the second PMOS transistor (P12) The sum of the absolute value of the threshold voltage |V _TP12 |, that is, V _DD <HV _DD <V _DD +|V _TP12 | (6) where |V _TP12 | represents the absolute voltage of the second PMOS transistor (P12) value.

(III) Standby mode

First, how the standby start circuit (4) of FIG. 5 causes the static random access memory to quickly enter the standby mode to effectively improve the standby performance of the static random access memory: first, before entering the standby mode, the reverse phase The standby mode control signal (/S) is logic High, and the inverted high standby mode control signal (/S) of the logic High causes the fourth PMOS transistor (P41) to be turned off (OFF), and causes the tenth NMOS transistor ( N41) is turned on (ON); then, after entering the standby mode, the inverted standby mode control signal (/S) is logic Low, and the inverted standby mode control signal (/S) of the logic Low causes the fourth PMOS The crystal (P41) is turned ON (ON), but during the initial period of the standby mode (the initial period is equal to the inverted standby mode control signal (/S) from the logic High to the logic Low, to the tenth NMOS transistor The gate voltage of (N41) is sufficient to turn off the tenth NMOS transistor (N41), which can be adjusted by a delay time provided by the second delay circuit (D2), the tenth NMOS transistor (N41) is still ON (ON), so the first low voltage node (VL1) can be quickly The voltage level at which the threshold voltage (V _TN23 ) of the sixth NMOS transistor (N23) is _charged , that is, the 單_埠 SRAM can quickly enter the standby mode. It is worth noting here that after the initial period of the standby mode, the tenth NMOS transistor (N41) is turned off and the supply current is stopped.

Referring to FIG. 5, in the standby mode, the standby mode control signal (S) is a logic high level, and the inverted standby mode control signal (/S) is a logic low level, and the logic low level is the reverse standby. The mode control signal (/S) may cause the fourth NMOS transistor (N21) in the control circuit (2) to be turned off (OFF), and the logic high level of the standby mode control signal (S) causes the fifth The NMOS transistor (N22) is turned on (ON), and the fifth NMOS transistor (N22) is used as an equalizer, so that the fifth NMOS transistor (N22) in an on state can be used. So that the voltage level of the first low voltage node (VL1) is equal to the voltage level of the second low voltage node (VL2), and the voltage levels are equal to the sixth NMOS transistor (N23) The voltage level of the threshold voltage (V _TN23 ). Figure 9 is a simplified circuit diagram of the preferred embodiment of the invention of Figure 5 during standby.

Next, how to reduce leakage current in the standby mode of the present invention will be described. Referring to FIG. 9, FIG. 9 depicts a leakage current I ₁ generated when the embodiment of the present invention is in the standby mode. I ₂ , I ₃ , wherein it is assumed that the output of the first inverter (ie, node A) in the SRAM cell is a logic Low (it is worth noting here that the second low voltage node (VL2) due to the standby mode The voltage level is maintained at the voltage level of the threshold voltage (V _TN23 ) of the sixth NMOS transistor (N23), so the voltage level of the node A is the logic Low and is maintained at the voltage level of the V _TN23 ) And the output of the second inverter (ie, node B) is a logic high (power supply voltage V _DD ). Referring to the prior art of FIG. 1b and the embodiment of the present invention of FIG. 9, the comparison between the static random access memory of the present invention and the 6T SRAM of FIG. 1b in terms of leakage current is first described. The leakage current I _{1 of the} third NMOS transistor (N13) is maintained at the voltage level of the V _{TN 23 due to} the voltage level of the node A in the standby mode, and the word line (WL) is assumed to be in the standby mode. The ground voltage is set, and the bit line (BL) is set to the power supply voltage (V _DD ) in the standby mode, so the gate-source voltage (V _GS ) of the third NMOS transistor (N13) of the present invention is set. Negative value, in contrast to the standby mode, the gate-source voltage (V _GS ) of the prior art NMOS transistor (N13) of Fig. 1b is equal to 0, according to the Gate Induced Drain Leakage (GIDL) effect. Or, as shown in the results of Figures 3(A) and 3(B) of the US Pat. No. 6,865,119, issued March 8, 2005, it is known that for an NMOS transistor, the sub-critical current of the gate-source voltage is -0.1 volt is approximately the gate. The source voltage is 1% of the subcritical current at 0 volts, thus resulting in the flow of the invention due to the GIDL effect The third NMOS transistor (N13) of the drain current I ₁ is much smaller than the prior art of FIG. 1b of the NMOS transistor (N13) are; Furthermore, the present invention is the third NMOS transistor (N13) of the drain-source voltage ( V _DS ) _deducts the voltage level of the V _{TN 23} for the power supply voltage (V _DD ), and the source voltage of the NMOS transistor (N13) of the conventional 1b to 6T static random access memory in the standby mode. (V _DS ) is equal to the power supply voltage (V _DD ), according to the Drain-Induced Barrier Lowering (DIBL) effect, the third NMOS transistor flowing through the present invention due to the DIBL effect (N13) of the drain current I ₁ is also smaller than the prior art of FIG. 1b NMOS transistor (N13) are; As a result, the third NMOS transistor (N13) of the present invention to flow through the drain current I ₁ is much smaller than the previous section in FIG. 1b The NMOS transistor (N13) of the art.

Next, regarding the leakage current I ₂ flowing through the first PMOS transistor (P11), the source of the first PMOS transistor (P11) is the power supply voltage (V _DD ) due to the standby mode, and the first The drain of the PMOS transistor (P11) is maintained at the voltage level of the V _TN23 , so the source drain voltage (V _SD ) of the first PMOS transistor (P11) of the present invention is the power supply voltage (V). _DD ) deducting the voltage level of the V _TN23 , and in the standby mode, the source drain voltage (V _SD ) of the prior art PMOS transistor (P11) of FIG. 1b is equal to the power supply voltage (V _DD ), according to The DIBL effect, therefore, the leakage current I ₂ flowing through the first PMOS transistor (P11) of the present invention will be smaller than that of the prior art PMOS transistor (P11) of Figure 1b.

Finally, regarding the leakage current I ₃ flowing through the second NMOS transistor (N12), since the voltage level of the second low voltage node (VL2) is maintained at the voltage level of the V _TN23 in the standby mode, the node A The voltage level is also maintained at the voltage level of the V _TN23 , and the voltage level of the node B is equal to the power supply voltage (V _DD ) and the base of the second NMOS transistor (N12) is the ground voltage, so The base-source voltage (V _BS ) of the second NMOS transistor (N12) is negative, and the 汲 source voltage (V _DS ) of the second NMOS transistor (N12) is the power supply voltage (V) _DD ) deducting the voltage level of the V _TN23 , in contrast to the standby mode, the base-source voltage (V _BS ) of the prior art NMOS transistor (N12) of FIG. 1b is equal to 0, and the NMOS transistor (N12) The source voltage (V _DS ) is equal to the power supply voltage (V _DD ). According to the body effect and the DIBL effect, the leakage current I ₃ flowing through the second NMOS transistor (N12) of the present invention is much smaller than the first 1b is a prior art NMOS transistor (N12). It can be seen from the above analysis that the 單埠 static random access memory proposed by the present invention has a lower leakage current than the prior art of Fig. 1b.

(IV) hold mode

In the hold mode, since the first low voltage node (VL1) and the second low voltage node (VL2) are both set to a ground voltage, the working principle is the same as that of the conventional 5T SRAM cell with a single bit line in FIG. This is not repeated here.

【Effects of invention】

The static random access memory proposed by the present invention has the following effects: (1) high design freedom: since the present invention reads the logic 0, the storage node (A) is pulled down to be lower than the second NMOS transistor ( The threshold voltage (V _TM12 ) of M12) has three mechanisms. The first is by the word line voltage level conversion circuit (5) to apply the access transistor to the selected unit cell (ie, the third NMOS transistor). The word line voltage of M13) is _pulled down to the power supply voltage (ie V _DD -V _TM51 ), and the second is the lowering of the storage node (A) by the accelerated read voltage (RGND) below the ground voltage, third High voltage design is achieved by applying a high power supply voltage (HV _DD ) higher than the power supply voltage (V _DD ) to the gate of the first NMOS transistor (N11) by the high voltage level control circuit (6). The effect of the degree of freedom; (2) effectively reducing the half-selected cell interference during reading: the present invention can be applied to the selected unit cell by the word line voltage level conversion circuit (5) during the read operation The word line voltage of the access transistor (ie, the third NMOS transistor N13) is _pulled down below the power supply voltage (ie, V _DD -V _TN51 ), On the one hand, the read disturb of the third NMOS transistor (N13) in the half-selected unit cell can be reduced, and on the other hand, the half-selection can be reduced by reducing the accelerated read voltage (RGND) required to satisfy equation (5). Read interference of the first NMOS transistor (N11) in the unit cell; (3) smaller cell size: since the present invention is the first NMOS transistor (N11) to the third NMOS transistor (N13) The channel width to length ratio is designed to be between 1.2 and 1.5, thus having a smaller cell size; (4) high read speed and avoiding unnecessary power consumption: the present invention employs a two-stage read operation, The first stage of the read operation effectively increases the read speed by setting the first low voltage node (VL1) to an accelerated read voltage (RGND) that is lower than the ground voltage, and in the second stage of the read operation. By setting the first low voltage node (VL1) back to the ground voltage to reduce unnecessary power consumption; (5) avoiding the difficulty of writing logic 1: the present invention can be configured by a smaller channel during a write operation The first NMOS transistor (N11) of aspect ratio is used to satisfy the equation without hindering the read operation (3) It is quite difficult to avoid the conventional SRAM with a single bit line to write logic 1; (6) Quickly enter standby mode: Since the present invention is provided with a standby start circuit (4) to prompt SRAM fast Entering the standby mode, and thereby seeking to improve the standby performance of the 單埠SRAM; (7) low standby current: since the present invention is in the standby mode, the fifth NMOS transistor (N22) in the on state can be used to make The voltage level of the first low voltage node (VL1) is equal to the voltage level of the second low voltage node (VL2), and the voltage levels are equal to the threshold voltage of the sixth NMOS transistor (N23). Therefore, the static random access memory proposed by the present invention also has the effect of low standby current; (8) the number of low transistors: for the SRAM array having 1024 columns and 1024 rows, the conventional 1b Figure 6T is static. A total of 1024×1024×6=6,291,456 transistors are required for the random access memory array, and the static random access memory proposed by the present invention only needs at least 1024×1024×5+1024×22+6=5,265,414 transistors. , which reduces the number of transistors by 16.3%.

1‧‧‧SRAM cell

2‧‧‧Control circuit

3‧‧‧Precharge circuit

4‧‧‧Standby start circuit

5‧‧‧Word line voltage level conversion circuit

P11‧‧‧First PMOS transistor

P12‧‧‧Second PMOS transistor

N11‧‧‧First NMOS transistor

N12‧‧‧Second NMOS transistor

N13‧‧‧ Third NMOS transistor

A‧‧‧ storage node

B‧‧‧ Inverting storage node

BL‧‧‧ bit line

WLC‧‧‧ word line control signal

S‧‧‧Standby mode control signal

/S‧‧‧Inverted standby mode control signal

VL1‧‧‧ first low voltage node

VL2‧‧‧ second low voltage node

N21‧‧‧4th NMOS transistor

N22‧‧‧ fifth NMOS transistor

N23‧‧‧ sixth NMOS transistor

N24‧‧‧ seventh NMOS transistor

N25‧‧‧ eighth NMOS transistor

N26‧‧‧Ninth NMOS transistor

RC‧‧‧ read control signal

RGND‧‧‧Accelerated reading voltage

INV‧‧‧ third inverter

D1‧‧‧First delay circuit

P31‧‧‧ Third PMOS transistor

P‧‧‧Precharge signal

N41‧‧‧ tenth NMOS transistor

P41‧‧‧4th PMOS transistor

D2‧‧‧second delay circuit

V _DD ‧‧‧Power supply voltage

WL‧‧‧ character line

R‧‧‧Read signal

/W‧‧‧Inverted write signal

/RW‧‧‧Inverted read/write control signal

P51‧‧‧ Fifth PMOS transistor

N51‧‧11 eleventh NMOS transistor

N52‧‧‧12th NMOS transistor

6‧‧‧High voltage level control circuit

V _DD ‧‧‧Power supply voltage

HV _DD ‧‧‧High power supply voltage

P61‧‧‧6th PMOS transistor

P62‧‧‧ seventh PMOS transistor

I63‧‧‧fourth inverter

VH‧‧‧ high voltage node

Claims (10)

A static random access memory comprising: a memory array consisting of a plurality of columns of memory cells and a plurality of rows of memory cells, each column of memory cells and each row of memory cells Each includes a plurality of memory cells (1); a plurality of control circuits (2), each column of memory cells is provided with a control circuit (2); a plurality of precharge circuits (3), each row of memory cells Providing a pre-charging circuit (3); a standby starting circuit (4), the standby starting circuit (4) prompting the static random access memory to quickly enter the standby mode to effectively improve the standby of the static random access memory Performance; a plurality of word line voltage level conversion circuits (5), each column memory cell is provided with a word line voltage level conversion circuit (5); and a plurality of high voltage level control circuits (6), each A column of memory cells is provided with a high voltage level control circuit (6); wherein each memory cell (1) further comprises: a first inverter, which is composed of a first PMOS transistor (P11) and a first NMOS transistor (N11), the first inverter is connected In a power supply voltage (V _DD) between a first node low voltage (VL1); a second inverter, a second line by a PMOS transistor (P12) and a second NMOS transistor (N12) The second inverter is connected between a high voltage node (VH) and a second low voltage node (VL2); a storage node (A) is outputted by the first inverter Formed; an inverting storage node (B) formed by the output of the second inverter; a third NMOS transistor (N13) connected to the storage node (A) and a bit line (BL), and the gate is connected to a word line control signal (WLC); wherein the first inverter and the second inverter are connected in an alternating coupling, that is, the first inverter The output end (ie, the storage node A) is connected to the input end of the second inverter, and the output end of the second inverter (ie, the inverting storage node B) is connected to the first inversion Each control circuit (2) further includes: a fourth NMOS transistor (N21), a fifth NMOS transistor (N22), a sixth NMOS transistor (N23), and a seventh NMOS. Transistor (N24), an eighth NMOS Crystal (N25), a ninth NMOS transistor (N26), a read control signal (RC), a third inverter (INV), a first delay circuit (D1), and an accelerated read voltage (RGND) a standby mode control signal (S) and an inverted standby mode control signal (/S); wherein the source, the gate and the drain of the fourth NMOS transistor (N21) are respectively connected to a ground voltage, The inverting standby mode control signal (/S) and the second low voltage node (VL2); the source, the gate and the drain of the fifth NMOS transistor (N22) are respectively connected to the second low voltage node (VL2), the standby mode control signal (S) and the first low voltage node (VL1); the source of the sixth NMOS transistor (N23) is connected to a ground voltage, and the gate is connected to the drain And connected to the first low voltage node (VL1); the source, the gate and the drain of the seventh NMOS transistor (N24) are respectively connected to the drain of the eighth NMOS transistor (N25), the read Taking a control signal (RC) and the first low voltage node (VL1); a source, a gate and a drain of the eighth NMOS transistor (N25) are respectively connected to the accelerated read voltage (RGND), the first Delayed electricity The output of the circuit (D1) and the source of the seventh NMOS transistor (N24); the first delay circuit (D1) is connected to the output of the third inverter (INV) and the eighth NMOS transistor ( Between the gates of N25); the input of the third inverter (INV) is for receiving the read control signal (RC), and the output is connected to the input of the first delay circuit (D1); a source, a gate and a drain of the NMOS transistor (N26) are respectively connected to a ground voltage, the inverted standby mode control signal (/S) and the first low voltage node (VL1); wherein, for the non-read The read control signal (RC) during the mode is set to the level of the accelerated read voltage (RGND) to prevent leakage current during the non-read mode of the seventh NMOS transistor (N24); The standby starting circuit (4) is designed to rapidly charge the parasitic capacitance at the first low voltage node (VL1) to the threshold voltage of the sixth NMOS transistor (N23) during an initial period of entering the standby mode ( The voltage level of V _TN23 ); in addition, each word line voltage level conversion circuit (5) further comprises: a fifth PMOS transistor (P51), an eleventh NMOS transistor (N51) a twelfth NMOS transistor (N52), a read signal (R), an inverted write signal (/W), an inverted read/write control signal (/RW), and the word line control signal (WLC); wherein the source, the gate and the drain of the fifth PMOS transistor (P51) are respectively connected to a word line (WL), the inverted write signal (/W) and the character a line control signal (WLC); a source, a gate and a drain of the eleventh NMOS transistor (N51) are respectively connected to the word line control signal (WLC), the read signal (R) and the word a source line (WL); and a source, a gate and a drain of the twelfth NMOS transistor (N52) are respectively connected to the word line control signal (WLC), and the inverted read/write control signal (/RW) And the word line (WL); wherein each word line voltage level conversion circuit (5) selects the word line (WL) of the selected cell from the power supply voltage (V) during a read operation _DD ) is converted to the power supply voltage (V _DD ) to the threshold voltage (V _TN51 ) of the eleventh NMOS transistor (N51) (ie, V _DD -V _TN51 ) and then supplied to the word line control signal ( WLC); while in the write operation, the power supply of the word line (WL) of the unit cell will be selected Shall voltage (V _DD) supplied to the word line control signal (the WLC); Finally, each of the high voltage level control circuit (6) further comprises: a sixth PMOS transistor (P61), a seventh PMOS Electrically a crystal (P62) and a fourth inverter (I63), wherein a source, a gate and a drain of the sixth PMOS transistor (P61) are respectively connected to the power supply voltage (V _DD ), the reading a control signal (RC) and the high voltage node (VH), the source, the gate and the drain of the seventh PMOS transistor (P62) are respectively connected to a high power supply voltage (HV _DD ), the fourth reverse The output of the phase comparator (I63) is connected to the high voltage node (VH), and the input of the fourth inverter (I63) is for receiving the read control signal (RC), and the output is connected to the seventh PMOS battery. The bottom of the crystal (P62). The static random access memory according to claim 1, wherein the first NMOS transistor (N11) in the memory cell (1) is the third NMOS transistor (N13) The ratio of the channel width to length ratio is designed to be between 1.2 and 1.5, and the level of the high power supply voltage (HV _DD ) is greater than the level of the power supply voltage (V _DD ). The static random access memory according to claim 2, wherein the first NMOS transistor (N11) and the second NMOS transistor (N12) in each memory cell (1) Having the same channel width to length ratio, and the first PMOS transistor (P11) and the second PMOS The transistor (P12) also has the same channel width to length ratio. The SRAM of claim 3, wherein the accelerated read voltage (RGND) in each control circuit (2) is set lower than each memory cell ( 1) The threshold voltage (V _TN11 ) of the first NMOS transistor (N11). The SRAM of claim 4, wherein the read signal (R) and the inverted write signal in the each word line voltage level conversion circuit (5) /W) is a read/write control pin from the 5T static random access memory, and the read operation is indicated when the read/write control pin is logic high (that is, the read signal R is a logic high level), and The read/write control pin is a logic low-level on-time indicating write operation (ie, the inverted write signal /W is a logic low level), and the inverted read/write control signal (/RW) is the read/write control pin. Inverted signal. The static random access memory according to claim 5, wherein the read control signal (RC) in each control circuit (2) is the read signal (R) and the word line. The result of the AND gate operation of the (WL) signal, that is, when the read signal (R) and the word line (WL) signal are both at a logic high level, the read control signal (RC) is The logic is high. The SRAM of claim 6, wherein each pre-charging circuit (3) is composed of a third PMOS transistor (P31) and a pre-charging signal (P); The source, the gate and the drain of the third PMOS transistor (P31) are respectively connected to a power supply voltage (V _DD ), the precharge signal (P) and the bit line (BL), so as to facilitate During a precharge period, the precharge signal (P) is logic low to precharge the bit line (BL) to the level of the power supply voltage (V _DD ). The static random access memory according to claim 7, wherein the standby starting circuit (4) is a fourth PMOS transistor (P41), a tenth NMOS transistor (N41), and a first a second delay circuit (D2) and the inverted standby mode control signal (/S); wherein the source, the gate and the drain of the fourth PMOS transistor (P41) are respectively connected to a power supply voltage (V) _DD ), the inverted standby mode control signal (/S) and the drain of the tenth NMOS transistor (N41); the source, the gate and the drain of the tenth NMOS transistor (N41) are respectively connected to The first low voltage node (VL1), the output of the second delay circuit (D2) and the drain of the fourth PMOS transistor (P41); the input of the second delay circuit (D2) is connected to the reverse standby The mode control signal (/S), and the output of the second delay circuit (D2) is connected to the gate of the tenth NMOS transistor (N41). The SRAM of claim 8, wherein the initial period of the standby start circuit (4) entering the standby mode is equal to the inverted standby mode control signal (/S) being at a logic high level. Converting to a logic low level, until the gate voltage of the tenth NMOS transistor (N41) is sufficient to turn off the tenth NMOS transistor (N41), which can be provided by the second delay circuit (D2) One delay time to adjust. The static random access memory according to claim 9, wherein the read operation of each memory cell (1) can be further subdivided into two stages, one of the read operations. The first stage is to increase the read speed by setting the first low voltage node (VL1) to the accelerated read voltage (RGND) which is lower than the ground voltage, and in the second stage of the read operation By setting the first low voltage node (VL1) back to the ground voltage to reduce unnecessary power consumption, the second phase of the read operation is separated from the first phase by the read control signal ( RC) from the logic low level to the logic high level, until the gate voltage of the eighth NMOS transistor (N25) is sufficient to turn off the eighth NMOS transistor (N25), which can be performed by the third The falling delay time of the phase converter (INV) is adjusted with another delay time provided by the first delay circuit (D1).