TWI579849B - Memory device and method of manufacturing the same - Google Patents

Description

Memory element and method of manufacturing same

The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a memory device and a method of fabricating the same.

Resistive Random Access Memory (RRAM) is a next-generation non-volatile memory that is currently actively developed. Resistive random access memory is a simple metal-insulator-metal (MIM) structure that can be integrated into the back-end metal process through an additional two mask steps. However, the resistive random access memory formed by the above method may cause plasma inductive damage (PID) due to the subsequent deposition process and the dry etching process. The above plasma damage not only affects the electrical performance of the memory element, but also reduces the reliability and yield of the product.

The invention provides a memory element and a manufacturing method thereof, which can reduce the generation of plasma damage to improve the reliability and yield of the product.

The present invention provides a memory device including a substrate, a capacitor, a protection element, a first metal interconnect, and a second metal interconnect. The substrate has a first zone and a second zone. The capacitor is located on the substrate of the first zone. The capacitor includes a plurality of lower electrodes, an upper electrode, and a capacitor dielectric layer. The upper electrode has a first portion and a second portion. The first portion covers the lower electrode and the second portion extends onto the substrate of the second region. A capacitor dielectric layer is between the lower electrode and the first portion of the upper electrode. The protective element is located in the base of the second zone. The first metal interconnect is located between the capacitor and the substrate, which electrically connects the lower electrode to the substrate. A second metal interconnect is located between the second portion of the upper electrode and the protective element that electrically connects the second portion of the upper electrode to the protective element.

In an embodiment of the invention, the capacitor dielectric layer is a continuous planar structure, a continuous relief structure or a discontinuous planar structure.

In an embodiment of the invention, the first portion of the upper electrode is a continuous planar structure or a continuous concave-convex structure.

In an embodiment of the invention, the memory element further includes a dielectric layer between the lower electrodes. The capacitor dielectric layer is a continuous planar structure and covers the lower electrode and the top surface of the dielectric layer.

In an embodiment of the invention, the capacitor dielectric layer is a continuous relief structure and covers a top surface and a sidewall of the lower electrode.

In an embodiment of the invention, the capacitive dielectric layer is a discontinuous planar structure covering a top surface of the lower electrode.

In an embodiment of the invention, the memory element further includes a plurality of spacers respectively located on the lower electrode and sidewalls of the capacitor dielectric layer.

In an embodiment of the invention, the protection element is a diode, a bipolar junction transistor, or a combination thereof.

In an embodiment of the invention, the material of the capacitor dielectric layer is a variable resistance material.

In an embodiment of the invention, the variable resistance material is ruthenium oxide or a transition metal oxide. The transition metal oxide is ZrO ₂ , HfO ₂ , Ta ₂ O ₅ , Al ₂ O ₃ , TiO ₂ or a combination thereof.

The present invention provides a method of manufacturing a memory element, the steps of which are as follows. A substrate is provided. The substrate has a first zone and a second zone. A capacitor is formed on the substrate of the first region. The capacitor includes a plurality of lower electrodes, an upper electrode, and a capacitor dielectric layer. The upper electrode has a first portion and a second portion. The first portion covers the lower electrode and the second portion extends onto the substrate of the second region. A capacitor dielectric layer is between the lower electrode and the first portion of the upper electrode. A protective element is formed in the substrate of the second region. A first metal interconnect is formed between the capacitor and the substrate. The first metal interconnect is electrically connected to the lower electrode and the substrate. A second metal interconnect is formed between the second portion of the upper electrode and the protective element. The second metal interconnect is electrically connected to the second portion of the upper electrode and the protection element.

In an embodiment of the invention, a method of forming a capacitor on a substrate of the first region is as follows. A lower electrode is formed on the substrate. A dielectric layer is formed on the substrate. The dielectric layer is disposed between the lower electrodes. A capacitor dielectric layer is formed on the lower electrode. A capacitor dielectric layer covers the lower electrode and the top surface of the dielectric layer. An upper electrode is formed on the capacitor dielectric layer.

In an embodiment of the invention, the dielectric layer and the lower electrode are coplanar, and the capacitor dielectric layer is a continuous planar structure.

In an embodiment of the invention, a method of forming a capacitor on a substrate of the first region is as follows. A lower electrode is formed on the substrate. A capacitor dielectric layer is conformally formed on the lower electrode. A capacitor dielectric layer covers the top and side walls of the lower electrode. An upper electrode is formed on the capacitor dielectric layer.

In an embodiment of the invention, the capacitor dielectric layer and the upper electrode above it are continuous relief structures.

In an embodiment of the invention, a method of forming a capacitor on a substrate of the first region is as follows. A lower electrode and a capacitor dielectric layer are sequentially formed on the substrate. The capacitor dielectric layer is a discontinuous planar structure covering the top surface of the lower electrode. A plurality of spacers are respectively formed on sidewalls of the lower electrode and the capacitor dielectric layer. An upper electrode is formed on the capacitor dielectric layer. The upper electrode covers a top surface of the capacitor dielectric layer and a top surface and a sidewall of the spacer.

In an embodiment of the invention, the method of forming the spacers on the sidewalls of the lower electrode and the capacitor dielectric layer is as follows. A plurality of sacrificial layers are respectively formed on the capacitor dielectric layer. A layer of spacer material is conformally formed on the sacrificial layer. The layer of spacer material on the top surface of the sacrificial layer is removed to form spacers on the sidewalls of the lower electrode and the capacitor dielectric layer, respectively. Remove the sacrificial layer.

In an embodiment of the invention, the material of the sacrificial layer comprises an oxide, a nitride, or a combination thereof.

In an embodiment of the invention, the material of the spacer material layer comprises nitride, aluminum oxide or a combination thereof.

In an embodiment of the invention, after forming the capacitor, patterning the upper electrode further includes forming a plurality of strip-shaped upper electrodes.

Based on the above, the present invention electrically connects the upper electrode to the protective element, which can avoid plasma damage (PID) caused by the post-deposition process and the dry etching process, thereby improving product reliability and yield.

The above described features and advantages of the invention will be apparent from the following description.

10, 20, 30‧‧‧ memory components

100‧‧‧Base

104, 110, 116‧‧‧ dielectric layer

106, 107, 112, 206, 212‧‧‧ contact plugs

108, 109, 208‧‧‧ patterned conductor layers

105, 205‧‧‧Metal interconnection

114, 214, 314‧‧‧ lower electrode

118, 218, 318‧‧‧ capacitor dielectric layer

120, 220, 320‧‧‧ upper electrode

120a, 220a, 320a‧‧‧ first part

120b, 220b, 320b‧‧‧ Part II

130, 230, 330‧ ‧ capacitors

202‧‧‧Protection components

322‧‧‧sacrificial layer

324‧‧‧ spacers

D1, D2‧‧‧ dent

R1‧‧‧ first district

R2‧‧‧Second District

S1‧‧‧ surface

1A to 1C are schematic cross-sectional views showing a manufacturing process of a memory element according to a first embodiment of the present invention.

2A to 2C are schematic cross-sectional views showing a manufacturing process of a memory element according to a second embodiment of the present invention.

3A to 3C are schematic cross-sectional views showing a manufacturing process of a memory element according to a third embodiment of the present invention.

1A to 1C are schematic cross-sectional views showing a manufacturing process of a memory element according to a first embodiment of the present invention.

Referring to FIG. 1A, a substrate 100 is provided. The substrate 100 has a first region R1 and a second region R2. In the present embodiment, the substrate 100 is not particularly limited. For example, substrate 100 can be any semiconductor substrate, can be a substrate having other film layers thereon, or can be a substrate having other components therein. In an embodiment, The first region R1 may be, for example, a memory cell region, and the second region R2 may be, for example, a protection element region or a peripheral circuit region.

Next, a protective element 202 is formed in the substrate 100 of the second region R2. In an embodiment, the protective element 202 can be, for example, a diode, a bipolar junction transistor, or a combination thereof. The type, material and size of the protective element of the present invention can be adjusted as needed, as long as it is a protective element that can avoid plasma damage caused by the subsequent deposition process and the dry etching process.

Thereafter, dielectric layers 104, 110 are formed on substrate 100. The material of the dielectric layers 104, 110 is, for example, a low K material or yttrium oxide. The low dielectric constant material is, for example, cerium oxycarbide (SiOC). The method of forming the dielectric layers 104, 110 may be, for example, a chemical vapor deposition method.

Then, a metal interconnect 105 is formed on the substrate 100 of the first region R1. A metal interconnect 205 is formed on the substrate 100 of the second region R2. In this embodiment, the metal interconnects 105 and the metal interconnects 205 can be formed simultaneously. However, the present invention is not limited thereto. In other embodiments, the metal interconnect 105 may be formed first, and then the metal interconnect 205 is formed. Conversely, the metal interconnect 205 may be formed first, and then the metal interconnect 105 is formed. For example, the method of forming the metal interconnect 105 and the metal interconnect 205 is as follows. A plurality of contact openings are formed in the dielectric layer 104 of the first region R1 and the second region R2, the contact opening exposing a surface (not shown) of the substrate 100. Thereafter, a conductor material is filled into the contact opening to form contact plugs 106, 107, 206 (as shown in Figure 1A). Next, patterned conductor layers 108, 109, 208 are formed on the dielectric layer 104 of the first region R1 and the second region R2. The patterned conductor layer 108 is electrically connected To the contact plug 106; the patterned conductor layer 109 is electrically connected to the contact plug 107; the patterned conductor layer 208 is electrically connected to the contact plug 206. Then, a plurality of contact window openings are formed in the dielectric layer 110 of the first region R1 and the second region R2, and the contact window openings respectively expose surfaces (not shown) of the patterned conductor layers 108, 208. Thereafter, a conductor material is filled into the contact opening to form contact plugs 112, 212 (as shown in Figure 1A). In an embodiment, the patterned conductor layer 109 and the contact plug 107 can be electrically connected to the source in the substrate 100; the metal interconnect 105 can be electrically connected to the drain in the substrate 100; The connection 205 can be regarded as a protection element 202 electrically connected to the substrate 100 of the second region R2, but the invention is not limited thereto.

In an embodiment, the material of the contact plugs 106, 107, 206 and the contact plugs 112, 212 may be, for example, titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), Titanium tungsten (TiW), aluminum (Al), copper (Cu), or a combination thereof. The material of the patterned conductor layers 108, 109, 208 may be, for example, titanium (Ti), tungsten (W), aluminum (Al), copper (Cu), or a combination thereof. The material of the contact plugs 106, 107, 206, 112, 212 may be the same as or different from the material of the patterned conductor layers 108, 109, 208. The method of forming the contact plugs 106, 107, 206, 112, 212 and the patterned conductor layers 108, 109, 208 may be, for example, a physical vapor deposition method or a chemical vapor deposition method.

Next, a plurality of lower electrodes 114 are formed on the dielectric layer 110 of the first region R1. Each lower electrode 114 is electrically connected to the corresponding metal interconnect 105. The material of the lower electrode 114 may be, for example, titanium, titanium nitride, tantalum nitride, tungsten, titanium tungsten, aluminum, copper, or a combination thereof. The formation method of the lower electrode 114 is, for example, a physical vapor deposition method or a chemical vapor deposition method. Thereafter, a dielectric layer 116 is formed between the lower electrodes 114. Dielectric layer 116 The forming method may be, for example, forming a dielectric material layer on the substrate 100 to cover the top surface and the sidewall of the lower electrode 114 and the top surface (not shown) of the dielectric layer 110. Thereafter, a chemical mechanical polishing (CMP) process is performed to expose the top surface of the lower electrode 114. In an embodiment, the material of the dielectric material layer may be, for example, ruthenium oxide, tantalum nitride, borophosphonium glass or a combination thereof, and the formation method thereof may be, for example, a chemical vapor deposition method. In other embodiments, the forming step of the lower electrode 114 may also be, for example, first depositing a layer of dielectric material over the contact plug 112 and then patterning the layer of dielectric material to define the location of the subsequently formed lower electrode 114. Thereafter, a layer of the lower electrode material is filled between the dielectric layers 116. Then, a chemical mechanical polishing (CMP) process is performed to planarize and expose the top surface of the lower electrode 114. In an embodiment, the material of the lower electrode material layer may be, for example, titanium, titanium nitride, tantalum nitride, tungsten, titanium tungsten, aluminum, copper, or a combination thereof.

Referring to FIG. 1B, a capacitor dielectric layer 118 is formed on the lower electrode 114. Capacitive dielectric layer 118 covers lower electrode 114 and the top surface of dielectric layer 116. In an embodiment, the dielectric layer 116 and the lower electrode 114 may be, for example, coplanar, such that the surface S1 of the capacitive dielectric layer 118 located thereon is also a plane. Since the capacitor dielectric layer 118 has a continuous planar structure and the subsequently formed upper electrode 120 is also a continuous planar structure (as shown in FIG. 1C), it can increase the subsequent deposition process and the lithography process window, and avoid single memory. When the unit cell is etched and patterned, sidewall damage occurs and its reliability is affected, thereby improving the process yield. In an embodiment, the material of the capacitor dielectric layer 118 can be, for example, a variable resistance material. The variable resistance material may be, for example, ruthenium oxide or a transition metal oxide. The transition metal oxide may be, for example, ZrO ₂ , HfO ₂ , Ta ₂ O ₅ , Al ₂ O ₃ , TiO ₂ or a combination thereof. However, the present invention is not limited thereto. In other embodiments, the material of the capacitor dielectric layer 118 may be, for example, a high dielectric constant material layer, such as an oxide of the following elements, such as germanium, zirconium, aluminum, Titanium, tantalum, niobium, tantalum or niobium, or aluminum nitride, or any combination of the above.

Referring to FIG. 1C, an upper electrode 120 is formed on the capacitor dielectric layer 118. The upper electrode 120 has a first portion 120a and a second portion 120b. The first portion 120a covers the capacitive dielectric layer 118. The second portion 120b extends onto the substrate 100 of the second region R2. Therefore, the upper electrode 120 of the embodiment can be electrically connected to the protection component 202 through the metal interconnection 205 to avoid plasma damage caused by the subsequent deposition process and the dry etching process, thereby improving product reliability and yield. In an embodiment, the material of the upper electrode 120 may be, for example, titanium, titanium nitride, tantalum nitride, tungsten, titanium tungsten, aluminum, copper, or a combination thereof. The formation method of the upper electrode 120 is, for example, a physical vapor deposition method or a chemical vapor deposition method.

In addition, after forming the capacitor 130, the embodiment may further pattern the upper electrode 120 to form a plurality of strip-shaped upper electrodes (not shown). The strip-shaped upper electrode may be parallel to the subsequently formed bit line, thereby reducing the loading of the bit line to further improve product reliability and yield.

Referring to FIG. 1C, the present invention provides a memory device 10 including a substrate 100, a dielectric layer 116, a capacitor 130, a protection element 202, a metal interconnect 105, and a metal interconnect 205. The substrate 100 has a first region R1 and a second region R2. The capacitor 130 is located on the substrate 100 of the first region R1. The capacitor 130 includes a plurality of lower electrodes 114, an upper electrode 120, and a capacitor dielectric layer 118. Dielectric layer 116 is located between lower electrodes 114. The upper electrode 120 has a first portion 120a and a second portion 120b. First The minute 120a covers the top surface of the lower electrode 114 and the dielectric layer 116, while the second portion 120b extends to the substrate 100 of the second region R2. Capacitive dielectric layer 118 is between lower electrode 114 and first portion 120a of upper electrode 120. The protective element 202 is located in the substrate 100 of the second zone R2. Metal interconnect 105 is located between capacitor 130 and substrate 100. The metal interconnect 105 can electrically connect the lower electrode 114 to the substrate 100. Metal interconnect 205 is between second portion 120b of upper electrode 120 and protective element 202. The metal interconnect 205 can electrically connect the second portion 120b of the upper electrode 120 to the protection element 202 to avoid plasma damage caused by the subsequent deposition process and the dry etching process, thereby improving product reliability and yield. In one embodiment, the capacitor 130 can be, for example, a resistive random access memory (RRAM), a dynamic random access memory (DRAM), or a combination thereof, and the invention is not limited thereto.

In the following embodiments, the same or similar elements, members, and layers are denoted by like reference numerals. For example, capacitor 130 of FIG. 1C is the same or similar component as capacitor 230 of FIG. 2C and capacitor 330 of FIG. 3C. The materials and forming methods of the same or similar members described above will not be described one by one.

2A to 2C are schematic cross-sectional views showing a manufacturing process of a memory element according to a second embodiment of the present invention.

Referring to FIG. 1A and FIG. 2A simultaneously, FIG. 1A is substantially similar to FIG. 2A, and the difference is that FIG. 2A forms only a plurality of lower electrodes 214 on the dielectric layer 110 of the first region R1 without configuration. A dielectric layer 116 between the lower electrodes 114.

Referring to FIG. 2B, a capacitor dielectric layer 218 is conformally formed on the lower electrode 214. The capacitor dielectric layer 218 covers the top and sidewalls of the lower electrode 214 and the dielectric layer 110 The top surface. Since the capacitive dielectric layer 218 conformally covers the top surface and sidewalls of the lower electrode 214 and the top surface of the dielectric layer 110, the capacitive dielectric layer 218 can be, for example, a continuous relief structure.

Thereafter, referring to FIG. 2C, the upper electrode 220 is formed on the capacitor dielectric layer 218. The upper electrode 220 has a first portion 220a and a second portion 220b. The first portion 220a covers the capacitive dielectric layer 218 of the first region R1. The capacitor dielectric layer 218 is disposed between the first portion 220a and the lower electrode 214. The second portion 220b extends to the substrate 100 of the second region R2 and is electrically connected to the protective member 202 by a metal interconnect 205.

Referring to FIG. 2C, the memory element 20 of the second embodiment of the present invention is substantially similar to the memory element 10 of the first embodiment of the present invention, except that the capacitive dielectric layer 218 of the memory element 20 can be, for example, It is a continuous concave-convex structure. Therefore, the upper electrode 220 disposed above the capacitor dielectric layer 218 may also be, for example, a continuous relief structure. In an embodiment, the surface corresponding to the upper electrode 220 between adjacent lower electrodes 214 has a recess D1.

3A to 3C are schematic cross-sectional views showing a manufacturing process of a memory element according to a third embodiment of the present invention.

Referring to FIG. 1A and FIG. 3A simultaneously, FIG. 1A is substantially similar to FIG. 3A, and the difference is that a plurality of lower electrodes 314 and a plurality of capacitors are sequentially formed on the dielectric layer 110 of the first region R1 of FIG. 3A. A dielectric layer 318 and a plurality of sacrificial layers 322. The capacitive dielectric layer 318 of FIG. 3A can be viewed as a discontinuous planar structure that covers the top surface of the lower electrode 314. In an embodiment, the material of the sacrificial layer 322 may be, for example, an oxide or a nitride. Or a combination thereof. The formation method of the sacrificial layer 322 may be, for example, a chemical vapor deposition method.

Referring to FIG. 3B, a spacer 324 is formed on the sidewalls of the lower electrode 314, the capacitor dielectric layer 318, and the sacrificial layer 322. In detail, the method of forming the spacer 324 is as follows. A spacer material layer is formed conformally on the sacrificial layer 322, the spacer material layer covering the lower electrode 314, the sidewall of the capacitor dielectric layer 318, the top surface and the sidewall of the sacrificial layer 322, and the top surface of the dielectric layer 110 (not drawn Show). An etching process is performed to remove a portion of the spacer material layer to expose the top surface of the sacrificial layer 322 and the top surface of the dielectric layer 110. In an embodiment, the material of the spacer material layer may be, for example, nitride, aluminum oxide, or a combination thereof.

Referring to FIG. 3C, after the sacrificial layer 322 is removed, the upper electrode 320 is formed on the capacitor dielectric layer 318. The upper electrode 320 has a first portion 320a and a second portion 320b. The first portion 320a covers the top surface of the capacitive dielectric layer 318 of the first region R1 and the top and sidewalls of the spacer 324. The second portion 320b extends to the substrate 100 of the second region R2 and is electrically connected to the protective member 202 by a metal interconnect 205.

Referring to FIG. 3C, the memory element 30 of the third embodiment of the present invention is substantially similar to the memory element 10 of the first embodiment of the present invention, except that the capacitive dielectric layer 318 of the memory element 30 can be, for example, It is a discontinuous planar structure that covers the top surface of the lower electrode 314. Therefore, the upper electrode 320 disposed on the capacitor dielectric layer 318 can be regarded as a continuous uneven structure. In an embodiment, the surface corresponding to the upper electrode 320 between adjacent lower electrodes 314 has a recess D2.

In summary, the present invention electrically connects the upper electrode to the protection element, which can avoid plasma damage caused by the post-deposition process and the dry etching process, thereby improving production. Product reliability and yield. In addition, since the capacitor dielectric layer of the first embodiment of the present invention has a continuous planar structure and the subsequently formed upper electrode is also a continuous planar structure, it can increase the subsequent deposition process and the lithography process margin to further improve the process. Yield.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

10‧‧‧ memory components

100‧‧‧Base

104, 110, 116‧‧‧ dielectric layer

106, 107, 112, 206, 212‧‧‧ contact plugs

108, 109, 208‧‧‧ patterned conductor layers

105, 205‧‧‧Metal interconnection

114‧‧‧ lower electrode

118‧‧‧Capacitive dielectric layer

120‧‧‧Upper electrode

120a‧‧‧Part 1

120b‧‧‧Part II

130‧‧‧ capacitor

202‧‧‧Protection components

R1‧‧‧ first district

R2‧‧‧Second District

S1‧‧‧ surface

Claims (12)

A memory element comprising: a substrate having a first region and a second region; a capacitor on the substrate of the first region, wherein the capacitor comprises: a plurality of lower electrodes; an upper electrode having a first portion and a a second portion, the first portion covering the lower electrode and the second portion extending onto the substrate of the second region; and a capacitor dielectric layer located at the lower electrode and the upper electrode Between the first portions; a protective element located in the substrate of the second region; a first metal interconnect between the capacitor and the substrate, electrically connecting the lower electrode to the a substrate; and a second metal interconnect between the second portion of the upper electrode and the protection element, electrically connecting the second portion of the upper electrode to the protection element . The memory device of claim 1, wherein the capacitor dielectric layer is a continuous planar structure, a continuous relief structure, or a discontinuous planar structure. The memory device of claim 1, further comprising a dielectric layer between the lower electrodes, wherein the capacitor dielectric layer is a continuous planar structure, and covers the lower electrode and the dielectric The top surface of the layer. The memory device of claim 1, wherein the capacitor dielectric layer is a discontinuous planar structure covering a top surface of the lower electrode. The memory device of claim 4, further comprising a plurality of spacers respectively located on the lower electrode and sidewalls of the capacitor dielectric layer. The memory device of claim 1, wherein the material of the capacitor dielectric layer is a variable resistance material. A method of fabricating a memory device, comprising: providing a substrate having a first region and a second region; forming a capacitor on the substrate of the first region, the capacitor comprising: a plurality of lower electrodes; an upper electrode Having a first portion covering the lower electrode and a second portion extending onto the substrate of the second region; and a capacitive dielectric layer located at the lower electrode Between the first portions of the upper electrode; forming a protective element in the substrate of the second region; forming a first metal interconnect between the capacitor and the substrate, the first metal An interconnecting wire electrically connecting the lower electrode and the substrate; and forming a second metal interconnect between the second portion of the upper electrode and the protection element, the second metal interconnect Electrically connecting the second portion of the upper electrode to the protective element. A method of manufacturing a memory element according to claim 7, wherein A method of forming the capacitor on the substrate of the first region includes: forming the lower electrode on the substrate; forming a dielectric layer on the substrate, the dielectric layer being disposed under the substrate Between the electrodes; forming the capacitor dielectric layer on the lower electrode, the capacitor dielectric layer covering the lower electrode and a top surface of the dielectric layer; and forming a layer on the capacitor dielectric layer The electrode is described. The method of manufacturing a memory device according to claim 7, wherein the method of forming the capacitor on the substrate of the first region comprises: forming the lower electrode on the substrate; The capacitor dielectric layer is conformally formed on a lower electrode, the capacitor dielectric layer covers a top surface and a sidewall of the lower electrode; and the upper electrode is formed on the capacitor dielectric layer. The method of manufacturing a memory device according to claim 7, wherein the method of forming the capacitor on the substrate of the first region comprises: sequentially forming the lower electrode and the substrate on the substrate a capacitor dielectric layer, wherein the capacitor dielectric layer is a discontinuous planar structure covering a top surface of the lower electrode; and a plurality of spacers are respectively formed on sidewalls of the lower electrode and the capacitor dielectric layer; And forming the upper electrode on the capacitor dielectric layer, wherein the upper electrode covers a top surface of the capacitor dielectric layer and a top surface and a sidewall of the spacer. A method of manufacturing a memory element according to claim 10, The method for forming the spacers on the sidewalls of the lower electrode and the capacitor dielectric layer respectively comprises: forming a plurality of sacrificial layers on the capacitor dielectric layer; conformally forming on the sacrificial layer Forming a spacer material layer; removing the spacer material layer on a top surface of the sacrificial layer to form the spacers on the sidewalls of the lower electrode and the capacitor dielectric layer, respectively; and removing The sacrificial layer. The method of manufacturing a memory device according to claim 7, after forming the capacitor, further comprising patterning the upper electrode to form a plurality of strip-shaped upper electrodes.