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TWI578865B - A circuit board manufacturing method that can embed high pin count components - Google Patents

A circuit board manufacturing method that can embed high pin count components Download PDF

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Publication number
TWI578865B
TWI578865B TW103138375A TW103138375A TWI578865B TW I578865 B TWI578865 B TW I578865B TW 103138375 A TW103138375 A TW 103138375A TW 103138375 A TW103138375 A TW 103138375A TW I578865 B TWI578865 B TW I578865B
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layer
copper
line
micro
circuit board
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TW103138375A
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Chinese (zh)
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TW201618613A (en
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ding-hao Lin
yi-fan Gao
jian-dong Lan
Yong-Lin Jia
An-Ping Zeng
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Description

可埋入高接腳數元件的電路板製作方法 Circuit board manufacturing method capable of embedding high pin number component

一種內埋元件式電路板製作方法及內埋元件式電路板結構,尤其是一種適合埋入高接腳數元件的電路板製作方法及可埋入高接腳數元件的電路板結構。 The invention relates to a method for manufacturing a buried component type circuit board and a buried component type circuit board structure, in particular to a circuit board manufacturing method suitable for embedding a high pin number component and a circuit board structure capable of embedding a high pin number component.

所謂“埋入式被動元件”(Embedded Passives),係指將被動元件埋入於多層板之中的製程,比如利用蝕刻或印刷方式,將電容器或電阻器等被動元件直接製作於多層板之內層板上,再經壓合成多層板後,藉以取代焊接於板面上的零散(Discrete)被動元件,以增加板面面積與板面上的空間,而供主、被動元件佈設及線路佈線者。 "Embedded Passives" refers to a process in which a passive component is embedded in a multilayer board, such as by etching or printing, and passive components such as capacitors or resistors are directly fabricated in the multilayer board. After the laminate is pressed into a multi-layered board, it replaces the discrete passive components welded on the surface of the board to increase the area of the board surface and the space on the board surface, and the main and passive components are arranged and routed. .

現在埋入元件式電路板除了埋入被動元件,利用類似的技術也能埋入主動元件等電子元件,以提高整體的封裝密度,但是目前如手機與各式電子裝置的功能越來越強大,因此晶片I/O數不斷的持續增加,載板製程更要求高腳數,腳距也需更細密,由於晶片的I/O數是透過電路的微導通孔(Micorvia)結構而與電路板的金屬線路構成電氣連接,因此如何大幅縮小微導通孔的尺寸與微導通孔之間的間隔,及金屬線路的尺寸與金屬線路之間的間隔攸關於能否把高接腳數內埋於電路板的一大重要課題。 Now embedded in component boards, in addition to embedding passive components, similar technologies can also be used to embed electronic components such as active components to increase the overall package density. However, functions such as mobile phones and various electronic devices are becoming more and more powerful. Therefore, the number of I/Os in the chip continues to increase, the carrier process requires a higher number of pins, and the pitch needs to be finer. Since the number of I/Os of the chip is transmitted through the microcord structure of the circuit and the circuit board. The metal lines constitute an electrical connection, so how to greatly reduce the size of the micro-vias and the spacing between the micro-vias, and the size of the metal lines and the spacing between the metal lines, whether or not the number of high-pins can be buried in the board A major issue.

目前微導通孔(Micorvia)的加工以雷射成孔為主,其中雷射鑽孔加工包含開銅窗加工(conformal mask Drill)、加大銅窗加工(Enlarge Window Drill)及直接銅面加工(Copper Direct Drill)等方法。參閱第一圖,第一圖為習知技術之開銅窗法的示意圖,如第一圖所示,第一層板1a上依序形成絕緣層3a、第二線路11a及第一線路7a,開銅窗法的加工方式是在第二線路11a的一部份藉由蝕刻來設置開口(銅窗9a),再於開口以雷射16a 進行加工而在絕緣層上形成導通孔14a。 At present, the processing of micro-vias (Micorvia) is mainly laser-forming, and the laser drilling process includes conformal mask Drill, Enlarge Window Drill and direct copper processing ( Copper Direct Drill) and other methods. Referring to the first figure, the first figure is a schematic diagram of the open copper window method of the prior art. As shown in the first figure, the first layer 1a is sequentially formed with an insulating layer 3a, a second line 11a and a first line 7a. The copper window method is processed by providing an opening (copper window 9a) by etching in a portion of the second line 11a, and a laser 16a at the opening. Processing is performed to form via holes 14a on the insulating layer.

然而以開銅窗加工所成型的導通孔的孔徑除了會受限於光罩的光束徑,尤其更是受易到光阻顯影與蝕刻製程本身的限制,導致導通孔的開孔孔徑無法變得更小,因此電路板的線路密度也無法更密集,而無法連接於高接腳數的主動元件。 However, the aperture of the via hole formed by the copper window processing is limited by the beam diameter of the reticle, and especially by the limitation of the photoresist development and etching process, the aperture of the via hole cannot be changed. Smaller, so the circuit board's line density can not be more dense, and can not be connected to the active components of the high pin count.

具體而言,由於銅箔層(第二線路11a)較難吸收雷射的波長,因此必須以光阻顯影搭配蝕刻的方式在第二線路11a先成型出開口,但以目前的製程能力而言,圖案化後的光阻層所形成的窗部(光阻層對應開口)的最小尺寸已經在50μm以上,因此經蝕刻第二線路11a而成型的開口的孔徑必然在50μm之上。 Specifically, since the copper foil layer (second line 11a) is more difficult to absorb the wavelength of the laser, it is necessary to form an opening in the second line 11a by means of photoresist development and etching, but in terms of current process capability The minimum size of the window portion (corresponding to the photoresist layer) formed by the patterned photoresist layer is already above 50 μm , so the aperture of the opening formed by etching the second line 11a must be above 50 μm . .

此外,經雷射鑽孔加工後,需再經去膠渣(Desmear)流程,嚴重造成開孔孔徑擴大問題,成品的間距約只能達到140微米。 In addition, after laser drilling, it is necessary to go through the Desmear process, which seriously causes the opening aperture to expand. The distance between the finished products can only reach 140 microns.

此外,現有技術常以機械鑽孔做為打件標記,機鑽成孔的通孔孔徑約0.5~3mm,而對位公差與IT轉印公差約15μm,因此機械鑽孔在打件所產生的誤差至少在30μm以上,況且因本身線路蝕刻上的限制造成金屬線路(銅墊)的線路寬度與線路間距無法更細及更密集。 In addition, the prior art often uses mechanical drilling as a marking, the through hole diameter of the hole drilled into the hole is about 0.5~3mm, and the alignment tolerance and the IT transfer tolerance are about 15 μm , so the mechanical drilling is in the hitting place. The error generated is at least 30 μm or more, and the line width and line spacing of the metal line (copper pad) cannot be thinner and denser due to the limitation of the etching of the line itself.

由此可知,習知技術的缺點在於,由於透過開銅窗加工所形成的開孔的孔徑的極限在50μm以上,金屬線路的跨距大於150μm,金屬線路之間的間隔大於30μm,導致只能與接腳數較少的晶片相連接,考量前述的對位公差與IT轉印公差因素的限制,造成微導通孔的尺寸,微導通孔之間的間距與金屬線路的尺寸無法更微小化,因此習知技術的作法及結構已不適用於埋入高接腳數的主動元件,因此必須提供一種可埋入高密度接腳元件的電路板製作方法。 It can be seen that the disadvantage of the prior art is that since the aperture of the opening formed by the processing of the copper window is limited to 50 μm or more, the span of the metal line is greater than 150 μm, and the interval between the metal lines is greater than 30 μm, resulting in It can only be connected to a wafer with a small number of pins, taking into account the above-mentioned alignment tolerance and IT transfer tolerance factors, resulting in the size of the micro-via, the spacing between the micro-vias and the size of the metal lines can not be smaller Therefore, the conventional techniques and structures are not suitable for embedding active components with high pin counts, so it is necessary to provide a circuit board manufacturing method that can embed high-density pin components.

本發明的主要目的在於提供一種可埋入高接腳數元件的電路板製作方法,其中包含一載板上鍍上一金屬層;該金屬層的一面系形成一第一線路,該第一線路包含複數個銅墊;覆蓋一光阻層於該金屬層與該第一線路上;圖案化該光阻層,以使該第一線路僅受圖案化後的該光阻層覆蓋;蝕刻未受圖案化後之該光阻層覆蓋的該金屬層,並去除該光阻層; 於該等銅墊之部份銅墊上形成一粘著層,接著將一元件固定於該粘著層上,該元件具有複數個I/O接腳,其中對應該元件之該等銅墊的任兩銅墊之間皆具有一微銅窗,每一微銅窗對應於每一I/O接腳,而未對應於該元件的該等銅墊之間皆具有一銅窗,將其中的一銅窗設為一靶點;在該第一線路及該元件上依序形成一絕緣層及一第二金屬層,並去除該載板及對該金屬層做蝕刻處理直至該粘著層對應於該微銅窗的部份與該絕緣層之對應於該銅窗的部份露出;對該靶點做光學對位,並藉一鑽孔方法貫穿在該I/O接腳及該微銅窗之間的該粘著層以形成一微通孔於該I/O接腳上,以及貫穿該絕緣層與該第二金屬層之對應於該銅窗的部份以形成一通孔;在該微通孔及內該通孔鍍上一導通層;透過蝕刻方式去除部份的該金屬層直至該第一線路露出,以形成複數個微導通孔與複數個通孔。 The main object of the present invention is to provide a circuit board manufacturing method capable of embedding a high-pin number component, wherein a carrier board is coated with a metal layer; one side of the metal layer forms a first line, and the first line Included in the plurality of copper pads; covering a photoresist layer on the metal layer and the first line; patterning the photoresist layer such that the first line is only covered by the patterned photoresist layer; etching is not affected Patterning the metal layer covered by the photoresist layer and removing the photoresist layer; Forming an adhesive layer on a portion of the copper pad of the copper pad, and then fixing an element to the adhesive layer, the element having a plurality of I/O pins, wherein the copper pads of the corresponding components There is a micro copper window between the two copper pads, and each micro copper window corresponds to each I/O pin, and a copper window is not provided between the copper pads corresponding to the component, one of which is The copper window is set as a target; an insulating layer and a second metal layer are sequentially formed on the first line and the component, and the carrier is removed and the metal layer is etched until the adhesive layer corresponds to a portion of the micro copper window and a portion of the insulating layer corresponding to the copper window are exposed; optically aligning the target, and a drilling method is used to penetrate the I/O pin and the micro copper window The adhesive layer is formed to form a micro via hole on the I/O pin, and a portion of the insulating layer and the second metal layer corresponding to the copper window to form a through hole; The via hole and the via hole are plated with a conductive layer; the portion of the metal layer is removed by etching until the first line is exposed to form a plurality of microvias A plurality of through holes.

其中,該等微導通孔的內端與該等I/O接腳構成電氣連接,該等微導通孔的外端則供外部電路使用。此外,該第二金屬層更圖案化成一第二線路,並藉由該等通孔與該第一線路構成電氣連接。 The inner ends of the microvias are electrically connected to the I/O pins, and the outer ends of the microvias are used by external circuits. In addition, the second metal layer is further patterned into a second line, and electrically connected to the first line through the through holes.

本發明的一主要特點在於,利用圖案化乾膜電鍍的方式以形成第一線路及微銅窗並定義靶點,並在去除載板後第一線路及微銅窗則形成內埋式線路,藉此,使粘著層得以露出並剛好介於任兩銅墊之間的微銅窗中,再利用雷射光束波長難以被銅吸收的特性,因此當雷射光束照射在兩銅墊及粘著層時,只有粘著層會被穿透而形成微通孔,因此微通孔的孔徑與第一線路中的微銅窗相同,而不被光罩光束徑的限制。 A main feature of the present invention is that a patterned dry film plating method is used to form a first line and a micro copper window and define a target point, and after removing the carrier board, the first line and the micro copper window form a buried line. Thereby, the adhesive layer is exposed and just in the micro copper window between any two copper pads, and the wavelength of the laser beam is hard to be absorbed by the copper, so that the laser beam is irradiated on the two copper pads and adhered. When the layer is layered, only the adhesive layer is penetrated to form a microvia, and thus the aperture of the microvia is the same as the micro copper window in the first line, and is not limited by the beam path of the mask.

此外,本發明的第一線路為內埋式線路,因此粘著層之將形成微導通孔的微通孔不受金屬層覆蓋,因此雷射可以直接穿透粘著層而形成微通孔;但是習知技術的絕緣層整面被金屬層覆蓋,由於雷射難以穿透金屬層,因此必須透過影像轉移方式先在金屬層開出銅窗後,再利用雷射對絕緣層做鑽孔處理,但經雷射鑽孔加工後,由於需再經去膠渣(Desmear)流程,仍會造成開孔孔徑擴大問題,成品的間距約只能達到140μm。 In addition, the first line of the present invention is a buried line, so that the micro-via holes of the adhesion layer that will form the micro-vias are not covered by the metal layer, so the laser can directly penetrate the adhesion layer to form micro-vias; However, the entire surface of the insulating layer of the prior art is covered by a metal layer. Since it is difficult for the laser to penetrate the metal layer, it is necessary to first open the copper window in the metal layer through image transfer, and then use the laser to drill the insulating layer. However, after laser drilling, the hole diameter expansion problem will still be caused by the Desmear process, and the finished product pitch can only reach 140 μm .

其中,第一線路與微銅窗係對金屬層以圖案化乾膜電鍍的方式形成,利用圖案化電鍍乾膜而成型出第一線路,以現有製程能力而言,第一線路的線寬及其間距可輕易控制在50μm以下。此外,第一線路與銅 窗的製作過程中,只對同是金屬材質的金屬層及載板做製程處理,製程參數容易控制也容易加工,因此第一線路的線寬及第一線路的間距得以被精準控制。 Wherein, the first line and the micro copper window system are formed by patterning dry film plating on the metal layer, and the first line is formed by using the patterned electroplating dry film, and the line width of the first line is in terms of the existing process capability and The spacing can be easily controlled below 50 μm . In addition, in the process of fabricating the first line and the copper window, only the metal layer and the carrier plate of the same metal material are processed, and the process parameters are easy to control and easy to process, so the line width of the first line and the spacing of the first line are Can be precisely controlled.

由於以圖案化電鍍乾膜成形的第一線路中的微銅窗能輕鬆控制在50μm以下,因此經雷射鑽孔處理後,所形成的微通孔的孔徑可大幅縮小在50μm以下,藉以大幅縮小微導通孔孔徑,因此可以大幅提高微導通孔的佈置密度,藉以有效對應可埋入具高密度接腳的元件的需求,此外本發明利用雷射開設微通孔且使用與跟微通孔同一層的靶點,藉由光學對位的方式去固定元件及作雷射鑽孔,因此可有效提高打件的精度,透過本發明提供可埋入高密度接腳元件的電路板的製作方法與結構,所形成的微導通孔的孔徑與銅墊的直徑可縮小至10μm以下,而埋入的元件的接腳數目高達2萬個。 Since the micro copper window in the first line formed by the patterned electroplating dry film can be easily controlled below 50 μm , the diameter of the formed micro via hole can be greatly reduced to 50 μm after laser drilling. In the following, the micro-via hole diameter is greatly reduced, so that the arrangement density of the micro-via holes can be greatly increased, thereby effectively meeting the requirements of embedding components with high-density pins, and the present invention uses a laser to open micro-vias and uses The target layer on the same layer as the micro-via hole is used to fix the component and perform laser drilling by means of optical alignment, thereby effectively improving the precision of the workpiece, and the circuit for embedding the high-density pin component is provided by the present invention. The manufacturing method and structure of the board, the diameter of the micro-via hole and the diameter of the copper pad can be reduced to less than 10 μm , and the number of pins of the embedded component is up to 20,000.

本發明的另一目的在於提供一種可埋入高接腳數元件的電路板結構,至少包含一絕緣層、一第一線路及一第二線路,該第一線路內埋於該絕緣層之內,該第二線路形成於絕緣層之外,該絕緣層更內埋有一粘著層及一元件,該元件固定於該粘著層之上,其中該粘著層內具有與該元件之複數個I/O接腳1構成電氣連接的複數個微導通孔,該絕緣層則具有使該第一線路及該第二線路構成電氣連接的複數個通孔。 Another object of the present invention is to provide a circuit board structure capable of embedding a high pin number component, comprising at least an insulating layer, a first line and a second line, wherein the first line is buried in the insulating layer The second line is formed outside the insulating layer. The insulating layer is further embedded with an adhesive layer and an element. The element is fixed on the adhesive layer, wherein the adhesive layer has a plurality of components in the adhesive layer. The I/O pin 1 constitutes a plurality of microvias electrically connected, and the insulating layer has a plurality of vias that electrically connect the first line and the second line.

〔習知〕 [study]

1a‧‧‧第一層板 1a‧‧‧ first floor

3a‧‧‧第二層板 3a‧‧‧Second floor

7a‧‧‧第一線路 7a‧‧‧First line

9a‧‧‧銅窗圖案 9a‧‧‧ copper window pattern

11a‧‧‧第二線路 11a‧‧‧second line

14a‧‧‧導通孔 14a‧‧‧through hole

16a‧‧‧雷射 16a‧‧‧Laser

〔本發明〕 〔this invention〕

S10~S28‧‧‧步驟 S10~S28‧‧‧Steps

10‧‧‧載板 10‧‧‧ Carrier Board

12‧‧‧金屬層 12‧‧‧metal layer

14‧‧‧第一線路 14‧‧‧First line

141‧‧‧銅墊 141‧‧‧ copper pad

16‧‧‧光阻層 16‧‧‧ photoresist layer

20‧‧‧粘著層 20‧‧‧Adhesive layer

100‧‧‧元件 100‧‧‧ components

101‧‧‧I/O接腳 101‧‧‧I/O pins

143‧‧‧微銅窗 143‧‧‧micro copper window

145‧‧‧銅窗 145‧‧‧ copper window

21‧‧‧絕緣層 21‧‧‧Insulation

22‧‧‧第二金屬層 22‧‧‧Second metal layer

201‧‧‧微通孔 201‧‧‧Microvia

211‧‧‧通孔 211‧‧‧through hole

221‧‧‧第二線路 221‧‧‧second line

30‧‧‧導通層 30‧‧‧ conduction layer

301‧‧‧微導通孔 301‧‧‧Micro-vias

303‧‧‧通孔 303‧‧‧through hole

A‧‧‧靶點 A‧‧‧ Target

第一圖為習知技術之開銅窗法的示意圖。 The first figure is a schematic diagram of the open copper window method of the prior art.

第二圖為本發明可埋入高接腳數元件的電路板製作方法的操作流程圖。 The second figure is an operational flowchart of a method for fabricating a circuit board capable of embedding a high pin number component.

第三A至第三J圖為本發明可埋入高接腳數元件的電路板製作方法的示意圖。 The third to third J diagrams are schematic diagrams of a method of fabricating a circuit board capable of embedding a high pin number component.

第四圖為本發明可埋入高接腳數元件的電路板的一較佳實施例示意圖。 The fourth figure is a schematic view of a preferred embodiment of a circuit board in which the high pin number component can be embedded in the present invention.

以下配合圖式及元件符號對本發明之實施方式做更詳細的 說明,俾使熟習該項技藝者在研讀本說明書後能據以實施。 The embodiments of the present invention are described in more detail below with reference to the drawings and the component symbols. Explain that the person skilled in the art can implement it after studying this manual.

參閱第二圖,本發明可埋入高接腳數元件的電路板製作方法的操作流程圖,參閱第三A至第三J圖,本發明可埋入高接腳數元件的電路板製作方法的示意圖。如第二圖所示,本發明電路板微導通孔之製作方法包括以下依序進行的步驟S10、S12、S14、S16、S18、S20、S22、S24、S26及S28。首先,配合第三A圖,主要是從步驟S10開始,在一載板10上鍍上一金屬層12,其中該金屬層12可以是單一金屬層或複數層金屬層,該金屬層為銅層(Cu)或其他適當材質的金屬層,該載板10亦可為金屬材質。 Referring to the second figure, an operation flowchart of a method for manufacturing a circuit board capable of embedding a high-pin number component according to the present invention, referring to FIGS. 3A to 3J, a circuit board manufacturing method capable of embedding a high-pin number component of the present invention Schematic diagram. As shown in the second figure, the method for fabricating the microvia of the circuit board of the present invention comprises the following steps S10, S12, S14, S16, S18, S20, S22, S24, S26 and S28. First, in conjunction with the third A picture, mainly from step S10, a metal layer 12 is plated on a carrier 10, wherein the metal layer 12 may be a single metal layer or a plurality of metal layers, and the metal layer is a copper layer. (Cu) or other suitable material metal layer, the carrier 10 may also be made of metal.

接著,在步驟S12中,圖案化該金屬層12的一面以形成一第一線路14,該第一線路14包含複數個銅墊141,如第三B圖所示。其中,該第一線路14透過圖案化乾膜電鍍的方式或其他適當方式形成。 Next, in step S12, one side of the metal layer 12 is patterned to form a first line 14, which includes a plurality of copper pads 141, as shown in FIG. The first line 14 is formed by patterning dry film plating or other suitable means.

之後,進行步驟S14,覆蓋一光阻層16於該金屬層12與該第一線路14上,如第三C圖所示。 Thereafter, step S14 is performed to cover a photoresist layer 16 on the metal layer 12 and the first line 14, as shown in FIG. 3C.

在步驟S16中,圖案化該光阻層16,以使該第一線路14只受圖案化後的該光阻層16覆蓋,如第三D圖所示。其中該光阻層16可為乾膜光阻或溼膜光阻。 In step S16, the photoresist layer 16 is patterned such that the first line 14 is only covered by the patterned photoresist layer 16, as shown in FIG. 3D. The photoresist layer 16 can be a dry film photoresist or a wet film photoresist.

接著進行步驟S18,蝕刻未受該光阻層16覆蓋之該金屬層12至一預定深度,比如可以參考第三E圖的實施例,在第三E圖中系將該金屬層12之對應預設元件的區域皆蝕刻去除,而未對應預設元件的區域僅蝕刻其金屬層的一部分待蝕刻完該金屬層12後,去除該光阻層16,如第三E圖所示。 Next, in step S18, the metal layer 12 not covered by the photoresist layer 16 is etched to a predetermined depth. For example, refer to the embodiment of the third E diagram, and in the third E diagram, the corresponding layer of the metal layer 12 is pre-processed. The regions of the component are all etched away, and the region not corresponding to the predetermined component is etched only by a portion of the metal layer. After the metal layer 12 is to be etched, the photoresist layer 16 is removed, as shown in FIG.

然而,步驟S18中的該金屬層12的蝕刻方式視實際情況而定,上述的蝕刻方式在此僅是說明用的實例而已,並非用以限制本發明的範圍,亦即該金屬層12之對應預設元件的區域亦可僅去除一部份,未被去除的部份可以再透過後續的蝕刻步驟去除。 However, the etching manner of the metal layer 12 in the step S18 is determined according to the actual situation. The above etching method is merely an example for illustration, and is not intended to limit the scope of the present invention, that is, the correspondence of the metal layer 12. The area of the predetermined component can also be removed only by a portion, and the unremoved portion can be removed by a subsequent etching step.

接著進行步驟S20,於該等銅墊141之部份銅墊上形成一粘著層20,比如該粘著層20設於該等銅墊141的預設元件區域部份,接著將一元件100固定於該粘著層20上,該元件100具有複數個I/O接腳101,其 中對應該元件100之該等銅墊141的任兩銅墊141之間皆具有一微銅窗143,每一微銅窗143對應於每一I/O接腳101,而未對應於該元件100的該等銅墊141之間則皆具有一銅窗145,將其中的一銅窗145設為一靶點A,如第三F圖所示。其中,該元件100的設置可利用該靶點A作對位,使對位公差最小化。 Then, in step S20, an adhesive layer 20 is formed on a portion of the copper pads of the copper pads 141. For example, the adhesive layer 20 is disposed on a predetermined component region of the copper pads 141, and then an element 100 is fixed. On the adhesive layer 20, the component 100 has a plurality of I/O pins 101, There is a micro copper window 143 between any two copper pads 141 of the copper pads 141 corresponding to the component 100, and each micro copper window 143 corresponds to each I/O pin 101 and does not correspond to the component. Each of the copper pads 141 of 100 has a copper window 145, and one of the copper windows 145 is set as a target point A, as shown in the third F. Wherein, the arrangement of the component 100 can be aligned by using the target A to minimize the alignment tolerance.

其中,該元件可以是主動元件、被動元件或其他適當元件;其中該粘著層20透過點膠技術、網版印刷技術(Screen print)或整片貼合於而形成之。 Wherein, the component may be an active component, a passive component or other suitable component; wherein the adhesive layer 20 is formed by a dispensing technique, a screen print or a whole sheet.

接著進行步驟S22,在該第一線路14及該元件100上依序形成一絕緣層21及一第二金屬層22,該絕緣層21覆蓋該第一線路14及該元件100,並去除該載板10及對該金屬層12做蝕刻處理直至該粘著層20之對應於該微銅窗143的部份與該絕緣層21對應於該銅窗145的部份露出,如第三G圖所示。 Next, in step S22, an insulating layer 21 and a second metal layer 22 are sequentially formed on the first line 14 and the device 100. The insulating layer 21 covers the first line 14 and the component 100, and the carrier is removed. The plate 10 and the metal layer 12 are etched until the portion of the adhesive layer 20 corresponding to the micro copper window 143 and the portion of the insulating layer 21 corresponding to the copper window 145 are exposed, as shown in the third G diagram. Show.

接著進行步驟S24,對該靶點A做光學對位,並藉一鑽孔方法貫穿在該I/O接腳101及該微銅窗143之間的該粘著層20以形成一微通孔201於該I/O接腳101上,以及貫穿該絕緣層21與該第二金屬層22之對應於該銅窗145的部份以形成一通孔211,如第三H圖所示。 Next, in step S24, the target point A is optically aligned, and the adhesion layer 20 is interposed between the I/O pin 101 and the micro copper window 143 by a drilling method to form a micro via hole. 201 is formed on the I/O pin 101, and a portion of the insulating layer 21 and the second metal layer 22 corresponding to the copper window 145 to form a through hole 211, as shown in FIG.

其中,該鑽孔方法為一雷射鑽孔,該微通孔201的孔徑則以該微銅窗143的大小而定。 The drilling method is a laser drilling hole, and the aperture of the micro through hole 201 is determined by the size of the micro copper window 143.

接著進行步驟S26,在該微通孔201及該通孔211內鍍上一導通層30,如第三I圖所示。其中該導通層30為一金屬層。 Next, in step S26, a conductive layer 30 is plated in the micro via 201 and the via 211, as shown in FIG. The conductive layer 30 is a metal layer.

接著進行步驟S28,透過蝕刻方式去除部份的該金屬層12直至該第一線路14露出,以形成複數個微導通孔301與複數個通孔303,該等微導通孔301的內端與該等I/O接腳101構成電氣連接,該等微導通孔303的外端則供外部電路使用。此外,該第二金屬層22更圖案化成一第二線路221,並藉由該等通孔303與該第一線路14構成電氣連接,如第三J圖所示。 Then, in step S28, a portion of the metal layer 12 is removed by etching until the first line 14 is exposed to form a plurality of micro vias 301 and a plurality of vias 303, and the inner ends of the micro vias 301 are The I/O pins 101 constitute an electrical connection, and the outer ends of the microvias 303 are used by an external circuit. In addition, the second metal layer 22 is further patterned into a second line 221, and the first line 14 is electrically connected by the through holes 303, as shown in FIG.

藉由上述流程,而製作出可埋入高接腳數元件的電路板製作方法,請參第三J圖,本發明可埋入高接腳數元件的電路板結構至少包含一 絕緣層21,該第一線路14內埋於該絕緣層21之內,該第二線路221形成於絕緣層221之外,該絕緣層21更內埋有一粘著層20及一元件100,該元件100固定於該粘著層20之上,其中該粘著層20內具有與該元件100之複數個I/O接腳101構成電氣連接的複數個微導通孔301,該絕緣層21則具有使該第一線路14及該第二線路221構成電氣連接的複數個通孔303。 According to the above process, a circuit board manufacturing method capable of embedding a high pin number component is manufactured. Referring to FIG. 3J, the circuit board structure in which the high pin number component can be embedded in the present invention includes at least one In the insulating layer 21, the first line 14 is buried in the insulating layer 21, and the second line 221 is formed outside the insulating layer 221, and the insulating layer 21 is further embedded with an adhesive layer 20 and an element 100. The component 100 is fixed on the adhesive layer 20, wherein the adhesive layer 20 has a plurality of microvias 301 electrically connected to the plurality of I/O pins 101 of the component 100, and the insulating layer 21 has The first line 14 and the second line 221 are configured to form a plurality of through holes 303 electrically connected.

參閱第四圖,本發明可埋入高接腳數元件的電路板的一較佳實施例示意圖。如第四圖所示,該粘著層20系整片貼合於該第一線路14上,如此更方便加工製作,也就是上述的步驟S20中,用片狀或捲狀的黏著層20直接貼設於該第一線路14上,該粘著層20對應於該銅窗145的部份亦被貫穿而形成該通孔211,後續的操作則參照前述的步驟,最後即形成如第四圖的結構。 Referring to the fourth figure, a schematic diagram of a preferred embodiment of a circuit board in which the present invention can be embedded in a high pin number component is shown. As shown in the fourth figure, the adhesive layer 20 is integrally attached to the first line 14, so that it is more convenient to process, that is, in the above step S20, the adhesive layer 20 is directly formed by a sheet or a roll. Attached to the first line 14, the portion of the adhesive layer 20 corresponding to the copper window 145 is also penetrated to form the through hole 211, the subsequent operation refers to the foregoing steps, and finally forms the fourth figure. Structure.

本發明的一主要特點在於,在步驟S10~S20,利用圖案化乾膜電鍍的方式以形成第一線路及微銅窗並定義靶點A,並在步驟S22去除載板後第一線路及微銅窗則形成內埋式線路,藉此,使粘著層得以露出並剛好介於任兩銅墊之間的微銅窗中,再利用雷射光束波長難以被銅吸收的特性,因此當雷射光束照射在兩銅墊及粘著層時,只有粘著層會被穿透而形成微通孔,因此微通孔的孔徑與第一線路中的微銅窗相同,而不被光罩光束徑的限制。 A main feature of the present invention is that, in steps S10 to S20, patterning dry film plating is used to form the first line and the micro copper window and define the target point A, and the first line and the micro after removing the carrier board in step S22. The copper window forms a buried circuit, whereby the adhesive layer is exposed and just in the micro copper window between any two copper pads, and then the wavelength of the laser beam is difficult to be absorbed by copper, so When the beam is irradiated on the two copper pads and the adhesion layer, only the adhesion layer is penetrated to form a micro-via, so that the aperture of the micro-via is the same as the micro-copper window in the first line, and is not covered by the reticle beam. Path limit.

此外,本發明的第一線路為內埋式線路,因此粘著層之將形成微導通孔的微通孔不受金屬層覆蓋,因此雷射可以直接穿透粘著層而形成微通孔;但是習知技術的絕緣層整面被金屬層覆蓋,由於雷射難以穿透金屬層,因此必須透過影像轉移方式先在金屬層開出銅窗後,再利用雷射對絕緣層做鑽孔處理,但經雷射鑽孔加工後,由於需再經去膠渣(Desmear)流程,仍會造成開孔孔徑擴大問題,成品的間距約只能達到140μm。 In addition, the first line of the present invention is a buried line, so that the micro-via holes of the adhesion layer that will form the micro-vias are not covered by the metal layer, so the laser can directly penetrate the adhesion layer to form micro-vias; However, the entire surface of the insulating layer of the prior art is covered by a metal layer. Since it is difficult for the laser to penetrate the metal layer, it is necessary to first open the copper window in the metal layer through image transfer, and then use the laser to drill the insulating layer. However, after laser drilling, the hole diameter expansion problem will still be caused by the Desmear process, and the finished product pitch can only reach 140 μm .

而本發明之第一線路與微銅窗係對金屬層以圖案化乾膜電鍍的方式形成,利用圖案化電鍍乾膜而成型出第一線路,以現有製程能力而言,第一線路的線寬及其間距可輕易控制在50μm以下。此外,第一線路與銅窗的製作過程中,只對同是金屬材質的金屬層及載板做製程處理,製程參數容易控制也容易加工,因此第一線路的線寬及第一線路的間距得 以被精準控制。 The first line and the micro copper window of the present invention are formed by patterning dry film plating on the metal layer, and the first line is formed by patterning the dry film, and the line of the first line is in terms of the existing process capability. The width and spacing can be easily controlled below 50 μm . In addition, in the process of fabricating the first line and the copper window, only the metal layer and the carrier plate of the same metal material are processed, and the process parameters are easy to control and easy to process, so the line width of the first line and the spacing of the first line are Can be precisely controlled.

由於以圖案化電鍍乾膜成形的第一線路中的微銅窗能輕鬆控制在50μm以下,因此經雷射鑽孔處理後,所形成的微通孔的孔徑可大幅縮小在50μm以下,藉以大幅縮小微導通孔孔徑,因此可以大幅提高微導通孔的佈置密度,藉以有效對應可埋入具高密度接腳的元件的需求,此外本發明利用雷射開設微通孔且使用與跟微通孔同一層的靶點,藉由光學對位的方式去固定元件及作雷射鑽孔,因此可有效提高打件的精度,透過本發明提供可埋入高密度接腳元件的電路板的製作方法與結構,所形成的微導通孔的孔徑與銅墊的直徑可縮小至10μm以下,而埋入的元件的接腳數目高達2萬個。 Since the micro copper window in the first line formed by the patterned electroplating dry film can be easily controlled below 50 μm , the diameter of the formed micro via hole can be greatly reduced to 50 μm after laser drilling. In the following, the micro-via hole diameter is greatly reduced, so that the arrangement density of the micro-via holes can be greatly increased, thereby effectively meeting the requirements of embedding components with high-density pins, and the present invention uses a laser to open micro-vias and uses The target layer on the same layer as the micro-via hole is used to fix the component and perform laser drilling by means of optical alignment, thereby effectively improving the precision of the workpiece, and the circuit for embedding the high-density pin component is provided by the present invention. The manufacturing method and structure of the board, the diameter of the micro-via hole and the diameter of the copper pad can be reduced to less than 10 μm , and the number of pins of the embedded component is up to 20,000.

於本發明的技術內並未見於已公開的刊物、期刊、雜誌、媒體、展覽場,因而具有新穎性,且能突破目前的技術瓶頸而具體實施,確實具有進步性。此外,本發明能解決習用技術的問題,改善整體使用效率,而能達到具產業利用性的價值。 It has not been seen in the published publications, periodicals, magazines, media, and exhibition fields in the technology of the present invention, and thus has novelty and can be implemented through the current technical bottlenecks, and is indeed progressive. In addition, the present invention can solve the problems of the conventional technology, improve the overall use efficiency, and can achieve the value of industrial utilization.

以上所述者僅為用以解釋本發明之較佳實施例,並非企圖據以對本發明做任何形式上之限制,是以,凡有在相同之發明精神下所作有關本發明之任何修飾或變更,皆仍應包括在本發明意圖保護之範疇。 The above is only a preferred embodiment for explaining the present invention, and is not intended to limit the present invention in any way, and any modifications or alterations to the present invention made in the spirit of the same invention. All should still be included in the scope of the intention of the present invention.

S10~S28‧‧‧步驟 S10~S28‧‧‧Steps

Claims (9)

一種可埋入高接腳數元件的電路板製作方法,包含:一載板上鍍上一金屬層;該金屬層的一面系形成一第一線路,該第一線路包含複數個銅墊;覆蓋一光阻層於該金屬層與該第一線路上;圖案化該光阻層,以使該第一線路僅受圖案化後的該光阻層覆蓋;蝕刻未受圖案化後之該光阻層覆蓋的該金屬層,並去除該光阻層;於該等銅墊之部份銅墊上形成一粘著層,接著將一元件固定於該粘著層上,該元件具有複數個I/O接腳,其中對應該元件之該等銅墊的任兩銅墊之間皆具有一微銅窗,每一微銅窗對應於每一I/O接腳,而未對應於該元件的該等銅墊之間皆具有一銅窗,將其中的一銅窗設為一靶點;在該第一線路及該元件上依序形成一絕緣層及一第二金屬層,並去除該載板及對該金屬層做蝕刻處理直至該粘著層對應於該微銅窗的部份與該絕緣層之對應於該銅窗的部份露出;對該靶點做光學對位,並藉一鑽孔方法貫穿在該I/O接腳及該微銅窗之間的該粘著層以形成一微通孔於該I/O接腳上,以及貫穿該絕緣層與該第二金屬層之對應於該銅窗的部份以形成一通孔;在該微通孔及內該通孔鍍上一導通層;以及透過蝕刻方式去除部份的該金屬層直至該第一線路露出,以形成複數個微導通孔與複數個通孔。 A circuit board manufacturing method capable of embedding a high pin number component, comprising: plating a metal layer on a carrier plate; forming a first line on one side of the metal layer, the first circuit comprising a plurality of copper pads; covering a photoresist layer on the metal layer and the first line; patterning the photoresist layer such that the first line is only covered by the patterned photoresist layer; etching the photoresist after being patterned Layering the metal layer and removing the photoresist layer; forming an adhesive layer on a portion of the copper pad of the copper pad, and then fixing an element to the adhesive layer, the component having a plurality of I/O a pin, wherein each of the copper pads of the copper pad corresponding to the component has a micro copper window, and each micro copper window corresponds to each I/O pin, and does not correspond to the component. A copper window is disposed between the copper pads, and one of the copper windows is set as a target point; an insulating layer and a second metal layer are sequentially formed on the first line and the component, and the carrier plate is removed and Etching the metal layer until the adhesive layer corresponds to the portion of the micro copper window and the insulating layer corresponds to the copper window Partially exposing; optically aligning the target, and inserting the adhesive layer between the I/O pin and the micro copper window by a drilling method to form a micro through hole in the I/O a through hole is formed on the pin and through the portion of the insulating layer and the second metal layer corresponding to the copper window; a through hole is formed in the micro via and the via hole; and the etching is removed by etching A portion of the metal layer is exposed until the first line to form a plurality of microvias and a plurality of vias. 依據申請專利範圍第1項所述之可埋入高接腳數元件的電路板製作方法,其中該載板為金屬材質。 The method for fabricating a circuit board capable of embedding a high pin number component according to the first aspect of the patent application, wherein the carrier board is made of a metal material. 依據申請專利範圍第1項所述之可埋入高接腳數元件的電路板製作方法,該第一線路以圖案化乾膜電鍍的方法而形成。 According to the method of fabricating a board capable of embedding a high pin number component according to the first aspect of the patent application, the first line is formed by a pattern dry plating method. 依據申請專利範圍第1項所述之可埋入高接腳數元件的電路板製作方法,其中該光阻層可為乾膜光阻或溼膜光阻。 A method of fabricating a circuit board capable of embedding a high pin number component according to claim 1, wherein the photoresist layer is a dry film photoresist or a wet film photoresist. 依據申請專利範圍第1項所述之可埋入高接腳數元件的電路板製作方法,其中該元件的設置利用該靶點A作對位。 A method of fabricating a circuit board capable of embedding a high pin number component according to the first aspect of the patent application, wherein the component is disposed using the target A for alignment. 依據申請專利範圍第1項所述之可埋入高接腳數元件的電路板製作方法,其中該元件為主動元件或被動元件。 A circuit board manufacturing method capable of embedding a high pin number component according to the first aspect of the patent application, wherein the component is an active component or a passive component. 依據申請專利範圍第1項所述之可埋入高接腳數元件的電路板製作方法,其中該粘著層系透過點膠技術、網版印刷技術或貼合方式而形成之,其中貼合方式以片狀或捲狀的該粘著層貼合於該第一線路上,該粘著層對應於該銅窗的部份亦被貫穿而形成該通孔。 The method for fabricating a circuit board capable of embedding a high pin number component according to claim 1, wherein the adhesive layer is formed by a dispensing technique, a screen printing technique or a bonding method, wherein the bonding layer is formed The adhesive layer in the form of a sheet or a roll is attached to the first line, and the portion of the adhesive layer corresponding to the copper window is also penetrated to form the through hole. 依據申請專利範圍第1項所述之可埋入高接腳數元件的電路板製作方法,其中該鑽孔方法為一雷射鑽孔。 A method of fabricating a circuit board capable of embedding a high pin number component according to claim 1 of the patent application, wherein the drilling method is a laser drilling. 依據申請專利範圍第1項所述之可埋入高接腳數元件的電路板製作方法,其中該微通孔為盲孔或埋孔。 The method for fabricating a circuit board capable of embedding a high pin number component according to the first aspect of the patent application, wherein the micro through hole is a blind hole or a buried hole.
TW103138375A 2014-11-05 2014-11-05 A circuit board manufacturing method that can embed high pin count components TWI578865B (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201029125A (en) * 2009-01-16 2010-08-01 Phoenix Prec Technology Corp Packaging substrate having semiconductor chip embedded therein, and method for manufacturing the same
TW201406217A (en) * 2012-07-27 2014-02-01 Tripod Technology Corp Device embedded printed circuit board and manufacturing method thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201029125A (en) * 2009-01-16 2010-08-01 Phoenix Prec Technology Corp Packaging substrate having semiconductor chip embedded therein, and method for manufacturing the same
TW201406217A (en) * 2012-07-27 2014-02-01 Tripod Technology Corp Device embedded printed circuit board and manufacturing method thereof

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