TWI570812B - Method for forming fin-shaped structure - Google Patents

Description

Method of forming a fin structure

The present invention relates to the field of semiconductor processing, and more particularly to a method of forming a fin structure.

As the field effect transistor (FETs) component size continues to shrink, the development of conventional planar field effect transistor components has faced the limits of the process. In order to overcome the process limitation, the replacement of planar transistor components with non-planar field-effect transistor components, such as Fin Field Effect Transistor (Fin FET) components, has become the mainstream trend. . In the current generation process of the sub-lithography feature, the optical lithography process is generally combined with a pull back to form a fin structure of the fin field effect transistor.

However, as the size of field-effect transistor components shrinks, the electrical and physical requirements of the regions of the various components are becoming more stringent; for example, the size of the fin structure (the current fin structure, which is only about 10 nanometers wide) M), shape, and distance between each other, how to achieve the required specifications and overcome these physical limits to form such structures and achieve these conditions has become an important issue in the semiconductor industry today.

The invention provides a method for forming a fin structure, which applies a sidewall pattern transfer technique to a multilayer structure to protect the fin structure from being damaged during pattern transfer to improve process quality.

The invention provides a method for manufacturing a fin structure, which comprises the following steps: First, a multi-layer structure is formed on a substrate, and then a sacrificial pattern is formed on the multi-layer structure, and a spacer is formed on a side of the sacrificial pattern, and is disposed on the multi-layer structure, and then the sacrificial pattern is removed. The plurality of spacers are used as a mask to etch the portion of the multilayer structure, and the substrate is used as a mask to etch the portion to form at least one fin structure in the substrate.

The invention is characterized in that a multi-layer structure is disposed between the substrate and the spacer, and the spacer is used as a mask to perform a pattern transfer process, the pattern is transferred to a multi-layer structure, and the multi-layer structure is used as a mask. Another pattern transfer process is performed, and the pattern is transferred to the substrate to form a plurality of fin structures in the substrate. In this way, after two or more pattern transfer processes, the patterned multilayer structure has a flat top surface, so that the mask on the fin structure is not easily broken during the etching process of the pattern transfer step. It is easy to transfer the pattern completely into the substrate to form a fin structure, which improves the process yield.

10‧‧‧Base

11‧‧‧Multilayer structure

12‧‧‧ top

13‧‧‧ bottom layer

14‧‧‧buffer layer

16‧‧‧Sacrificial material layer

18‧‧‧sacrificial pattern

20‧‧‧ spacer

21‧‧‧ patterned multi-layer structure

22‧‧‧ patterned top layer

23‧‧‧ patterned bottom layer

24‧‧‧ patterned buffer layer

26‧‧‧Fin structure

27‧‧‧The first shallow ditch

28‧‧‧Insulation

32‧‧‧ First shallow trench isolation

33‧‧‧Second shallow ditch

34‧‧‧Second shallow trench isolation

36‧‧‧Sacrificial material layer

42‧‧‧ photoresist layer

44‧‧‧ patterned photoresist layer

P1‧‧‧First flattening step

P2‧‧‧Second flattening step

S01~S11‧‧‧Steps

1 to 9 are schematic views showing a method of fabricating a fin structure according to a first preferred embodiment of the present invention.

Figure 10 is a top view of the structure of Figure 9.

Figure 11 is a flow chart showing the preparation of the first preferred embodiment of the present invention.

FIG. 12 is a schematic view showing a manufacturing method of a fin structure according to a second preferred embodiment of the present invention.

FIG. 13 is a schematic view showing a manufacturing method of a fin structure according to a third preferred embodiment of the present invention.

FIG. 14 is a schematic view showing a manufacturing method of a fin structure according to a fourth preferred embodiment of the present invention.

The present invention will be further understood by those of ordinary skill in the art to which the present invention pertains. .

For the convenience of description, the drawings of the present invention are only for the purpose of understanding the present invention, and the detailed proportions thereof can be adjusted according to the design requirements. As described in the text for the relative relationship between the relative elements in the figure, it should be understood by those skilled in the art that it refers to the relative position of the object, and therefore can be flipped to present the same member, which should belong to the same specification. The scope of the disclosure is hereby stated.

Please refer to Figure 1 to Figure 9, with reference to Figure 11. 1 to 9 are schematic views showing a method of fabricating a fin structure according to a first preferred embodiment of the present invention. Figure 11 is a corresponding preparation flow chart. As shown in FIG. 1 and FIG. 11, first, step S01 is performed to provide a substrate 10, such as a bulk silicon substrate or a silicon-on-insulator (SOI) substrate, and the like. A multilayer structure 11 is formed on the substrate 10 as a mask layer, wherein the multilayer structure 11 comprises at least two or more different materials. In this embodiment, the multilayer structure 11 includes a top layer 12 and a bottom layer 13 The formation can be done through a general deposition process. In addition, in the embodiment, between the multilayer structure 11 and the substrate 10, a buffer layer 14 is further selectively formed, which can be used as a protective layer of the protective substrate 10 in addition to being used as a mask layer in the subsequent pattern transfer process. . It should be noted that the layers of materials included in the multilayer structure 11 have different etching selectivity ratios. For example, the material of the top layer 12 in this embodiment is selected as yttrium oxide, and the material of the bottom layer 13 is selected as nitriding. Oh, so when the two are etched, the rate of etching is different. In addition, the buffer layer 14 is located between the multilayer structure 11 and the substrate 10, and the etching options are compared. Preferably, it is different from the adjacent bottom layer 13 to facilitate subsequent pattern transfer steps. Thereafter, at least one sacrificial material layer 16 is formed on the multilayer structure 11, which comprises a material having a different etching rate from the multilayer structure 11. In this embodiment, amorphous silicon or poly silicon is preferably used. It is easy to remove in the subsequent etching step, but is not limited thereto, and other suitable materials may be selected as the sacrificial material layer 16 in the present invention. In this embodiment, the height of the buffer layer 14 is preferably about 40 to 80 angstroms, the height of the bottom layer 13 is preferably about 300 to 500 angstroms, and the height of the top layer 12 is preferably about 200 to 400 angstroms, and the sacrificial material layer 16 The height is preferably about 800 to 1200 angstroms.

Next, in step S03, as shown in FIG. 2 and FIG. 11, a sacrificial material layer 16 is sequentially subjected to at least one exposure, development and etching step by a lithography etching step, and a portion of the sacrificial material layer 16 is removed to form a portion. At least one sacrificial pattern 18 is on the multilayer structure 11. The dimensions of the sacrificial patterns 18 are greater than or equal to the minimum exposure limit of the optical lithography. Step S05 is further performed. As shown in FIG. 3, at least one material layer (not shown) is formed to cover each sacrificial pattern 18 in a forward direction, and the composition may include a material having a different etching rate from the sacrificial pattern 18, such as nitrogen. A suitable material such as bismuth oxide, cerium oxide, cerium oxynitride or cerium carbide is used. In this embodiment, cerium nitride is selected as an example, but is not limited thereto. Then, the material layer is subjected to an etching step, such as a plasma etching process, to form a plurality of spacers 20 having a sail shape in the sidewalls of the sacrificial patterns 18, so that the spacers 20 have a smaller dimension than the optical lithography. Minimum exposure limit. Wherein, the minimum exposure limit is normal, and in the subsequent exposure process, the adjacent two patterns can be clearly distinguished and identified after exposure and development, and the minimum spacing allowed, for example, if the phase pattern The minimum exposure interval is about 118 nm. When the spacing between the two patterns is less than 118 nm, the two patterns may be joined together after the exposure and development steps of the two patterns. The material of the spacer 20 in this embodiment is tantalum nitride, which is the same as the bottom layer 13, but is not limited thereto. In addition, the sacrificial pattern 18 and the sacrificial material layer 16 have substantially the same height, about 800 to 1200 angstroms, and the spacer 20 has a height of about 800 to 1200 angstroms and a width of about 100 to 150 angstroms. However, it is not limited thereto, and the size of each component can be adjusted according to actual needs.

Next, step S07 is performed. As shown in FIGS. 4~5 and FIG. 11, the sacrificial pattern 18 is completely removed, and the remaining spacers 20 are used as a mask layer to perform a pattern transfer process on the multilayer structure 11 to The pattern of the spacers 20 is transferred into the multilayer structure 11 to form a plurality of corresponding patterned multilayer structures 21, and each of the patterned multilayer structures 21 includes a patterned top layer 22 and a patterned underlayer 23, respectively. In addition, since the buffer layer 14 has been formed between the multilayer structure 11 and the substrate 10 in this embodiment, the layout pattern is also transferred to the buffer layer 14 to form a plurality of patterned buffer layers 24. It should be noted that the pattern transfer process may include a plurality of etching steps. The preferred embodiment is described as follows. First, the sacrificial pattern 18 is removed by a general etching process (dry etching or wet etching), leaving only the spacers. 20 is on the multilayer structure 11. And the etching process does not etch the spacers 20. Next, one or more anisotropic etching processes are performed, and the spacers 20 are used as an etch mask to sequentially etch the multilayer structure 11 and the buffer layer 14 downward. At this point, the pattern defined by the spacers 20 can be transferred into the multilayer structure 11 and the buffer layer 14. In addition, since the etching step is performed multiple times, when the etching step proceeds to the underlayer 13 or the buffer layer 14, the upper sail-shaped spacer 20 may have been etched out or completely removed, thus In a preferred embodiment of the present invention, the thickness of the top layer 12 is thicker than that of the buffer layer 14 (the thickness of the top layer 12 is about 300 angstroms, and the thickness of the buffer layer 14 is about 40 to 80 angstroms), so that during the etching of the buffer layer 14, Even if the spacers 20 are removed by etching, the patterned top layer 22 remains partially, and serves as a mask to protect the underlying patterned underlayer 23 and the patterned buffer layer 24. It should be noted that the "pattern transfer process" referred to in the full text includes the concept of "sidewall pattern transfer process", that is, the "pattern transfer process" can be regarded as the "sidewall pattern transfer process". . It should be noted that because the buffer layer 14 is selectively formed in the present invention, the patterned buffer layer 24 may or may not be present between the substrate 10 and the patterned multilayer structure 21.

Next, proceeding to step S09, see FIGS. 6 and 11, to pattern the multilayer structure 21 as a mask layer, and performing another pattern transfer process to continue the pattern on the patterned multilayer structure 21 to the lower side. In the substrate 10, the removed portion of the substrate 10 forms a plurality of first shallow trenches 27, and at least one fin structure 26 is formed between the first shallow trenches 27 of the substrate 10. It should be noted that the patterned top layer 22 illustrated in FIG. 4 has been completely removed during the etching process in this step, and thus is not illustrated in FIG. 6, but the invention is not limited thereto, and is patterned. The top layer 22 may be adjusted due to actual needs, and there is still some residue, which is also within the scope of the present invention. In addition, the pattern transfer process herein is the same as the above steps, and may include one or more etching steps, and details are not described herein again.

Step S11 is further performed, and at the same time, referring to FIGS. 7-9 and FIG. 11, a plurality of shallow trenches are formed to be isolated in the substrate 10. The steps are described as follows: As shown in FIG. 7, after the fin structures 26 are completed, a plurality of first shallow trenches 27 are formed in the substrate 10 next to the fin structures 26, and then an insulating layer 28 is filled in the first A shallow trench 27 is partially covered on top of the fin structure 26. The insulating layer 28 is made of, for example, tantalum oxide or tantalum nitride to isolate telecommunications interference between the components. A planarization step P1 is then performed, such as a chemical-mechanical polishing, to planarize and remove excess insulating layer 28. It should be noted that the surface of the planarization step P1 may stay on the patterned underlayer 23, the patterned buffer layer 24 or the fin structure 26, that is, when the planarization step P1 is performed, the depth of the polishing may be selected until exposed. The patterned bottom layer 23, the patterned buffer layer 24 or even the fin structure 26 is used. Since the spacer 20 having the shape of a sailboat has been completely etched away in the etching process described above, and the patterned top layer 22 of the present invention can serve as a mask to protect the underlying patterned underlayer 23 and the patterned buffer layer 24, the patterning is performed. The bottom layer 23, the patterned buffer layer 24 or the fin structure 26 all have a flat top surface, so when the planarization step P1 is performed, the polishing is easier to stop at the top of the components, and there is no remaining spacer 20 A source of particles is formed during the grinding process resulting in scratches. In this embodiment, it is preferred to stop at the top of the patterned buffer layer 24 to reach To protect the function of the fin structure 26.

Then, as shown in FIG. 8, the etching buffer layer 24 remaining on the top of the fin structure 26 is removed by an etching process, such as a SiCoNi process, which is a cleaning process containing nitrogen trifluoride and ammonia, or A wet etching process using dilute Hydrofluoric Acid (DHF) is used to expose the top of the fin structure 26, and an etching back process is used to further remove portions of the insulating layer 28, such that A portion of the sidewall of the fin structure 26 is exposed and a plurality of first shallow trench isolations 32 are completed to isolate the respective fin structures 26. In this embodiment, the height of the first shallow trench isolation 32 is about 1000 angstroms, and the top width of the fin structure 26 is labeled W1, and in the embodiment, it is about 100 angstroms, and the height of the side exposed surface is labeled W2. The embodiment is about 300 angstroms. Of course, the present invention is not limited thereto. The height of the first shallow trench isolation 32, the width and height of the fin structure can be adjusted according to actual needs. The width and height exposed by the fin structure 26 will determine the channel width of the subsequent fin-shaped transistor. For example, a tri-gate fin-FET is formed by subsequently forming the fin structure. The channel width of the gate fin transistor is W1+W2+W2, and a cap layer (not shown) may be additionally covered or the patterned buffer layer 24 remaining on the surface of the fin structure 26 may not be removed. It is also within the scope of the present invention to form the fin structure 26 into a double-gate fin-FET in a subsequent step.

In a preferred embodiment of the present invention, as shown in FIG. 9, another etching step is performed to form at least one second shallow trench 33 in the substrate 10 and the insulating layer 28, and then filled in another insulating layer ( The second shallow trenches 33 are filled and covered on the fin structures 26, and then a second planarization step P2 is performed, for example, the same chemical mechanical polishing process as the first planarization step P1. The excess insulating layer is removed to complete at least one second shallow trench isolation 34. The second shallow trench isolation 34 preferably surrounds each of the fin structures 26 and the first shallow trench isolation 32, but is not limited thereto. It should be noted that the depth of the second shallow trench isolation 34 in the embodiment is preferably greater than the first The shallow trench isolation 32 is approximately 2000-2500 angstroms to more effectively isolate the components formed in the subsequent steps, but is not limited thereto, and the depth of the second shallow trench isolation 34 may also be isolated from the first shallow trench in the present invention. 32 is the same or shallower and is also within the scope of the present invention. Finally, an etching process can be performed again to partially expose the fin structures 26 to complete the fin structure manufacturing method of the present invention. The fin structure formed by the present invention can be subsequently matched with other related semiconductor processes, for example, Fin-like transistors and the like, since the fin-shaped transistor process is not the main technical feature of the present invention, it will not be described herein for the sake of brevity.

It should be noted that the second shallow trench isolation 34 of the present invention can achieve the function of slot-cut. Please refer to FIG. 3 to FIG. 10, and FIG. 10 is a structural upper view of FIG. More specifically explained as follows: Since the present invention performs the pattern transfer step with the spacers 20 as a mask, the spacers 20 may appear to surround the sacrificial pattern 18 from the top view, resulting in the pattern transfer step being completed and formed on the substrate. The fin structure 26 on the upper 10 also appears to have a ring shape from the top view. In order to fabricate the subsequent fin-shaped transistor, the annular fin structure 26 is preferably divided into a plurality of elongated strips separated from each other. Fin structure 26. In order to achieve the above purpose, when the second shallow trench isolation 34 is formed, the first shallow trench 33 formed first can partially remove part of the fin structure 26, especially the interconnected partial fin structure at both ends (10th) In the figure, the removed partial fin structure 26 is indicated by a broken line. After the removal, the end of the fin structure 26 is cut, and the fin structures 26 are elongated strips that do not contact each other, as shown in FIG. It is shown that the second shallow trench isolation 34 surrounds the outer side of the fin structure 26 and the first shallow trench isolation 32 to achieve a better electrical isolation effect and to properly cut the pattern of the fin structure 26.

In the first preferred embodiment of the present invention, referring to FIG. 7 to FIG. 9 , after the first shallow trench 27 is formed, the insulating layer 28 is filled in and the first planarization step P1 is performed to complete the plurality of stages. A shallow trench isolation 32, after which at least a second shallow trench 33 is formed and filled in the insulating layer, and a second planarization step P2 is performed to complete at least one second shallow trench isolation 34. But the invention The manufacturing process is not limited thereto. In the second preferred embodiment of the present invention, the step of forming the fin structure 26 is the same as that of the first preferred embodiment (please refer to the first to sixth figures), and then refer to the 12, the first shallow groove 27 and the second shallow groove 33 may be formed first (in which the order of formation of the first shallow groove 27 and the second shallow groove 33 may be arbitrarily adjusted), and then simultaneously in the first shallow groove 27 and The second shallow trench 33 is filled with an insulating layer, and then only one planarization step is performed to remove the excess insulating layer, and the first shallow trench isolation 32 and the second shallow trench isolation 34 are completed, and finally an etching process is performed. Exposed part of each fin structure (the completed structure is the same as Fig. 9). The production process is also within the scope of the present invention. The remaining steps and materials are the same as the first preferred embodiment of the present invention, and details are not described herein again. It should be noted that, in this embodiment, if the first shallow groove 27 is formed after the first shallow groove 27 is formed, the second shallow groove 33 may be selectively formed after the first shallow groove 27 is completed, before the second shallow groove 33 is formed. A shallow trench 27 is filled with a sacrificial material layer 36 to protect the interior of the first shallow trench 27 from being damaged during subsequent etching. The sacrificial material layer 36 may be an insulating layer such as tantalum nitride or tantalum oxide. Or, or an adhesive layer, to improve the adhesion between the subsequent substrate 10 and the insulating layer 28.

In the third preferred embodiment of the present invention, the step of forming the fin structure 26 is the same as that of the first preferred embodiment (please refer to the first to sixth figures), and then refer to FIG. 13, a photoresist layer. 42 is formed on the substrate 10, and fills each of the first shallow trenches 27, and then performs an exposure development process and an etching process on the photoresist layer 42 to remove a portion of the photoresist layer 42 and the remaining photoresist layer. In the 42-covered substrate 10, at least one second shallow trench 33 is formed, and then the remaining photoresist layer 42 is removed, and then an insulating layer is filled in the first shallow trench 27 and the second shallow trench 33, respectively. Performing a planarization step to remove the excess insulating layer while completing the first shallow trench isolation 32 and the second shallow trench isolation 34, and finally performing an etching process to expose portions of the fin structure (completed structure and ninth) The figure is the same). The production process is also within the scope of the present invention. The remaining steps and materials are the same as the first preferred embodiment of the present invention, and details are not described herein again.

In the fourth preferred embodiment of the present invention, the step of forming the fin structure 26 is the same as that of the first preferred embodiment (please refer to the first to sixth figures), and then fills in an insulating layer 28 for each first. In the shallow trench 27, a first planarization step P1 is performed (please refer to FIG. 7 above), and then, as shown in FIG. 14, a patterned photoresist layer 44 is formed on the top end of the insulating layer 28, and patterned. The photoresist layer 44 is used as a mask layer to perform an etching process, removing a portion of the insulating layer 28 and a portion of the substrate 10, forming at least one second shallow trench 33 in the substrate 10, and then removing the patterned photoresist layer 44. The second shallow trench 33 is further filled with another insulating layer (not shown) to fill each of the second shallow trenches 33, and then another planarization step (not shown) is performed, for example, with the first planarization step. The same chemical mechanical polishing step of P1 removes the excess insulating layer and completes at least one second shallow trench isolation 34. Finally, an etching process is performed to expose some of the fin structures (the completed structure is the same as in FIG. 9). The production process is also within the scope of the present invention. The remaining steps and materials are the same as the first preferred embodiment of the present invention, and details are not described herein again.

The present invention utilizes the sidewall pattern transfer technique to perform a pattern transfer process. Generally, the sidewall pattern transfer technique is generally implemented by forming a plurality of sacrificial patterns on a substrate, and the scales of the sacrificial patterns are greater than the minimum exposure of the optical lithography. limit. A spacer is then formed on the sidewalls of the sacrificial pattern by a deposition and etching process. Since the dimension of the spacer is smaller than the exposure limit of the optical lithography, the spacer can be utilized as a mask for etching the substrate, and the pattern of the spacer is further transferred into the substrate. The present invention is characterized in that the present invention further comprises a multi-layer structure between the substrate and the spacer, first using the spacer as a mask, performing a pattern transfer process, transferring the pattern to a multi-layer structure, and using the multi-layer structure as The mask performs another pattern transfer process, and the pattern is transferred to the substrate to form a plurality of fin structures in the substrate. In this way, after two or more pattern transfer processes, the patterned multilayer structure has a flat top surface, so that the mask on the fin structure is not easily broken during the etching process of the pattern transfer step. It is easy to transfer the pattern completely into the substrate to form a fin structure, which improves the process yield.

S01~S11‧‧‧Steps

Claims (14)

A method for fabricating a fin structure includes: forming a multilayer structure on a substrate; forming a sacrificial pattern on the multi-layer structure; forming a spacer on a side of the sacrificial pattern, and located on the multi-layer structure; Removing the sacrificial pattern; using the spacer as a mask to etch the portion of the multi-layer structure, and then using the multi-layer structure as a mask to etch the portion to form at least one fin structure and at least one in the substrate a shallow trench; and after the first shallow trench is formed, another etching step is performed to form at least one second shallow trench in the substrate, wherein the second shallow trench has a depth deeper than each of the first shallow trenches. The method of claim 1, wherein the multilayer structure comprises a plurality of layers of material, and each layer of materials has a different etching selectivity ratio to each other. The method of claim 2, wherein at least one of the plurality of layers of material is the same as the spacer. The method of claim 1, wherein the multilayer structure comprises at least a tantalum nitride layer and a tantalum oxide layer stacked on the tantalum nitride layer. The method of claim 1, further comprising forming a buffer layer between the multilayer structure and the substrate. The method of claim 5, wherein the buffer layer comprises cerium oxide. The method of claim 1, further comprising: forming the first shallow trench in the substrate; filling a first insulating layer in each of the first shallow trenches; and performing a first insulating layer on the first insulating layer a planarizing step; forming the second shallow trench in the substrate, wherein the second shallow trench has a depth deeper than each of the first shallow trenches; and filling a second insulating layer in each of the second shallow trenches; Another planarization step is performed on the second insulating layer. The method of claim 7, wherein a portion of the fin structure is removed when each of the second shallow trenches is formed. The method of claim 7, wherein the first planarization step is stopped in the multilayer structure. A method for fabricating a fin structure includes: forming a multilayer structure on a substrate; forming a sacrificial pattern on the multi-layer structure; forming a spacer on a side of the sacrificial pattern, and located on the multi-layer structure; Removing the sacrificial pattern; using the spacer as a mask to etch the portion of the multilayer structure, and then using the multilayer structure as a mask to etch the portion to form at least one fin structure in the substrate; forming at least one a first shallow trench is formed in the substrate; at least one second shallow trench is formed in the substrate, wherein the second shallow trench has a depth deeper than each of the first shallow trenches; and an insulating layer is filled in each of the first shallow a trench and each of the second shallow trenches; and performing a planarization step on the insulating layer. The method of claim 10, wherein a portion of the fin structure is removed when each of the second shallow trenches is formed. The method of claim 10, wherein before forming each of the second shallow trenches, further comprising filling a layer of sacrificial material in each of the first shallow trenches. The method of claim 10, wherein the performing the planarizing step further comprises performing an etching process on the insulating layer and partially exposing each of the fin structures. The method of claim 10, wherein the sacrificial pattern comprises amorphous germanium or polycrystalline germanium.