TWI570700B - Display device and method for driving the same - Google Patents

Description

Display device and driving method thereof

The present invention relates to a display device and a method of driving the same.

As the resolution of a liquid crystal display (LCD) increases, the gate lines are correspondingly increased to control corresponding pixels in the liquid crystal display panel. However, since the number of gate lines is increased, the opening time of each gate line can be shortened, the charging time for the pixels is reduced, and the load of the active area in the liquid crystal display panel is increased, so that the pixels cannot be fully charged or mischarged. Causes the display quality to drop or display abnormality.

As described above, please refer to FIG. 1 , which is a schematic diagram showing the structure of the liquid crystal display panel. In FIG. 1, the active matrix region 104 has four regions A, B, C, and D, wherein the A region is the closest to the driver output starting point, and the first data signal and the gate signal are received, and the B region is the distance source driver. The far end of 102, the C area is the end farther from the gate driver 103, and the D area is far from the gate driver 103 and far from the source driver 102. When the source driver 102 of the liquid crystal panel sequentially outputs the data signals from the A region to the B region of the active matrix region 104, the RC load causes a delay effect of the data signal at the end B region farther from the source driver 102, resulting in a delay effect. The display is undercharged. When the gate driver 103 outputs the gate signal from the A region to the C region of the active matrix region 104, the gate signal is also turned off due to the RC load causing the gate signal to be affected from the farther C region of the gate driver 103. Incomplete charging occurs due to incompleteness, resulting in a wrong color gradation. In the large-sized display panel, the problem that the D-zone display quality of the active matrix region 104 is degraded or displayed abnormally is more conspicuous.

In order to solve the above problems, the related art has not exhausted its efforts to seek a solution, and an object of the present invention is to provide a display device and a driving method thereof, thereby improving the problems existing in the prior art.

SUMMARY OF THE INVENTION The Summary of the Disclosure is intended to provide a basic understanding of the present disclosure. This Summary is not an extensive overview of the disclosure, and is not intended to be an

One aspect of the present invention relates to a display device driving method, wherein the display device includes a source driver, a gate driver, and an active array region, and the driving method includes sequentially providing a plurality of source start signals to the source. The driver is configured to control the source driver to sequentially output the complex data signal to the active array region; and sequentially provide the plurality of gate-level enable signal pulse to the gate driver for controlling the gate driver to sequentially output the plurality of gate signals to Active array area; wherein the period of the source start signal pulse is gradually lengthened.

According to another embodiment of the present invention, the period of the gate-enable signal pulse in the driving method is gradually lengthened.

According to another embodiment of the present invention, the period of each of the gate-enable signal pulses includes a period of a working pulse period and a period of a cut-off pulse wave, wherein each of the working pulse periods is substantially the same for controlling each of the gate signals to have The substantially identical signal enable time, and wherein the Nth cutoff pulse period is greater than the (N-1)th cutoff period, N is the number of gate lines and is a positive integer greater than one.

According to another embodiment of the present invention, the Nth cutoff pulse period in the gate enable signal pulse has a relationship with the (N-1) cut pulse period: the Nth cutoff period = (2) /(N+1))* The (N-1)th cutoff period, where N is the number of gate lines.

According to still another embodiment of the present invention, in the driving method, the period of the source start signal pulse wave and the period of the gate enable signal pulse wave have a sequential one-to-one correspondence relationship.

In order to achieve the above object, still another aspect of the present invention relates to a display device. The foregoing display device includes a source driver, a gate driver and a timing controller. The source driver is electrically connected to the plurality of data lines, and the gate driver is electrically connected to the plurality of gate lines. The timing controller sequentially outputs the complex source start signal pulse wave to the source driver and sequentially outputs the complex gate enable signal pulse wave to the gate driver. The gate driver sequentially outputs the plurality of gate signals to the gate line according to the gate-enable signal pulse wave, and the source driver sequentially outputs the plurality of data signal enable data lines according to the source start signal pulse wave, and The timing controller includes a source start signal pulse wave control component to gradually increase the period of the source start signal pulse wave.

According to another embodiment of the present invention, the timing controller further includes a gate enable signal pulse wave control component to control the period of the gate enable signal pulse to be gradually lengthened.

According to another embodiment of the present invention, the period of each gate enable signal pulse outputted by the timing controller includes a working pulse period and a cutoff pulse period, wherein each working pulse period is substantially the same for controlling each The gate signal has substantially the same signal enable time, and wherein the Nth cutoff pulse period is greater than the (N-1)th cutoff period, and N is the number of gate lines and is a positive integer greater than one.

According to another embodiment of the present invention, the Nth cutoff pulse period in the gate enable signal pulse outputted by the timing controller has a relationship with the (N-1) cutoff pulse period: the Nth cutoff pulse Wave period = (2 / (N + 1)) * (N - 1) cutoff pulse period, where N is the number of gate lines.

According to still another embodiment of the present invention, in the display device, the period of the source start signal pulse wave and the period of the gate enable signal pulse wave have a sequential one-to-one correspondence relationship.

Therefore, according to the technical content of the present invention, an embodiment of the present invention provides a display device and a driving method thereof, thereby improving the problem of data mischarge caused by a transmission delay due to a transmission delay, and improving the data signal level to cause charging. Insufficient phenomenon.

The basic spirit and other objects of the present invention, as well as the technical means and implementations of the present invention, will be readily apparent to those skilled in the art of the invention.

The description of the embodiments of the present invention is intended to be illustrative and not restrictive. The features of various specific embodiments, as well as the method steps and sequences thereof, are constructed and manipulated in the embodiments. However, other specific embodiments may be utilized to achieve the same or equivalent function and sequence of steps.

The scientific and technical terms used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the invention pertains, unless otherwise defined herein. In addition, the singular noun used in this specification covers the plural of the noun in the case of no conflict with the context; the plural noun of the noun is also included in the plural noun used.

In order to improve the delay effect caused by the internal RC load of the display device, the data signal is undercharged or mischarged. The display device and the driving method thereof are used to adjust the driving mode of the data signal, so as to reduce the insufficient integrity of the remote pixel data signal in the panel, and the display screen color gradation error causes a bright dark line problem. The contents of the display device and the driving method thereof according to the present invention will be described in detail in the following embodiments.

As shown in FIG. 2, the source start signal pulse (STB) is used to control the output time (t1) of each data signal to determine the length of each data signal (Data) charging time. However, when the opening time of the gate enable signal pulse (OE) control gate line is insufficient, that is, the working pulse period (t2) is too short, the data signal voltage has not been charged to the ideal level, and the gate is enabled to signal the pulse. The wave (OE) controls the gate line to enter the off state, that is, enters the cutoff pulse period (t3), resulting in insufficient charging of the data signal as shown by the solid line frame 201 in FIG. 2, thereby making the output data signal level incorrect. , causing the displayed gradation error.

In order to solve the above problem of insufficient charging, another driving method is proposed as shown in FIG. 3, in which the working pulse period (t2) of the gate enable signal pulse (OE) is extended to avoid insufficient gate opening time. The nth gate signal farther away from the gate driver (G turns on the nth gate line, but the RC load delay relationship and the cutoff pulse period (t3) time are too short, so that the nth gate line has not yet been Close completely, the n+1th gate signal (G That is, the n+1th gate line is controlled to be continuously turned on, so that the pixel on the nth gate line is incorrectly charged to the data signal received by the pixel on the n+1th gate line (Data). The voltage causes a mischarge phenomenon as shown by the solid line frame 301 in Fig. 3, so that the gradation is displayed. In order to increase the time required for the gate enable signal pulse (OE), the cutoff pulse period (t3) is compressed when the data signal output time (t1) is fixed, and there is still room for improvement in this driving mode.

The present invention further provides a driving method of an embodiment to solve the above-mentioned undercharge and mischarge phenomenon and can be performed by the architecture of the display device shown in FIG. 1. However, the driving method is not limited to the components of the display device. The following examples are merely illustrative of one of the implementations of the present invention. Referring to FIG. 1 and FIG. 4 , the liquid crystal display panel architecture of FIG. 1 includes a timing controller 101 , a source driver 102 , a gate driver 103 , and an active matrix region 104 , including N gate lines 109 and M data lines 108 . And a plurality of pixels arranged in a matrix. The timing controller 101 outputs the signals 105, 106 to the source driver 102 and outputs the signal 107 to the gate driver 103. The signal 105 is the data signal (Data) shown in FIG. 4, the signal 106 is the source start signal pulse (STB) shown in FIG. 4, and the signal 107 is the gate enable signal pulse (OE shown in FIG. ), wherein the source start signal pulse (STB) and the gate enable signal pulse (OE) have the same cycle time length. The gate driver 103 sequentially outputs the gate signal according to the gate enable signal pulse (OE) to turn on the corresponding gate line 109, and the source driver 102 sequentially outputs the plurality of data according to the source start signal pulse (STB). The signal (Data) to the plurality of data lines 108 are used to sequentially write the data signal (Data) into the pixels corresponding to the gate line in the active matrix area 104 to display the desired picture.

In detail, the timing controller 101 controls the data signal latching time of the pixels in each of the turned-on gate lines by the data signal output time (t1) of the source start signal pulse (STB). In addition, the timing controller 101 also sends a gate enable signal pulse (OE), and the period of each gate enable signal pulse (OE) includes a working pulse period (t2) and a cutoff pulse period (t3). During each working pulse period (t2), the gate driver 103 outputs a gate signal to turn on the on or enable time of a column of pixels corresponding to a gate line 109, so that the data signal can be written or displayed on the data signal (Data). a row of pixels corresponding to the active matrix region 104, wherein each of the working pulse waves (t2) in a gate or frame period gate enable signal pulse (OE) is fixed for a sufficient length of time Charging the data signals required by the pixels to the required voltage level, and gradually increasing the period of each source start signal pulse (STB) cycle time, and thus transmitting the distance to the source matrix 104 The data signal output time (t1) of the pixel on the gate of the remote end of the driver 102 is increased. For example, the source start signal pulse (STB) period of the B region of the active matrix region 104 is greater than the source start signal of the A region. Pulse wave (STB) period, that is, source start signal pulse (STB) data signal output time t1 (N) is greater than source start signal pulse (STB) data signal output time t1 (N-1), source The initial start signal pulse (STB) data signal output time t1 (N-1) is greater than the source start signal pulse (STB) Data signal output time t1 (N-2), ... source start signal pulse (STB) data signal output time t1 (2) is greater than the source start signal pulse (STB) data signal output time t1 (1) To avoid the shortage of remote data signal (Data) due to RC loading effect.

In addition, as each source start signal pulse (STB) period is gradually lengthened, the data length (Data) latching time of the remote column number is controlled to prevent the remote data signal from being undercharged due to the RC load. . In the case that the working pulse period (t2) of the gate enable signal pulse (OE) is fixed and long enough, the opening time of the gate line 109 is constant, but the closing time of the corresponding gate line 109 is prolonged. The period of the cutoff pulse period (t3(2)) of the second gate line 109 is made larger than the period of the cutoff pulse wave of the first gate line 109 (t3(1)), and the last line can be seen from FIG. The off-pulse period (t3(N)) of the gate line 109 will be the longest, during which the N-th cutoff pulse in the complex gate pulse wave (OE) of a picture or frame period (frame) is The (N-1)th cutoff pulse period has the following relationship: the Nth cutoff pulse period = (2/(N+1))* (N-1) cutoff pulse period, thereby solving the far end The problem that the gate line 109 is incompletely closed due to the possible RC effect can be solved, and the problem of mischarge can also be improved.

Therefore, the driving method of the display device proposed in the present invention comprises sequentially providing a plurality of source start signal pulse waves and a data signal to the source driver by a timing controller, wherein the source start signal pulse wave is used to control the output of the data signal. Time, and the period length of the complex source start signal pulse wave has an increasing trend, and the timing controller sequentially supplies the gate enable signal pulse wave to the gate driver, and the gate driver sequentially according to the gate enable signal pulse wave A gate signal is provided to the corresponding gate line, and the source driver provides a plurality of data signals according to the source start signal pulse wave to the plurality of data lines connected to the pixels on the corresponding open gate line. Wherein, the period of each gate-enable signal pulse wave includes a period of the working pulse wave period and the cut-off pulse wave period, and the plurality of gate pulse-enable pulse waves during the frame period are the same or fixed during the complex working pulse wave period, and the gate is The length of time during the complex cut-off pulse of the ultimate signal pulse is longer and longer, so that the remote data signal (Data) undercharge or mischarge caused by the RC load effect is improved.

Although the embodiments of the present invention are disclosed in the above embodiments, the present invention is not intended to limit the invention, and the present invention may be practiced without departing from the spirit and scope of the invention. Various changes and modifications may be made thereto, and the scope of the invention is defined by the scope of the appended claims.

101‧‧‧ timing controller
102‧‧‧Source Driver
103‧‧‧gate driver
104‧‧‧Active Matrix Area
105, STB‧‧‧ source start signal pulse wave
106, Data‧‧‧ data signal
107, OE‧‧‧ gate enable signal pulse
108‧‧‧Information line
109‧‧‧ gate line
201‧‧‧Insufficient charging
301‧‧‧ Mistakes
G‧‧‧第nth gate signal
G‧‧‧第n+1 gate signal
T1, t1(1)~t1(N)‧‧‧ data signal output time
t2‧‧‧Working pulse period
T3, t3 (1) ~ t3 (N) ‧ ‧ cut-off pulse period

The above and other objects, features, advantages and embodiments of the present invention will become more <RTIgt; FIG. 2 is a schematic diagram showing a driving waveform of insufficient charging. FIG. 3 is a schematic diagram showing a driving waveform of a gate line being incompletely closed. 4 is a schematic diagram showing driving waveforms of an embodiment of the present invention.

STB‧‧‧ source start signal pulse

OE‧‧‧gate enable signal pulse

Data‧‧‧Information Signal

T1(1)‧‧‧data signal output time

T1(2)‧‧‧data signal output time

T1(M)‧‧‧data signal output time

t2‧‧‧Working pulse period

T3(1)‧‧‧During the pulse period

T3(2)‧‧‧During the pulse period

T3 (N) ‧ ‧ cut-off pulse period

Claims (10)

A driving method for driving a display device, the display device comprising a source driver, a gate driver and an active array region, the driving method comprising the steps of: sequentially providing a plurality of source start signal pulses to the a source driver for controlling the source driver to sequentially output a plurality of data signals to the active array region; and sequentially providing a plurality of gate-level enable signal pulses to the gate driver for controlling the gate driver sequentially And outputting a plurality of gate signals to the active array region; wherein each of the source start signal pulses has a working pulse period and a cut pulse period, the source pulse of the source start signal pulse The lengths of the wave periods are the same, and the lengths of the pulse cutoff periods of the different source start signal pulses are gradually increased according to different source start signal pulse waves. The driving method of claim 1, wherein the periods of the gate-enable signal pulses are gradually lengthened. The driving method of claim 2, wherein the period of each of the gate-enable signal pulses comprises a working pulse period and a cut-off pulse period, wherein each of the working pulse periods is substantially the same, The method is configured to control each of the gate signals to have substantially the same signal enable time, and wherein one of the Nth cutoff pulse periods is greater than a (N-1)th cutoff period, and N is the number of gate lines and Is a positive integer greater than one. The driving method of claim 3, wherein the Nth cutoff pulse period of the gate enable signal pulses has the following relationship with the (N-1) cutoff pulse period: an Nth cutoff Pulse period = (2 / (N + 1)) * (N - 1) cut-off pulse period, where N is the number of gate lines. The driving method of claim 2, wherein the periods of the source start signal pulses have a sequential and one-to-one correspondence with the periods of the gate enable signal pulses. A display device includes: a source driver electrically connecting a plurality of data lines; a gate driver electrically connecting the plurality of gate lines; and a timing controller for sequentially outputting the plurality of source start signal pulses And outputting a plurality of gate-enable pulse signals to the gate driver in sequence; wherein the gate driver is configured to sequentially output the plurality of gate signals to the gates according to the gate-enable signal pulses a line, and the source driver is configured to sequentially output the plurality of data signals according to the source start signal pulses to enable the data lines, and wherein each of the source start signal pulses has a working pulse During a period and a cutoff pulse period, the timing controller includes a source start signal pulse wave control component for controlling the length of the working pulse wave of the different source start signal pulse waves, the source The length of the pulse wave cut-off period of the start signal pulse control component for controlling the different source start signal pulse waves is gradually increased according to different source start signal pulse waves. The display device of claim 6, wherein the timing controller further comprises a gate enable signal pulse wave control component for controlling the periods of the gate enable signal pulses to be gradually lengthened. The display device of claim 7, wherein the period of each of the gate-enable signal pulses output by the timing controller comprises a working pulse period and a cut-off pulse period, wherein each of the working pulses The period is essentially the same, which is used to control each of these gate signals. The same signal enable time, and one of the Nth cutoff pulse periods is greater than one (N-1) cutoff pulse period, and N is the number of gate lines and is a positive integer greater than 1. The display device according to claim 8, wherein the Nth cutoff pulse period in the gate enable signal pulse wave output by the timing controller has the following relationship with the (N-1) cutoff pulse period : Nth cutoff pulse period = (2 / (N + 1)) * (N - 1) cutoff pulse period, where N is the number of gate lines. The display device of claim 7, wherein the periods of the source start signal pulses have a sequential one-to-one correspondence with the periods of the gate enable signal pulses.