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TWI567840B - Fabrication process and its welding method - Google Patents

Fabrication process and its welding method Download PDF

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Publication number
TWI567840B
TWI567840B TW104114120A TW104114120A TWI567840B TW I567840 B TWI567840 B TW I567840B TW 104114120 A TW104114120 A TW 104114120A TW 104114120 A TW104114120 A TW 104114120A TW I567840 B TWI567840 B TW I567840B
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Taiwan
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flip chip
wafer
primer
flux
circuit substrate
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TW104114120A
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Chinese (zh)
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TW201639049A (en
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shu-hui Hong
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector

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  • Wire Bonding (AREA)

Description

覆晶封裝製程及其焊接方法 Flip chip packaging process and welding method thereof

本發明係屬覆晶封裝的技術領域,尤指其技術上提供一覆晶封裝製程及其焊接方法,透過3D陣列噴嘴列印裝置精確地控制助焊劑之噴覆範圍及噴覆劑量,始能盡量降低經過金屬熔接後所殘留助焊劑的量,輔以耐壓艙對殘存有限的助焊劑進行處裡,使助焊劑能加速溶解於底膠之中而無須進行溶劑沖洗等清除助焊劑殘渣作業,有效簡化覆晶封裝製程,大幅度提高了生產效率。 The invention belongs to the technical field of flip chip packaging, in particular to providing a flip chip packaging process and a soldering method thereof, and precisely controlling the spraying range and the spraying dose of the flux through the 3D array nozzle printing device. Minimize the amount of flux remaining after metal welding, supplemented by a pressure tank to keep a limited amount of flux, so that the flux can be accelerated in the primer without solvent flushing and other flux removal. It effectively simplifies the flip chip packaging process and greatly improves production efficiency.

在科技日新月異的世代,高科技電子技術相繼問世,使得更人性化、功能更佳的電子產品不斷地推陳出新,並朝向輕、薄、短、小的趨勢設計。為達成上述的要求,必須滿足電子元件的高速處理化、多功能化、積集化、小型輕量化及低價化等多方面的要求,為此積體電路封裝技術也跟著朝向微型化、高密度化發展。在各種封裝技術中,覆晶構裝(Flip Chip package,F/C package)與其他採用凸塊(bump)或焊球(solder ball)進行電性連接之高密度積體電路封裝技術,由於可縮短配線長度並進而提昇訊號傳遞速度,因此已逐漸成為高密度封裝的主流。 In the ever-changing generation of technology, high-tech electronic technology has come out one after another, making more humanized and functional electronic products constantly innovating and designing towards light, thin, short and small trends. In order to achieve the above requirements, it is necessary to meet the requirements of high-speed processing, multi-function, integration, small size, light weight, and low cost of electronic components. Therefore, the integrated circuit packaging technology is also becoming miniaturized and high. Density development. Among various packaging technologies, the Flip Chip package (F/C package) and other high-density integrated circuit packaging technologies that are electrically connected by bumps or solder balls are available. Shortening the wiring length and thus the signal transmission speed has gradually become the mainstream of high-density packaging.

參閱第1圖所示為習知覆晶封裝製程的流程圖,其步驟包括:a.(步驟101)製備一晶片,該晶片設有一主動表面,該主動表面上設置複數個導電凸塊。b.(步驟102)製備一線路基板,其中該線路基板設有一承載表面,該承載表面上對應於各該導電凸塊分別配置一焊墊。 Referring to FIG. 1 , a flow chart of a conventional flip chip packaging process includes the steps of: a. (Step 101) preparing a wafer having an active surface on which a plurality of conductive bumps are disposed. b. (Step 102) A circuit substrate is prepared, wherein the circuit substrate is provided with a bearing surface, and a bonding pad is disposed on each of the conductive bumps.

c.(步驟103)在線路基板之承載表面上填加助焊劑,並使各該導電凸塊及焊墊表面沾浸助焊劑(Flux Dipping)。d.(步驟104)將晶片翻覆(Flip Chip)並對位,以使晶片之主動表面朝向線路基板之承載表面配置,並使各該導電凸塊分別經由助焊劑之輔助良好接合各該焊墊,接續進行一迴焊(Reflow Soldering)作業,以製成一覆晶封裝結構,使線路基板與晶片之間可進行訊號的傳輸。 c. (Step 103) Filling the bearing surface of the circuit substrate with flux, and immersing each of the conductive bumps and the pad surface with Flux Dipping. d. (Step 104) Flip Chip and position the wafer so that the active surface of the wafer is disposed toward the bearing surface of the circuit substrate, and each of the conductive bumps is respectively bonded to each of the pads by the aid of a flux. Then, a reflow soldering operation is performed to form a flip chip package structure, so that signal transmission can be performed between the circuit substrate and the wafer.

e.(步驟105),進行清除助焊劑殘渣(Flux Residue)作業。使用 助焊劑進行迴焊作業後所殘留之助焊劑會與周圍物質發生反應而造成腐蝕結果,故需進行清除助焊劑殘渣作業,以除去殘留的助焊劑,而避免以後該覆晶封裝結構受到腐蝕,其執行過程為:(e1)藉由噴灑以溶劑沖洗該覆晶封裝結構上殘留的助焊劑。(e2)對該覆晶封裝結構再執行一沖洗程序,例如使用去離子水(deionized water)進行沖洗。(e3)對該覆晶封裝結構執行一乾燥程序,例如使用一離心裝置,利用離心力將殘留的去離子水脫除,或使用一烘烤裝置,利用高溫烘烤將殘留的去離子水蒸發去除。 e. (Step 105), performing flux removal (Flux Residue) operation. use The flux remaining after the flux is reflowed will react with the surrounding materials to cause corrosion. Therefore, it is necessary to remove the flux residue to remove the residual flux, so as to avoid corrosion of the flip chip package structure in the future. The execution process is: (e1) rinsing the flux remaining on the flip chip package structure by spraying with a solvent. (e2) Performing a further rinsing procedure on the flip chip package structure, for example, using deionized water for rinsing. (e3) performing a drying process on the flip chip package structure, for example, using a centrifugal device to remove residual deionized water by centrifugal force, or using a baking device to evaporate residual deionized water by high temperature baking. .

f.(步驟106),對該覆晶封裝結構執行一電漿清潔作業,藉以改善覆晶封裝結構表面的潔淨度及潤溼性,有效提升下一步驟中底膠(例如環氧樹酯)的填充性,減少氣泡產生。 f. (Step 106), performing a plasma cleaning operation on the flip chip package structure, thereby improving the cleanliness and wettability of the surface of the flip chip package structure, and effectively improving the primer (eg, epoxy resin) in the next step. The filling is done to reduce bubble generation.

g.(步驟107),利用一點膠工具進行填膠程序,填充一底膠於晶片與線路基板之間。 g. (Step 107), using a glue tool to perform a glue filling process, filling a primer between the wafer and the circuit substrate.

h.(步驟108),將完成填膠程序之覆晶封裝結構移入一烤箱內,對該底膠進行加熱固化程序使其完全固化。 h. (Step 108), the flip chip package structure that completes the glue filling process is moved into an oven, and the primer is subjected to a heat curing process to completely cure.

前述,在步驟104中進行迴焊作業後,由於助焊劑殘渣遍佈線路基板之承載表面,必須在步驟105中進行繁複的清除助焊劑殘渣作業,導致耗費大量清洗人工、設備、場地、材料(水、溶劑)和能源的消耗,並使覆晶封裝製程變得冗長,嚴重降低生產效率;在步驟107中若填膠材料流動之速度控制不當則容易將空氣包覆在底膠內,而造成底膠內產生氣泡,而步驟105所進行清除助焊劑殘渣作業若清除作業未完全,將會造成填膠材料流動之速度無法控制而將空氣包覆在底膠內形成氣泡;或由於銲墊間距日益細微化,覆晶晶片與線路基板的接合間隙亦日益縮小化,使得所填膠材之毛細現象不易流動而需更長的時間來覆滿晶片下方之空間,也由於覆滿晶片下方空間之困難度增加,而導致填膠材料中氣泡的存在,使得導電性或導熱性不佳,甚而影響覆晶封裝結構之使用壽命;由於焊墊間距日益細微化,晶片與線路基板的接合間隙亦日益縮小化,助焊劑殘渣夾雜於晶片、各該導電凸塊與線路基板的縫隙中,使用步驟105之清除助焊劑殘渣作業,已難以將助焊劑殘渣清除乾淨,實有加以改良的必要。 As described above, after the reflowing operation is performed in step 104, since the flux residue is distributed over the bearing surface of the circuit substrate, complicated cleaning flux residue must be performed in step 105, resulting in a large amount of cleaning labor, equipment, site, material (water) , solvent) and energy consumption, and make the flip chip packaging process become tedious, seriously reducing production efficiency; in step 107, if the speed of the filling material flow is not properly controlled, it is easy to wrap the air in the primer, resulting in a bottom Air bubbles are generated in the glue, and if the cleaning operation is not completed in step 105, if the cleaning operation is not complete, the speed of the filling material may be uncontrollable and the air may be coated in the primer to form bubbles; or due to the increasingly uneven spacing of the pads The miniaturization, the bonding gap between the flip chip and the circuit substrate is also increasingly reduced, so that the capillary phenomenon of the filled material is not easy to flow, and it takes a longer time to cover the space under the wafer, and also the difficulty of covering the space under the wafer. The increase in degree leads to the presence of bubbles in the filler material, which makes the conductivity or thermal conductivity poor, and even affects the structure of the flip chip package. Lifetime; due to the increasingly finer pitch of the pad, the bonding gap between the wafer and the circuit substrate is also increasingly reduced, and the flux residue is interposed in the gap between the wafer, each of the conductive bumps and the circuit substrate, and the flux residue is removed using step 105. It has been difficult to remove the flux residue and it is necessary to improve it.

是以,針對上述習知覆晶封裝製程所存在之問題點,如何開發一種更具理想實用性並兼顧經濟效益之封裝製程,實為相關業者積極 研發突破之目標及方向。 Therefore, in view of the problems existing in the above-mentioned conventional flip chip packaging process, how to develop a packaging process that is more ideal and practical, and that combines economic benefits, is actively related to the relevant industry. The goal and direction of research and development breakthroughs.

有鑑於此,發明人本於多年從事相關產品之製造開發與設計經驗,針對上述之目標,詳加設計與審慎評估後,終得一確具實用性之本發明。 In view of this, the inventor has been engaged in the manufacturing development and design experience of related products for many years. After detailed design and careful evaluation, the inventor has finally obtained the practical invention.

習知覆晶封裝製程,由於助焊劑殘渣遍佈線路基板之承載表面,必須進行繁複的清除助焊劑殘渣作業,嚴重降低生產效率;填膠材料中氣泡的存在,使得導電性或導熱性不佳,甚而影響覆晶封裝結構之使用壽命;助焊劑殘渣夾雜於晶片、各該導電凸塊與線路基板的縫隙中,進行清除助焊劑殘渣作業,已難以將助焊劑殘渣清除乾淨,實有加以改良的必要。 In the conventional flip chip packaging process, since the flux residue is spread over the bearing surface of the circuit substrate, complicated flux residue removal operation must be performed, and the production efficiency is seriously reduced; the presence of bubbles in the filler material makes the conductivity or thermal conductivity poor. It even affects the service life of the flip chip package structure; the flux residue is mixed in the gap between the wafer, each of the conductive bumps and the circuit substrate, and the flux residue is removed, and it is difficult to remove the flux residue, which is improved. necessary.

為改善上述之問題,本發明提供一種覆晶封裝製程之焊接方法,其係應用於製造一覆晶封裝結構,其中該覆晶封裝結構包括一晶片及一線路基板。該焊接方法其步驟包括:a.提供該晶片,其中該晶片設有一主動表面,該主動表面上設置複數個導電凸塊,該導電凸塊成份為錫、銀、銅、金、銦、鉛、鉍、鋅、鎳至少其中之一,或是其他利於焊接的材質。b.提供該線路基板,其中該線路基板設有一承載表面,該承載表面上對應於各該導電凸塊分別配置一焊墊。 In order to improve the above problems, the present invention provides a soldering method for a flip chip packaging process for manufacturing a flip chip package structure, wherein the flip chip package structure includes a wafer and a circuit substrate. The soldering method comprises the steps of: a. providing the wafer, wherein the wafer is provided with an active surface, and the active surface is provided with a plurality of conductive bumps, the conductive bumps being tin, silver, copper, gold, indium, lead, At least one of bismuth, zinc, and nickel, or other materials that are good for welding. The circuit substrate is provided, wherein the circuit substrate is provided with a bearing surface, and a soldering pad is disposed on each of the conductive bumps on the bearing surface.

c.利用一3D陣列噴嘴列印(3D Matrix Inkjet Printing)裝置將助焊劑(Flux)精準噴覆於各該焊墊表面,經由該3D陣列噴嘴列印裝置之程式設定,可精確地控制助焊劑之噴覆範圍及噴覆劑量,可有效避免噴覆於各該焊墊區域之外,其中助焊劑係採用液態助焊劑,該液態助焊劑之黏度為1厘泊(cps,centipoises)至100厘泊的範圍,其主要作用是清除焊料和被焊母材表面的氧化物,使焊接表面達到必要的清潔度,防止焊接時表面的再次氧化,降低液態焊料的表面張力,使潤濕性能明顯得到提高。 c. Using a 3D Matrix Inkjet Printing device to precisely spray the flux (Flux) on the surface of each pad, and accurately control the flux through the programming of the 3D array nozzle printing device The spray range and the spray dose can effectively avoid spraying outside the solder pad area, wherein the flux is a liquid flux, and the liquid flux has a viscosity of 1 centipoise (cps, centipoises) to 100%. The scope of the mooring is mainly to remove the oxides on the surface of the solder and the surface of the soldered material, to achieve the necessary cleanliness of the soldered surface, to prevent re-oxidation of the surface during soldering, to reduce the surface tension of the liquid solder, and to obtain the wettability. improve.

d.將晶片翻覆(Flip Chip)並對位,以使晶片之主動表面朝向線路基板之承載表面配置,並使各該導電凸塊分別經由助焊劑接合各該焊墊。e.最後進行一金屬熔接作業,以使得晶片藉由各該導電凸塊而與線路基板上之各該焊墊電性(Electrically)及結構性(Structurally)連接,製成該覆晶封 裝結構,使線路基板與晶片之間可進行訊號的傳輸。 d. Flip Chip and position the wafer so that the active surface of the wafer is disposed toward the bearing surface of the circuit substrate, and each of the conductive bumps is bonded to each of the pads via a flux. e. Finally, a metal welding operation is performed, so that the wafer is electrically and structurally connected to each of the pads on the circuit substrate by the conductive bumps to form the chip seal. The structure is configured to enable signal transmission between the circuit substrate and the wafer.

前述,該金屬熔接作業是將對位好的晶片與線路基板及各該導電凸塊執行金屬熔接,使得受熱熔融或半熔融狀態的各該導電凸塊結合線路基板之承載表面上的各該焊墊。 In the foregoing, the metal welding operation is to perform metal welding on the aligned wafer and the circuit substrate and each of the conductive bumps, so that each of the conductive bumps in the heat-melted or semi-molten state is bonded to the soldering surface of the circuit substrate. pad.

前述,該助焊劑之噴覆乃使用該3D陣列噴嘴列印裝置將電腦設計出的圖形,經由事先定義出複數個噴嘴的座標與精確定位出該線路基板上各個焊墊的位置及所欲噴覆之範圍,並由該3D陣列噴嘴列印裝置依設計逐層堆疊出複數個仿照3D圖形的助焊劑噴覆層。 In the foregoing, the spraying of the flux uses the 3D array nozzle printing device to design a graphic of the computer, by predefining the coordinates of the plurality of nozzles and accurately positioning the positions of the pads on the circuit substrate and the desired spraying. Covering the range, and the 3D array nozzle printing device stacks a plurality of flux spray coatings in the form of 3D patterns.

本發明更提供一種覆晶封裝製程,其步驟包括:a.製備一晶片,其中該晶片設有一主動表面,該主動表面上設置複數個導電凸塊,該導電凸塊成份為錫、銀、銅、金、銦、鉛、鉍、鋅、鎳至少其中之一,或是其他利於焊接的材質。b.製備一線路基板,其中該線路基板設有一承載表面,該承載表面上對應於各該導電凸塊分別配置一焊墊。 The invention further provides a flip chip packaging process, the steps comprising: a. preparing a wafer, wherein the wafer is provided with an active surface, the active surface is provided with a plurality of conductive bumps, the conductive bumps are tin, silver and copper At least one of gold, indium, lead, antimony, zinc, and nickel, or other materials that are good for welding. b. Preparing a circuit substrate, wherein the circuit substrate is provided with a bearing surface, and a bonding pad is disposed on each of the conductive bumps.

c.利用一3D陣列噴嘴列印裝置將助焊劑噴覆於各該焊墊表面,經由該3D陣列噴嘴列印裝置之程式設定,可精確地控制助焊劑之噴覆範圍及噴覆劑量,可有效避免噴覆於各該焊墊區域之外。 c. spraying a flux onto each surface of the pad by using a 3D array nozzle printing device, and accurately setting the spraying range and the spraying amount of the flux through the programming of the 3D array nozzle printing device. Effectively avoid spraying over the area of each pad.

d.將晶片翻覆並對位,以使晶片之主動表面朝向線路基板之承載表面配置,並使各該導電凸塊分別經由助焊劑接合各該焊墊,接續進行一金屬熔接作業,以使得晶片藉由各該導電凸塊而與線路基板上之各該焊墊電性及結構性連接,製成一覆晶封裝結構,使線路基板與晶片之間可進行訊號的傳輸。e.對該覆晶封裝結構執行一電漿清潔作業,藉以改善覆晶封裝結構表面的潔淨度及潤溼性,有效提升產品的可靠性。 d. flipping the wafer to the ground so that the active surface of the wafer is disposed toward the bearing surface of the circuit substrate, and each of the conductive bumps is respectively joined to each of the pads via a flux, and then a metal welding operation is performed to make the wafer The conductive bumps are electrically and structurally connected to the pads on the circuit substrate to form a flip chip package structure, so that signal transmission can be performed between the circuit substrate and the wafer. e. Performing a plasma cleaning operation on the flip chip package structure to improve the cleanliness and wettability of the surface of the flip chip package structure, thereby effectively improving product reliability.

f.使用一點膠工具於晶片與線路基板之間填充一底膠,該底膠包覆各該導電凸塊,用以對該晶片與該線路基板之間可能產生之熱應力與機械應力提供緩衝的功能,且該執行金屬熔接作業後所殘留的微量助焊劑殘渣可溶解於底膠。 f. using a glue tool to fill a primer between the wafer and the circuit substrate, the primer coating each of the conductive bumps for providing thermal stress and mechanical stress between the wafer and the circuit substrate The buffering function, and the trace flux residue remaining after performing the metal welding operation can be dissolved in the primer.

g.將完成填膠程序之覆晶封裝結構移入一耐壓艙內,施加壓力使該金屬熔接作業後所殘留的助焊劑殘渣得溶解於該底膠並對該底膠進行除泡及固化程序,以消除該底膠與該線路基板接面處之氣泡、該底膠與該晶片接面處之氣泡、以及該底膠內部氣泡,並將底膠加熱烘烤使其完全 固化。 g. moving the flip chip package structure of the filling process into a pressure-resistant chamber, applying pressure to dissolve the flux residue remaining after the metal welding operation, and defoaming and curing the primer. In order to eliminate the bubble at the junction of the primer and the circuit substrate, the bubble at the junction of the primer and the wafer, and the bubble inside the primer, and heat the baking to make the primer completely Cured.

前述,該助焊劑之噴覆乃使用該3D陣列噴嘴列印裝置將電腦設計出的圖形,經由事先定義出複數個噴嘴的座標與精確定位出該線路基板上各個焊墊的位置及所欲噴覆之範圍,並由該3D陣列噴嘴列印裝置依設計逐層堆疊出複數個仿照3D圖形的助焊劑噴覆層。 In the foregoing, the spraying of the flux uses the 3D array nozzle printing device to design a graphic of the computer, by predefining the coordinates of the plurality of nozzles and accurately positioning the positions of the pads on the circuit substrate and the desired spraying. Covering the range, and the 3D array nozzle printing device stacks a plurality of flux spray coatings in the form of 3D patterns.

前述,助焊劑係採用液態助焊劑,該液態助焊劑之黏度為1厘泊至100厘泊的範圍。 In the foregoing, the flux is a liquid flux having a viscosity in the range of 1 centipoise to 100 centipoise.

前述,底膠成份為摻雜有二氧化矽(SiO2)粉末等填充物之環氧樹脂(Epoxy Resin)。 In the foregoing, the primer component is an epoxy resin (Epoxy Resin) doped with a filler such as cerium oxide (S i O 2 ) powder.

前述,填充底膠之方法主要係利用該點膠工具,將液態的填膠材料點於該晶片的邊緣,填膠材料會因毛細現象流動至該晶片下方,即可填滿於該晶片及該線路基板之間的空隙。 In the foregoing, the method of filling the primer mainly uses the dispensing tool to point the liquid filling material to the edge of the wafer, and the filling material flows to the lower side of the wafer due to capillary phenomenon, and the wafer can be filled and A gap between the circuit boards.

前述,該耐壓艙內壓力之設定介於10-3托耳(Torr)至30大氣壓(atm)的範圍,該耐壓艙內溫度之設定介於攝氏20度至500度的範圍。 In the foregoing, the pressure in the pressure chamber is set in a range of 10 -3 Torr to 30 atm, and the temperature in the pressure tank is set in the range of 20 to 500 degrees Celsius.

前述,為溶解助焊劑殘渣於該底膠並對該底膠進行除泡及固化程序所施加的壓力,以振盪變化的方式呈現,其變化範圍之設定介於10-3托耳(Torr)至30大氣壓(atm)的範圍。 In the foregoing, the pressure applied to dissolve the flux residue in the primer and defoam and cure the primer is presented in an oscillating manner, and the range of variation is set to 10 -3 Torr to 30 atmosphere (atm) range.

本發明之覆晶封裝製程及其焊接方法,藉由3D陣列噴嘴列印裝置精確地控制助焊劑之噴覆範圍及噴覆劑量,使得金屬熔接作業後所殘留之助焊劑殘渣極為微量,輔以耐壓艙對殘存有限的助焊劑進行處裡,使助焊劑能加速溶解於底膠之中而無須進行溶劑沖洗等清除助焊劑殘渣作業,有效簡化覆晶封裝製程,大幅度提高了生產效率;該些微量的助焊劑殘渣可將其溶解於底膠中,完全無清除助焊劑殘渣之困擾,有效提升產品的可靠性;藉由耐壓艙透過壓力高低變化所形成的壓力差,將氣泡完全擠壓排出,徹底解決了覆晶封裝結構中氣泡殘留的問題。 The flip chip packaging process and the soldering method thereof of the invention accurately control the spraying range and the spraying dose of the flux by the 3D array nozzle printing device, so that the flux residue remaining after the metal welding operation is extremely small, supplemented by The pressure-resistant chamber carries the limited flux remaining in the flux, so that the flux can be accelerated to dissolve in the primer without solvent washing and the like to remove the flux residue, which effectively simplifies the flip chip packaging process and greatly improves the production efficiency; The trace amount of the flux residue can be dissolved in the primer, completely eliminating the trouble of removing the flux residue, and effectively improving the reliability of the product; the bubble is completely separated by the pressure difference formed by the pressure chamber through the pressure change. Extrusion and discharge completely solve the problem of bubble residue in the flip chip package structure.

有關本發明所採用之技術、手段及其功效,茲舉較佳實施例並配合圖式詳細說明於後,相信本發明上述之目的、構造及特徵,當可由之得一深入而具體的瞭解。 The above described objects, structures, and features of the present invention will be apparent from the following description of the preferred embodiments of the invention.

〔習知〕 [study]

101-108‧‧‧步驟 101-108‧‧‧Steps

〔本發明〕 〔this invention〕

201-207‧‧‧步驟 201-207‧‧‧Steps

300‧‧‧覆晶封裝結構 300‧‧‧Flip chip package structure

310‧‧‧晶片 310‧‧‧ wafer

311‧‧‧主動表面 311‧‧‧Active surface

320‧‧‧導電凸塊 320‧‧‧Electrical bumps

330‧‧‧線路基板 330‧‧‧Line substrate

331‧‧‧承載表面 331‧‧‧bearing surface

332‧‧‧焊墊 332‧‧‧ solder pads

340‧‧‧3D陣列噴嘴列印裝置 340‧‧‧3D array nozzle printing device

341‧‧‧助焊劑噴覆層 341‧‧‧flux spray coating

350‧‧‧噴嘴 350‧‧‧ nozzle

410‧‧‧底膠 410‧‧‧Bottom glue

510‧‧‧耐壓艙 510‧‧ ‧ Pressure tank

第1圖係習知覆晶封裝製程的流程圖。 Figure 1 is a flow chart of a conventional flip chip packaging process.

第2圖係本發明之較佳實施例之覆晶封裝製程的流程圖。 2 is a flow chart of a flip chip packaging process of a preferred embodiment of the present invention.

第3A至第3F圖係第2圖之覆晶封裝製程的剖面示意圖。 3A to 3F are schematic cross-sectional views showing the flip chip packaging process of FIG.

參閱第2圖及第3A至第3F圖所示,其中第2圖為本發明之較佳實施例之覆晶封裝製程的流程圖,而第3A至第3F圖為此覆晶封裝製程的剖面示意圖,本發明係提供一種覆晶封裝製程,其步驟包括:a.(步驟201)製備一晶片310,其中該晶片310設有一主動表面311,該主動表面311上設置複數個導電凸塊320(如第3A圖所示),該導電凸塊320係藉由一般的凸塊製程(bumping process)所製作而成之焊料凸塊,其成份為錫、銀、銅、金、銦、鉛、鉍、鋅、鎳至少其中之一,或是其他利於焊接的材質。 Referring to FIG. 2 and FIGS. 3A to 3F, wherein FIG. 2 is a flow chart of a flip chip packaging process according to a preferred embodiment of the present invention, and FIGS. 3A to 3F are cross-sectional views of the flip chip packaging process. The present invention provides a flip chip packaging process, the steps of which include: a. (Step 201) preparing a wafer 310, wherein the wafer 310 is provided with an active surface 311 on which a plurality of conductive bumps 320 are disposed ( As shown in FIG. 3A, the conductive bumps 320 are solder bumps formed by a general bumping process, and are composed of tin, silver, copper, gold, indium, lead, and antimony. At least one of zinc, nickel, or other materials that are good for welding.

b.(步驟202)製備一線路基板330,其中該線路基板330設有一承載表面331,該承載表面331上對應於各該導電凸塊320分別配置一焊墊332(如第3B圖所示)。 b. (Step 202) Preparing a circuit substrate 330, wherein the circuit substrate 330 is provided with a bearing surface 331, and a bonding pad 332 is disposed on each of the conductive bumps 320 corresponding to each of the conductive bumps 320 (as shown in FIG. 3B). .

c.(步驟203)利用一3D陣列噴嘴列印裝置340將助焊劑噴覆於各該焊墊332表面,經由該3D陣列噴嘴列印裝置340之程式設定,可精確地控制助焊劑之噴覆範圍及噴覆劑量,有效避免噴覆於各該焊墊332表面之助焊劑外溢,其中該助焊劑之噴覆乃使用該3D陣列噴嘴列印裝置340將電腦設計出的圖形,經由事先定義出複數個噴嘴350的座標與精確定位出該線路基板330上各個焊墊332的位置及所欲噴覆之範圍,並由該3D陣列噴嘴列印裝置340依設計逐層堆疊出複數個仿照3D圖形的助焊劑噴覆層341(如第3C圖所示),其中助焊劑係採用液態助焊劑,其主要作用是清除焊料和被焊母材表面的氧化物,使焊接表面達到必要的清潔度,防止焊接時表面的再次氧化,降低液態焊料的表面張力,使潤濕性能明顯得到提高。 c. (Step 203) spraying a flux onto the surface of each of the pads 332 by using a 3D array nozzle printing device 340, and precisely controlling the spraying of the flux through the programming of the 3D array nozzle printing device 340. The range and the spraying dose are effective to avoid the overflow of the flux sprayed on the surface of each of the pads 332. The spraying of the flux is defined by using the 3D array nozzle printing device 340 to define the graphic of the computer. The coordinates of the plurality of nozzles 350 accurately position the respective pads 332 on the circuit substrate 330 and the range of the desired spray, and the 3D array nozzle printing device 340 stacks a plurality of simulated 3D graphics layer by layer. Flux spray coating 341 (as shown in Figure 3C), wherein the flux is a liquid flux, the main function of which is to remove the oxides from the solder and the surface of the soldered base material to achieve the necessary cleanliness of the solder surface. Prevents reoxidation of the surface during soldering, reduces the surface tension of the liquid solder, and significantly improves the wetting performance.

d.(步驟204)將晶片310翻覆並對位,以使晶片310之 主動表面311朝向線路基板330之承載表面331配置,並使各該導電凸塊320分別經由助焊劑接合各該焊墊332(如第3D圖所示),接續進行一金屬熔接作業,以使得晶片310藉由各該導電凸塊320而與線路基板330上之各該焊墊332電性及結構性連接,製成一覆晶封裝結構300,使線路基板330與晶片310之間可進行訊號的傳輸,此處所進行的金屬熔接(例如迴焊)是將對位好的晶片310與線路基板330及各該導電凸塊320與各該焊墊332執行金屬熔接,使得受熱熔融或半熔融狀態的各該導電凸塊320結合線路基板330之承載表面331上的各該焊墊332。 d. (Step 204) flipping the wafer 310 into position to make the wafer 310 The active surface 311 is disposed toward the bearing surface 331 of the circuit substrate 330, and each of the conductive bumps 320 is respectively soldered to the pads 332 (as shown in FIG. 3D), and then a metal bonding operation is performed to make the wafer The conductive bumps 320 are electrically and structurally connected to the pads 332 on the circuit substrate 330 to form a flip chip package structure 300, so that signals can be made between the circuit substrate 330 and the wafer 310. Transmission, the metal welding (for example, reflow) performed here is to perform metal welding of the aligned wafer 310 and the circuit substrate 330 and each of the conductive bumps 320 and each of the pads 332 so as to be in a heated or semi-molten state. Each of the conductive bumps 320 is bonded to each of the pads 332 on the bearing surface 331 of the circuit substrate 330.

e.(步驟205)對該覆晶封裝結構300執行一電漿清潔作業,藉以改善覆晶封裝結構300表面的潔淨度及潤溼性,有效提升產品的可靠性。 e. (Step 205) Perform a plasma cleaning operation on the flip chip package structure 300 to improve the cleanliness and wettability of the surface of the flip chip package structure 300, thereby effectively improving product reliability.

f.(步驟206)使用一點膠工具於晶片310與線路基板330之間填充一底膠410(如第3E圖所示),該底膠410係包覆各該導電凸塊320,用以對晶片310與線路基板330之間可能產生之熱應力及機械應力提供緩衝的功能,其中該底膠410例如是摻雜有二氧化矽(SiO2)粉末等填充物之環氧樹脂,其可與執行金屬熔接作業後所殘留的微量助焊劑殘渣互溶。此處所進行的液態填膠方法主要係利用該點膠工具,將液態的填膠材料點於晶片310的邊緣,填膠材料會因毛細現象流動至晶片310下方,即可填滿於晶片310及線路基板330之間的空隙。 f. (Step 206) filling a primer 410 (shown in FIG. 3E) between the wafer 310 and the circuit substrate 330 using a glue tool, the primer 410 coating each of the conductive bumps 320 for The function of providing thermal buffer and mechanical stress between the wafer 310 and the circuit substrate 330 is provided, wherein the primer 410 is, for example, an epoxy resin doped with a filler such as cerium oxide (S i O 2 ) powder. It is miscible with the trace flux residue remaining after performing the metal welding operation. The liquid filling method performed here mainly uses the dispensing tool to point the liquid filling material to the edge of the wafer 310, and the filling material flows to the lower side of the wafer 310 due to capillary phenomenon, and can be filled on the wafer 310 and A gap between the circuit substrates 330.

g.(步驟207)將完成填膠程序之覆晶封裝結構300移入一耐壓艙510內,使底膠410進行助焊劑殘渣之溶解並去除各式氣泡及固化程序(如第3F圖所示),以消除該底膠410與該線路基板330接面處之氣泡、該底膠410與該晶片310接面處之氣泡、以及該底膠410內部氣泡,並將底膠410加熱烘烤使其完全固化,其中該耐壓艙510內壓力之設定介於10-3托耳(Torr)至30大氣壓(atm)的範圍,且溫度之設定介於攝氏20度至500度的範圍,在除泡過程中壓力係呈現振盪式變化,藉由壓力高低變化所形成的壓力差,可將氣泡由該底膠410之四周完全擠壓排出。 g. (Step 207) The flip chip package structure 300 that completes the glue filling process is moved into a pressure-resistant chamber 510, so that the primer 410 dissolves the flux residue and removes various bubbles and curing procedures (as shown in FIG. 3F). ), the air bubbles at the junction of the primer 410 and the circuit substrate 330, the bubbles at the junction of the primer 410 and the wafer 310, and the bubbles inside the primer 410 are removed, and the primer 410 is heated and baked. It is fully cured, wherein the pressure in the pressure chamber 510 is set in the range of 10 -3 Torr to 30 atm, and the temperature is set in the range of 20 to 500 degrees Celsius. During the bubble process, the pressure system exhibits an oscillating change, and the bubble is completely squeezed out from the periphery of the primer 410 by the pressure difference formed by the change in pressure.

本發明之覆晶封裝製程及其焊接方法,在步驟203中藉由 3D陣列噴嘴列印裝置340精確地控制助焊劑之噴覆範圍及噴覆劑量,使得在步驟204中執行金屬熔接作業後所殘留之助焊劑殘渣極為微量,此些微量的助焊劑殘渣可在步驟207中將其溶解於底膠410中,相較於習知覆晶封裝製程由於助焊劑殘渣遍佈線路基板之承載表面,必須進行溶劑沖洗等清除助焊劑殘渣作業,本發明有效簡化覆晶封裝製程,大幅度提高了生產效率。 The flip chip packaging process of the present invention and the soldering method thereof are carried out in step 203 The 3D array nozzle printing device 340 accurately controls the spraying range and the spraying amount of the flux, so that the flux residue remaining after performing the metal welding operation in step 204 is extremely small, and the trace amount of the flux residue can be in the step. In 207, it is dissolved in the primer 410. Compared with the conventional flip chip packaging process, since the flux residue is distributed over the bearing surface of the circuit substrate, the flux residue must be removed by solvent rinsing, etc., and the present invention effectively simplifies the flip chip packaging process. , greatly improving production efficiency.

本發明之覆晶封裝製程及其焊接方法,在步驟204中執行金屬熔接後所殘留之助焊劑殘渣極為微量,該些微量的助焊劑殘渣可在步驟207中將其溶解於底膠410中,故完全無清除助焊劑殘渣之困擾,相較於習知覆晶封裝製程由於焊墊間距日益細微化,晶片與線路基板的接合間隙亦日益縮小化,助焊劑殘渣夾雜於晶片、各該導電凸塊與線路基板的縫隙中,使用溶劑沖洗等清除助焊劑殘渣作業,已難以將助焊劑殘渣清除乾淨,本發明在覆晶封裝製程中,有效提升產品的可靠性。 In the flip chip packaging process of the present invention and the soldering method thereof, the flux residue remaining after the metal fusion is performed in step 204 is extremely small, and the trace amount of the flux residue may be dissolved in the primer 410 in step 207. Therefore, there is no trouble of removing the flux residue. Compared with the conventional flip chip packaging process, the bonding gap between the wafer and the circuit substrate is increasingly reduced due to the increasingly finer pitch of the pad, and the flux residue is mixed with the wafer and each of the conductive bumps. In the gap between the block and the circuit substrate, the flux residue is used to remove the flux residue, and it has been difficult to remove the flux residue. The present invention effectively improves the reliability of the product in the flip chip packaging process.

本發明之覆晶封裝製程及其焊接方法,在步驟207中藉由耐壓艙510透過壓力高低變化所形成的壓力差,將氣泡完全擠壓排出,相較於習知覆晶封裝製程由於焊墊間距日益細微化,覆晶晶片與線路基板的接合間隙亦日益縮小化,使得所填膠材覆滿晶片下方空間之困難度增加,而導致填膠材料中氣泡的存在,本發明徹底解決了覆晶封裝結構中氣泡殘留的問題。 In the flip chip packaging process and the soldering method thereof, in step 207, the bubble is completely squeezed out by the pressure difference formed by the pressure change of the pressure chamber 510, which is compared with the conventional flip chip packaging process. The pad pitch is increasingly finer, and the bonding gap between the flip chip and the circuit substrate is also increasingly reduced, so that the difficulty of filling the space under the wafer by the filled adhesive material increases, and the existence of bubbles in the rubber filling material is completely solved by the present invention. The problem of air bubbles remaining in the flip chip package structure.

前文係針對本發明之較佳實施例為本發明之技術特徵進行具體之說明;惟,熟悉此項技術之人士當可在不脫離本發明之精神與原則下對本發明進行變更與修改,而該等變更與修改,皆應涵蓋於如下申請專利範圍所界定之範疇中。 The present invention has been described with reference to the preferred embodiments of the present invention. However, those skilled in the art can change and modify the present invention without departing from the spirit and scope of the invention. Such changes and modifications shall be covered in the scope defined by the following patent application.

201-207‧‧‧步驟 201-207‧‧‧Steps

Claims (9)

一種覆晶封裝製程,其步驟包括:(a)製備一晶片,該晶片設有一主動表面,該主動表面上設置複數個導電凸塊;(b)製備一線路基板,該線路基板設有一承載表面,該承載表面上對應於各該導電凸塊分別配置一焊墊;(c)利用一3D陣列噴嘴列印裝置將一助焊劑噴覆於各該焊墊表面,經由該3D陣列噴嘴列印裝置之程式設定,控制該助焊劑之噴覆範圍及噴覆劑量;(d)將該晶片翻覆並對位,以使該晶片之該主動表面朝向該線路基板之該承載表面配置,並使各該導電凸塊分別經由該助焊劑接合各該焊墊,接續進行一金屬熔接作業,使該晶片藉由各該導電凸塊與該線路基板上之各該焊墊電性及結構性連接,製成一覆晶封裝結構;(e)使用一點膠工具於該晶片與該線路基板之間填充一底膠,該底膠包覆各該導電凸塊,用以對該晶片與該線路基板之間產生之熱應力與機械應力提供緩衝的功能;(f)將完成填膠程序之該覆晶封裝結構移入一耐壓艙內,施加壓力使該金屬熔接作業後所殘留的助焊劑殘渣得溶解於該底膠並對該底膠進行除泡及固化程序,以消除該底膠與該線路基板接面處之氣泡、該底膠與該晶片接面處之氣泡、以及該底膠內部氣泡,並將該底膠加熱烘烤使其完全固化。 A flip chip packaging process, the steps comprising: (a) preparing a wafer, the wafer is provided with an active surface, the active surface is provided with a plurality of conductive bumps; (b) preparing a circuit substrate, the circuit substrate is provided with a bearing surface a solder pad is disposed on each of the conductive bumps on the bearing surface; (c) a flux is sprayed onto each of the pads by a 3D array nozzle printing device, and the device is printed by the 3D array nozzle Programming, controlling the spray range and the spray dose of the flux; (d) flipping the wafer to the position so that the active surface of the wafer is disposed toward the bearing surface of the circuit substrate, and each of the conductive The bumps are respectively connected to the pads via the flux, and then a metal fusing operation is performed to electrically and structurally connect the conductive bumps to the pads on the circuit substrate. a flip chip package structure; (e) using a glue tool to fill a gap between the wafer and the circuit substrate, the primer coating each of the conductive bumps for generating between the wafer and the circuit substrate Thermal stress and machinery The stress provides a buffering function; (f) the flip chip package structure that completes the filling process is moved into a pressure-resistant chamber, and pressure is applied to dissolve the flux residue remaining after the metal welding operation in the primer and The primer is subjected to a defoaming and curing process to eliminate bubbles at the junction of the primer and the circuit substrate, bubbles at the junction of the primer and the wafer, and bubbles inside the primer, and heat the primer. Bake it to fully cure. 如申請專利範圍第1項所述之覆晶封裝製程,其中該助焊劑係為液態助焊劑,該液態助焊劑之黏度為1厘泊(cps,centipoises)至100厘泊的範圍。 The flip chip packaging process of claim 1, wherein the flux is a liquid flux having a viscosity of from 1 centipoise (centipoises) to 100 centipoise. 如申請專利範圍第1項所述之覆晶封裝製程,其中該3D陣列噴嘴列印裝置將電腦設計出的圖形,經由事先定義出複數個噴嘴的座標與精確定位出該線路基板上各個焊墊的位置及所欲噴覆之範圍,並由該3D陣列噴嘴列印裝置依設計逐層堆疊出複數個仿照3D圖形的助焊劑噴覆層。 The flip chip packaging process of claim 1, wherein the 3D array nozzle printing device defines a graphic of the computer by pre-defining coordinates of the plurality of nozzles and accurately positioning each pad on the circuit substrate. The position and the range of the desired spray, and the 3D array nozzle printing device layer-by-layer stacks a plurality of flux spray coatings that follow the 3D pattern. 如申請專利範圍第1項所述之覆晶封裝製程,其中該底膠成份為環氧樹脂(Epoxy Resin)。 The flip chip packaging process of claim 1, wherein the primer component is epoxy resin (Epoxy Resin). 如申請專利範圍第1項所述之覆晶封裝製程,其中填充該底膠之方法係利用該點膠工具,將液態的填膠材料點於該晶片的邊緣,填膠材料因毛細現象流動至該晶片下方,並填滿該晶片及該線路基板之間的空隙。 The flip chip packaging process of claim 1, wherein the method of filling the primer uses the dispensing tool to point the liquid filling material to the edge of the wafer, and the filling material flows to the edge due to capillary phenomenon. The wafer is underneath and fills the gap between the wafer and the circuit substrate. 如申請專利範圍第1項所述之覆晶封裝製程,其中該耐壓艙內壓力之設定介於10-3托耳(Torr)至30大氣壓(atm)的範圍。 The flip chip packaging process of claim 1, wherein the pressure in the pressure chamber is set in a range of 10 -3 Torr to 30 atmospheres (atm). 如申請專利範圍第1項所述之覆晶封裝製程,其中為溶解助焊劑殘渣於該底膠並對該底膠進行除泡及固化程序所施加的壓力,以振盪變化的方式呈現,其變化範圍之設定介於10-3托耳(Torr)至30大氣壓(atm)的範圍。 The flip chip packaging process of claim 1, wherein the pressure applied to dissolve the flux residue in the primer and defoam and cure the primer is presented in an oscillating manner, the change The range is set between 10 -3 Torr to 30 atmospheres (atm). 如申請專利範圍第1項所述之覆晶封裝製程,其中該耐壓艙內溫度之設定介於攝氏20度至500度的範圍。 The flip chip packaging process of claim 1, wherein the temperature in the pressure chamber is set between 20 degrees Celsius and 500 degrees Celsius. 如申請專利範圍第1項所述之覆晶封裝製程,其中介於步驟(d)與步驟(e)間更包含對該覆晶封裝結構執行一電漿清潔作業,藉以改善該覆晶封裝結構表面的潔淨度及潤溼性,提升產品的可靠性。 The flip chip packaging process of claim 1, wherein the step (d) and the step (e) further comprise performing a plasma cleaning operation on the flip chip package structure, thereby improving the flip chip package structure. The cleanliness and wettability of the surface enhance the reliability of the product.
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TWI239090B (en) * 2000-08-24 2005-09-01 Advanced Micro Devices Inc Controlled and programmed deposition of flux on a flip-chip die by spraying
TW200927292A (en) * 2007-10-31 2009-07-01 Nordson Corp Fluid dispensers and methods for dispensing viscous fluids with improved edge definition

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Publication number Priority date Publication date Assignee Title
TWI239090B (en) * 2000-08-24 2005-09-01 Advanced Micro Devices Inc Controlled and programmed deposition of flux on a flip-chip die by spraying
TW200927292A (en) * 2007-10-31 2009-07-01 Nordson Corp Fluid dispensers and methods for dispensing viscous fluids with improved edge definition

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