TWI566357B - Semiconductor package and its manufacturing method and its bearing structure and manufacturing method thereof - Google Patents
Semiconductor package and its manufacturing method and its bearing structure and manufacturing method thereof Download PDFInfo
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- TWI566357B TWI566357B TW103100153A TW103100153A TWI566357B TW I566357 B TWI566357 B TW I566357B TW 103100153 A TW103100153 A TW 103100153A TW 103100153 A TW103100153 A TW 103100153A TW I566357 B TWI566357 B TW I566357B
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- power strip
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- semiconductor package
- support block
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Lead Frames For Integrated Circuits (AREA)
Description
本發明係有關一種半導體封裝件，尤指一種承載有半導體元件之半導體封裝件及其承載結構。 The present invention relates to a semiconductor package, and more particularly to a semiconductor package carrying a semiconductor component and a carrier structure thereof.
隨著電子產業的蓬勃發展，電子產品也逐漸邁向多功能、高性能的趨勢。隨著電子產業的蓬勃發展，許多電子產品都逐漸朝往輕、薄、短、小等高集積度方向發展，半導體封裝件也發展出許多種不同的封裝模組，例如，覆晶封裝(Flip Chip Package)、打線接合(Wire Bond)等。 With the rapid development of the electronics industry, electronic products are gradually moving towards multi-functional and high-performance trends. With the rapid development of the electronics industry, many electronic products are gradually moving towards light, thin, short, and small high integration. Semiconductor package parts have also developed many different package modules, for example, flip chip package (Flip) Chip Package), Wire Bond, etc.
目前打線接合技術常以導線架作為承載晶片之承載結構。如第1A及1B圖所示，習知打線式半導體封裝件9中，其導線架1包含一承載晶片90之座部(die pad)10、位於該座部10邊緣之複數導腳12及複數電源條(Power Bar)11，各該導腳12具有外腳部(outer leads portion)120及內腳部(inner leads portion)121，且該外腳部120係用以電性連接至一外部電路(圖未示)。該晶片90利用複數銲 線(bonding wire)900電性連接該導腳12之內腳部121。又藉由如環氧樹脂(epoxy)製成絕緣材料之封裝材91包覆該晶片90、座部10、電源條11、導腳12及銲線900。另外，第1B圖係為第1A圖之導線架1之B-B剖線之剖面示意圖。 At present, wire bonding technology often uses a lead frame as a load bearing structure for carrying a wafer. As shown in FIGS. 1A and 1B, in the conventional wire-wound semiconductor package 9, the lead frame 1 includes a die pad 10 for carrying the wafer 90, a plurality of pins 12 at the edge of the block 10, and a plurality of pins 12 Each of the lead pins 12 has an outer lead portion 120 and an inner lead portion 121, and the outer leg portion 120 is electrically connected to an external circuit. (not shown). The wafer 90 utilizes a plurality of solders A bonding wire 900 is electrically connected to the inner leg 121 of the lead pin 12. The wafer 90, the seat portion 10, the power strip 11, the lead pins 12, and the bonding wires 900 are covered by a sealing material 91 made of an insulating material such as epoxy. In addition, FIG. 1B is a schematic cross-sectional view taken along line B-B of the lead frame 1 of FIG. 1A.
習知半導體封裝件9中，當有同電性需求時，會使用該電源條11連接該導腳12之設計，但當該電源條11長度越長時，該電源條11之變形量相對變大(如第1B’圖所示，該電源條11’下彎)，致使該些導腳12之整體平面度容易發生不平整之情況，而造成無法進行打線作業或低產量(Low Yield)之問題，因而無法符合產品需求。 In the conventional semiconductor package 9, when the power supply requirement is required, the power strip 11 is used to connect the design of the lead 12, but when the length of the power strip 11 is longer, the deformation amount of the power strip 11 is relatively changed. Large (as shown in FIG. 1B', the power strip 11' is bent down), so that the overall flatness of the guide pins 12 is prone to unevenness, which makes it impossible to perform wire bonding operations or low yield. The problem is therefore not in line with the product requirements.
因此，如何克服上述習知技術之問題，實已成目前亟欲解決的課題。 Therefore, how to overcome the above-mentioned problems of the prior art has become a problem that is currently being solved.
鑑於上述習知技術之種種缺失，本發明係揭露一種承載結構，係包括：一座部；複數導電部，係設於該座部周圍；至少一電源條，係設於該座部周圍；以及至少一支撐塊，係設於該電源條上。 In view of the above-mentioned various deficiencies of the prior art, the present invention discloses a load-bearing structure comprising: a portion; a plurality of conductive portions disposed around the seat; at least one power strip disposed around the seat; and at least A support block is disposed on the power strip.
本發明亦揭露一種承載結構之製法，係包括提供一座部，且該座部周圍設有複數導電部與至少一電源條；以及形成支撐塊於該電源條上。 The invention also discloses a method for manufacturing a load-bearing structure, comprising: providing a portion, wherein the seat portion is provided with a plurality of conductive portions and at least one power strip; and forming a support block on the power strip.
前述之承載結構及其製法中，該支撐塊係與該電源條一體成形。例如，利用化學蝕刻或機械沖壓之方式製作該些支撐塊。 In the foregoing load-bearing structure and method of manufacturing the same, the support block is integrally formed with the power strip. For example, the support blocks are fabricated by chemical etching or mechanical stamping.
本發明又揭露一種半導體封裝件，係包括：承載結構，係包含一座部、設於該座部周圍之複數導電部與至少一電源條、及設於該電源條上之至少一支撐塊；至少一半導體元件，係設於該座部上且電性連接該導電部與電源條；以及封裝材，係包覆該座部、導電部、電源條與半導體元件。 The present invention further discloses a semiconductor package comprising: a load-bearing structure comprising a portion, a plurality of conductive portions disposed around the portion and at least one power strip, and at least one support block disposed on the power strip; A semiconductor component is disposed on the seat and electrically connected to the conductive portion and the power strip; and the package material covers the seat portion, the conductive portion, the power strip, and the semiconductor component.
本發明另揭露一種半導體封裝件之製法，係包括：提供一承載結構，其包含一座部、設於該座部周圍之複數導電部與至少一電源條、及設於該電源條上之至少一支撐塊；設置至少一半導體元件於該座部上，且該半導體元件電性連接該導電部與電源條；以及形成封裝材於該承載結構上，以包覆該座部、導電部、電源條與半導體元件。 The invention further provides a method for fabricating a semiconductor package, comprising: providing a load-bearing structure comprising a portion, a plurality of conductive portions disposed around the portion, at least one power strip, and at least one disposed on the power strip a support block; at least one semiconductor component is disposed on the seat portion, and the semiconductor component is electrically connected to the conductive portion and the power strip; and the package material is formed on the load-bearing structure to cover the seat portion, the conductive portion, and the power strip With semiconductor components.
前述之半導體封裝件及其製法中，該半導體元件藉由複數導電元件電性連接該導電部與電源條。 In the above semiconductor package and method of manufacturing the same, the semiconductor component is electrically connected to the conductive portion and the power strip by a plurality of conductive elements.
前述之半導體封裝件及其製法中，該封裝材外露該支撐塊、或者該封裝材完全包覆該支撐塊。 In the foregoing semiconductor package and method of manufacturing the same, the package exposes the support block, or the package completely covers the support block.
前述之半導體封裝件與其製法及承載結構與其製法中，該承載結構係為導線架或覆晶基板。 In the foregoing semiconductor package, the manufacturing method and the supporting structure thereof, and the manufacturing method thereof, the bearing structure is a lead frame or a flip chip substrate.
前述之半導體封裝件與其製法及承載結構與其製法中，該承載結構具有複數該支撐塊，且該些支撐塊係以等距間隔方式或非等距間隔方式排設於該電源條上。 In the foregoing semiconductor package, the manufacturing method and the supporting structure thereof, the supporting structure has a plurality of the supporting blocks, and the supporting blocks are arranged on the power strip in an equidistantly spaced manner or in a non-equidistant interval manner.
前述之半導體封裝件與其製法及承載結構與其製法中，該支撐塊係電性連接該電源條。 In the foregoing semiconductor package, the manufacturing method and the supporting structure thereof, the supporting block is electrically connected to the power strip.
前述之半導體封裝件與其製法及承載結構與其製法中，該電源條係具有本體及連結該本體之至少一引腳。例 如，該支撐塊係設於該本體、引腳或其兩者上。 In the foregoing semiconductor package, the manufacturing method and the carrier structure thereof, the power strip has a body and at least one pin connecting the body. example For example, the support block is disposed on the body, the pin or both.
另外，前述之半導體封裝件與其製法及承載結構與其製法中，該承載結構復具有設於該座部周圍之接地部。 In addition, in the foregoing semiconductor package, the manufacturing method and the load-bearing structure thereof, and the manufacturing method, the load-bearing structure further has a ground portion disposed around the seat portion.
由上可知，本發明之半導體封裝件與其製法及承載結構與其製法，係藉由該些支撐塊之設計，以增強該電源條之機械強度，故相較於習知導線架，當該電源條長度越長時，本發明之電源條不易發生下彎或其它變形，因而能避免影響該承載結構之整體導電部之平面度。 It can be seen from the above that the semiconductor package of the present invention, the manufacturing method and the supporting structure thereof and the manufacturing method thereof are designed to enhance the mechanical strength of the power strip by using the support blocks, so that the power strip is compared with the conventional lead frame. The longer the length, the lower the power strip of the present invention is less likely to be bent or otherwise deformed, thereby avoiding affecting the flatness of the overall conductive portion of the load-bearing structure.
1‧‧‧導線架 1‧‧‧ lead frame
10、20‧‧‧座部 10, 20‧‧‧
11、11’、21、21’‧‧‧電源條 11, 11', 21, 21' ‧ ‧ power strips
12‧‧‧導腳 12‧‧‧ lead
120‧‧‧外腳部 120‧‧‧ outside foot
121‧‧‧內腳部 121‧‧‧foot
2、2’、2”‧‧‧承載結構 2, 2', 2" ‧ ‧ bearing structure
21a‧‧‧底側 21a‧‧‧ bottom side
210‧‧‧本體 210‧‧‧ body
211‧‧‧引腳 211‧‧‧ pin
22‧‧‧導電部 22‧‧‧Electrical Department
23、23’、23”、33‧‧‧支撐塊 23, 23’, 23”, 33‧‧‧ support blocks
24‧‧‧接地部 24‧‧‧ Grounding Department
3、3’、4、9‧‧‧半導體封裝件 3, 3', 4, 9‧‧‧ semiconductor packages
30、30’,40‧‧‧半導體元件 30, 30', 40‧‧‧ semiconductor components
300、400‧‧‧導電元件 300, 400‧‧‧ conductive elements
31、31’、91‧‧‧封裝材 31, 31', 91‧‧‧ packaging materials
90‧‧‧晶片 90‧‧‧ wafer
900‧‧‧銲線 900‧‧‧welding line
第1A圖係為習知導線架之平面底視示意圖；第1B圖係為習知半導體封裝件之剖面示意圖；第1B’圖係為第1A圖之C-C剖線之剖面示意圖；第2A至2B圖係為本發明之半導體封裝件之製法之示意圖；其中，第2A圖係為本發明之承載結構之平面底視示意圖，第2B圖係為第2A圖之A-A剖線之剖面圖，第2A’圖係為第2A圖的另一態樣，第2B’圖係為第2B圖的另一態樣；以及 第3圖係為本發明之半導體封裝件之另一實施例之剖面示意圖。 1A is a schematic plan view of a conventional lead frame; FIG. 1B is a schematic cross-sectional view of a conventional semiconductor package; FIG. 1B' is a cross-sectional view taken along line CC of FIG. 1A; 2A to 2B BRIEF DESCRIPTION OF THE DRAWINGS FIG. 2A is a schematic plan view of a carrier structure of the present invention, and FIG. 2B is a cross-sectional view taken along line AA of FIG. 2A, 2A. 'The figure is another aspect of FIG. 2A, and the 2B' figure is another aspect of FIG. 2B; Figure 3 is a cross-sectional view showing another embodiment of the semiconductor package of the present invention.
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。 The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.
須知，本說明書所附圖式所繪示之結構、比例、大小 等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“底”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。 It should be noted that the structure, proportion and size depicted in the drawings of this specification And the like, which are used for the understanding and reading of those skilled in the art, and are not intended to limit the implementation of the invention, and thus do not have technical significance, any structural modification, The change of the proportional relationship or the adjustment of the size should be within the scope of the technical content disclosed by the present invention without affecting the effects and the achievable effects of the present invention. In the meantime, the terms "upper", "bottom" and "one" are used in the description for the purpose of description, and are not intended to limit the scope of the invention. Adjustments, where there is no material change, are considered to be within the scope of the invention.
第2A至2B圖係為本發明之半導體封裝件3之製法的示意圖，其中，第2A係為本發明之承載結構2之平面底視示意圖。 2A to 2B are schematic views showing the manufacturing method of the semiconductor package 3 of the present invention, wherein the second embodiment is a plan bottom view of the load-bearing structure 2 of the present invention.
如第2A圖所示，所述之承載結構2係為導線架，其包括：一座部20、設於該座部20周圍之複數導電部22與複數電源條21、以及接觸結合該電源條21之複數支撐塊23,23’,23”,33。 As shown in FIG. 2A, the load-bearing structure 2 is a lead frame, and includes a base portion 20, a plurality of conductive portions 22 disposed around the seat portion 20, a plurality of power strips 21, and a contact strip of the power strip 21 The plurality of support blocks 23, 23', 23", 33.
所述之座部20係用以承載如晶片之半導體元件(圖略)。於本實施例中，該座部20之形狀係為矩形。 The seat portion 20 is used to carry a semiconductor component such as a wafer (not shown). In this embodiment, the shape of the seat portion 20 is a rectangle.
所述之導電部22係為導腳而位於該座部20之邊緣外，而所述之電源條21係為較該導腳寬之肋條。於本實施例中，該電源條21係具有一本體210及連結該本體210之引腳211。 The conductive portion 22 is a guide pin and is located outside the edge of the seat portion 20, and the power strip 21 is a rib wider than the guide pin. In the embodiment, the power strip 21 has a body 210 and a pin 211 connecting the body 210.
所述之支撐塊23,23’,23”,33係設於該本體210、引腳 211或其兩者上並電性連接該電源條21，且該支撐塊23,23’,23”,33之形狀係為幾何形體，如矩形、圓形等。於本實施例中，該些支撐塊23可以等距間隔方式直線排設於該電源條21上，或者該些支撐塊23’以非等距間隔方式直線排設於該電源條21上，又該電源條21上亦可僅具有單一該支撐塊23”。或者，如第2A’圖所示，該些支撐塊23以非直線方式排設於該電源條21上。 The support blocks 23, 23', 23", 33 are disposed on the body 210, pins The power strip 21 is electrically connected to the 211 or both of the power strips 21, and the shape of the support blocks 23, 23', 23", 33 is a geometric shape, such as a rectangle, a circle, etc. In the embodiment, the The support blocks 23 may be arranged in a straight line on the power strip 21 in an equidistant manner, or the support blocks 23' may be linearly arranged on the power strip 21 in a non-equally spaced manner, and the power strip 21 may be only There is a single support block 23". Alternatively, as shown in Fig. 2A', the support blocks 23 are arranged on the power strip 21 in a non-linear manner.
再者，該支撐塊23,23’,23”,33係與該電源條21,21’一體成形，例如利用化學蝕刻(Chemical Etching)或機械沖壓等方法製做本發明之承載結構2及該些支撐塊23,23’,23”,33。於其它實施例中，該支撐塊23,23’,23”,33亦可以黏貼方式結合至該電源條21,21’上。 Furthermore, the support blocks 23, 23', 23", 33 are integrally formed with the power strips 21, 21', and the load-bearing structure 2 of the present invention is fabricated by, for example, chemical etching or mechanical stamping. Some support blocks 23, 23', 23", 33. In other embodiments, the support blocks 23, 23', 23", 33 can also be adhesively bonded to the power strips 21, 21'.
又，該承載結構2復包括設於該座部20周圍之接地部24。於本實施例中，該接地部24之形狀係為環狀，且該接地部24與該座部20相連成一體，但於其它實施例中，該接地部24與該座部20可相分離。 Moreover, the load-bearing structure 2 further includes a ground portion 24 disposed around the seat portion 20. In this embodiment, the grounding portion 24 is annular in shape, and the grounding portion 24 is integrally connected with the seat portion 20. However, in other embodiments, the grounding portion 24 and the seat portion 20 are separable. .
另外，於另一實施例中，如第2A’圖所示，該承載結構2’係具有單一電源條21’。 Further, in another embodiment, as shown in Fig. 2A', the load-bearing structure 2' has a single power strip 21'.
本發明之承載結構2,2’係藉由該些支撐塊23,23’,23”,33之設計，以增強該電源條21,21’之機械強度，故當該電源條21,21’長度越長時，該電源條21,21’不易發生下彎或其它變形，因而該承載結構2,2’之整體導電部22之平面度能符合需求。 The bearing structure 2, 2' of the present invention is designed to enhance the mechanical strength of the power strips 21, 21' by the support blocks 23, 23', 23", 33, so when the power strips 21, 21' The longer the length, the lower the power strips 21, 21' are less likely to be bent or otherwise deformed, so that the flatness of the overall conductive portion 22 of the load-bearing structure 2, 2' can meet the requirements.
如第2B圖所示，接續第2A圖之製程，設置一半導體 元件30於該座部20上，且該半導體元件30電性連接該導電部22、接地部24與電源條21。接著，形成封裝材31於該承載結構2上，以包覆該座部20、導電部22、電源條21、接地部24與半導體元件30，以製成該半導體封裝件3。 As shown in FIG. 2B, following the process of FIG. 2A, a semiconductor is provided. The component 30 is on the seat 20 , and the semiconductor component 30 is electrically connected to the conductive portion 22 , the ground portion 24 , and the power strip 21 . Next, a package member 31 is formed on the carrier structure 2 to cover the seat portion 20, the conductive portion 22, the power strip 21, the ground portion 24, and the semiconductor element 30 to form the semiconductor package 3.
於本實施例中，該半導體元件30係以複數如銲線之導電元件300電性連接該導電部22、接地部24與電源條21，且該封裝材31係外露該支撐塊23。 In the present embodiment, the semiconductor device 30 is electrically connected to the conductive portion 22, the ground portion 24, and the power strip 21 by a plurality of conductive elements 300, such as solder wires, and the package member 31 exposes the support block 23.
再者，於另一實施例中，如第2B’圖所示之半導體封裝件3’，設置複數半導體元件30’(例如堆疊該些半導體元件30’)於該座部20上，且該封裝材31’完全包覆該支撐塊23。 Furthermore, in another embodiment, as shown in the semiconductor package 3' shown in FIG. 2B', a plurality of semiconductor elements 30' (for example, stacked semiconductor elements 30') are disposed on the seat portion 20, and the package is The material 31' completely covers the support block 23.
又，於另一實施例中，如第3圖所示之半導體封裝件4，該承載結構2”係為覆晶基板，且該半導體元件40係以複數如覆晶凸塊之導電元件400電性連接該導電部22、接地部24與電源條21。 In another embodiment, as shown in FIG. 3, the semiconductor package 4 is a flip-chip substrate, and the semiconductor device 40 is electrically connected to a plurality of conductive members 400 such as flip-chip bumps. The conductive portion 22, the ground portion 24, and the power strip 21 are connected.
本發明之半導體封裝件3,3’,4，係藉由該些支撐塊23,23’,23”,33設於該電源條21之底側21a上，以增強該電源條21,21’之機械強度，使該電源條21,21’不易發生下彎或其它變形，因而該承載結構2,2’,2”之整體導電部22之平面度能符合需求，故該半導體元件30,30’,40能順利進行打線或覆晶作業，使該些導電元件300,400能有效電性連接至該導電部22與電源條21,21’，以提高產量，致使滿足產品需求。 The semiconductor packages 3, 3', 4 of the present invention are provided on the bottom side 21a of the power strip 21 by the support blocks 23, 23', 23", 33 to enhance the power strips 21, 21' The mechanical strength makes the power strips 21, 21' less likely to be bent or otherwise deformed, so that the flatness of the integral conductive portion 22 of the load-bearing structure 2, 2', 2" can meet the requirements, so the semiconductor component 30, 30 ', 40 can smoothly perform wire bonding or flip chip operation, so that the conductive elements 300, 400 can be electrically connected to the conductive portion 22 and the power strips 21, 21' to increase the yield, so as to meet the product requirements.
本發明提供一種半導體封裝件3,3’,4，其包括：一承 載結構2,2’,2”、設於該承載結構2,2’,2”上之至少一半導體元件30,30’,40、以及包覆該半導體元件30,30’,40之封裝材31,31’。 The present invention provides a semiconductor package 3, 3', 4 comprising: a bearing Carrier structure 2, 2', 2", at least one semiconductor component 30, 30', 40 disposed on the carrier structure 2, 2', 2", and a package covering the semiconductor component 30, 30', 40 31, 31'.
所述之承載結構2,2’,2”係可如第2及2’圖所示之態樣，其可應用於四方平面無引腳封裝(Quad Flat No leads,QFN)或四方扁平封裝(Quad Flat Package,QFP)，且該支撐塊23,23’,23”,33係接觸結合該電源條21,21’之底側21a。 The bearing structure 2, 2', 2" can be applied to the Quad Flat No leads (QFN) or the quad flat package (as shown in Figures 2 and 2'). Quad Flat Package (QFP), and the support blocks 23, 23', 23", 33 are in contact with the bottom side 21a of the power strips 21, 21'.
所述之半導體元件30,30’係如晶片，其設於該座部20上且藉由複數導電元件300,400電性連接該導電部22、接地部24與電源條21,21’。 The semiconductor device 30, 30' is a wafer, and is disposed on the seat portion 20 and electrically connected to the conductive portion 22, the ground portion 24, and the power strips 21, 21' by a plurality of conductive members 300, 400.
所述之封裝材31,31’復包覆該導電元件300,400、座部20、導電部22與電源條21，且該封裝材31外露該支撐塊23,23’,23”,33；或者，該封裝材31完全包覆該支撐塊23,23’,23”,33。 The package member 31, 31' overlies the conductive member 300, 400, the seat portion 20, the conductive portion 22 and the power strip 21, and the package member 31 exposes the support block 23, 23', 23", 33; The package material 31 completely covers the support blocks 23, 23', 23", 33.
綜上所述，本發明之半導體封裝件與其製法及承載結構與其製法，主要藉由該支撐塊設於該電源條上，以增強該電源條之機械強度，使該電源條不易發生下彎或其它變形，因而該承載結構之整體導電部之平面度能符合需求，以利於後續打線製程，俾能提高產量，而滿足產品需求。 In summary, the semiconductor package of the present invention, the manufacturing method thereof and the supporting structure thereof are mainly provided on the power strip by the support block to enhance the mechanical strength of the power strip, so that the power strip is less likely to be bent or Other deformations, so that the flatness of the overall conductive portion of the load-bearing structure can meet the demand, so as to facilitate the subsequent wire-laying process, and can improve the output, and meet the product demand.
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。 The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.
2‧‧‧承載結構 2‧‧‧bearing structure
20‧‧‧座部 20‧‧‧s
21‧‧‧電源條 21‧‧‧Power strip
21a‧‧‧底側 21a‧‧‧ bottom side
22‧‧‧導電部 22‧‧‧Electrical Department
23‧‧‧支撐塊 23‧‧‧Support block
24‧‧‧接地部 24‧‧‧ Grounding Department
3‧‧‧半導體封裝件 3‧‧‧Semiconductor package
30‧‧‧半導體元件 30‧‧‧Semiconductor components
300‧‧‧導電元件 300‧‧‧Conducting components
31‧‧‧封裝材 31‧‧‧Package
Claims (34)
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| TW103100153A TWI566357B (en) | 2014-01-03 | 2014-01-03 | Semiconductor package and its manufacturing method and its bearing structure and manufacturing method thereof |
| CN201410011290.XA CN104766852B (en) | 2014-01-03 | 2014-01-10 | Semiconductor package and its manufacturing method and its carrying structure and its manufacturing method |
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| TW103100153A TWI566357B (en) | 2014-01-03 | 2014-01-03 | Semiconductor package and its manufacturing method and its bearing structure and manufacturing method thereof |
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| TW201528465A TW201528465A (en) | 2015-07-16 |
| TWI566357B true TWI566357B (en) | 2017-01-11 |
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| TW200705519A (en) * | 2005-07-19 | 2007-02-01 | Siliconware Precision Industries Co Ltd | Semiconductor package without chip carrier and fabrication method thereof |
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| US6882035B2 (en) * | 2003-07-09 | 2005-04-19 | Agilent Technologies, Inc. | Die package |
| US7087986B1 (en) * | 2004-06-18 | 2006-08-08 | National Semiconductor Corporation | Solder pad configuration for use in a micro-array integrated circuit package |
| US7816186B2 (en) * | 2006-03-14 | 2010-10-19 | Unisem (Mauritius) Holdings Limited | Method for making QFN package with power and ground rings |
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| CN104766852B (en) | 2017-10-03 |
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