TWI553618B - Liquid crystal display device and display device - Google Patents

Description

Liquid crystal display and display

The present invention relates to a liquid crystal display and display.

A buffer amplifier in a data drive circuit of a display such as a liquid crystal display is usually driven with a large bias current to provide a strong thrust so that the data voltage of each output can reach the target data voltage faster, thereby correspondingly The target data voltage can be quickly written to the load capacitors (such as liquid crystal capacitors) of each column by multiple data lines.

For displays that use the column inversion drive mode, when displaying a single grayscale picture, the buffer amplifier provides the same data voltage to the load capacitors in the same column that are connected. Moreover, the buffer amplifier has the property that after the output ground voltage is pushed to the target data voltage, the target data voltage of the output is not changed, and the buffer amplifier does not actually need a large thrust.

However, in the display of the column inversion driving mode, when each single gray scale picture is displayed, each buffer amplifier first supplies a data voltage to a part of the load capacitance of each column, and then drives with a larger bias current, and then each When the same data voltage is supplied to the rest of the load capacitors in the same column, the same large bias current is used for driving, which results in waste of electric energy.

In view of this, it is necessary to provide a liquid crystal display with less power consumption.

In view of this, it is necessary to provide a display that is more energy efficient.

A liquid crystal display comprising: a liquid crystal display panel comprising a plurality of display units and a plurality of data lines for transmitting data voltages to said plurality of display units; a timing control circuit, said timing control circuit receiving image signals and corresponding to said image signals Providing image data and a timing signal, the timing control circuit further determining, according to the image signal, whether the picture pre-displayed by the liquid crystal display panel is a single gray-scale picture; a common voltage generating circuit, the common voltage generating circuit providing a common voltage to the plurality a display unit; and a data driving circuit, wherein the data driving circuit converts the image data into a corresponding data voltage, and outputs the data voltage to the plurality of display units by the plurality of data lines to define a data voltage greater than or equal to the common voltage For the positive data voltage, a data voltage smaller than the common voltage is defined as a negative data voltage. For a display unit connected to the same data line, the data driving circuit provides a data voltage of the same polarity, and the data driving circuit according to the timing The judgment result of the control circuit Selecting to drive with a first bias current or a second bias current to output a received data voltage, the first bias current being greater than the second bias current; wherein, when the timing control circuit determines that the pre-display is known When the picture is a single gray scale picture, the timing control circuit outputs a first control signal to the data driving circuit, and the data driving circuit selects to drive the first bias current according to the first control signal to output the received data voltage. a predetermined time, after the predetermined time is reached, the data driving circuit next selects to drive with a second bias current to output the received data voltage for driving the plurality of display units to display the single grayscale image, wherein At the latest when the predetermined time is reached, the data voltage output by the data driving circuit reaches a predetermined target data voltage, and the predetermined target data voltage is at least 85% of the data voltage received by the complex buffer amplifier.

A display comprising: a display panel comprising a plurality of display units and a plurality of data lines for transmitting data voltages to the plurality of display units; a timing control circuit, the timing control circuit receives the image signals, and provides a map according to the image signals The image control circuit further determines, according to the image signal, whether the picture pre-displayed by the display panel is a single gray-scale picture; the common voltage generating circuit, the common voltage generating circuit provides a common voltage to the plurality of display units; And a data driving circuit, wherein the data driving circuit converts the image data into a corresponding data voltage, and outputs the data voltage to the plurality of display units by the plurality of data lines, and defines a data voltage greater than or equal to the common voltage to be positive polarity a data voltage, wherein the data voltage smaller than the common voltage is a negative data voltage, and for a display unit connected to the same data line, the data driving circuit provides a data voltage of the same polarity, and the data driving circuit controls the circuit according to the timing Judging result corresponding selection The bias current or the second bias current is driven to output the received data voltage, the first bias current is greater than the second bias current; wherein, when the timing control circuit determines that the pre-displayed picture is a single gray In the step mode, the timing control circuit outputs a first control signal to the data driving circuit, and the data driving circuit selects to drive the first bias current according to the first control signal to output the received data voltage for a predetermined time. After the predetermined time is reached, the data driving circuit next selects to drive with a second bias current to output the received data voltage for driving the plurality of display units to display the single grayscale image, wherein the latest grayscale image is reached. At the predetermined time, the data voltage output by the data driving circuit reaches a predetermined target data voltage, and the predetermined target data voltage is at least 85% of the data voltage received by the complex buffer amplifier.

A liquid crystal display comprising: a liquid crystal display panel comprising a plurality of display units and a plurality of data lines for transmitting data voltages to said plurality of display units; timing control circuit The timing control circuit receives the image signal, and provides image data and timing signals according to the image signal. The timing control circuit further determines, according to the image signal, a gray scale pre-displayed by the display unit connected to the same data line. Whether the same; a common voltage generating circuit, the common voltage generating circuit supplies a common voltage to the plurality of display units; and a data driving circuit, wherein the data driving circuit converts the image data into corresponding data voltages, and the plurality of data lines Outputting the data voltage to the plurality of display units, defining a data voltage greater than or equal to the common voltage as a positive data voltage, defining a data voltage smaller than the common voltage as a negative data voltage, and displaying a display unit connected to the same data line The data driving circuit provides a data voltage of the same polarity, the data driving circuit includes a plurality of buffer amplifiers connected in one-to-one correspondence with the plurality of data lines, the complex buffer amplifier receiving the converted data voltage, and controlling the circuit according to the timing The judgment result correspondingly selects the first bias The current or the second bias current is driven to output the received data voltage for driving the display screen of the plurality of display units, the first bias current is greater than the second bias current; wherein, when the timing control circuit determines When it is known that the gray scales of the pre-displayed display units connected to the same data line are the same, the timing control circuit outputs the first control signal to the data driving circuit, and the same data line and the display unit with the same gray level are pre-displayed. The connected buffer amplifier is driven by the first bias current according to the first control signal to output the received data voltage for a predetermined time. After the predetermined time is reached, the second bias current is selected to be driven. Outputting the received data voltage for driving the display unit connected to the same data line and pre-displaying the same gray level to display the same gray level, wherein the same data line is reached at the latest by the same data line Pre-displaying the data voltage output by the buffer amplifier connected to the display unit with the same gray scale reaches the predetermined target data voltage, the pre-predetermined Target data voltage for at least 85% of the plurality of buffer amplifier of the received data voltage.

A display comprising: a display panel comprising a plurality of display units and a plurality of data lines for transmitting data voltages to the plurality of display units; a timing control circuit, the timing control circuit receives the image signals, and provides a map according to the image signals The image control circuit further determines, according to the image signal, whether the gray level pre-displayed by the display unit connected to the same data line is the same; the common voltage generating circuit, the common voltage generating circuit provides a common voltage to the plurality a display unit; and a data driving circuit, wherein the data driving circuit converts the image data into a corresponding data voltage, and outputs the data voltage to the plurality of display units by the plurality of data lines to define a data voltage greater than or equal to the common voltage For the positive data voltage, a data voltage smaller than the common voltage is defined as a negative data voltage. For a display unit connected to the same data line, the data driving circuit provides a data voltage of the same polarity, and the data driving circuit includes Multiple data lines one-to-one correspondence a buffer amplifier, the complex buffer amplifier receives the converted data voltage, and according to the judgment result of the timing control circuit, selects to use the first bias current or the second bias current to drive to output the received data voltage, And driving the plurality of display unit display screens, wherein the first bias current is greater than the second bias current; wherein, when the timing control circuit determines that there is a gray level of the display unit that is connected to the same data line The timing control circuit outputs a first control signal to the data driving circuit, and the buffer amplifier connected to the display unit with the same gray level by the same data line is driven by the first bias current according to the first control signal. And outputting the received data voltage for a predetermined time. After the predetermined time is reached, the second bias current is selected to be driven to output the received data voltage for driving and connecting with the same data line. A display unit displaying the same gray scale displays the same gray scale, wherein the predetermined time is reached at the latest, With the same data line and said pre-amplifier is the same gray level in the display buffer of the display unit is connected to the output The data voltage reaches a predetermined target data voltage, and the predetermined target data voltage is at least 85% of the data voltage received by the complex buffer amplifier.

Since the liquid crystal display displays a single gray scale picture, the buffer amplifier selects to drive the first bias current to output the received data voltage for the predetermined time, and after the predetermined time is reached, the buffer amplifier next selects Driving a second bias current that is less than the first bias current to output the received data voltage, wherein, at the latest, the predetermined voltage is output, the data voltage output by the complex buffer amplifier reaches a predetermined target data voltage, thereby Save energy.

1‧‧‧LCD display

10‧‧‧LCD panel

20‧‧‧Sequence Control Circuit

30‧‧‧Data Drive Circuit

40‧‧‧Scan drive circuit

50‧‧‧Common voltage generating circuit

Vcom‧‧‧Common voltage

Vd‧‧‧ data voltage

G1~Gm‧‧‧ scan line

D1~Dn‧‧‧ data line

15‧‧‧Display unit

350‧‧‧film transistor

C1‧‧‧Liquid Crystal Capacitor

C2‧‧‧ storage capacitor

G‧‧‧ gate

S‧‧‧ source

D‧‧‧汲

200‧‧‧ source

301‧‧‧Transition circuit

303‧‧‧ Bias circuit

305‧‧‧Buffer amplifier

T1~Tk, t1‧‧‧ time period

N1‧‧‧ first control signal

N2‧‧‧second control signal

1 is a block diagram showing a preferred embodiment of a liquid crystal display of the present invention.

2 is a block diagram showing the structure of a data driving circuit of the liquid crystal display shown in FIG. 1.

3 is a waveform diagram of a data voltage applied to a display unit connected to a data line when the liquid crystal display panel of the liquid crystal display shown in FIG. 1 displays a single gray scale screen.

4 is a waveform diagram of a data voltage applied to a display unit connected to a data line by a data driving circuit when the liquid crystal display panel of the liquid crystal display shown in FIG. 1 displays a non-single gray scale screen.

The invention will be further described in detail below with reference to the accompanying drawings. This embodiment is described by taking a liquid crystal display driven by a column inversion driving method as an example, and the present invention can also be applied to other suitable types of displays.

Please refer to FIG. 1. FIG. 1 is a block diagram showing the first embodiment of a liquid crystal display according to the present invention. intention. The liquid crystal display 1 includes a liquid crystal display panel 10, a timing control circuit 20, a data driving circuit 30, a scan driving circuit 40, and a common voltage generating circuit 50. The timing control circuit 20 is connected to the data driving circuit 30 and the scan driving circuit 40, respectively. The scan driving circuit 40 is connected to the liquid crystal display panel 10. The common voltage generating circuit 50 is connected to the liquid crystal display panel 10.

The common voltage generating circuit 50 supplies a common voltage Vcom to the liquid crystal display panel 10.

The liquid crystal display panel 10 includes a plurality of scanning lines G1 to Gm, a plurality of data lines D1 to Dn insulated from the complex scanning lines G1 to Gm, and a plurality of display units 15, wherein m and n are positive integers. Each display unit 15 is located at an insulated intersection of a scan line Gm and a data line Dn. The plurality of scanning lines G1 to Gm are connected to the scan driving circuit 40. The plurality of data lines D1 to Dn are connected to the data driving circuit 30. Each display unit 15 includes a Thin Film Transistor (TFT) 350, a liquid crystal capacitor C1, and a storage capacitor C2. The liquid crystal capacitor C1 is connected in parallel with the storage capacitor C2 for storing electric charge. Each of the TFTs 350 includes a gate G, a source S, and a drain D. The gate G is connected to the scan line Gm, the source S is connected to the data line D _1n , and the drain D and the liquid crystal capacitor C1 are connected to one end of the storage capacitor C2. The liquid crystal capacitor C1 and the other end of the storage capacitor C2 are connected to the common voltage generating circuit 50, and receive the common voltage Vcom.

The timing control circuit 20 receives an image signal of a signal source 200, and provides a plurality of image data (eg, RGB three primary color image data) and a horizontal direction timing signal to the data driving circuit 30 according to the image signal. The direction timing signal is given to the scan driving circuit 40. The timing control circuit 20 further determines, according to the image signal, whether the picture pre-displayed by the liquid crystal display panel 10 is a single gray-scale picture, and correspondingly outputs the first control signal N1 or the second control signal N2 to the data drive according to the determination result. The circuit 30. Specifically, when the timing control circuit 20 determines that the pre-displayed picture of the liquid crystal display panel 10 is a single gray-scale picture according to the image signal, the timing control circuit 20 outputs the first control signal N1 to the data driving circuit 30; When the timing control circuit 20 determines that the picture pre-displayed by the liquid crystal display panel 10 is a non-single gray scale picture according to the image signal, the timing control circuit 20 outputs the second control signal N2 to the data driving circuit 30.

The scan driving circuit 40 receives the vertical direction timing signal, and sequentially outputs the scan signal to the complex scan lines G1 G Gm according to the vertical direction timing signal to activate the horizontal column display units 15 connected to the plurality of scan lines G1 G Gm. .

The data driving circuit 30 receives the plurality of image data and the horizontal direction timing signal, converts the complex image data into a corresponding complex data voltage Vd, and outputs the plurality of data lines D1 to Dn according to the horizontal direction timing signal. The complex data voltage Vd is given to the complex display unit 15.

A data voltage Vd that is greater than or equal to the common voltage Vcom is defined as a positive polarity data voltage, and a data voltage Vd that is less than the common voltage Vcom is defined as a negative polarity data voltage. Since the liquid crystal display 1 is driven by the column inversion driving method, the data driving circuit 30 supplies the data voltage Vd having the same polarity for the display unit 15 connected to the same data line Dn.

Please refer to FIG. 2 together. FIG. 2 is a schematic structural diagram of a circuit block of the data driving circuit 30. The data driving circuit 30 includes a conversion circuit 301, at least one bias circuit 303, and a complex buffer amplifier 305. The conversion circuit 301 is connected to the timing control circuit 20 and the complex buffer amplifier 305, respectively. The complex buffer amplifiers 305 are respectively connected in one-to-one correspondence with the plurality of data lines D1 to Dn. Each buffer amplifier 305 is further coupled to the timing control circuit 20 by a bias circuit 303. In this embodiment, the at least A number of bias circuits 303 are two, and each bias circuit 303 is connected to a portion of the buffer amplifier 305. However, in other embodiments, the number of the at least one biasing circuit 303 may also be one, three or more, even the same as the number of the complex buffer amplifiers 305.

The conversion circuit 301 receives the complex image data and the horizontal direction timing signal, converts the received complex image data into a corresponding complex data voltage Vd, and outputs the complex data voltage Vd to the complex buffer according to the horizontal direction timing signal. Amplifier 305.

The bias circuit 303 receives the first control signal N1 or the second control signal N2 from the timing control circuit 20, and selects and outputs the first bias voltage according to the received first control signal N1 or the second control signal N2. Or a second bias voltage is applied to the complex buffer amplifier 305. Specifically, when the timing control circuit 20 determines that the pre-displayed picture of the liquid crystal display panel 10 is a single gray-scale picture according to the image signal, the timing control circuit 20 outputs the first control signal N1 to each of the bias circuits 303. When the bias circuit 303 receives the first control signal N1, the bias circuit 303 selects to output the first bias voltage to the connected buffer amplifier 305 for a predetermined time according to the first control signal N1; After the predetermined time is reached, the bias circuit 303 next selects to output a second bias voltage to the connected buffer amplifier 305; when the timing control circuit 20 determines that the liquid crystal display panel 10 is pre-displayed according to the image signal When the picture is a non-single gray scale picture, the timing control circuit 20 outputs a second control signal N2 to each of the bias circuits 303. When the bias circuit 303 receives the second control signal N2, the corresponding selection is provided. The two bias voltages are applied to the coupled buffer amplifier 305. The first bias voltage is greater than the second bias voltage.

The complex buffer amplifier 305 receives the complex data voltage Vd and the voltage from the bias voltage a first bias voltage or a second bias voltage of the path 303, and correspondingly generating a first bias current or a second bias current according to the received first bias voltage or the second bias voltage to amplify the driving capability, The plurality of data lines D1 to Dn are driven to write the complex data voltage Vd to the liquid crystal capacitor C1 and the storage capacitor C2 connected to the activated TFT 350 to drive the liquid crystal display panel 10 to display a corresponding gray scale picture. Preferably, the complex buffer amplifier 305 has the same circuit structure, which are respectively operational amplifiers. The buffer amplifier 305 receiving the first bias voltage correspondingly generates a first bias current, and the buffer amplifier 305 receiving the second bias voltage correspondingly generates a second bias current, the first bias current being greater than the second bias current Current.

Referring to FIG. 3-4 together, FIG. 3 is a waveform diagram of the data voltage Vd applied to the display unit 15 connected to a data line Dn when the liquid crystal display panel 10 displays a single gray scale screen. . 4 is a waveform diagram of the data voltage Vd applied to the display unit 15 connected to a data line Dn when the liquid crystal display panel 10 displays a non-single gray scale screen. The time period T1~Tk (k is a positive integer) shown in FIG. 3-4 is the time when the partial display unit 15 is sequentially activated, and the data driving circuit 30 applies the data voltage Vd to each partial display unit 15. Since the liquid crystal display 1 is driven by the column inversion driving mode, when the liquid crystal display panel 10 displays a single gray scale screen, the data driving circuit 30 is applied to each display unit 15 connected to the same data line Dn. The same data voltage Vd is as shown in FIG. 3; when the liquid crystal display panel 10 displays a non-single grayscale image, at least one data line Dn is present, and the data driving circuit 30 is applied to each of the data lines Dn. The data voltages Vd of the display unit 15 are not all the same, as shown in FIG. Since the voltage change is a gradual process, a target voltage undergoes a series of transition voltages between the two target voltages in the process of changing to another voltage of different magnitude, and the waveform is as shown in the time zone of FIG. 3-4. T1 is shown.

The operation principle of the liquid crystal display 1 is as follows: when the timing control circuit 20 determines that the screen pre-displayed by the liquid crystal display panel 10 is a single gray scale screen according to the image signal, the timing control circuit 20 outputs the first control signal N1. Each of the bias circuits 303 is supplied to the conversion circuit 301. The conversion circuit 301 converts the received image data into a corresponding data voltage Vd, and outputs the converted data voltage Vd to the complex buffer amplifier 305. Each of the bias circuits 303 selects to output a first bias voltage to the connected buffer amplifier 305 for a predetermined time according to the first control signal N1. The complex buffer amplifier 305 receives the first bias voltage and the data voltage Vd. The complex buffer amplifier 305 generates a first bias current under the action of the first bias voltage to drive the output of the received data voltage Vd to the plurality of data lines D1 D Dn, after the predetermined time is reached. Each bias circuit 303 next selects to output a second bias voltage to the connected buffer amplifier 305. The complex buffer amplifier 305 generates a second bias current under the second bias voltage to drive the output. The received data voltage Vd is given to the plurality of data lines D1 to Dn, thereby driving the complex display unit 15 to display the single gray scale picture. The material voltage output by the complex buffer amplifier 305 reaches the predetermined target data voltage at the latest when the predetermined time is reached. In this embodiment, the predetermined target data voltage is at least 85%, preferably 90% to 95%, of the data voltage received by the complex buffer amplifier 305. In other embodiments, the predetermined target data voltage may also be the same as the data voltage received by the complex buffer amplifier 305. Preferably, the predetermined time is a time when the display unit 15 is activated each time, as shown in FIG. The predetermined time may also be a time when the adjacent two horizontal columns or the plurality of horizontal column display units 15 are activated in succession.

When the timing control circuit 20 determines the liquid crystal display panel 10 based on the image signal When the pre-displayed picture is a non-single grayscale picture, the timing control circuit 20 outputs a second control signal N2 to each of the bias circuits 303, and outputs corresponding image data to the conversion circuit 301. The conversion circuit 301 converts the received image data into a corresponding data voltage Vd, and outputs the converted data voltage Vd to the complex buffer amplifier 305. For the complex display unit 15, each bias circuit 303 selects and outputs a second bias voltage to the connected buffer amplifier 305 according to the second control signal N2, and the complex buffer amplifier 305 receives the second bias voltage and the The data voltage Vd generates a second bias current under the action of the second bias voltage to drive the output of the received data voltage Vd to the plurality of data lines D1 D Dn, thereby driving the complex display unit 15 to display the non- A single grayscale picture.

Since for a single gray scale picture, the buffer amplifier 305 of the liquid crystal display 1 is selected to be driven by the first bias current to output the received data voltage Vd for the predetermined time, and after the predetermined time is reached, the liquid crystal display The buffer amplifier 305 of 1 next selects to drive with a second bias current less than the first bias current to output the received data voltage Vd, wherein the complex buffer amplifier 305 outputs at the latest when the predetermined time is reached. The data voltage reaches a predetermined target data voltage, and the predetermined target data voltage is at least 85% of the data voltage received by the complex buffer amplifier 305, thereby saving power.

The present invention is not limited to the above embodiments. For example, the timing control circuit 20 does not detect whether the pre-displayed picture is a single grayscale picture, but determines the display unit connected to the same data line Dn according to the image signal. 15 is the same gray level of the pre-display, correspondingly, when the timing control circuit 20 determines that there is the same gray level pre-displayed by the display unit 15 connected to the same data line Dn, the timing control circuit 20 outputs the first control The signal N1 is given to the data driving circuit 30 by the same data line Dn and pre-display The buffer amplifier 305 connected to the display unit 15 having the same gray scale is driven by the first bias current according to the first control signal N1 to output the received data voltage Vd for the predetermined time. After the predetermined time is reached, Then, the second bias current is selected to be driven to output the received data voltage Vd, thereby driving the display unit 15 connected to the same data line Dn and pre-displaying the same gray scale to display the same gray scale. The data voltage output by the buffer amplifier 305 connected to the display unit 15 having the same pre-display gray scale by the same data line Dn reaches the predetermined target data voltage at the latest when the predetermined time is reached.

When the timing control circuit 20 determines that the gray level pre-displayed by the display unit 15 connected to the same data line Dn is different, the timing control circuit 20 outputs the second control signal N2 to the data driving circuit 30, and displays the current During the picture period, the buffer amplifier 305 connected to the display unit 15 different in pre-display gray scale by the same data line Dn is driven by the second bias current according to the second control signal N2 to output the received data voltage Vd. Thereby, the display unit 15 connected to the same data line Dn and pre-displayed with different gray levels is driven to display the corresponding gray scale.

Specifically, when the timing control circuit 20 determines that the gray level pre-displayed by the display unit 15 connected to the same data line Dn is the same, the timing control circuit 20 outputs the first control signal N1 to the same data. The line Dn is connected to the display unit 15 having the same gray level as the pre-displayed bias circuit 303. The bias circuit 303 selects to output the first bias voltage to the same data line according to the first control signal N1. The buffer amplifier 303 connected to the display unit 15 having the same gray level is pre-displayed for the predetermined time, so that the buffer amplifier 305 connected to the display unit 15 having the same pre-display gray scale by the same data line Dn is correspondingly generated first. The bias current is output to output the received data voltage Vd, and after the predetermined time is reached, the bias circuit 303 next selects the output The second bias voltage is applied to the buffer amplifier 305 connected to the display unit 15 having the same gray level by the same data line Dn, so that the same data line Dn is displayed on the same display unit 15 as the pre-display gray scale. The connected buffer amplifier 305 generates a second bias current to output the received data voltage Vd.

When the timing control circuit 20 determines that the gray scales pre-displayed by the display unit 15 connected to the same data line Dn are different, the timing control circuit 20 outputs the second control signal N2 to the same data line Dn and Pre-displaying a bias circuit 303 connected to the display unit 15 having different gray levels, during the display of the current picture, the bias circuit 303 selects to output a first bias voltage according to the second control signal N2 to the same The buffer amplifier 305, which is connected to the display unit 15 different in pre-display gray scale, causes the buffer amplifier 305 connected to the display unit 15 different in pre-display gray scale to generate the first bias correspondingly by the same data line Dn. The current is applied to output the received data voltage Vd.

The number of the at least one biasing circuit 303 is preferably the same as the number of the complex buffer amplifiers 305.

When the number of the at least one biasing circuit 303 is less than the number of the plurality of buffer amplifiers 305, if there are a plurality of buffer amplifiers 305 connected to the same biasing circuit 303, the same biasing circuit 303 may receive the same simultaneously. a control signal N1 and a second control signal N2. Therefore, in order to distinguish which buffer amplifier 305 corresponds to the first control signal N1 and the second control signal N2, the timing control circuit 20 also needs to provide the first control signal N1 and The second control signal N2 corresponds to which of the buffer amplifiers 305 respectively to the bias circuit 303, so that the buffer amplifier 305 selects the corresponding first bias current or the second bias current to drive.

In summary, the present invention complies with the requirements of the invention patent and submits a patent application according to law. but The above is only the preferred embodiment of the present invention, and the scope of the present invention is not limited to the above-described embodiments, and equivalent modifications or changes made by those skilled in the art to the spirit of the present invention should be It is covered by the following patent application.

20‧‧‧Sequence Control Circuit

30‧‧‧Data Drive Circuit

Vd‧‧‧ data voltage

D1~Dn‧‧‧ data line

301‧‧‧Transition circuit

303‧‧‧ Bias circuit

305‧‧‧Buffer amplifier

N1‧‧‧ first control signal

N2‧‧‧second control signal

Claims (30)

A liquid crystal display comprising: a liquid crystal display panel comprising a plurality of display units and a plurality of data lines for transmitting data voltages to said plurality of display units; a timing control circuit, said timing control circuit receiving image signals and corresponding to said image signals Providing image data and a timing signal; a common voltage generating circuit, the common voltage generating circuit supplies a common voltage to the plurality of display units; and a data driving circuit, wherein the data driving circuit converts the image data into corresponding data voltages, and according to the Whether the pre-displayed picture of the liquid crystal display panel is a single gray scale picture, correspondingly selecting to be driven by the first bias current or the second bias current, and outputting the converted data voltage to the plurality of display units by the plurality of data lines, The first bias current is greater than the second bias current, and the data voltage defining the common voltage is a positive data voltage, and the data voltage smaller than the common voltage is a negative data voltage for the same data line. Connected display unit, the data drive circuit provides the same polarity a material voltage; wherein, when the pre-displayed picture is a single gray scale picture, the data driving circuit selects to drive the first bias current to output the converted data voltage for a predetermined time, after the predetermined time is reached The data driving circuit next selects to drive with a second bias current to output the converted data voltage for driving the plurality of display units to display the single grayscale image, wherein the data is reached at the latest at the latest time. The data voltage outputted by the driving circuit reaches a predetermined target data voltage, and the predetermined target data voltage is at least 85% of the data voltage converted by the data driving circuit. The liquid crystal display according to claim 1, wherein the predetermined target data voltage is at least the capital The material voltage of the material drive circuit is 90%~95%. The liquid crystal display according to any one of the preceding claims, wherein the timing control circuit determines, according to the image signal, whether the picture pre-displayed by the liquid crystal display panel is a single gray scale picture, and the data driving circuit is based on the timing The determination result of the control circuit is driven by using the first bias current or the second bias current to output the converted data voltage to the plurality of display units by the plurality of data lines, and the timing control circuit determines that the pre-determination is When the displayed picture is a single gray scale picture, the timing control circuit outputs a first control signal to the data driving circuit to control the data driving circuit to select and use the first bias current and the second bias current to drive and output the conversion. After the data voltage. The liquid crystal display according to claim 3, wherein the data driving circuit comprises at least one bias circuit and a plurality of buffer amplifiers, each buffer amplifier is connected to a bias circuit and a data line, the at least one bias circuit Connected to the timing control circuit, the complex buffer amplifier receives the converted data voltage, and the at least one bias circuit selectively outputs the first bias voltage or the second bias voltage according to the determination result of the timing control circuit. The buffer amplifier is such that the complex buffer amplifier generates a first bias current or a second bias current to drive the output of the received data voltage. The liquid crystal display according to claim 4, wherein when the pre-displayed picture is a single grayscale picture, the timing control circuit outputs the first control signal to each bias circuit, and each bias circuit selects First outputting a first bias voltage to the connected buffer amplifier for the predetermined time, so that the complex buffer amplifier generates a first bias current to output the received data voltage, and after reaching the predetermined time, each bias voltage The circuit then selects to output a second bias voltage to the connected buffer amplifier, so that the complex buffer amplifier generates a second bias current to output the received data voltage for driving the complex display unit to display the single gray scale picture. Wherein the first bias voltage is greater than the second bias voltage. The liquid crystal display according to claim 3, wherein when the timing control circuit determines that the pre-display is known When the screen is a non-single grayscale screen, the timing control circuit outputs a second control signal to the data driving circuit. For the plurality of display units, the data driving circuit selects a second bias current according to the second control signal. Driving is performed to output the received data voltage for driving the plurality of display units to display the non-single grayscale picture. The liquid crystal display according to claim 4, wherein when the timing control circuit determines that the pre-displayed picture is a non-single grayscale picture, the timing control circuit outputs the second control signal to each of the bias circuits. For the complex display unit, each bias circuit selects and outputs a second bias voltage to the connected buffer amplifier, so that the complex buffer amplifier generates a first bias current to output the received data voltage for driving. The complex display unit displays the non-single grayscale picture. The liquid crystal display according to claim 1, wherein the liquid crystal display further comprises a scan driving circuit, the liquid crystal display panel further comprising a plurality of scan lines, each data line and each scan line, which are insulated from the plurality of data lines. Defining a display unit, the scan driving circuit provides a scan signal to the plurality of scan lines according to the timing signal of the timing control circuit to activate the plurality of display units, and the data driving circuit is activated during the activation of the display unit The data voltage is applied to the activated display unit by the plurality of data lines, the predetermined time being a time each time the display unit is activated. A display comprising: a display panel comprising a plurality of display units and a plurality of data lines for transmitting data voltages to the plurality of display units; a timing control circuit, the timing control circuit receives the image signals, and provides a map according to the image signals a data source and a timing signal; a common voltage generating circuit that supplies a common voltage to the plurality of display units; and a data driving circuit that converts the image data into corresponding data voltages, and According to whether the pre-displayed picture of the display panel is a single gray-scale picture, the first bias current or the second bias current is selected to be driven to output the converted data voltage to the plurality of display units by the plurality of data lines. The first bias current is greater than the second bias current, and the data voltage defining the common voltage is a positive data voltage, and the data voltage smaller than the common voltage is a negative data voltage for the same data line. a data connection circuit that provides a data voltage of the same polarity; wherein, when the pre-displayed picture is a single gray scale picture, the data driving circuit selects to drive with the first bias current to output the converted The data voltage reaches a predetermined time. After the predetermined time is reached, the data driving circuit next selects to drive with a second bias current to output the converted data voltage for driving the plurality of display units to display the single gray scale. a picture in which, at the latest, the predetermined time is reached, the data voltage output by the data driving circuit reaches Set the target data voltage, the drive voltage of at least a predetermined target data voltage of 85% of the data conversion circuit for the data. The display of claim 9, wherein the predetermined target data voltage is at least 90% to 95% of the data voltage converted by the data driving circuit. The display according to any one of claims 9 to 10, wherein the timing control circuit determines, according to the image signal, whether the picture pre-displayed by the display panel is a single gray-scale picture, and the data driving circuit controls the circuit according to the timing The determination result is selected to be driven by using the first bias current or the second bias current to output the converted data voltage to the plurality of display units by the plurality of data lines, and the timing control circuit determines that the pre-display is known. When the picture is a single gray scale picture, the timing control circuit outputs a first control signal to the data driving circuit to control the data driving circuit to select the first bias current and the second bias current to drive the output after the conversion. Information voltage. The display device of claim 11, wherein the data driving circuit comprises at least one bias circuit and a plurality of buffer amplifiers, each buffer amplifier being connected to a bias circuit and a data line, The at least one bias circuit is connected to the timing control circuit, the complex buffer amplifier receives the converted data voltage, and the at least one bias circuit selectively outputs the first bias voltage or the second according to the determination result of the timing control circuit. The bias voltage is applied to the connected buffer amplifier such that the complex buffer amplifier generates a first bias current or a second bias current to drive the output of the received data voltage. The display device of claim 12, wherein when the timing control circuit determines that the pre-displayed picture is a single grayscale picture, the timing control circuit outputs the first control signal to each of the bias circuits, each The bias circuit selects to first output the first bias voltage to the connected buffer amplifier for the predetermined time, so that the complex buffer amplifier generates a first bias current to output the received data voltage, after the predetermined time is reached, Each bias circuit next selects to output a second bias voltage to the connected buffer amplifier, so that the complex buffer amplifier generates a second bias current to output the received data voltage for driving the display of the plurality of display units. The single gray scale picture, wherein the first bias voltage is greater than the second bias voltage. The display device of claim 11, wherein when the timing control circuit determines that the pre-displayed picture is a non-single grayscale picture, the timing control circuit outputs a second control signal to the data driving circuit for the complex display And the data driving circuit is driven by the second bias current according to the second control signal to output the converted data voltage for driving the plurality of display units to display the non-single gray scale picture. The display device of claim 12, wherein when the timing control circuit determines that the pre-displayed picture is a non-single grayscale picture, the timing control circuit outputs the second control signal to each of the bias circuits. The plurality of display circuits each output a second bias voltage to the connected buffer amplifier, so that the complex buffer amplifier generates a first bias current to output the received data voltage for driving the The plural display unit displays the non-single grayscale picture. The display of claim 9, wherein the display further comprises a scan driving circuit, The display panel further includes a plurality of scan lines that are insulated from the plurality of data lines, and a display unit is defined at an intersection of each of the data lines and each of the scan lines, and the scan drive circuit controls the timing signals of the circuit according to the timing Correspondingly, a scan signal is provided to the plurality of scan lines to activate the plurality of display units. During the activation of the display unit, the data drive circuit applies a data voltage to the activated display unit by the plurality of data lines, the predetermined time being one. The time at which the display unit is activated each time. A liquid crystal display comprising: a liquid crystal display panel comprising a plurality of display units and a plurality of data lines for transmitting data voltages to said plurality of display units; a timing control circuit, said timing control circuit receiving image signals and corresponding to said image signals Providing image data and a timing signal, the timing control circuit further determining, according to the image signal, whether a gray level pre-displayed by the display unit connected to the same data line is the same; a common voltage generating circuit, the common voltage generating circuit provides a common voltage a plurality of display units; and a data driving circuit, wherein the data driving circuit converts the image data into corresponding data voltages, and outputs the data voltages to the plurality of display units by the plurality of data lines to define the common voltage The data voltage is a positive data voltage, and a data voltage smaller than the common voltage is a negative data voltage. For a display unit connected to the same data line, the data driving circuit provides a data voltage of the same polarity, and the data driving circuit includes One-to-one correspondence with the multiple data lines a complex buffer amplifier, the complex buffer amplifier receives the converted data voltage, and according to the judgment result of the timing control circuit, selects to use the first bias current or the second bias current to drive to output the received data a voltage for driving the display screen of the plurality of display units, wherein the first bias current is greater than the second bias current; wherein, when the timing control circuit determines that there is a gray display pre-displayed by the display unit connected to the same data line When the steps are the same, the timing control circuit outputs the first control signal to the data driving a buffer amplifier that is connected to the display unit having the same gray level by the same data line and is driven by the first bias current according to the first control signal to output the received data voltage for a predetermined time. After the predetermined time is reached, the second bias current is selected to be driven to output the received data voltage for driving the display unit connected to the same data line and pre-displaying the same gray level to display the same gray level, wherein And at the latest, when the predetermined time is reached, the data voltage output by the buffer amplifier connected by the same data line and the display unit having the same gray level is the predetermined target data voltage, and the predetermined target data voltage is at least the plural 85% of the data voltage received by the buffer amplifier. The liquid crystal display of claim 17, wherein the predetermined target data voltage is at least 90% to 95% of a data voltage received by the complex buffer amplifier. The liquid crystal display according to any one of claims 17 to 18, wherein, when the timing control circuit determines that there is a difference in gray level pre-displayed by the display unit connected to the same data line, the timing control circuit outputs the The second control signal is applied to the data driving circuit, and the buffer amplifier connected to the display unit different in pre-display gray scale by the same data line is driven by the second bias current according to the second control signal during the display of the current picture. The received data voltage is output to drive the display unit connected to the same data line and pre-displayed with different gray levels to display the corresponding gray level. The liquid crystal display according to claim 19, wherein the data driving circuit further comprises at least one bias circuit, each buffer amplifier is connected to a bias circuit, and the at least one bias circuit is connected to the timing control circuit. The at least one bias circuit selectively outputs a first bias voltage or a second bias voltage to the connected buffer amplifier according to the determination result of the timing control circuit, so that the complex buffer amplifier generates a first bias current or a corresponding Two bias currents, the first bias voltage being greater than the second bias voltage. The liquid crystal display according to claim 20, wherein the timing control circuit determines that there is a gray level of the pre-displayed display unit connected to the same data line. The first output signal is output to the bias circuit connected to the display unit with the same gray level by the same data line, and the bias circuit selects the first bias voltage according to the first control signal. And the buffer amplifier connected to the display unit with the same gray scale by the same data line is connected to the buffer amplifier corresponding to the display unit with the same gray level by the same data line for the predetermined time. Generating a first bias current to output the received data voltage. After the predetermined time is reached, the bias circuit next selects to output a second bias voltage to the same gray line as the pre-display gray scale by the same data line. The buffer amplifiers connected to the display unit are configured to generate a second bias current corresponding to the display unit connected to the display unit having the same gray level by the same data line to output the received data voltage. The liquid crystal display according to claim 21, wherein when the timing control circuit determines that there is a difference in gray level pre-displayed by the display unit connected to the same data line, the timing control circuit outputs a second control signal to the a bias circuit connected to the display unit different in pre-display gray scale by the same data line, during the displaying of the current picture, the bias circuit selects and outputs the second bias voltage according to the second control signal to the borrowing a buffer amplifier connected to the display unit different in pre-display gray scale by the same data line, so that the buffer amplifier connected by the same data line and the display unit different in pre-display gray scale generates a second bias current to output The received data voltage. The liquid crystal display of claim 17, wherein the liquid crystal display further comprises a scan driving circuit, the liquid crystal display panel further comprising a plurality of scan lines insulated from the plurality of data lines, each data line and each scan line Defining a display unit, the scan driving circuit provides a scan signal to the plurality of scan lines according to the timing signal of the timing control circuit to activate the plurality of display units, and the data driving circuit is activated during the activation of the display unit The data voltage is applied to the activated display unit by the plurality of data lines, the predetermined time being a time each time the display unit is activated. A display comprising: The display panel includes a plurality of display units and a plurality of data lines for transmitting data voltages to the plurality of display units; the timing control circuit receives the image signals, and provides image data and timing signals according to the image signals. The timing control circuit further determines, according to the image signal, whether the gray level pre-displayed by the display unit connected to the same data line is the same; the common voltage generating circuit, the common voltage generating circuit provides a common voltage to the plurality of display units; and the data a driving circuit, the data driving circuit converts the image data into a corresponding data voltage, and outputs the data voltage to the plurality of display units by the plurality of data lines, and defines a data voltage equal to or greater than the common voltage as a positive data voltage a data voltage that is less than the common voltage is a negative data voltage. For a display unit connected to the same data line, the data driving circuit provides a data voltage of the same polarity, and the data driving circuit includes one of the plurality of data lines. a correspondingly connected complex buffer amplifier, the complex The buffer amplifier receives the converted data voltage, and according to the judgment result of the timing control circuit, selectively drives the first bias current or the second bias current to output the received data voltage for driving the complex display. The unit display screen, the first bias current is greater than the second bias current; wherein, when the timing control circuit determines that there is a gray level that is pre-displayed by the display unit connected to the same data line, the timing control circuit And outputting the first control signal to the data driving circuit, and the buffer amplifier connected to the display unit with the same gray level by the same data line is driven by the first bias current according to the first control signal to output the received signal The data voltage reaches a predetermined time. After the predetermined time is reached, the second bias current is selected to be driven to output the received data voltage for driving the same data line and pre-displaying the same gray level. The display unit displays the same gray scale, wherein the same data line is reached at the latest by the same data line Pre same gray scale display buffer amplifier connected to the display unit output a data voltage of a predetermined target data voltage, the predetermined target data electrically The voltage is at least 85% of the data voltage received by the complex buffer amplifier. The display of claim 24, wherein the predetermined target data voltage is at least 90% to 95% of a data voltage received by the complex buffer amplifier. The display according to any one of claims 24 to 25, wherein the timing control circuit outputs a second when the timing control circuit determines that there is a difference in gray level pre-displayed by the display unit connected to the same data line. The control signal is sent to the data driving circuit, and the buffer amplifier connected to the display unit different in pre-display gray scale by the same data line is driven by the second bias current according to the second control signal during the display of the current picture. The received data voltage is used to drive a display unit connected to the same data line and pre-displayed with different gray levels to display corresponding gray levels. The display device of claim 26, wherein the data driving circuit further comprises at least one bias circuit, each buffer amplifier is connected to a bias circuit, and the at least one bias circuit is coupled to the timing control circuit, The at least one bias circuit correspondingly selects to output the first bias voltage or the second bias voltage to the connected buffer amplifier according to the determination result of the timing control circuit, so that the complex buffer amplifier correspondingly generates the first bias current or the second a bias current, the first bias voltage being greater than the second bias voltage. The display device of claim 27, wherein the timing control circuit outputs the first control signal to the borrowing when the timing control circuit determines that there is a gray level pre-displayed by the display unit connected to the same data line. a bias circuit connected to the same display unit with the same gray line as the pre-displayed gray line, the bias circuit first selecting the first bias voltage according to the first control signal to the same data line and the pre- Displaying a buffer amplifier connected to the display unit with the same gray scale for the predetermined time, so that the buffer amplifier connected by the same data line and the display unit with the same gray scale is correspondingly generates a first bias current to output and receive The data voltage, after the predetermined time is reached, the bias circuit next selects to output a second bias voltage to the buffer amplification of the same data line connected to the pre-display gray scale by the same data line. The buffer amplifier connected by the same data line and the display unit having the same gray level as the pre-displayed gray line generates a second bias current to output the received data voltage. The display device of claim 28, wherein the timing control circuit outputs a second control signal to the borrowing when the timing control circuit determines that there is a difference in gray level pre-displayed by the display unit connected to the same data line. a bias circuit connected to the display unit different in pre-display gray scale by the same data line, and during the displaying of the current picture, the bias circuit selects and outputs a second bias voltage according to the second control signal to a buffer amplifier connected to a display unit different in pre-display gray scale, so that the buffer amplifier connected by the same data line and the display unit different in pre-display gray scale generates a second bias current to output the same Received data voltage. The display of claim 24, wherein the display further comprises a scan driving circuit, the display panel further comprising a plurality of scan lines insulated from the plurality of data lines, the intersection of each data line and each scan line Defining a display unit, the scan driving circuit provides a scan signal to the plurality of scan lines according to the timing signal of the timing control circuit to activate the plurality of display units, and the data driving circuit is used by the data driving circuit during the activation of the display unit The plurality of data lines apply a data voltage to the activated display unit for a time each time the display unit is activated.