TWI543159B - Semiconductor memory device - Google Patents

Description

Semiconductor memory device Related application

This application is based on US Patent Application Serial No. 61/815,197 (filed on Apr. 23, 2013). The entire contents of this basic application are incorporated herein by reference.

The embodiment of the present specification relates to a semiconductor memory device.

In recent years, resistance variable memory has been attracting attention as a candidate for flash memory. The variable resistance memory generally has a cross-point type structure in which memory cells including variable resistance elements at intersections of a plurality of bit lines and a plurality of word lines intersecting the plurality of bit lines are arranged in a matrix.

In such a cross-point type of resistance variable memory, a voltage is applied to the selected memory cell to change the resistance of the variable resistance element, thereby causing sufficient current to flow, and on the other hand, based on the selection of the selection element. Function, etc., does not allow current to flow to the non-selected memory unit. The increase in the leakage current of the non-selective memory unit causes the malfunction of the resistance-variable memory, and also increases the power consumption.

Embodiments of the present invention provide a semiconductor memory device capable of preventing malfunction, suppressing an increase in power consumption, and improving an operation speed.

A semiconductor memory device according to an embodiment of the present invention includes: a memory cell array having a plurality of bit lines; a plurality of word lines crossing a plurality of bit lines; a memory unit at an intersection of a plurality of bit lines and a plurality of word lines; and a control unit that controls voltages applied to the bit lines and the word lines. When the control unit continuously performs a specific operation on the plurality of memory cells, the control unit selects the first bit line selected from the plurality of bit lines and the first word line selected from the plurality of word lines, and After the first operation of the memory unit, in the second operation subsequent to the first operation, the second bit line different from the first bit line and the second word line different from the first word line are selected. And select the second memory unit.

According to the semiconductor memory device of the embodiment, it is possible to provide a semiconductor memory device capable of preventing malfunction, suppressing an increase in power consumption, and improving the operation speed.

1‧‧‧Memory Cell Array

2‧‧‧ line control circuit

3‧‧‧ column control circuit

4‧‧‧ Data input and output buffer

5‧‧‧ address register

6‧‧‧ instruction interface

7‧‧‧ State Machine

8‧‧‧ Circuitry

9‧‧‧ pulse generator

11‧‧‧Memory Cell Array

50‧‧‧Substrate

60‧‧‧Selecting the transistor layer

61‧‧‧ Conductive layer

63‧‧‧ Conductive layer

65‧‧‧ Columnar semiconductor layer

65a‧‧‧N+ type semiconductor layer

65b‧‧‧P+ type semiconductor layer

65c‧‧‧N+ type semiconductor layer

66‧‧‧ gate insulation

70‧‧‧ memory layer

71a‧‧‧Interlayer insulation

71b‧‧‧Interlayer insulation

71c‧‧‧Interlayer insulation

71d‧‧‧Interlayer insulation

72a‧‧‧ Conductive layer

72b‧‧‧ Conductive layer

72c‧‧‧ Conductive layer

72d‧‧‧ Conductive layer

73‧‧‧ columnar conductive layer

74‧‧‧ sidewall layer

75‧‧‧Variable Resistance Layer

76‧‧‧Oxide layer

B‧‧‧ pattern

C‧‧‧pattern

D‧‧‧ pattern

E‧‧‧pattern

F‧‧‧ pattern

G‧‧‧pattern

H‧‧‧pattern

I‧‧‧ pattern

J‧‧‧ pattern

K‧‧‧pattern

L‧‧‧ pattern

M‧‧‧ pattern

N‧‧‧ pattern

O‧‧‧pattern

P‧‧‧ pattern

Q‧‧‧ pattern

BL‧‧‧ bit line

BL0‧‧‧ bit line

BL0<0>‧‧‧Non-selected bit line

BL0<1>‧‧‧Select bit line

BL0<2>‧‧‧Non-selected bit line

BL1‧‧‧ bit line

BL1<0>‧‧‧ bit line

BL1<1>‧‧‧ bit line

BL1<2>‧‧‧ bit line

BL2‧‧‧ bit line

BL3‧‧‧ bit line

GBL‧‧‧Global Bit Line

MA(1)‧‧‧ memory layer

MA(2)‧‧‧ memory layer

MA(3)‧‧‧ memory layer

MA(4)‧‧‧ memory layer

MA(5)‧‧‧ memory layer

MC‧‧‧ memory unit

MC0‧‧‧ memory unit

MC0<0,0>‧‧‧ non-selective memory unit

MC0<0,1>‧‧‧ non-selective memory unit

MC0<0,2>‧‧‧ Non-selective memory unit

MC0<1,0>‧‧‧ non-selective memory unit

MC0<1,1>‧‧‧Select memory unit

MC0<1,2>‧‧‧ Non-selective memory unit

MC0<2,0>‧‧‧ Non-selective memory unit

MC0<2,1>‧‧‧ non-selective memory unit

MC0<2,2>‧‧‧ Non-selective memory unit

MC1‧‧‧ memory unit

MC1<1,0>‧‧‧ memory unit

MC1<1,1>‧‧‧ memory unit

MC1<1,2>‧‧‧ memory unit

Rf‧‧‧Rectifying components

SG‧‧‧Selected gate line

STr‧‧‧Selected transistor

VR‧‧‧Variable Resistive Components

WL‧‧‧ character line

WL0‧‧‧ character line

WL0<0>‧‧‧Non-selected word line

WL0<1>‧‧‧Select word line

WL0<2>‧‧‧Non-selected word line

WL1‧‧‧ character line

WL2‧‧‧ character line

WL3‧‧‧ character line

WL4‧‧‧ character line

Fig. 1 is a block diagram showing an example of a nonvolatile semiconductor memory device according to a first embodiment.

Fig. 2 is a perspective view showing an example of a configuration of a memory cell of the nonvolatile semiconductor memory device of the first embodiment.

Fig. 3 is a perspective view showing an example of a configuration of a memory unit of the nonvolatile semiconductor memory device of the first embodiment.

4 is a view showing an example of a combination of a configuration of a variable resistance element and a rectifying element of a memory cell of the nonvolatile semiconductor memory device according to the first embodiment.

Fig. 5 is a view showing an example of a state of current flowing through a selection memory unit and a non-selection memory unit of the nonvolatile semiconductor memory device of the first embodiment.

Fig. 6 is a view showing an example of a bias state in a case where the nonvolatile semiconductor memory device of the first embodiment is operated in a single pole.

Fig. 7 is a view showing an example of a bias state in a case where the nonvolatile semiconductor memory device of the first embodiment is subjected to bipolar operation.

FIG. 8 is a view showing an example of an operation method when a plurality of memory cells of the nonvolatile semiconductor memory device of the first embodiment are continuously subjected to a setting operation or a reset operation. Concept map.

9A and FIG. 9B are conceptual diagrams showing an example of an operation method when a plurality of memory cells of the nonvolatile semiconductor memory device of the first embodiment are continuously operated or reset.

FIG. 10 is a conceptual diagram showing an example of an operation method when a plurality of memory cells of the nonvolatile semiconductor memory device of the second embodiment are continuously subjected to a setting operation or a reset operation.

FIG. 11 is a conceptual diagram showing an example of an operation method when a plurality of memory cells of the nonvolatile semiconductor memory device of the third embodiment are continuously subjected to a setting operation or a reset operation.

FIG. 12 is a conceptual diagram showing an example of an operation method when a plurality of memory cells of the nonvolatile semiconductor memory device of the fourth embodiment are continuously subjected to a setting operation or a reset operation.

Fig. 13A is a view showing an example of a perspective view showing a configuration of a memory cell of the nonvolatile semiconductor memory device of the fifth embodiment.

13B and FIG. 13C are conceptual diagrams showing an example of an operation method when a plurality of memory cells of the nonvolatile semiconductor memory device of the fifth embodiment are continuously subjected to a setting operation or a reset operation.

Fig. 13D is a conceptual diagram showing an example of assigning a logical address of the nonvolatile semiconductor memory device of the fifth embodiment.

Fig. 14 is a conceptual diagram showing an example of assigning a logical address of the nonvolatile semiconductor memory device of the sixth embodiment.

Fig. 15A is an example of a circuit diagram of a memory cell array according to a seventh embodiment.

Fig. 15B is a perspective view showing an example of a laminated structure of the memory cell array of the seventh embodiment.

Fig. 15C is an example of a cross-sectional view of Fig. 15B.

16 to 19 show an example of the procedure of selecting a memory cell of the nonvolatile semiconductor memory device of the seventh embodiment.

Hereinafter, a nonvolatile semiconductor memory device according to an embodiment will be described with reference to the drawings.

[First Embodiment]

<All systems>

Fig. 1 is a block diagram showing an example of a nonvolatile semiconductor memory device according to a first embodiment.

The non-volatile semiconductor memory device includes: a memory cell array 1 having a plurality of word lines WL, a plurality of bit lines BL crossing the plurality of word lines WL, and a bit line WL and a bit disposed thereon A plurality of memory cells MC at the intersection of the lines BL.

At a position adjacent to the direction of the bit line BL of the memory cell array 1, a row control circuit 2 is provided which controls the bit line BL of the memory cell array 1 to perform data deletion on the memory cell MC and to the memory cell MC Data is written and read from the memory unit MC.

Further, at a position adjacent to the direction of the word line WL of the memory cell array 1, a column control circuit 3 is provided which selects the word line WL of the memory array unit 1, applies data deletion to the memory cell MC, and the memory unit The data of the MC is written and the voltage required to read the data from the memory unit MC.

The data input/output buffer 4 is connected to an external host (not shown) via an I/O line, and receives reception of a write data, reception of a delete command, output of read data, and reception of address data or command data. The data input/output buffer 4 transmits the received write data to the row control circuit 2, receives the data read by the self-control circuit 2, and outputs it to the outside. The address supplied from the outside to the data input/output buffer 4 is transmitted to the row control circuit 2 and the column control circuit 3 via the address register 5. And, an instruction supplied from the host to the data input/output buffer 4 is sent to the instruction interface 6.

The command interface 6 receives an external control signal from the host, and determines whether the data input to the data input/output buffer 4 is a write data, an instruction, or an address. If it is an address, it is transmitted to the state machine 7 as a receive command signal.

The state machine 7 manages all of the non-volatile semiconductor memory devices, and receives commands from the host, and reads, writes, deletes, and inputs and outputs data. Further, a part of the row control circuit 2, the column control circuit 3, the data input/output buffer 4, the address register 5, the instruction interface 6, and the state machine 7 may be referred to as a control circuit.

Further, the data input from the host to the data input/output buffer 4 is sent to the codec circuit 8, and the output signal is input to the pulse generator 9. The pulse generator 9 outputs a specific voltage and a write pulse of a specific timing based on the input signal. The pulse generated and output by the pulse generator 9 is transmitted to the selected one of the wirings by the row control circuit 2 and the column control circuit 3.

<memory unit>

Next, the memory cell MC used in the embodiment shown in Fig. 1 will be described.

The memory cell MC of the present embodiment has a memory element and a non-ohmic element which are connected in series to the intersection of the word line WL and the bit line BL. A non-ohmic element is a non-ohmic junction element such as a metal and a semiconductor, or a semiconductor having a different amount or concentration of added impurities, and examples thereof include a PN diode, a PIN diode, a PNP device, an NPN device, and a NIN device. , PIP components, etc. A variable resistance element or a phase change element can be used in the memory element. The variable resistance element is an element including a material whose resistance value changes depending on voltage, current, heat, or the like. The phase change element refers to an element including a material whose resistance such as a resistance value or a capacitance changes with a phase change.

Here, the phase transition (phase transition) means the ones listed below.

(1) Metal-semiconductor transformation, metal-insulator transition, metal-metal transition, insulator insulator transition, insulator-semiconductor transition, insulator-metal transition, half Conductor-semiconductor transition, semiconductor-metal transition, or semiconductor-insulator transition

(2) Phase transition of quantum state of metal-superconductor transition

(3) Paramagnetic-ferromagnetic transition, antiferromagnetic-ferromagnetic transition, ferromagnet-ferromagnetic transition, ferrite magnet-ferromagnetic transition, or a transition comprising a combination of such transitions.

(4) Paraelectric-ferroelectric transformation, paraelectric-thermoelectric transformation, paraelectric-piezoelectric transformation, ferroelectric-ferroelectric transformation, antiferroelectric-ferroelectric transformation, or inclusion The transformation of the combination of these transformations.

(5) A transition comprising a combination of the transitions of (1) to (4) above, for example, from a metal, an insulator, a semiconductor, a ferroelectric, a paraelectric, a pyroelectric, a piezoelectric, a ferromagnetic, or a ferrite magnet , a spiral magnet, a paraelectric or antiferromagnetic to ferroelectric ferromagnet transition, or vice versa.

According to this definition, the phase change element is included in the variable resistance element. However, the variable resistance element of the present embodiment mainly means an element including a metal oxide, a metal compound, an organic thin film, carbon, or a carbon nanotube.

Further, in the present embodiment, a ReRAM having a variable resistance element as a memory element or a PCRAM or MRAM having a phase change element as a memory element is used as a variable resistance memory.

Fig. 2 is an example of a perspective view of a memory cell MC in the case where a PIN diode is used as a non-ohmic element.

As shown in FIG. 2, the memory cell MC is disposed at an intersection of the lower layer word line WL (or the bit line BL) and the upper layer bit line BL (or the word line WL). The memory cell MC is formed from a lower layer to an upper layer to form a PIN diode including an n-type semiconductor (N+Si)/true semiconductor (Non dope Si: undoped Si)/p-type semiconductor (P+Si), and includes The column of the memory element portion of the electrode/memory element/electrode. Further, the film thickness of the PIN diode is set to be in the range of 50 nm to 150 nm.

Fig. 3 is an example of a perspective view of a memory cell MC in the case where a PNP element is used as a non-ohmic element.

As shown in FIG. 3, the memory cell MC is disposed at an intersection of the lower layer word line WL (or the bit line BL) and the upper layer bit line BL (or the word line WL). It is formed of a PNP element including a lower electrode, a p-type semiconductor (P+Si)/n-type semiconductor (N+Si)/p-type semiconductor (P+Si), and a memory element portion from the lower layer to the upper layer.

The film thickness of the PNP device is also set in the range of 50 nm to 150 nm. Further, as the non-ohmic element of the memory cell MC, an NPN device including an n-type semiconductor (N+Si)/p-type semiconductor (P+Si)/n-type semiconductor (N+Si) may be used instead of the PNP element.

As can be seen from FIG. 2 and FIG. 3, since the memory cells MC can form a cross-point type, a large memory capacitance can be realized by three-dimensional integration. Moreover, based on the characteristics of the variable resistance element, it is possible to achieve faster high-speed operation than the flash memory.

Hereinafter, a memory element which is a variable resistance element such as ReRAM will be mainly described.

When the memory cell array 1 is three-dimensionally structured, various combinations of the positional relationship between the variable resistance element of the memory cell MC and the rectifying element which is a non-ohmic element, and the direction of the rectifying element can be selected for each layer.

As shown in a of FIG. 4, FIG. 4 illustrates memory cells MC0 and MC1 in the case where the memory cell MC0 belonging to the lower memory cell array 1 shares the word line WL0 with the memory cell MC1 belonging to the upper memory cell array 1. A diagram of an example of a combination of patterns. In FIG. 4, although the rectifying element is indicated by a symbol of a diode for the sake of convenience, the rectifying element is not limited to the diode.

As shown by b to q in FIG. 4, as a combination of the memory cell MC0 and the memory cell MC1, 16 kinds of patterns such as the arrangement relationship of the variable resistance element VR and the rectifying element Rf or the direction of the rectifying element Rf may be reversed. The selection of these patterns can be selected in consideration of the operational characteristics, the operation method, the manufacturing steps, and the like.

<data writing/deleting action>

Next, the data writing/deleting operation for the memory unit MC will be described. Hereinafter, the writing operation of changing the variable resistance element VR from the high resistance state to the low resistance state is referred to as "setting operation", and the deletion operation for changing the low resistance state to the high resistance state is referred to as "reset operation". "." The current value, the voltage value, and the like appearing in the following description are examples, and are different depending on the material, size, and the like of the variable resistance element VR or the rectifying element Rf.

Fig. 5 is a view showing an example of a schematic view of a portion of the memory cell array 1. In the case of FIG. 5, the memory cell MC0 of the lower layer is disposed at the intersection of the bit line BL0 and the word line WL0. The memory cell MC1 of the upper layer is disposed at an intersection of the word line WL0 and the bit line BL1. The word line WL0 is shared by the memory cells MC0 and MC1.

Furthermore, the combination of the arrangement of the memory cells MC0, MC1 will be described by the pattern of b in FIG. In other words, the memory cell MC0 is stacked in the order of the rectifying element Rf and the variable resistive element VR from the bit line BL0 to the word line WL0. The rectifying element Rf is arranged in a direction along the direction from the word line WL0 to the bit line BL0. On the other hand, the memory cell MC1 is stacked in the order from the word line WL0 to the bit line BL1 in the order of the rectifying element Rf and the variable resistive element VR. The rectifying element Rf is arranged in a direction along the direction from the bit line BL to the word line WL0.

Here, the setting/reset operation in the case where the memory cells MC0<1, 1> provided at the intersection of the bit line BL0<1> and the word line WL0<1> are selected as the memory cell is examined.

Regarding the setting/resetting operation of the memory cell MC, there is a unipolar operation of setting operation and resetting operation by applying a bias of the same polarity, and setting action and resetting by applying bias voltages of different polarities Two ways of action bipolar action.

First, the unipolar action will be described.

In the setting operation, it is necessary to apply a current having a current density of 1 × 10 ⁵ to 1 × 10 ⁷ A/cm ² or a voltage of 1 to 2 V to the variable resistance element VR. Therefore, in the setting operation of the memory cell MC, in order to apply such a specific current or voltage, a forward current needs to flow in the rectifying element Rf.

In the reset operation, it is necessary to apply a current having a current density of 1 × 10 ³ to 1 × 10 ⁶ A/cm ² or a voltage of 1 to 3 V to the variable resistive element VR. Therefore, in the case of resetting the memory cell MC, in order to apply such a specific current or voltage, a forward current needs to flow in the rectifying element Rf.

In the unipolar action, for example, a bias voltage as shown in FIG. 6 can be applied to the memory cell array 1.

That is, as shown in FIG. 6, a specific voltage V (for example, 3 V) is supplied to the selected word line WL0<1>, and 0V is supplied to the other word lines WL0<0> and WL0<2>. Further, 0 V is supplied to the selected bit line BL0<1>, and a voltage V is supplied to the other bit lines BL0<0> and BL0<2>.

As a result, the potential difference V is supplied to the selection memory cells MC0<1, 1>. Non-selected memory cells MC0<0,0>, MC0<0, 2> connected to the unselected word line WL0<0>, WL0<2>, and the unselected bit lines BL0<0>, BL0<2>, MC0<2, 0>, MC0<2, 2> are supplied with a potential difference -V. The other memory cell MC0, that is, the non-selected memory cell (hereinafter referred to as "non-select memory cell") MC0<1, which is connected only to any one of the selected word line WL0<1> and the selected bit line BL0<1>. 0>, MC0<1, 2>, MC0<0, 1>, MC0<2, 1> are supplied with a potential difference of 0.

In this case, it is necessary to use a diode-like element having a voltage-current characteristic in which a current flows at a voltage of -V at a reverse bias and a rapid current flows in a forward bias as a non-ohmic element. By using such a non-ohmic element in the memory cell MC, it is possible to perform setting/resetting operations only on the selected memory cells MC0<1, 1>.

Next, the bipolar operation will be described.

In the case of bipolar action, it is basically necessary to consider the following: (1) and monopole The situation of the sexual action is different, the bidirectional flow of the memory cell MC has a current; (2) the operating speed, the operating current, and the operating voltage start to change from the value of the unipolar action; (3) the bias is also applied to the semi-selective memory cell MC.

Fig. 7 is a view showing an example of a case where a bias voltage is applied to the memory cell array 1 during bipolar operation. In the bipolar operation, for example, a bias voltage as shown in FIG. 7 can be applied to the memory cell array 1.

That is, as shown in FIG. 7, a specific voltage V (for example, 3 V) is supplied to the selected word line WL0<1>, and a voltage V/2 (for example, 1.5 V) is supplied to the other word lines WL0<0> and WL0<2>. . Further, 0 V is supplied to the selected bit line BL0<1>, and a voltage V/2 is supplied to the other bit lines BL0<0> and BL0<2>.

As a result, the potential difference V is supplied to the selection memory cells MC0<1, 1>. Non-selected memory cells MC0<0,0>, MC0<0, 2> connected to the unselected word line WL0<0>, WL0<2>, and the unselected bit lines BL0<0>, BL0<2>, MC0<2, 0>, MC0<2, 2> are supplied with a potential difference of zero. The other memory cell MC0, that is, the non-select memory cell (semi-select memory cell) MC0<1, 0>, MC0<1, which is only connected to any one of the selected word line WL0<1> and the selected bit line BL0<1>. , 2>, MC0<0, 1>, MC0<2, 1> are supplied with a potential difference V/2.

Therefore, in the bipolar operation, a non-ohmic element in which a current does not flow when the potential difference is V and the potential difference is V/2 or less is required.

As described above, regardless of whether the unipolar operation or the bipolar operation is employed, if the selection memory unit is selected for the setting operation or the reset operation, a specific current flows in the selection memory unit. For example, as shown in FIG. 6, it is assumed that the memory cells MC0<1, 1> are selected as the selection memory unit of the setting operation or the reset operation. In this case, after the setting operation or the reset operation of the selection memory cells MC0<1, 1> is completed, the voltage application of the selected memory cells MC0<1, 1> is ended, and ideally, the selection memory is distributed. The current of cells MC0<1, 1> will be instantaneously zero. However, the choice of memory in reality In the case of the element MC0<1, 1>, there is a case where a reverse recovery current flows in a short time even after the voltage application is completed. Further, when the application of the voltage to the selected memory cell is completed, for example, a residual charge remains in the bonded portion of the true semiconductor portion or the PN diode of the PIN diode. In particular, when the IMPAT (Impact Ionization Avalanche Transit Time) diode is used as a diode, and the current is increased by the impact ionization phenomenon, the residual charge will be more remarkable.

The present inventors have begun to study whether the reverse recovery current or the residual charge affects the setting operation or the reset operation of the memory unit which is the target of the next setting operation or reset operation. That is, when the reverse recovery current flows through the memory cells MC0<1, 1> after the setting operation or the reset operation is completed, when the memory cells MC0<1, 1> are selected, the memory cells that are half-selected memory cells are reselected (for example, When MC0<1, 0>, MC0<1, 2>, MC0<0, 1> or MC0<2, 1> in Fig. 6 and the setting operation or reset operation is restarted, a setting action or a heavy Set a malfunction in the action, or cause problems such as increased power consumption. The reason is that the potential of the selected bit line BL or the selected word line WL changes under the influence of the reverse recovery current or residual charge of the previous selection memory cell MC0<1, 1>.

Therefore, the semiconductor memory device of the present embodiment is configured to perform an operation as shown in FIG. 8 when a plurality of memory cells MC are continuously subjected to a setting operation or a reset operation. Here, the term "continuous" means that the next setting operation or the reset operation is performed during a period in which a reverse operation current such as a setting operation or a reset operation is still performed, and is approximately n sec to μ sec. That is, the control circuit selects the memory cells MC0<1, 1>, and when the setting operation or the reset operation is completed, when the next setting operation and the reset operation are performed, the half-select memory unit as described above is not selected (for example, In Fig. 6, MC0<1, 0>, MC0<1, 2>, MC0<0, 1> or MC0<2, 1>). Instead, the control circuit will connect the memory cells connected to the bit line BL and the word line WL which are different from the bit line BL0<1>, the word line WL0<1, 1> connected to the memory cells MC0<1, 1>. The MC is selected as the new selection memory unit. Make As an example, as shown in FIG. 8, the control circuit may select a bit line BL0 to which the memory cells MC0<1, 1> are connected, a bit line BL0<2> adjacent to the word line WL0<1>, and a connection. The memory cells MC0<0, 2> of the word line WL0<0>. Thereafter, if the same selection is repeated, as shown in FIG. 9A, the memory cell is moved in the oblique direction with respect to the length direction of the bit line BL in the memory cell array and the length direction of the word line WL. , select in order. Here, when the wiring width and the wiring interval of the word line WL and the bit line BL are equal, it is considered that the length direction of the bit line BL and the word line WL are selected with respect to the memory cell array. In the length direction, it moves in a direction with a slope of 45 degrees.

In addition, when the memory unit is selected to move in the oblique direction as described above, the same operation may be performed on the selected memory cells sequentially selected, or different operations may be included. That is, when the control circuit performs the first operation, the second operation, and the nth operation (n is an integer of 3 or more) for a plurality of the memory cells, the control unit selects the length direction of the memory cell with respect to the bit line and the word line. Select the memory unit in the order of the tilt direction. Here, the first to nth operations are, for example, a setting operation, a reset operation, a reading operation, and the like.

"effect"

As described above, according to the present embodiment, when a certain memory cell is selected as the object of the setting operation or the reset operation, if the operation is completed, the bit is not shared with the memory unit in the next setting operation or reset operation. A non-selective memory unit of either line BL or word line WL. Thereby, it is possible to proceed to the next setting operation or resetting operation without affecting the influence of the reverse recovery current or residual electric charge of the memory unit before the circulation. Therefore, it is possible to prevent malfunction of the setting operation or the reset operation, and it is also possible to suppress an increase in power consumption and to increase the operation speed. Further, in the above description, the case where the operations shown in FIGS. 8 and 9A are performed during the setting operation and the reset operation has been described, but the same operation can be performed even in the reading operation. Further, in the reading operation, since the voltage applied to each of the wires is lower than the voltage applied to each of the wires in the setting operation and the resetting operation, it is possible to adopt Use different action methods.

Furthermore, since the memory unit is selected based on a certain rule, the physical address and the logical address can be easily changed. For example, as shown in FIG. 9B, when the physical addresses are sequentially allocated along the length direction of the bit line BL of the memory cell array, the bit directions of the bit lines BL of the memory cell array may be sequentially allocated in the oblique direction. The address of the logical address is changed. For example, let n data be one page. Thus, if the data of the data length n is input from the external host or the like, the control circuit will follow the values of the logical address ((1, 1), (1, 2), (1, 3), (1, 4), In the order of ... (1, n)), the setting action or the resetting action is performed, and the data is memorized in each memory unit. When the data such as the data length of the next page is input from the host, the control circuit will follow the value of the logical address ((2, 1), (2, 2), (2, 3), (2, 4). In the order of ..., (2, n)), the setting action or the resetting action is performed, and the data is memorized in each memory unit.

[Second Embodiment]

Next, a semiconductor memory device according to a second embodiment will be described with reference to FIG. The configuration of the semiconductor memory device is substantially the same as that of the first embodiment. Moreover, when the control circuit selects a certain memory unit, after the setting operation or the resetting operation is completed, in the next setting operation and the resetting operation, the control circuit additionally sets the bit line BL and the word line WL. The aspect in which the different memory cells MC are selected as the new selection memory cells is also the same as in the first embodiment.

However, in the second embodiment, as shown in Fig. 10, the control circuit selects two bit lines BL separated from the previous selected bit line BL, and selects one line from the previous selected word line WL. The aspect of the adjacent word line WL is different from that of the first embodiment. Even in accordance with this operation, the same effects as those of the first embodiment can be exhibited.

Furthermore, by separating the selected memory unit from the previous selected memory unit, the effect of the heat generated by the previous selected memory unit can be reduced. Moreover, since the memory unit is selected based on a certain rule, the physical address and the logical address can be easily changed.

[Third embodiment]

Next, a semiconductor memory device according to a third embodiment will be described with reference to Fig. 11 . The configuration of the semiconductor memory device is substantially the same as that of the first embodiment. Moreover, the control circuit selects a certain memory unit, and after completing the setting operation or the resetting operation, the control circuit memorizes the difference between the bit line BL and the word line WL in the next setting operation and the resetting operation. The aspect in which the unit MC is selected as the new selection memory unit is also the same as in the first embodiment.

However, as shown in Fig. 11, in the third embodiment, the control circuit is different from the first embodiment in that the control unit selects the memory cells in the zigzag order in the longitudinal direction of the bit line BL and the word line WL. Specifically, similarly to the first embodiment, the control circuit reselects the memory cell located obliquely below the previous selection memory cell MC. After the operation of the memory unit is completed, the control circuit then reselects the memory unit that is obliquely above when viewed from the memory unit. The control circuit repeats this selection, and as a result, it controls to select the memory cells in a zigzag manner. According to this operation, the same effects as those of the first embodiment can be exhibited.

[Fourth embodiment]

Next, a semiconductor memory device according to a fourth embodiment will be described with reference to FIG. The configuration of the semiconductor memory device is substantially the same as that of the first embodiment. Moreover, the control circuit selects a certain memory unit, and after completing the setting operation or the resetting operation, the control circuit sets the bit line BL and the word line WL differently when performing the next setting operation and the resetting operation. The aspect in which the memory cell MC is selected as the new selection memory cell is also the same as in the first embodiment.

However, in the fourth embodiment, as shown in FIG. 12, the state machine 7 differs from the first embodiment in that it includes a table for determining the order in which the setting operation or the reset operation is performed. For example, as shown at the bottom of Figure 12, a logical address is assigned to a physical address. The control circuit performs a setting action or reset according to the values of the logical address ((1, 1), (1, 2), (1, 3), (1, 4), ... (1, n), ...) action. Although FIG. 12 shows the case where the memory cell MC is moved as shown in the upper diagram of FIG. 12, it is not intended to be limited thereto. According to this operation, the same effects as those of the first embodiment can be exhibited. Here, the form can be remembered in advance for non-swing The only memory (ROM) area of a semiconductor memory device. Further, an external memory controller, a host, or the like may be provided with a table.

[Fifth Embodiment]

Next, a semiconductor memory device according to a fifth embodiment will be described with reference to Figs. 13A to 13D. The schematic configuration of the semiconductor memory device is substantially the same as that of the first embodiment (FIG. 1). However, in this embodiment, it is assumed that the memory cell array 1 has a plurality of memory layers MA by, for example, a laminated structure as shown in FIG. 13A. In FIG. 13A, only five memory layers MA(1) to MA(5) are illustrated for simplification purposes, but the following description will be repeated for the same structure in the stacking direction. That is, the number of lamination directions of the memory layer MA is arbitrary, and is not limited to five as shown in FIG. 13A. Further, each memory layer MA has a plurality of word lines WL, a plurality of bit lines BL crossing the word line WL, and a plurality of memories disposed at intersections of the word lines WL and the bit lines BL. Unit MC. That is, it can be said that in each of the memory layers MA, the memory cells MC are arranged in a matrix as shown in FIG. 13C.

In the first to fourth embodiments, the following example has been described in which the memory unit existing in a certain memory layer MA(i) is selected, and after the setting operation or the resetting operation is completed, the next setting operation and resetting operation are performed. In the middle, another memory unit existing in the same memory layer MA(i) is selected as a new selection memory unit. On the other hand, in the fifth embodiment, the control circuit is configured to select, for example, a certain memory cell of the memory layer MA (1), and after the setting operation or the reset operation is completed, in the next setting operation and the reset operation, Memory cells located in different memory layers MA (eg, memory layer MA(3)) are selected.

In the following description, the physical address of a certain memory cell of one memory layer MA is represented by the x-axis and the y-axis along the surface of the semiconductor substrate and the z-axis orthogonal thereto. For example, using the xyz coordinates, the physical address of a certain memory unit located at the upper left of the memory layer MA(1) is represented as P(1, 1, 1). The physical address of the memory unit at the lower right of the memory unit MA(2) is expressed as (k, k, 2) (when the number of word lines and bit lines is k, k is an integer of 2 or more) ).

On the other hand, assuming that the memory cells of the complex layer memory layer MA are located on a imaginary plane, the z coordinate is not used, and only the logical address is represented by the xy coordinate such as L (1, 1). However, this is only used for convenience of explanation. The method of allocating the physical address and the logical address is not limited thereto.

In the present embodiment, the operation in the case where the memory cells are sequentially selected in the z direction will be described with reference to Figs. 13B and 13C. When the memory cell is sequentially selected in the z direction, as an example, as shown in FIG. 13B and FIG. 13C, for example, a memory cell whose physical address is P (1, 1, 1) in the memory layer MA(1) is selected. (The logical address is L (1, 1)), and then, in the case of the selected memory layer MA (3), the memory unit of the physical address P (1, 1, 1) from the memory layer MA (1) is selected. The memory unit (logical address L(1, 2)) of the physical address P (2, 2, 3) existing obliquely above is observed. Next, in the case where the memory cell MA(5) is selected, the memory cell selected from the physical address P(2, 2, 3) of the memory layer MA(3) is present at an obliquely upper physical address P ( 3, 3, 5) memory unit (logical address is L (1, 3)). In addition, the memory unit of the physical address P (1, 1, 1) of the memory layer MA (1) is assigned a logical address L (1, 1), and the physical position P (2, 2) of the memory layer MA (3) 3) The memory unit allocates a logical address L (1, 2), and the memory unit of the physical address P (3, 3, 5) of the memory layer MA (5) allocates a logical address L (1, 3). Hereinafter, according to the same principle, the memory cells are selected one by one from the plurality of memory layers MA of the stacked layers.

Since the memory layer MA(1) and the memory layer MA(3) hold the memory layer MA(2) therebetween, the bit line BL and the word line WL are not shared. The same is true for the memory cells MA(3) and MA(5). Therefore, by adopting the selection order as described above, the next setting operation or the reset operation can be performed without being affected by the reverse recovery current or the residual charge or the like flowing through the previous selection memory unit. The selection procedure shown in FIGS. 13B and 13C is only an example, and the order of selection of the memory layer MA can be in various orders as long as the influence of the reverse recovery current or residual charge can be limited.

Fig. 13D is a conceptual diagram showing an example of allocation of logical addresses shown in Figs. 13B and 13C. This example shows a case where a memory cell array is provided with 2k-1 layers of memory layers MA and k*k memory cells are present in one memory layer MA. In the case of this example, the logical addresses L (1, 1), L (1, 2), L (1, 3), ... L (2, 1), L (2, 2), L (2) are selected. 3)... Even if the memory cell is selected to move in the z direction, if it is viewed from the XY plane, it moves in the oblique direction.

For example, let k data be one page. Thus, if the data of the data length k is input from the outside by the host or the like, the control circuit will follow the values of the logical address ((1, 1), (1, 2), (1, 3), (1, 4), In the order of ... (1, k)), the set action or the reset action is performed, and the data is memorized in each memory unit. When the data such as the data length of the next page is input from the host, the control circuit will follow the value of the logical address ((2, 1), (2, 2), (2, 3), (2, 4). , (2, k)), perform setting action or reset action, and store data in each memory unit.

As described above, in the present embodiment, a method of sequentially selecting a plurality of memory layers of the stacked layers in the order of the stacking direction is employed. The memory layer is selected, for example, by skipping one, and selecting a memory layer that does not share the bit line BL or the word line WL with the currently selected memory layer (in other words, the newly selected memory layer has the current selection. The bit line and the word line of the memory layer have different bit lines and word lines). Since the memory layer selected continuously does not share the bit line or the word line, for example, during the setting operation of the memory layer MA(1), the bit line BL and the word line WL for the memory layer MA(3) can be started. Perform the charging action. Therefore, according to this embodiment, the speed of the operation can be increased. Further, the fifth embodiment and the first to fourth embodiments can be combined as appropriate.

Further, when viewed in three dimensions, the memory unit can be selected in the tilt direction of the XYZ axis. As a result, the selected memory unit can be kept at a distance from the memory unit selected thereafter. Therefore, erroneous writing to the memory unit can be reduced.

[Sixth embodiment]

Next, a semiconductor memory device according to a sixth embodiment will be described with reference to FIG. 14. Semiconductor record The schematic configuration of the device is substantially the same as that of the first embodiment (Fig. 1). Further, similarly to the fifth embodiment, the sixth embodiment assumes that the memory cell array 1 has a plurality of memory layers MA by, for example, a laminated structure as shown in FIG. 13A. Further, similarly to the fifth embodiment, the control circuit of the sixth embodiment is configured to select, for example, a certain memory cell of the memory layer MA(1), and after performing the setting operation or the reset operation, the next setting operation and In the reset action, a memory cell located in a different memory layer MA (for example, memory layer MA(3)) is selected.

The sixth embodiment differs from the fifth embodiment in the method of allocating logical addresses. That is, according to the logical address allocation method shown in FIG. 14, according to logical addresses (1, 1), (1, 2), (1, 3), ... (2, 1), (2, 2), When the order of (2, 3)... is selected, the selected memory unit moves in the YZ plane (not moving in the X-axis direction). Further, when the memory cell is selected to reach the end in the Y direction, the X coordinate is also incremented. Hereinafter, the memory cell is selected according to the same principle.

According to this embodiment, the same effects as those of the fifth embodiment can be obtained.

[Seventh embodiment]

Next, a semiconductor memory device according to a seventh embodiment will be described with reference to Figs. 15A to 16 . The schematic configuration of the semiconductor memory device is substantially the same as that of the first embodiment (FIG. 1). Further, in this embodiment, the memory cell array 1 has a shape as shown in Figs. 15A to 15C.

As shown in Figs. 15A to 15C, the semiconductor memory device of the seventh embodiment has a memory cell array 11 different from that of the first embodiment. The bit line BL is formed to extend in the vertical direction.

First, the circuit configuration of the memory cell array 11 of the seventh embodiment will be described with reference to Fig. 15A. Fig. 15A is an example of a circuit diagram of the memory cell array 11. In addition, in FIG. 15A, the X direction, the Y direction, and the Z direction are orthogonal to each other, and the X direction is a direction perpendicular to the plane of the paper. Moreover, the structure shown in FIG. 15A is repeatedly disposed in the X direction.

As shown in FIG. 15, the memory cell array 11 of the seventh embodiment is divided by the above word line. In addition to the WL, the bit line BL and the memory cell MC, there are a selection transistor STr, a global bit line GBL, and a selection gate line SG.

As shown in FIG. 15A, the word lines WL1 to WL4 are arranged in the Z direction and extend in the X direction. The bit lines BL are arranged in a matrix in the X direction and the Y direction, and extend in the Z direction. The memory cell MC is disposed where the word line WL and the bit line BL intersect. Therefore, the memory cells MC are arranged in a three-dimensional matrix in the X, Y, and Z directions.

As shown in FIG. 15A, the selection transistor STr is disposed between one end of the bit line BL and the global bit line GBL. The global bit lines GBL are arranged in the X direction and extend in the Y direction. A global bit line GBL is commonly connected to one end of a plurality of selection transistors STr arranged in a row in the Y direction. In other words, it can be said that the bit line BL arranged along the Y direction is connected to one global bit line GBL. The gate lines SG are arranged in the Y direction and extend in the X direction. A selection gate line SG is commonly connected to the gates of a plurality of selection transistors STr arranged in a row along the X direction.

Next, a laminated structure of the memory cell array 11 of the seventh embodiment will be described with reference to FIGS. 15B and 15C. Fig. 15B is a view showing an example of a perspective view of the laminated structure of the memory cell array 11. Fig. 15C is an example of a cross-sectional view of Fig. 15B. In addition, the interlayer insulating layer is omitted in FIG. 15B.

As shown in FIGS. 15B and 15C, the memory cell array 11 has a selective transistor layer 60 and a memory layer 70 laminated on a substrate 50. A plurality of selection transistors STr are disposed on the selected transistor layer 60, and a plurality of memory cells MC are disposed on the memory layer 70.

As shown in FIGS. 15B and 15C, the selective transistor layer 60 has a conductive layer 61, an interlayer insulating layer 62, a conductive layer 63, and an interlayer insulating layer 64 which are laminated in the Z direction perpendicular to the principal plane of the substrate 50. The conductive layer 61 functions as a global bit line GBL, and the conductive layer 63 functions as a gate for selecting the gate line SG and the selection transistor STr.

The conductive layers 61 are arranged at a specific pitch in the X direction parallel to the principal plane of the substrate 50, and extend in the Y direction. An interlayer insulating layer 62 covers the upper surface of the conductive layer 61. The conductive layers 63 are arranged at a specific pitch in the Y direction and extend in the X direction. The interlayer insulating layer 64 covers the side surfaces and the upper surface of the conductive layer 63. For example, the conductive layers 61, 63 are composed of polycrystalline germanium. The interlayer insulating layers 62, 64 are made of, for example, cerium oxide (SiO ₂ ).

Further, the selective transistor layer 60 has a columnar semiconductor layer 65 and a gate insulating layer 66. The columnar semiconductor layer 65 functions as a main body (channel) of the selective transistor STr, and the gate insulating layer 66 functions as a gate insulating film for selecting the transistor STr.

The columnar semiconductor layers 65 are arranged in a matrix in the X and Y directions, and extend in a columnar shape in the Z direction. Further, the columnar semiconductor layer 65 is in contact with the upper surface of the conductive layer 61, and is in contact with the side surface of the end portion of the conductive layer 63 in the Y direction via the gate insulating layer 66. Further, the columnar semiconductor layer 65 has, for example, a laminated N+ type semiconductor layer 65a, a P+ type semiconductor layer 65b, and an N+ type semiconductor layer 65c.

The N+ type semiconductor layer 65a is in contact with the interlayer insulating layer 62 on the side surface of the end portion in the Y direction. The P + -type semiconductor layer 65b is in contact with the side surface of the conductive layer 63 on the side surface of the end portion in the Y direction. The N + -type semiconductor layer 65c is in contact with the interlayer insulating layer 64 on the side surface of the end portion in the Y direction. The N+ type semiconductor layers 65a and 65c are made of polycrystalline germanium implanted with N+ type impurities, and the P+ type semiconductor layer 65b is made of polycrystalline germanium implanted with P+ type impurities. The gate insulating layer 66 is made of, for example, hafnium oxide (SiO ₂ ).

The memory layer 70 has interlayer insulating layers 71a to 71d and conductive layers 72a to 72d which are alternately laminated in the Z direction. The conductive layers 72a to 72d function as the word lines WL1 to WL4. The conductive layers 72a to 72d have a comb-tooth shape corresponding to each of the X directions. The interlayer insulating layers 71a to 71d are made of, for example, hafnium oxide (SiO ₂ ), and the conductive layers 72a to 72d are made of, for example, polycrystalline germanium.

Furthermore, the memory layer 70 has a columnar conductive layer 73 and a sidewall layer 74. The columnar conductive layers 73 are arranged in a matrix in the X and Y directions, are in contact with the upper surface of the columnar semiconductor layer 65, and extend in a columnar shape in the Z direction. The columnar conductive layer 73 functions as a bit line BL.

The side wall layer 74 is provided on the side of the end portion of the columnar conductive layer 73 in the Y direction. Side wall layer 74 There is a variable resistance layer 75 and an oxide layer 76. The variable resistance layer 75 functions as a variable resistance element VR. The oxide layer 76 has a lower electrical conductivity than the variable resistance layer 75.

The variable resistance layer 75 is provided between the columnar conductive layer 73 and the side faces of the conductive layers 72a to 72d in the Y direction. The oxide layer 76 is provided between the columnar conductive layer 73 and the side faces of the interlayer insulating layers 71a to 71d in the Y direction.

The columnar conductive layer 73 is made of, for example, polycrystalline silicon, and the sidewall layer 74 (variable resistance layer 75 and oxide layer 76) is made of, for example, a metal oxide.

In the memory cell array of the structure shown in Figs. 15A to 15C, two memory cells are formed in the same layer with respect to one bit line BL. Further, since the bit line BL is formed of a semiconductor (for example, polysilicon), there is a case where the residual carrier remains for a long time.

Therefore, in the present embodiment, when the memory cell is sequentially selected, the selection transistor STr is turned on or off, whereby the bit line to be read is sequentially changed (along the same bit line). The memory unit of BL is not the object of continuous reading).

Here, FIG. 16 shows an example of the allocation of the physical addresses of the memory cells of FIGS. 15A to 15C and an example of the selection order of the memory cells. As shown in the circuit diagram on the right side of Fig. 16, the memory cell at the lower left of the nearest front is P (1, 1, 1). Taking the memory unit of the physical address P (1, 1, 1) as the reference, as the X axis extends deeper into the paper surface, the address of X increases, and as the Y axis extends toward the right side of the paper, the address of Y increases. Large, as the Z axis extends toward the top of the paper, the address of Z increases. Here, FIG. 16 shows an example in which a total of 16 bit lines of 4×4 and a 4-layer bit line WL are laminated.

Next, the selection of the memory unit will be described. For example, as shown in FIG. 16, after the memory unit of the physical address P (1, 1, 1) is selected, the bit line BL that is not shared with the memory unit of the physical address P (1, 1, 1) is selected. And the memory unit of the physical address P (1, 3, 1). Hereinafter, according to the same principle, the memory cells of the physical address P (1, 5, 1) and the physical address P (1, 7, 1) are sequentially selected. FIG. 16 shows a case where memory cells connected to the same word line WL (memory cells having the same Z coordinates) are sequentially selected and the X coordinates are not changed. in In the seventh embodiment, it is considered that the selected bit line BL is sequentially changed. Therefore, in FIG. 16, since the influence of the residual electric charge of the selected gate line and the bit line is suppressed, as described above, the memory cell having the Y coordinate phase difference of 2 is sequentially selected. Further, as shown in FIG. 17, the Z coordinates of the memory cells sequentially selected may be sequentially changed (for example, incremented by one). There are cases where a plurality of word lines WL are shared in the same memory layer. As a result, by changing the layer of the selected word line WL, it is possible to prevent the influence of residual charges or the like of the word line.

Figure 18 is a conceptual diagram showing another selection sequence. In the example of Fig. 18, when the memory cells are sequentially selected, only the Z coordinate is fixed, and the X coordinate system is changed by 1 and the Y coordinate system is changed by 2 (P (1). 1, 1) → P (2, 3, 1) → P (3, 5, 3) →....). As a result, it can be said that the selected global bit line GBL is sequentially changed. As a result, it is possible to prevent the influence of the residual charge or the like of the global bit line GBL.

Furthermore, as shown in FIG. 19, the Z coordinate can also be added to the general selection order (P (1, 1, 1) → P (2, 3, 2) → P (3, 5, 3). )→...). By changing all the coordinates of X, Y, and Z, the influence of residual charges and the like can be further reduced.

Furthermore, the allocation of logical addresses can be assigned in the same manner as in the sixth embodiment.

In the seventh embodiment, the same effects as those of the first to sixth embodiments can be obtained.

[Material of memory cell array]

Finally, the materials used in the memory cell arrays of the first to seventh embodiments are summarized. In addition, x and y represent arbitrary composition ratios.

<rectifying element>

The material of the p-type semiconductor, the n-type semiconductor, and the true semiconductor which constitute the rectifying element of the non-ohmic element can be selected from the group of semiconductors such as Si, SiGe, SiC, Ge, and C.

The joint portion of the semiconductor constituting the upper portion of the rectifying element is made of Si, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Rh, Pd, Ag, Cd, In, Sn, La, Hf, Ta. , W, Re, Os, Ir, Pt, Au, etc., which are made of telluride By adding one or two or more of the following elements: Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Sn, La, Hf, Ta, W, Re, Os, Ir, Pt, Au.

In the case where the rectifying element comprises an insulating layer, the insulating layer may, for example, be selected from the following materials.

(1) Oxide

. SiO ₂ , Al ₂ O ₃ , Y ₂ O ₃ , La ₂ O ₃ , Gd ₂ O ₃ , Ge ₂ O ₃ , CeO ₂ , Ta ₂ O ₅ , HfO ₂ , ZrO ₂ , TiO ₂ , HfSiO, HfAlO, ZrSiO , ZrAlO, AlSiO

. AM ₂ O ₄

Among them, A and M are the same or different elements, and are one of Al, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge.

Examples of the AM ₂ O ₄ include Fe ₃ O ₄ , FeAl ₂ O ₄ , Mn _1+x Al _2-x O _4+y , Co _1+x Al _2-x O _4+y , MnO _{x ,} and the like.

. AMO ₃

Wherein, A and M are the same or different elements, and are one of the following elements: Al, La, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, Tl, Pb, Bi, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Sn.

Examples of AMO ₃ include LaAlO ₃ , SrHfO ₃ , SrZrO ₃ , and SrTiO ₃ .

(2) Nitrogen oxides

. SiON, AlON, YON, LaON, GdON, CeON, TaON, HfON, ZrON, TiON, LaAlON, SrHfON, SrZrON, SrTiON, HfSiON, HfAlON, ZrSiON, ZrAlON, AlSiON

. A material which replaces a part of the oxygen element of the oxide represented by the above (1) with a nitrogen element, in particular, an insulating layer constituting the rectifying element, preferably from SiO ₂ , SiN, Si ₃ N ₄ , Al ₂ O _{3 , respectively.} Select from the group consisting of SiON, HfO ₂ , HfSiON, Ta ₂ O ₅ , TiO ₂ and SrTiO ₃ .

In addition, the Si-based insulating film such as SiO ₂ , SiN or SiON contains a concentration of oxygen and nitrogen of 1×10 ¹⁸ atoms/cm ³ or more.

However, the bias voltages of the plurality of insulating layers are different from each other.

Furthermore, the insulating layer also contains a material containing impurity atoms forming defects, or semiconductor/metal dots (quantum dots).

<variable resistance element>

The memory layer in the case where a memory function is incorporated in the variable resistive element or the rectifying element of the memory cell MC uses, for example, the following materials.

(1) Oxide

. SiO ₂ , Al ₂ O ₃ , Y ₂ O ₃ , La ₂ O ₃ , Gd ₂ O ₃ , Ce ₂ O ₃ , CeO ₂ , Ta ₂ O ₅ , HfO ₂ , ZrO ₂ , TiO ₂ , HfSiO, HfAlO, ZrSiO , ZrAlO, AlSiO.

. AM ₂ O ₄

Wherein A and M are the same or different elements, and are one or a combination of Al, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge.

The AM ₂ O _{4 is,} for example, Fe ₃ O ₄ , FeAl ₂ O ₄ , Mn _1+x Al _2-x O _4+y , Co _1+x Al _2-x O _4+y , MnO _x or the like.

. AMO ₃

Wherein, A and M are the same or different elements, and are one or a combination of the following elements: Al, La, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, Tl, Pb , Bi, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn Ga, Ge, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Sn.

Examples of AMO ₃ include LaAlO ₃ , SrHfO ₃ , SrZrO ₃ , and SrTiO ₃ .

(2) Nitrogen oxides

. SiON, AlON, YON, LaON, GdON, CeON, TaON, HfON, ZrON, TiON, LaAlON, SrHfON, SrZrON, SrTiON, HfSiON, HfAlON, ZrSiON, ZrAlON, AlSiON

The memory element is composed of, for example, a metal oxide or an organic substance (including a single layer film or a nanotube) of a binary system or a ternary system. For example, in the case of carbon, a two-dimensional structure including a single layer film, a nanotube tube, graphene, and fullerene is included. The metal oxide contains the oxide shown in the above (1) or the nitrogen oxide shown in (2).

<electrode layer>

The electrode layer used in the memory cell MC is exemplified by a metal element monomer or a plurality of mixtures, a halide or an oxide, a nitride, or the like.

Specifically, it is composed of the following materials: Pt, Au, Ag, TiAlN, SrRuO, Ru, RuN, Ir, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, TiN, TaN, LaNiO, Al, PtIrO _x , PtRhO _x , Rh, TaAlN, SiTiO _x , WSix, TaSi _x , PdSi _x , PtSi _x , IrSi _x , ErSi _x , YSi _x , HfSi _x , NiSi _x , CoSi _x , TiSi _x , VSi _x , CrSi _x , MnSi _x , FeSi _x and the like.

The electrode layer can also function as a barrier metal layer or an adhesive layer at the same time.

<character line WL, bit line BL>

The conductive lines functioning as the word line WL and the bit line BL of the memory cell array 1 are composed of W, WN, Al, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, TiN, WSi _x , TaSi _x , PdSi _x , ErSi _x , YSi _x , PtSi _x , HfSi _x , NiSi _x , CoSi _x , TiSi _x , VSi _x , CrSi _x , MnSi _x , FeSi _{x ,} or the like.

Although several embodiments of the invention have been described, the embodiments are presented by way of example only and are not intended to limit the scope of the invention. The novel embodiments may be embodied in a variety of other forms and various modifications, substitutions and changes can be made without departing from the scope of the invention. The scope of the invention or its modifications are intended to be included within the scope and spirit of the invention, and are also included within the scope of the invention as described in the claims.

BL0<0>‧‧‧Non-selected bit line

BL0<1>‧‧‧Select bit line

BL0<2>‧‧‧Non-selected bit line

MC0<0,0>‧‧‧ non-selective memory unit

MC0<0,1>‧‧‧ non-selective memory unit

MC0<0,2>‧‧‧ Non-selective memory unit

MC0<1,0>‧‧‧ non-selective memory unit

MC0<1,1>‧‧‧Select memory unit

MC0<1,2>‧‧‧ Non-selective memory unit

MC0<2,0>‧‧‧ Non-selective memory unit

MC0<2,1>‧‧‧ non-selective memory unit

MC0<2,2>‧‧‧ Non-selective memory unit

WL0<0>‧‧‧Non-selected word line

WL0<1>‧‧‧Select word line

WL0<2>‧‧‧Non-selected word line

Claims (13)

A semiconductor memory device, comprising: a memory cell array having a plurality of bit lines, a plurality of word lines crossing the plurality of bit lines, and a plurality of bit lines and a plurality of words disposed on the plurality of bit lines a memory unit at an intersection of the line; and a control unit that controls a voltage applied to the bit line and the word line; the memory unit includes a variable resistance element and a non-ohmic element; and the control unit is in the plurality of memories When the unit continuously performs a specific operation, selecting the first bit line selected from the plurality of bit lines and the first word line selected from the plurality of word lines, and performing the first memory unit After the first operation, in the second operation subsequent to the first operation, the second bit line different from the first bit line and the second word line different from the first word line are selected and selected. 2 memory unit; the memory unit array is configured by a plurality of memory layer layers each having a plurality of bit lines, a plurality of word lines, and a memory unit disposed at an intersection thereof; the control unit is in a plurality of pairs When the memory unit performs the first operation and the second operation, the first memory layer of the plurality of memory layers is selected from the plurality of bit lines selected from the plurality of bit lines and from the plurality of word lines Selecting the word line, and performing the first operation on the memory unit, selecting a bit line selected from the plurality of bit lines and from the plurality of second memory layers different from the first memory layer The selected character line in the word line, and the opposite The second cell layer is connected to the bit line and the word line different from the bit line and the word line of the first memory layer. The semiconductor memory device of claim 1, wherein the control circuit sequentially selects the first operation, the second operation, and the nth operation (n is an integer of 3 or more) for the plurality of memory cells. The memory unit moves in the stacking direction and moves in one of the first direction or the second direction perpendicular to the stacking direction, and does not move in the other of the first direction or the second direction. A semiconductor memory device comprising: a memory cell array having a plurality of bit lines extending in a longitudinal direction in a stacking direction and arranged in a first direction and a second direction crossing the stacking direction; a plurality of word lines extending in the first direction and laminated along the stacking direction; a memory unit disposed at an intersection of the plurality of bit lines and the plurality of word lines; and a control unit for controlling application a voltage to one of the bit lines and one of the word lines; each of the memory cells includes a variable resistance element; and the control unit performs a first operation and a second operation subsequent to the plurality of memory cells Selecting a first bit line from the plurality of bit lines and selecting a first word line from the plurality of word lines to perform the first operation on the first memory unit, and thereafter following the first action In the subsequent second operation, the second bit line adjacent to the first bit line in the diagonal direction with respect to the first direction and the second direction is selected, and product A second word line adjacent to the first character on the line direction. The semiconductor memory device of claim 3, which is provided a global bit line extending in the second direction and connected to the plurality of bit lines arranged along the second direction; and a selection transistor connected to the global bit line and the plurality of bits, respectively Between the lines. The semiconductor memory device of claim 3, wherein the control unit changes the selected bit line in the first direction and the second direction, and sequentially changes the selected word line. A semiconductor memory device comprising: a memory cell array having a plurality of bit lines extending in a longitudinal direction in a stacking direction and arranged in a first direction and a second direction crossing the stacking direction; a plurality of word lines extending in the first direction and laminated along the stacking direction; a memory unit disposed at an intersection of the plurality of bit lines and the plurality of word lines; and a control unit for controlling application a voltage to one of the bit lines and one of the word lines; each of the memory cells includes a variable resistance element; and wherein (i) is at an intersection between the first word line and the first bit line The memory unit to be installed is defined as a first memory unit, and (ii) a memory unit set at an intersection between the second character line and the first bit line is defined as a second memory unit, the above The two-character line is adjacent to the first character line in the second direction, and (iii) the memory unit provided at the intersection between the second word line and the second bit line is defined as In the third memory unit, the second bit line is in the second direction a memory cell provided at an intersection of the second word line and the third bit line in the first bit line, wherein the second memory cell and the second word line are located therebetween Is defined as a fourth memory unit, wherein the third bit line is adjacent to the second bit line in the first direction, and (v) is in the third The memory cell provided at the intersection between the word line and the third bit line is defined as a fifth memory cell, and the third word line is adjacent to the second word line in the stacking direction. The control unit selects the first memory unit in the first operation, and selects the fifth memory unit in the second operation subsequent to the first operation. The semiconductor memory device of claim 6, further comprising: a global bit line extending in the second direction and connected to the plurality of bit lines arranged along the second direction; and selecting a transistor Connected between the global bit line and the plurality of bit lines, respectively. The semiconductor memory device of claim 6, wherein the control unit changes the selected bit line in the first direction and the second direction, and sequentially changes the selected word line. A semiconductor memory device comprising: a memory cell array having a plurality of bit lines extending in a longitudinal direction in a stacking direction and arranged in a first direction and a second direction crossing the stacking direction; a plurality of word lines extending in the first direction and laminated along the stacking direction; a memory unit disposed at an intersection of the plurality of bit lines and the plurality of word lines; and a control unit for controlling application a voltage to one of the bit lines and one of the word lines; each of the memory cells includes a variable resistance element; and wherein (i) is at an intersection between the first word line and the first bit line The memory unit to be installed is defined as a first memory unit, and (ii) the memory unit provided at the intersection between the second word line and the first bit line is defined as a second memory unit, and the second The word line is adjacent to the first character in the second direction a line, (iii) a memory cell provided at an intersection between the third word line and the first bit line is defined as a third memory unit, and the third word line is located in the stacking direction Above or below the first character line, (iv) a memory cell provided at an intersection between the fourth word line and the first bit line is defined as a fourth memory unit, the fourth word The element line is located above or below the second character line in the stacking direction; and when the first memory unit is selected in the first operation, the control unit is followed by the second operation of the first operation The second memory unit, the third memory unit, and the fourth memory unit are unselected. The semiconductor memory device of claim 9, further comprising: a global bit line extending in the second direction and connected to the plurality of bit lines arranged along the second direction; and selecting a transistor Connected between the global bit line and the plurality of bit lines, respectively. The semiconductor memory device of claim 9, wherein the control unit selects a different word line in the first operation and the second operation. The semiconductor memory device of claim 9, wherein the control unit changes the selected bit line in the first direction and the second direction in the first operation and the second operation. The semiconductor memory device of claim 12, wherein the control unit sequentially changes the selected word line in the first operation and the second operation.