TWI540736B - Trench gate metal oxide semiconductor field effect transistor and fabricating method thereof - Google Patents

Description

Trench gate MOS half field effect transistor component and manufacturing method thereof

The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a trench gate MOS field device and a method of fabricating the same.

A typical trench gate MOS field device includes a gate structure located in the trench. The conventional trench gate MOS field-effect transistor component is formed by forming a trench in a semiconductor substrate and then forming a gate dielectric layer on the sidewall of the trench by thermal oxidation. Thereafter, a polycrystalline germanium semiconductor material is filled in the trench, and after planarization, a polysilicon gate is formed in the trench.

With the increasing complexity of integrated circuits, the feature size of the components and the wiring space are increasingly limited, the size of the polysilicon gate is also reduced, which may cause the polysilicon gate to be subsequently connected to the metal contact plug formed thereon. Misalignment causes metal contact plugs to shift, which in turn causes metal breakdown plugs and peripheral circuits to cause charge breakdown problems.

Therefore, there is a need to provide an advanced trench gate MOS field device and a method of fabricating the same, which solves the problems faced by the prior art.

One aspect of the present invention provides a trench gated metal oxide half field effect transistor device comprising: a substrate and a gate. Wherein the substrate has a groove, Extending downward from the surface of the substrate. The gate has an embedded portion and a symmetrical protrusion. Wherein, the embedded portion is embedded in the groove, and the symmetric protruding portion protrudes symmetrically on the surface.

In an embodiment of the invention, the width of the symmetrical protrusion is substantially greater than the opening size of the groove.

In an embodiment of the invention, the gate is a T-shaped structure of a line in a symmetric trench.

In an embodiment of the invention, the trench has a width substantially equal to or less than 0.8 μm and a depth of substantially 1.6 μm.

In an embodiment of the invention, the trench gate MOS field device further includes a dielectric layer and a contact plug. The dielectric layer is over the substrate and the gate. The contact plug passes through the dielectric layer and is in electrical contact with the symmetric protrusion.

In an embodiment of the invention, the trench gate MOS field device further includes a first electrically doped region, a second electrically doped region, a gate dielectric layer, and a source. pole. Wherein the first electrically doped region is located in the substrate; the second electrically doped region is located in the substrate and forms a P/N junction with the first electrically doped region; the trench is surfaced Lower extending through the first electrically doped region and the P/N junction and into the second electrically doped region; the gate dielectric layer is on the sidewall of the trench; the source region is located in the substrate, And adjacent to the gate dielectric layer.

In an embodiment of the invention, the first electrically doped region is a P-type body region, and the second electrically-doped region is an N-type well region.

In an embodiment of the invention, the trench gate MOS field device further includes an N-type buried layer under the second electrically doped region.

In an embodiment of the invention, the source region is an N-type doped structure that extends from the surface into the first electrically doped region.

Another aspect of the present invention provides a method of fabricating a trench gate MOS field device, comprising the steps of first forming a hard mask layer on a substrate. Next, an etching process is performed to remove a portion of the hard mask layer and form a trench in the substrate. Thereafter, a flared etch is performed on the hard mask layer. Subsequently, a conductor layer is formed on the hard mask layer and the trench is filled. Then, the hard mask layer is used as a stop layer, and the conductor layer is planarized.

In an embodiment of the invention, a pad yttria layer is formed over the substrate prior to forming the hard mask layer.

In an embodiment of the invention, after the hard mask layer is formed, a sacrificial layer is formed over the hard mask layer.

In an embodiment of the invention, before the forming of the conductor layer, a thermal oxidation step is further performed to form a gate dielectric layer on the sidewall of the trench. In an embodiment of the invention, the hard mask layer is a hafnium oxide layer or a tantalum nitride layer.

According to the above embodiment, the present invention provides a trench gate MOS field device and a method of fabricating the same. The trench gate MOS field device component is formed by forming a hard mask layer over the substrate and etching the hard mask layer and the substrate to form a trench in the substrate. Thereafter, the hard mask layer of the trench opening is flank-etched. Subsequently, a layer is formed on the hard mask layer, and the conductor fills the trench. Further, the hard mask layer is used as a stop layer, and the conductor layer is planarized to form a gate electrode embedded in the trench and having symmetric protrusions symmetrically protruding from the surface of the substrate.

By symmetrically protruding the symmetric protrusions on the surface of the substrate, the gate can provide a larger contact space for the metal contact plugs formed thereon, and the conventional technology is limited by the feature size of the components, resulting in metal Contact plug alignment error.

In addition, due to the formation of symmetrical protrusions, it is not etched with yellow light. The method is accomplished by flaring the hard mask layer, increasing the size of the trench opening, and filling the conductor material. There is no need for additional yellow light processing. Therefore, not only the process part can be simplified, but also the process cost can be reduced. The alignment accuracy of the metal contact plug and the gate can be improved because the mask alignment is not required to be repeated.

The present invention is to provide a solution to the problems of the prior art. The above and other objects, features and advantages of the present invention will become more apparent and understood.

Referring to FIGS. 1A through 1F, FIGS. 1A through 1F are cross-sectional views showing a process structure for fabricating a trench gate MOS field device 100 in accordance with a comparative example of the present invention. A method of fabricating a trench gate MOS field device 100 includes the steps of first providing a substrate 101. In an embodiment of the invention, the substrate 101 is a germanium substrate comprising a first electrically doped region 101a, a second electrically doped region 101b, a source region 120, and a second electrically deep well region. 101c.

The first electrically doped region 101a, the second electrically doped region 101b, the source region 120, and the second electrically deep well region 101c are formed on a substrate 101 by a plurality of ion implantation processes. in. The second electrically doped region 101b is located in the substrate 101. The first electrically doped region 101a is located above the second electrically doped region 101b and extends downward from the surface 101d of the substrate 101. The two electrically doped regions 101b are in contact, thereby forming a P/N junction 102. The source region 120 extends downward from the surface 101d of the substrate 101 into the first electrically doped region 101a. The second electrical deep well region 101c is extended downward from the surface 101d of the substrate 101. And extending into contact with the second electrically doped region 101b as the drain region of the trench gate MOS field device 100. In the comparative example of the present invention, below the second electrically-doped region 101b, a buried layer 119 (shown as 1A) having the same electrical conductivity as the second electrically-doped region 101b is further included.

In the comparative example, the second electrically doped region 101b is an N-type well region having a lower doping concentration; the first electrically doped region 101a is a P-type body region; and the source region 120 is a doped region. The N-type well region with higher impurity concentration; the second electrical deep well region 101c is an N-type deep well region, separated by the shallow trench isolation structure 103 and the first electrically-doped region 101a; the buried layer 119 is a blend The N-doped layer having a higher impurity concentration is located below the second electrically doped region 101b and is in contact with the second electrically deep well region 101c. In addition, in order to reduce the contact resistance of the drain, it is preferable to further form an N-type well region 101e having a doping concentration higher than that of the N-type (second-electric) deep well region 101c, by the substrate 101. The surface 101d extends downward and enters the N-type deep well region 101c.

Thereafter, a pad yttrium oxide layer 104, a hard mask layer 105, and a patterned photoresist layer 106 are sequentially formed on the surface 101d of the substrate 101 by thin film deposition or other suitable method to cover the second electrical deep well region. 101c; a source region 120 and a first electrically doped region 101a (as shown in FIG. 1B). For example, the hard mask layer 105 is made of a tantalum nitride material. In addition, the hard mask layer 105 may be made of a yttria material.

Next, using the photoresist of the patterned photoresist layer 106 as a mask, an etching process 107 is performed to remove a portion of the hard mask layer 105, a portion of the pad oxide layer 104, and a portion of the substrate 101, and form a substrate 101. The trench 108, from the surface 101d of the substrate 101, extends downward through the source region 120 and into the second electrically doped region 101b (as depicted in FIG. 1C). In the comparative example of the present invention, the etching process 107 is preferably a dry etching process. The formed trench 108 has substantial A width of 0.8 μm or less and a depth of substantially 1.6 μm.

After removing the patterned photoresist layer 106 and the remaining hard mask layer 105, a thermal oxidation step is performed to form a gate dielectric layer 109 on the sidewall 108a of the trench 108. A polysilicon layer 110 is formed over the pad yttria layer 104 and fills the trenches 108. Then, the polysilicon layer 110 is planarized, such as a chemical mechanical polishing process 111 (as shown in FIG. 1D).

Forming a photoresist layer 112 on the polysilicon layer 110 after planarization, and using the pad oxide layer 104 as an etch stop layer, performing another etching process 113, thereby removing a portion of the planarized polysilicon layer 110, thereby forming The polysilicon gate 114 is as shown in FIG. 1E. The polysilicon gate 114 is a T-shaped structure having an embedded portion 114a embedded in the trench 108 and a surface 101d protruding from the substrate 101 and outwardly defined by the central axis 108b of the trench 108. A laterally extending projection 114b.

Subsequently, a metal interconnect process is performed to form a dielectric material layer 117 before the surface 101d of the substrate 101 and the polysilicon gate 114; and a plurality of metal contact plugs are formed in the dielectric material layer 117. The plug 118 completes the preparation of the trench gate MOS field device 100 (as shown in FIG. 1F).

Referring again to FIG. 1F, since the protruding portion 114b has a lateral extent substantially larger than the embedded portion 114a, the metal contact plug 118 formed on the polysilicon gate 114 can be provided with a large process margin. However, due to the formation of the polysilicon gate 114, at least two yellow etching processes must be performed, and each time the mask alignment error causes an increase in alignment accuracy variation.

In addition, when the etching process 113 is performed, the polysilicon layer 110 after planarization is completely covered on the surface 101d of the substrate 101. It may block the alignment mark of the etch process 113, causing a misalignment of the reticle, causing the protrusion 114b of the polysilicon gate 114 to produce an unintended asymmetric lateral extension. Stretch. If the (alignment) process error of the metal contact plug 118 is subsequently added, it is easy to make the total misalignment error of the component in the process too large, thereby causing the voltage of the metal contact plug 118 and the peripheral circuit to collapse. .

In order to solve this problem, the manner in which the polysilicon gate 114 is formed can be changed. For example, referring to FIGS. 2A through 2E, FIGS. 2A through 2E are cross-sectional views showing a process structure for fabricating a trench gate MOS field device 200 in accordance with an embodiment of the present invention.

In the present embodiment, after the trenches 108 are formed (as depicted in FIG. 1C), the hard mask layer 105 is not removed immediately. Rather, after removing the patterned photoresist layer 106, a flare etch process 215 is performed to remove a portion of the hard mask layer 105; and a portion of the pad oxide layer 104 located in the opening 108c of the trench 108 is exposed. Outside (as shown in Figure 2A). In an embodiment of the invention, the hard mask layer 105 is made of tantalum nitride material; and the flare etching process 215 is performed by using a phosphoric acid to remove a portion of the hard mask layer 105. . However, in another embodiment of the present invention, the hard mask layer 105 is made of ruthenium dioxide material; and the flare etch process 215 is performed by buffer etchant (Buffer Oxide Etcher, BOE). A wet process to remove a portion of the hard mask layer 105.

It should be noted that in order to achieve better control of the flare etch process 215, in an embodiment of the invention, it is preferred to form another layer over the hard mask layer 105 prior to forming the patterned photoresist layer 106. A layer of ruthenium dioxide layer 316 is used as a sacrificial layer of the flare etch process 215 to control the depth and extent of the flare etch process 215 (as shown in FIG. 3).

Thereafter, a thermal oxidation step is performed to form a gate dielectric layer 109 on the sidewall 108a of the trench 108 (as shown in FIG. 2B). A polysilicon layer 110 is formed over the remaining hard mask layer 105 and over the exposed pad oxide layer 104, and fills the trenches 108. Then, using the hard mask layer 105 as a polishing stop layer, the polysilicon layer 110 A planarization is performed, such as a chemical mechanical polishing process 111 (as depicted in Figure 2C).

After removing the remaining hard mask layer 105, a polysilicon gate 214 as depicted in FIG. 2D is formed. The polysilicon gate 214 is a T-shaped structure symmetric to the center line 108b of the trench 108, has an embedded portion 214a embedded in the trench 108, and a surface 101d protruding from the substrate 101, and is symmetric with respect to The central axis 108b of the groove 108 is a laterally extending symmetrical projection 214b.

Subsequently, a metal interconnect process is further performed to form a dielectric material layer 117 over the surface 101d of the substrate 101 and the polysilicon gate 214; and a plurality of metal contact plugs are formed in the dielectric material layer 117. 118, completing the preparation of the trench gate MOS field device 200 (as shown in Figure 2E).

Since the polysilicon gate 214 is wet-processed, the hard mask layer 105 (refer to FIG. 2A) located in the opening 108c of the trench 108 is anisotropically etched, and the polysilicon layer 110 is filled, and the planarization step is performed. Formed. Therefore, the symmetrical protrusion 214b extends symmetrically laterally centering on the center line 108 of the groove 108 (please refer to FIG. 2D). A larger process margin of the metal contact plugs 118 formed on the symmetric protrusions 214b can be provided, which solves the conventional technique, and the metal contact plugs 218 are misaligned due to the limitation of the feature size of the components.

In addition, compared with the comparative example, since a yellow etching process is omitted, not only the process steps can be simplified, but also the use of the reticle can be reduced, and the symmetrical protrusion 214b can be prevented from being unexpected due to misalignment of the reticle. Symmetrical lateral extension to increase the overall alignment error of the components in the process.

According to the above embodiment, the present invention provides a trench gate MOS field device and a method of fabricating the same. The trench gate MOS field device component is formed by forming a hard mask layer over the substrate and etching the hard mask layer and the substrate to form a trench in the substrate. Thereafter, the hard mask layer of the trench opening is flank-etched. Follow-up, forming a guide on the hard mask layer Body layer and fill the trench. Further, the hard mask layer is used as a stop layer, and the conductor layer is planarized to form a gate electrode embedded in the trench and having symmetric protrusions symmetrically protruding from the surface of the substrate.

By symmetrically protruding symmetrically from the surface of the substrate, the gate can provide a greater processing margin for the metal contact plugs subsequently formed thereon. Solving the problem that the conventional technology is miniaturized due to the feature size of the component, resulting in misalignment of the metal contact plug.

In addition, due to the formation of the symmetrical protrusions, the method of etch etching by yellow light is not used, but the hard mask layer is etched by flaring, the opening size of the trench is increased, and the conductor material is filled. There is no need for additional yellow light processing. Therefore, not only the process steps can be simplified, but also the process cost can be reduced. The alignment accuracy of the metal contact plug and the gate can be improved because the mask alignment is not required to be repeated.

While the invention has been described above in the preferred embodiments, it is not intended to limit the invention. Anyone having ordinary knowledge in the field can make some changes and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100‧‧‧Terrace gate MOS half field effect transistor

101‧‧‧Substrate

101a‧‧‧First electrically doped area

101b‧‧‧Second electrically doped area

101c‧‧‧Second electric deep well area

101d‧‧‧Substrate surface

101e‧‧‧N type well area

102‧‧‧P/N junction

103‧‧‧Shallow trench isolation structure

104‧‧‧The ruthenium oxide layer

105‧‧‧hard mask layer

106‧‧‧ patterned photoresist layer

107‧‧‧ etching process

108‧‧‧ trench

108a‧‧‧ trench sidewall

108b‧‧‧Center of the groove

108c‧‧‧Gap opening

109‧‧‧gate dielectric layer

110‧‧‧Polysilicon layer

111‧‧‧Chemical mechanical grinding process

112‧‧‧ patterned photoresist layer

113‧‧‧ etching process

114‧‧‧Polysilicon gate

114a‧‧‧ Embedding Department

114b‧‧‧Protruding

117‧‧‧ dielectric material layer

118‧‧‧Metal contact plug

119‧‧‧buried layer

120‧‧‧ source area

200‧‧‧Terrace gate MOS half field effect transistor

215‧‧‧ flare etch process

214‧‧‧Polysilicon gate

214a‧‧‧ Embedding Department

214b‧‧ symmetrical protrusion

316‧‧ 二2 layer

1A to 1F are cross-sectional views showing a process structure for fabricating a trench gate MOS field device according to a comparative example of the present invention.

2A through 2E are cross-sectional views showing a process structure for fabricating a trench gate MOS field device in accordance with an embodiment of the present invention.

3 is a cross-sectional view showing a portion of a process structure for fabricating a trench gate MOS field device in accordance with another embodiment of the present invention.

101‧‧‧Substrate

101a‧‧‧First electrically doped area

101b‧‧‧Second electrically doped area

101c‧‧‧Second electric deep well area

103‧‧‧Shallow trench isolation structure

101e‧‧‧N type well area

102‧‧‧P/N junction

104‧‧‧The ruthenium oxide layer

109‧‧‧gate dielectric layer

117‧‧‧ dielectric material layer

118‧‧‧Metal contact plug

119‧‧‧buried layer

120‧‧‧Source/Bungee Area

200‧‧‧Terrace gate MOS half field effect transistor

214‧‧‧Polysilicon gate

214a‧‧‧ Embedding Department

214b‧‧ symmetrical protrusion

Claims (5)

A method for fabricating a trench gate MOS field device, comprising: forming a hard mask layer on a substrate; performing an etching process to remove a portion of the hard mask layer and on the substrate Forming a trench; performing a flare etching on the hard mask layer; forming a conductor layer on the hard mask layer and filling the trench; and using the hard mask layer as a stop layer, The conductor layer is subjected to a chemical mechanical polishing process. The method for fabricating a trench gate MOS field device according to claim 1, wherein before forming the hard mask layer, forming a pad yttrium oxide on the substrate Floor. The method for fabricating a trench gate MOS field device according to claim 1, wherein after forming the hard mask layer, forming a sacrificial layer on the hard mask layer Floor. The method for fabricating a trench gate MOS field device according to claim 1, wherein before forming the conductor layer, further comprising performing a thermal oxidation step on the sidewall of the trench, A gate dielectric layer is formed. The method for fabricating a trench gate MOS field device according to claim 1, wherein the hard mask layer is a ruthenium oxide layer or a nitrogen 矽 layer.