TWI438895B - Light-emitting diode array - Google Patents

Description

Light-emitting diode array

The present invention relates to a light emitting device, and more particularly to an array of light emitting diodes.

Light emitting diodes (LEDs) have been used in a variety of lighting applications and provide exit light across the visible, ultraviolet, and/or infrared wavelengths. The above lighting applications include displays, printers, and communications. One of the light-emitting diodes is a III-V compound semiconductor element such as a GaN-light emitting diode (GaN LED).

However, it is often desirable to use a greater number of light emitting diodes in the above illumination applications to provide sufficient brightness. However, since such light-emitting diodes may operate simultaneously in a lighting application. Therefore, it is necessary to provide appropriate light-resistance characteristics between adjacent light-emitting diodes to prevent the emitted light from being absorbed by the adjacent light-emitting diodes, thereby increasing the light output efficiency.

According to an embodiment, the present invention provides an array of light emitting diodes, comprising: a substrate on which an array formed by sequentially arranging a plurality of light emitting diode chips, a dielectric layer, a plug, and A conductive connection layer. In one embodiment, each of the LED chips is separated from the other LEDs in the adjacent columns by a trench, and each of the LEDs includes: a buffer layer a first type semiconductor formed on the buffer layer, wherein the first type semiconductor includes a higher second land area and a lower first land area; an active layer is formed on the second land area; A second type semiconductor is formed on the active layer; a first type electrode is formed on the second type semiconductor; and a second type electrode is formed on the active layer. The dielectric layer covers the surface of the substrate exposed by each trench and the sidewalls of the light-emitting diode chip on both sides of the trench and a portion of the surface of the first-type semiconductor layer and a portion of the second-type semiconductor layer, and exposes the above A type electrode and the above second type electrode. The plug is filled in the trench and is surrounded by the dielectric layer and surrounded by the dielectric layer. The conductive connection layer is located on the plug and the dielectric layer, such that the first type electrode of each of the light emitting diodes and the second of the other light emitting diodes adjacent to each other are adjacent to each other. Type electrode connection.

The above described objects, features and advantages of the present invention will become more apparent and understood.

Referring to FIG. 1-4, a method for fabricating an LED array according to an embodiment of the present invention is shown. The LED array produced has better light output efficiency.

As shown in Fig. 1, first, a substrate 100 is provided on which a plurality of light emitting diode wafers are formed. For the purpose of simplifying the illustration, only two adjacent light emitting diode wafers 150 and 160 formed on the substrate 100 are shown. In one embodiment, the substrate 100 is, for example, a sapphire substrate or a germanium-containing substrate, and the light-emitting diode wafers 150 and 160 are formed on one portion of the substrate 100 in a spaced relationship, and are sequentially arranged to form an array. As shown in FIG. 1, the adjacent LED chips 150 and 160 are separated by a trench 110, and the trench 110 exposes a portion of the surface of the substrate 100.

Continuing to refer to FIG. 1 , the LED chips 150 and 160 can be simultaneously formed on different portions of the surface of the substrate 100 by conventional LED chips, and respectively include one of the portions of the substrate 100. The buffer layer 102, a first type semiconductor layer 104, an active layer 106 and a second type semiconductor layer 108. Here, the first type semiconductor layer 104 is a non-flat film layer including a lower one of the first land area 105a and a higher one of the second land area 105b, and the active layer 106 and the second type semiconductor layer 108 Formed on the first land area 105a of the first type semiconductor layer 104 in sequence. In one embodiment, the material of the buffer layer 102 is, for example, selected from the group consisting of gallium nitride, aluminum nitride, aluminum indium, aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), and indium aluminum nitride (AlInN). And at least one material of the material group formed by indium aluminum nitride (AlInGaN), and the material of the first type semiconductor layer 104 and the second type semiconductor layer 108 is, for example, a gallium-containing nitride, and the material of the active layer 106 For example, a gallium-containing nitride, and a plurality of layers of quantum well structure layers (not shown) may be included in the active layer 106. In one embodiment, the first type semiconductor layer 104 can be a P-type semiconductor layer, and the second type semiconductor layer 108 can be an N-type semiconductor layer. Alternatively, in another embodiment, the first type semiconductor layer 104 may be an N type semiconductor layer, and the second type semiconductor layer 108 may be a P type semiconductor layer.

Referring to FIG. 2, a dielectric material (not shown) is then deposited on the substrate 100 and the LED wafers 150, 160, and then formed by a patterning process (not shown). A dielectric layer 112 is disposed within the trench 110. The dielectric layer 112 covers, in addition to the surface of the substrate 100 exposed by the trench 110, partially covering the plurality of light emitting diode wafers 150 adjacent to the trench 110. One of the 160.

As shown in FIG. 2, the dielectric layer 112 covers the entire surface of the substrate 100 in the trench 110 and partially covers one of the light-emitting diode chips 150, 160 adjacent to the trench 110, for example, covering the light-emitting diodes a portion of the surface of the first land region 105a of the first type semiconductor layer 104 of the polar body wafer 150, a sidewall of the first type semiconductor layer 104 and the buffer layer 102 in the light emitting diode chip 150, and a light emitting diode wafer 160 The first type semiconductor layer 104, the buffer layer 102, the sidewalls of the active layer 106 and the second type semiconductor layer 108, and the second type on the second land area 105b of the first type semiconductor layer 104 of the LED wafer 160 Part of the surface of the semiconductor layer 108. The dielectric layer 112 may include at least one material selected from the group consisting of cerium oxide, cerium nitride, cerium oxynitride, and aluminum oxide.

Referring to FIG. 3, a resist material (not shown) is formed on the substrate 100, for example, a negative resist material, to cover the LED chips 150 and 160 in a frank manner. The surface of the substrate 100. Next, a patterning process is performed to pattern the resist material and expose the trench 110 again, and form a patterned resist layer 114 over the substrate 100.

As shown in FIG. 3, the patterned resist layer 114 covers the light-emitting diode wafers 150, 160 and a portion of the substrate 100. A deposition process 120 is then performed to deposit the reflective material 116 over the substrate 100 in a candid manner. Here, the deposition process 120 is, for example, a sputtering process or an evaporation process, and the reflective material 116 formed includes a material group selected from the group consisting of aluminum, silver, titanium, platinum, rhodium, palladium, iridium, ruthenium, and zinc. At least one of the materials in the set, the reflective material 116 has a reflectivity of greater than 80% for light (not shown) emitted by the LED chips 150 and 160.

As shown in FIG. 3, after deposition, the reflective material 116 is partially filled in the trench 110 and is formed over the patterned resist layer 114, and the reflective material formed in the trench 110 is formed. 116 may have a circular arc-like surface 118 that is substantially no higher than the surface of dielectric layer 112 that covers adjacent light-emitting diode wafers 150 and 160.

Referring to FIG. 4, a removal process (not shown) is then performed to remove the resist layer 114 and simultaneously lift-off the portion of the reflective material 116 formed on the resist layer 114, thereby in the trench 110. One of the plugs 116a formed by the reflective material 116 (see Fig. 3) is left. Next, a conductive material, such as gold, silver, nickel, platinum or an alloy thereof, is deposited and formed by a patterning process (not shown) to simultaneously form a plurality of phase-separated conductive connection layers 122 on the substrate 100. The conductive layer 124 and the conductive layer 126.

As shown in FIG. 4, the conductive layer 124 is formed on a portion of the second type semiconductor layer 108 of the light emitting diode wafer 150 for use as a second type electrode. The conductive connection layer 122 connects the light emitting diode 150 and the light emitting diode 160. In more detail, the conductive connection layer 122 is partially formed on a portion of the first land area 105a of the first type semiconductor layer 114 of the LED chip 150 as one of the light emitting diode chips 150. For a type of electrode, the conductive connection layer 122 is formed on the upper surface of the plug 116a and the dielectric layer 112 in the trench 110 and extends to the LED wafer 160 to partially cover the LED wafer 160. A portion of the second type semiconductor layer 108 is used as a second type electrode of the light emitting diode wafer 160. Moreover, the conductive layer 126 is formed on the first land region 105a of the first type semiconductor layer 104 of the LED substrate 160 for use as a first type electrode.

Referring to the schematic diagram of Fig. 5, the advantages of the preferred light output efficiency of the LED array according to an embodiment of the present invention shown in Fig. 4 are shown. As shown in FIG. 5, in operation, a portion of the light 170 emitted by the active layer 106 in the LED array 160 in the LED array can be mostly the dielectric layer 112 and the plug 116a. The light rays 170 that are reflected and reflected may pass through the first type semiconductor layer 104 and the buffer layer 102 and finally reflect through the substrate 100, and then emit light toward the side of the light emitting diode wafer 160 not adjacent to the trench 110. Therefore, it does not penetrate and absorb the adjacent light-emitting diode chip 150, so that the light-emitting performance of the light-emitting diode wafer 150 is not affected and the light output efficiency of the light-emitting diode wafer 160 itself can be improved. In addition, since the plug 116a formed in the trench 110 is made of a metal material, it also has high thermal conductivity, which also contributes to the heat dissipation effect of the LED chips 150 and 160.

Referring to Figures 6-7, respectively, one of the possible cases of a light-emitting diode array as shown in Fig. 4 is shown, wherein the cross-sectional condition of the line segment 4-4 is as shown in Fig. 4. Light-emitting diode array.

Referring to FIG. 6, in this embodiment, the plug 116a is formed only in a portion of the trench 110 to separate the LED chips 150 and 160, and the other portions of the trench 110 are not filled. The surface of the substrate 100 that is filled in with the plug 116a and not filled in the portion of the trench 110 of the plug 116a is still exposed by the trench 110.

Alternatively, as shown in FIG. 7, the plug 116a can be completely filled in the trench 110 separating the LEDs 150 and 160, and thus does not expose the surface of the substrate 100 under the trench 110.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the invention may be modified and retouched without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application attached.

100. . . Substrate

102. . . The buffer layer

104. . . First type semiconductor layer

105a. . . First platform area

105b. . . Second platform area

106. . . Active layer

108. . . Second type semiconductor layer

110. . . ditch

112. . . Dielectric layer

114. . . Resistive layer

116. . . Reflective material

116a. . . Plug

118. . . Top surface

120. . . Deposition process

122. . . Conductive connection layer

124, 126. . . Conductive layer

150, 160. . . Light-emitting diode chip

170. . . Light

Figures 1-4 illustrate the fabrication of an array of light emitting diodes in accordance with an embodiment of the present invention;

Figure 5 is a schematic diagram showing the operation of an array of light emitting diodes in accordance with an embodiment of the present invention;

Figure 6 is a top view showing an array of light emitting diodes in accordance with an embodiment of the present invention;

Figure 7 is a top view showing an array of light emitting diodes in accordance with another embodiment of the present invention.

100. . . Substrate

102. . . The buffer layer

104. . . First type semiconductor layer

105a. . . First platform area

105b. . . Second platform area

106. . . Active layer

108. . . Second type semiconductor layer

110. . . ditch

112. . . Dielectric layer

116a. . . Plug

122. . . Conductive connection layer

124, 126. . . Conductive layer

150, 160. . . Light-emitting diode chip

Claims (12)

An array of light emitting diodes includes: a substrate on which an array formed by sequentially arranging a plurality of light emitting diode chips, wherein each of the light emitting diode chips is adjacent to another column The light emitting diodes are separated by a trench, and each of the light emitting diode chips comprises: a buffer layer; a first type semiconductor is formed on the buffer layer, and the first type semiconductor comprises a a second second platform region and a lower first platform region; an active layer formed on the second platform region; a second type semiconductor formed on the active layer; a first type electrode formed on the first a platform region; and a second type electrode formed on the second type semiconductor; a dielectric layer covering the surface of the substrate exposed by each trench and sidewalls of the LED array on both sides of the trench and a portion of the surface of the first type semiconductor layer and a portion of the second type semiconductor layer, and exposing the first type electrode and the second type electrode; a plug is filled in the trench and located on the dielectric layer Surrounded by; and one An electrical connection layer disposed on the plug and the dielectric layer such that the first type electrode of each of the light emitting diodes and the other one of the other light emitting diodes adjacent to the one of the light emitting diodes Type 2 electrode connection. The light-emitting diode array according to claim 1, wherein the plug is formed by a reflective material filled in part or all of the inner space of the trench. The light-emitting diode array of claim 2, wherein the plug has a reflectance higher than 80% for light emitted by the active layer. The light-emitting diode array according to claim 3, wherein the plug comprises at least one selected from the group consisting of aluminum, silver, titanium, platinum, rhodium, palladium, iridium, ruthenium and zinc. material. The light-emitting diode array of claim 4, wherein the dielectric layer comprises at least one material selected from the group consisting of cerium oxide, cerium nitride, cerium oxynitride, and aluminum oxide. The light-emitting diode array of claim 5, wherein the conductive connection layer comprises gold, silver, nickel, platinum or an alloy thereof. The light emitting diode array of claim 1, wherein the first type semiconductor and the second type semiconductor are both gallium-containing nitrides. The light-emitting diode array according to claim 7, wherein the buffer layer is selected from the group consisting of gallium nitride, aluminum nitride, aluminum indium nitride, aluminum gallium nitride, indium gallium nitride, indium aluminum nitride, and At least one material selected from the group consisting of gallium indium nitride. The illuminating diode array of claim 8, wherein the active layer is a gallium-containing nitride. The illuminating diode array of claim 9, wherein the active layer further comprises a plurality of quantum well structure layers. The illuminating diode array according to any one of claims 1 to 10, wherein the first type is a P type and the second type is an N type, or the first type is an N type and the second type For the P type. The illuminating diode array according to claim 11, wherein the substrate is a sapphire substrate or a ruthenium-containing substrate.