TWI437777B - Electric assembly and application thereof - Google Patents

Description

Electronic assembly and its application

The present invention relates to an electronic assembly and its use, and more particularly to an electronic assembly suitable for use in a Universal Serial Bus (USB) architecture and its applications.

Universal Serial Bus 3.0 (USB 3.0) is a signal transmission specification developed from USB 2.0 with a transfer rate of 5G bps, while traditional USB 2.0 has a transfer rate of only 480M bps. The USB 3.0 electrical connector has been determined to be compatible with USB 2.0 electrical connectors, meaning that USB 3.0 uses the same electrical connector structure as USB 2.0 and adds several pins for USB 3.0 functionality. Therefore, under the USB 2.0-based electrical connector structure, it is necessary to propose a USB 3.0 electrical connector structure to meet the demand.

The invention provides an electronic assembly and an application thereof, which has a relatively simple structure and can save manufacturing costs of electronic assembly.

The present invention provides an electronic assembly that includes a circuit board and a plurality of pins. The circuit board has a stack of layers and a plurality of pads. The laminated layer has a surface. The pad includes a pair of differential signal pads, and the pair of differential signal pads are disposed on the surface of the laminated layer. The pins are soldered to the board separately. The pin includes a pair of first differential signal pins and a pair of second differential signal pins.

The invention further provides a storage device comprising a circuit board, a plurality of pins, a control wafer and a storage wafer. The circuit board includes a stack of layers and a plurality of pads. The laminated layer has a surface. The pad includes a pair of differential signal pads, and the pair of differential signal pads are disposed on the surface of the laminated layer. The pins are soldered to the board separately. The pin includes a pair of first differential signal pins and a pair of second differential signal pins. The control wafer is mounted to the laminated layer of the wiring board. The storage wafer is mounted to the laminate layer of the circuit board.

Based on the above, since the electronic assembly of the present invention and its application directly form a plurality of pads by the patterned metal layer of the surface of the wiring board closest to the surface of the laminated layer, the electronic assembly structure of the present invention is relatively simple and can save Manufacturing costs for electronic assembly.

The above described features and advantages of the present invention will be more apparent from the following description.

The electronic assembly proposed by the present invention is applicable to the USB 3.0 architecture. In the USB 3.0 architecture of the present invention, the present invention directly forms a plurality of pads by using a patterned metal layer closest to the surface of the circuit board, compared to the conventional USB 2.0 and USB 3.0 suitable circuit boards. The pad is, for example, a pad that supports a USB 1.0 architecture or a USB 2.0 architecture. In addition, the present invention also includes multiple pins on the circuit board, which are, for example, five pins supporting the USB 3.0 architecture, wherein the four pins are used for transmitting a differential signal pair and receiving. The differential signal pair is used, and the fifth pin is used for the grounding function. In short, the electronic assembly of the present invention integrates pads and pins supporting different architectures to be streamlined on the same circuit board. The design of the electronic assembly will be separately and in detail described below using a number of different embodiments.

1A is a schematic view of an electronic assembly in accordance with an embodiment of the present invention. 1B is a partial cross-sectional view of the electronic assembly of FIG. 1A. Figure 1C is a schematic illustration of a receptacle connector to which the present invention is applicable. 1D is a partial cross-sectional view of the receptacle connector of FIG. 1C. Referring first to FIG. 1A and FIG. 1C, in the present embodiment, the electronic assembly 100 is adapted to be coupled to a receptacle connector 10, such as a receptacle connector 10 that supports a USB 3.0 architecture. The portion of the electronic assembly 100 described herein that is coupled to the receptacle connector 10 can be considered a plug, and the receptacle connector 10 can be considered a receptacle.

In detail, referring to FIG. 1C and FIG. 1D, the socket connector 10 applicable to the USB 3.0 architecture described in this embodiment includes a pin row 20 and another pin row arranged side by side with the pin row 20. 30. The pin string 20 includes a pair of differential signal pins 22, another pair of differential signal pins 24, and a ground pin 26 between the pair of differential signal pins 22 and 24.

In this embodiment, the pair of differential signal pins 22 are, for example, a pair of receiving differential signal pin terminals R _x ⁺ and R _x ^- in the USB 3.0 architecture, which receive the differential signal pins from the plug end. The signals of the terminals T _x ⁺ and T _x ^- and the other pair of differential signal pins 24 are, for example, a pair of differential signal pin terminals T _x ⁺ and T _x ^- in the USB 3.0 architecture, which transmit signals to The plug end receives the differential signal pin terminals R _x ⁺ and R _x ^- . The pin string 30 includes a ground pin 32, a power pin 34 and a pair of differential signal pins 36 between the ground pin 32 and the power pin 34. In addition, the pair of differential signal pins 36 are, for example, a pair of transmit/receive differential signal terminals D ⁺ and D ^{- that} can support the USB 1.0 architecture or the USB 2.0 architecture.

Referring to FIG. 1A and FIG. 1B , the electronic assembly 100 of the present embodiment includes a circuit board 110 and a plurality of pins 120 . The circuit board 110 has a stacking layer 112, a plurality of through holes 114, and a plurality of pads 116. In this embodiment, the laminated layer 112 has a surface 112a, and the laminated layer 112 is composed of, for example, a plurality of dielectric layers 112b and a plurality of patterned metal layers 112c that are alternately overlapped with the dielectric layers, wherein The patterned metal layers 112c are electrically connected to each other through vias 112d. These through holes 114 extend through the laminated layer 112. The pads 116 include a pair of differential signal pads 116a, a ground pad 116b, and a power pad 116c. The pair of differential signal pads 116a, the grounding pads 116b and the power pads 116c are disposed on the surface 112a of the laminated layer 112, and the pair of differential signal pads 116a are located on the ground pad 116b and the power pad 116c. between. It is worth mentioning that the pads 116 of the present embodiment are formed by a patterned metal layer 112c closest to the surface 112a of the laminated layer 112.

The pins 120 are soldered to the through holes 114 of the circuit board 110 , wherein the pins 120 include a pair of first differential signal pins 122 , a pair of second differential signal pins 124 , and a ground pin 126 . . The pair of first differential signal pins 122 and the pair of second differential signal pins 124 are projected on the surface 112a of the layer 112 and the pair of differential signal pads 116a on the surface 112a of the layer 112. The orthographic projections do not overlap. That is, the pair of first differential signal pins 122, the pair of second differential signal pins 124, and the pair of differential signal pads 116a are staggered. In addition, the ground pin 126 is located between the pair of first differential signal pins 122 and the pair of second differential signal pins 124.

In the present embodiment, the pads 116a, for example, which support USB 1.0 or USB 2.0 architecture schema pair of transmitting / receiving the differential signals D ⁺ and D terminal of the differential signal ^-. In general, the transmit/receive differential signal terminals (D ⁺ and D ^- ) are half-duplex transmission mode, that is, the transmission or reception of signals can only be performed one by one. That is to say, when data transmission is performed, data reception cannot be performed, and when data reception is performed, data transmission cannot be performed.

In addition, the pair of first differential signal pins 122 are, for example, a pair of differential signal terminals T _x ⁺ and T _x ^- in the USB 3.0 architecture, and the pair of second differential signal pins 124 are in the USB 3.0 architecture. The pair receives the differential signal terminals R _x ⁺ and R _x ^- . In the USB 3.0 architecture, the differential signal terminals (T _x ⁺ and T _x ^- ) and the differential signal terminals (R _x ⁺ and R _x ^- ) are transmitted in a full-duplex transmission mode, that is, the transmission or reception of signals. Can be done directly. It should be noted that the transmission speed supported by the pair of first differential signal pins 122 and the pair of second differential signal pins 124 is higher than the transmission speed supported by the pair of differential signal pads 116a.

In this embodiment, the shape of one end of the pins 120 is, for example, a reversed hook shape, but the invention is not limited thereto. In other embodiments, the shape of one end of the pins 120 may also be a protrudent shape. However, the present invention does not limit the form of these pins 120, although the pins 120 referred to herein are individually separate members and are soldered to the through holes 114 of the circuit board 110, respectively.

Referring to the embodiment of FIG. 1E, portions of the pins 120 may also be partially encapsulated in the insulative housing 150 through an insulative housing 150. That is to say, the individual independent pins 120 can be first integrated into the unitary structure through the insulating housing 150. Thereafter, the integral structure is soldered to the circuit board 110 to help reduce the time required to position the pins 120 prior to soldering.

In addition, in another example not shown, the circuit board 110 may not have the through holes 114, and the pins 120 are soldered to the circuit board 110 in a surface mount manner. In addition, in another example not shown, the circuit board 110 may have only a part of the through holes 114, and some of the pins 120 are soldered to the through holes 114 of the circuit board 110, and the rest of the other The pins 120 are soldered to the circuit board 110 in a surface mount manner. Accordingly, the shapes of the pins 120 described herein are for illustrative purposes only and are not intended to limit the scope of the invention.

2A is a schematic illustration of the socket assembly of FIG. 1C plugged into the electronic assembly of FIG. 1A. 2B is a partial cross-sectional view of the electronic connector of FIG. 1A plugged into the socket assembly of FIG. 1C. Referring to FIG. 2A and FIG. 2B simultaneously, when the socket connector 10 is connected to the electronic assembly 100, the pair of differential signal pins 22 of the pin row 20 directly contact the pair of first differential signals of the pins 120, respectively. The legs 122, and the pair of differential signal pins 24 directly contact the pair of second differential signal pins 124 of the pins 120, and the ground pins 26 directly contact the ground pins 126. The grounding pin 32 of the pin row 30 directly contacts the grounding pad 116b, and the power pin 34 directly contacts the power pad 116c, and the pair of differential signal pins 36 directly contact the pair of differential signal pads 116a. Since the receptacle connector 10 can directly contact the pads 116 formed by the circuit board 110, the quality of the high speed signal path can be maintained.

In short, since the electronic assembly 100 of the present embodiment is provided with the pads 116 supporting the USB architecture (for example, USB 1.0 or USB 2.0 architecture) on the surface 112a of the laminated layer 112 of the circuit board 110, These pins 120 supporting another USB architecture (e.g., USB 3.0 architecture) are soldered to the through holes 114 of the circuit board 110, respectively. In this way, the pads 116 supporting the different architectures can be integrated with the pins 120 to be streamlined on the same circuit board 110, and the transmission speeds supported by the pins 120 are higher than those supported by the pads 116. speed.

In addition, a plurality of pads 116 supporting the USB architecture are directly formed by the patterned metal layer 112c of the surface 110a of the circuit board 110 closest to the surface 112a of the stacked layer 112, so that the socket connector 10 having different architectures can be simultaneously supported. The structure of the electronic assembly 100 of the present embodiment is also relatively simple, and the manufacturing is also relatively simple, and the manufacturing cost of the electronic assembly 100 can be saved.

In one embodiment, the electronic assembly 100 of the present embodiment can be applied to a storage device, particularly a thin, card-type storage device (eg, a thin memory card). Since the present invention directly forms a plurality of pads 116 supporting the USB architecture by using the patterned metal layer 112c of the surface 110a of the wiring board 110 closest to the overlapping layer 112, the entire electronic assembly 100 is smaller and lighter. It is convenient for users to carry with them. The user can connect to the socket end of another electronic device through the plug of the electronic assembly 100, and the data can be accessed at any time. In addition, the pair of differential signal pads 116a, the pair of first differential signal pins 122, and the pair of second differential signal pins 124 are electrically connected to the control chip respectively for signal transmission. The structural design of the storage devices 100a to 100g will be separately described below using a plurality of different embodiments.

The following embodiments are used to identify the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted portions, reference may be made to the foregoing embodiments, and the detailed description thereof will not be repeated in the following embodiments.

3A is a block diagram of a storage device in accordance with an embodiment of the present invention. Referring to FIG. 3A, the storage device 100a of the present embodiment is similar to the electronic assembly 100 of the foregoing embodiment, and the main difference is that the storage device 100a of the present embodiment further includes a control chip 130a mounted to the circuit board 110 and an installation. The storage wafer 140a of the circuit board 110 is electrically connected to the storage wafer 140a for signal transmission. In detail, in the embodiment, the control wafer 130a is, for example, a wafer for controlling access of the storage wafer 140a, wherein the type of the storage wafer 140a is, for example, a NAND Flash, but is not limited. herein.

3B to 3G are schematic cross-sectional views of a storage device according to various embodiments of the present invention. Referring first to FIG. 3B, in the present embodiment, the memory wafer 140b is stacked on the control wafer 130b, for example, and the control wafer 130b is transmitted through the patterned metal layers (not shown) in the stacked layer 112 of the circuit board 110. Electrically connected to the pins 120 (only one first differential signal pin 122 is schematically illustrated in FIG. 3B) and the pads 116 (only one ground pad 116b is schematically illustrated in FIG. 3B). It should be noted that, in other embodiments not shown, the control chip 130b can also be electrically connected to the pins 120 and the pads 116 through via holes (not shown) and the patterned metal layers. .

It is worth mentioning that the present invention does not limit the position of the control wafer 130b and the storage wafer 140b. For example, in other embodiments, referring to FIG. 3C, the control wafer 130c and the memory wafer 140c may also be embedded in the circuit board 110 independently and independently.

Referring to FIG. 3D, the control wafer 130d and the memory wafer 140d may also be individually and independently disposed on the surface 112a of the laminate layer 112 of the circuit board 110.

Referring to FIG. 3E, the memory wafer 140e is stacked on the control wafer 130e, and the memory wafer 140e and the control wafer 130e are buried in the circuit board 110.

Referring to FIG. 3F, the control wafer 130f is disposed on the surface 112a of the stacked layer 112 of the circuit board 110, and the memory wafer 140f is buried in the circuit board 110.

Referring to FIG. 3G, the memory wafer 140g is disposed on the surface 112a of the stacked layer 112 of the circuit board 110, and the control wafer 130g is buried in the circuit board 110.

The locations of the control wafers 130a-130g and the memory wafers 140a-140g described herein are for illustrative purposes only and are not intended to limit the scope of the invention.

In summary, since the electronic assembly of the present invention and its application are directly formed by a patterned metal layer on the surface of the circuit board, a plurality of pads supporting the USB architecture (for example, USB 1.0 or USB 2.0 architecture) are soldered. A plurality of pins supporting another USB architecture (for example, USB 3.0 architecture), in addition to supporting socket connectors having different USB architectures at the same time, the electronic assembly structure of the present invention is also relatively simple, thereby saving manufacturing of electronic components. cost. In addition, a part of the pins of the socket connector can directly contact the plurality of pads formed by the circuit board of the electronic assembly of the present invention, thereby maintaining the quality of the high-speed signal channel.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10. . . Socket connector

20. . . Pin column

twenty two. . . Differential signal pin

twenty four. . . Differential signal pin

26. . . Grounding pin

30. . . Pin column

32. . . Grounding pin

34. . . Power pin

36. . . Differential signal pin

100. . . Electronic assembly

100a～100g. . . Storage device

110. . . circuit board

112. . . Laminated layer

112a. . . surface

112b. . . Dielectric layer

T12c. . . Patterned metal layer

112d. . . Guide hole

114. . . Through hole

116. . . Pad

116a. . . Differential signal pad

116b. . . Grounding pad

116c. . . Power pad

120. . . Pin

122. . . First differential signal pin

124. . . Second differential signal pin

126. . . Grounding pin

130a～130g. . . Control chip

140a～140g. . . Storage chip

150. . . Insulating housing

1A is a schematic view of an electronic assembly in accordance with an embodiment of the present invention.

1B is a partial cross-sectional view of the electronic assembly of FIG. 1A.

Figure 1C is a schematic illustration of a receptacle connector to which the present invention is applicable.

1D is a partial cross-sectional view of the receptacle connector of FIG. 1C.

1E is a schematic view of the pin of FIG. 1A packaged in an insulative housing.

2A is a schematic illustration of the socket assembly of FIG. 1C plugged into the electronic assembly of FIG. 1A.

2B is a partial cross-sectional view of the electronic connector of FIG. 1A plugged into the socket assembly of FIG. 1C.

3A is a block diagram of a storage device in accordance with an embodiment of the present invention.

3B to 3G are schematic cross-sectional views of a storage device according to various embodiments of the present invention.

100. . . Electronic assembly

110. . . circuit board

112. . . Laminated layer

112a. . . surface

112c. . . Patterned metal layer

114. . . Through hole

116. . . Pad

116a. . . Differential signal pad

116b. . . Grounding pad

116c. . . Power pad

120. . . Pin

122. . . First differential signal pin

124. . . Second differential signal pin

126. . . Grounding pin

Claims (14)

An electronic assembly comprising: a circuit board comprising a laminated layer and a plurality of pads, wherein the laminated layer has a surface, and the pads comprise a pair of differential signal pads, and the pair of differential signals a pad disposed on the surface of the laminated layer, wherein the laminated layer comprises at least one patterned metal layer, wherein the patterned metal layer closest to the surface forms the pads; and the plurality of pins are soldered to The circuit board, wherein the pins comprise a pair of first differential signal pins and a pair of second differential signal pins, and the pads and the pins are adapted to be connected to the same socket connector. The electronic assembly of claim 1, wherein the pair of first differential signal pins and the pair of second differential signal pins support a transmission speed higher than that supported by the pair of differential signal pads. transfer speed. The electronic assembly of claim 1, wherein the circuit board has a plurality of through holes extending through the laminated layer, and the pins are respectively soldered into the through holes. The electronic assembly of claim 1, wherein the pads further comprise a grounding pad and a power pad disposed on the surface of the laminated layer and respectively located in the pair of differential signals The side of the pad; the pins further include a grounding pin between the pair of first differential signal pins and the pair of second differential signal pins. The scope of the patent application to item 1 of the electronic assembly, wherein the pair of differential signal pad is a pair of transmitting / receiving terminal of the differential signal D ⁺ and D ^-; the first differential signal pair is a pair of conveyance pin The differential signal terminals T _x ⁺ and T _x ^- ; the pair of second differential signal pins are a pair of receiving differential signal terminals R _x ⁺ and R _x ^- . The electronic assembly of claim 1, further comprising an insulative housing, wherein the pins are partially encapsulated in the insulative housing. A storage device comprising: a circuit board comprising a laminated layer and a plurality of pads, wherein the laminated layer has a surface, and the pads comprise a pair of differential signal pads, and the pair of differential signals a pad disposed on the surface of the laminated layer, wherein the laminated layer comprises at least one patterned metal layer, wherein the patterned metal layer closest to the surface forms the pads; a plurality of pins are soldered to the a circuit board, wherein the pins comprise a pair of first differential signal pins and a pair of second differential signal pins, and the pads and the pins are adapted to be connected to the same socket connector; a control chip And the stacked layer mounted to the wiring board; and a storage wafer mounted to the laminated layer of the wiring board. The storage device of claim 7, wherein the control wafer is located on or embedded in the surface of the laminated layer. The storage device of claim 7, wherein the storage wafer is located on or embedded in the surface of the laminate layer. The storage device of claim 7, wherein the pair of first differential signal pins and the pair of second differential signal pins support a transmission speed higher than that supported by the pair of differential signal pads transfer speed. The storage device of claim 7, wherein the circuit board has a plurality of through holes extending through the laminated layer, and the pins are respectively soldered into the through holes. The storage device of claim 7, wherein the pads further comprise a grounding pad and a power pad disposed on the surface of the laminated layer and respectively located in the pair of differential signals The side of the pad; the pins further include a grounding pin between the pair of first differential signal pins and the pair of second differential signal pins. The application storage device of claim patentable scope of item 7, wherein the pair of differential signal pad is a pair of transmitting / receiving terminal of the differential signal D ⁺ and D ^-; the first differential signal pair is a pair of conveyance pin The differential signal terminals T _x ⁺ and T _x ^- ; the pair of second differential signal pins are a pair of receiving differential signal terminals R _x ⁺ and R _x ^- . The storage device of claim 7, further comprising an insulative housing, wherein the pins are partially encapsulated in the insulative housing.